sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
- sandbox_nolto:
- TEST_PY_BD: "sandbox"
- BUILD_ENV: "NO_LTO=1"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
---find-maintainer-files --maintainer-path=.
+--find-maintainer-files --git --maintainer-path=.
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
-sandbox without LTO test.py:
- variables:
- TEST_PY_BD: "sandbox"
- BUILD_ENV: "NO_LTO=1"
- <<: *buildman_and_testpy_dfn
-
sandbox64 test.py:
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
-sandbox64 without LTO test.py:
- variables:
- TEST_PY_BD: "sandbox64"
- BUILD_ENV: "NO_LTO=1"
- <<: *buildman_and_testpy_dfn
-
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"
ACPI:
M: Simon Glass <sjg@chromium.org>
S: Maintained
+F: board/emulation/configs/acpi.config
F: cmd/acpi.c
F: lib/acpi/
M: Igor Opaniuk <igor.opaniuk@gmail.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
+F: boot/android_ab.c
F: cmd/ab_select.c
-F: common/android_ab.c
F: doc/android/ab.rst
F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
S: Maintained
-F: arch/arm/include/asm/arch-m1/
+F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/dt-bindings/clock/mediatek,*
+F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
F: arch/arm/include/asm/arch-tegra*/
F: arch/arm/mach-tegra/
F: drivers/*/tegra*
+F: drivers/*/tegra*/
ARM TI
M: Tom Rini <trini@konsulko.com>
F: arch/arm/include/asm/ti-common/
F: board/ti/
F: drivers/dma/ti*
+F: drivers/dma/ti*/
F: drivers/firmware/ti_sci.*
F: drivers/gpio/omap_gpio.c
F: drivers/memory/ti-aemif.c
F: drivers/phy/phy-ti-am654.c
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
+F: drivers/ram/k3*/
F: drivers/remoteproc/ipu_rproc.c
F: drivers/remoteproc/k3_system_controller.c
F: drivers/remoteproc/pruc_rpoc.c
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
-W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
+W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
F: env/
+F: include/env/
F: include/env*
F: test/env/
+F: tools/env/
F: tools/env*
F: tools/mkenvimage.c
F: test/py/tests/test_stackprotector.py
TARGET_BCMNS3
-M: Bharat Gooty <bharat.gooty@broadcom.com>
M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
S: Maintained
F: board/broadcom/bcmns3/
S: Maintained
F: drivers/video/tda19988.c
+TI LP5562 LED DRIVER
+M: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+S: Supported
+F: drivers/led/led_lp5562.c
+
TI SYSTEM SECURITY
M: Andrew F. Davis <afd@ti.com>
S: Supported
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
+KBUILD_CFLAGS += $(call cc-option,-mstack-protector-guard=global)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
else
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
libs-$(CONFIG_API) += api/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += boot/
-libs-y += cmd/
+libs-$(CONFIG_CMDLINE) += cmd/
libs-y += common/
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += env/
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
- $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not override OF_HAS_PRIOR_STAGE by
@# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG))
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a tee-os-path=${TEE} \
+ -a ti-dm-path=${TI_DM} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
different from COUNTER_FREQUENCY, and can only be determined
at run time.
-- Tegra SoC options:
- CONFIG_TEGRA_SUPPORT_NON_SECURE
-
- Support executing U-Boot in non-secure (NS) mode. Certain
- impossible actions will be skipped if the CPU is in NS mode,
- such as ARM architectural timer initialization.
-
- Linux Kernel Interface:
CONFIG_OF_LIBFDT
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
- CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
- CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
- CFG_SYS_NAND_ECCBYTES
+ CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE,
+ CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE,
+ CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS,
+ CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
globally (CONFIG_CMD_MEMORY).
- CONFIG_SPL_BUILD
- Set when the currently-running compilation is for an artifact
- that will end up in the SPL (as opposed to the TPL or U-Boot
- proper). Code that needs stage-specific behavior should check
- this.
+ Set when the currently running compilation is for an artifact
+ that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
+ VPL. Code that needs phase-specific behaviour can check this,
+ or (where possible) use spl_phase() instead.
+
+ Note that CONFIG_SPL_BUILD *is* always defined when either
+ of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
+ counter-intuitive and should perhaps be changed.
- CONFIG_TPL_BUILD
- Set when the currently-running compilation is for an artifact
- that will end up in the TPL (as opposed to the SPL or U-Boot
- proper). Code that needs stage-specific behavior should check
- this.
+ Set when the currently running compilation is for an artifact
+ that will end up in the TPL build (as opposed to SPL, VPL or
+ U-Boot proper). Code that needs phase-specific behaviour can
+ check this, or (where possible) use spl_phase() instead.
+
+- CONFIG_VPL_BUILD
+ Set when the currently running compilation is for an artifact
+ that will end up in the VPL build (as opposed to the SPL, TPL
+ or U-Boot proper). Code that needs phase-specific behaviour can
+ check this, or (where possible) use spl_phase() instead.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
The U-Boot projects depends on contributions from the user community.
If you want to participate, please, have a look at the 'General'
-section of https://u-boot.readthedocs.io/en/latest/develop/index.html
+section of https://docs.u-boot.org/en/latest/develop/index.html
where we describe coding standards and the patch submission process.
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
-#if defined(CONFIG_SCSI)
- specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
- specs[ENUM_SCSI].enum_started = 0;
- specs[ENUM_SCSI].enum_ended = 0;
- specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
- specs[ENUM_SCSI].name = "scsi";
-#endif
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
+ select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
- select CMD_POWEROFF
+ select CMD_POWEROFF if CMDLINE
select DM
select DM_EVENT
select DM_FUZZING_ENGINE
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
- select SYSRESET_CMD_POWEROFF
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
- select SUPPORT_EXTENSION_SCAN
+ select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
imply BINMAN
imply CMD_MBR
imply CMD_MMC
+ imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
+ imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
+ imply CMD_SYSBOOT if BOOTSTD_FULL
config SH
bool "SuperH architecture"
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
- imply DM_SCSI
+ imply SCSI
imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
#define __ARC_BCR_H
#ifndef __ASSEMBLY__
-#include <config.h>
-
union bcr_di_cache {
struct {
#ifdef CONFIG_CPU_BIG_ENDIAN
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
-#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
-#include <config.h>
-
/*
* As of today we may handle any L1 cache line length right in software.
* For that essentially cache line length is a variable not constant.
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
+#include <bootm.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
board_jump_and_run(kernel_entry, r0, 0, r2);
}
-int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* No need for those on ARC */
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
+#include <config.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
+ imply SYS_THUMB_BUILD
config ARCH_DAVINCI
bool "TI DaVinci"
select DM_SPI_FLASH if SPI
select DM_KEYBOARD
select DM_MMC if MMC
- select DM_SCSI if SCSI
select DM_SERIAL
select OF_BOARD_SETUP
select OF_CONTROL
select PCI
select DM_RNG
select DM_RTC
- select DM_SCSI
+ select SCSI
select DM_SERIAL
select DM_SPI
select GPIO_EXTRA_HEADER
select REGMAP
select SYSCON
select SYSRESET
- select SYS_THUMB_BUILD
+ select SYS_THUMB_BUILD if !ARM64
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
select PCI
select DM_PCI
select SCSI
- select DM_SCSI
select DM_SERIAL
imply CMD_PCI
help
* actually 0x20, this the associated <destination address>. Loading the PC
* register with an address performs a jump to that address.
*/
+noinline __attribute__((target("arm")))
void mx28_fixup_vt(uint32_t start_addr)
{
/* ldr pc, [pc, #0x18] */
/* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
+
+ /* Make sure ARM core points to low vectors */
+ set_cr(get_cr() & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/sections.h>
+#include <asm/system.h>
#include <linux/compiler.h>
#include "mxs_init.h"
return i;
}
-static void mxs_spl_fixup_vectors(void)
+static noinline
+__attribute__((target("arm")))
+void mxs_spl_fixup_vectors(void)
{
/*
* Copy our vector table to 0x0, since due to HAB, we cannot
/* cppcheck-suppress nullPointer */
memcpy(0x0, _start, 0x60);
+
+ /* Make sure ARM core points to low vectors */
+ set_cr(get_cr() & ~CR_V);
}
static void mxs_spl_console_init(void)
if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
- bo_int = readl(cfg->reg);
- clrbits_le32(cfg->reg, cfg->bo_enirq);
+ bo_int = readl(&power_regs->hw_power_ctrl);
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ cfg->bo_enirq);
}
setbits_le32(cfg->reg, cfg->bo_offset_mask);
}
if (adjust_up && powered_by_linreg) {
writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
if (bo_int & cfg->bo_enirq)
- setbits_le32(cfg->reg, cfg->bo_enirq);
+ setbits_le32(&power_regs->hw_power_ctrl,
+ cfg->bo_enirq);
}
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
ENTRY(_start)
SECTIONS
{
-#ifndef CONFIG_CMDLINE
- /DISCARD/ : { *(__u_boot_list_2_cmd_*) }
-#endif
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
+ sun50i-h618-orangepi-zero3.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
+ imx8mm-phyboard-polis-rdk.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw7904.dtb \
imx8mm-venice-gw7905-0x.dtb \
imx8mm-verdin-wifi-dev.dtb \
- phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
+ imx8mp-debix-model-a.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
- imx93-11x11-evk.dtb
+ imx93-11x11-evk.dtb \
+ imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
+dtb-$(CONFIG_STM32MP25X) += \
+ stm32mp257f-ev1.dtb
+
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
- k3-j721e-r5-sk.dtb
+ k3-j721e-r5-sk.dtb \
+ k3-j721e-beagleboneai64.dtb \
+ k3-j721e-r5-beagleboneai64.dtb
+
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
+
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
&gpio4 {
bootph-some-ram;
+
+ usbh_en {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
};
&gpio5 {
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
model = "Toradex Apalis iMX8";
bootph-some-ram;
};
+&gpio_expander_43 {
+ usb-bypass-n-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ line-name = "usb-bypass-n";
+ output-high;
+ };
+ usb-reset-n-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ line-name = "usb-reset-n";
+ output-low;
+ };
+};
+
&gpio0 {
bootph-some-ram;
};
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
-#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX8X";
gpio-controller;
#gpio-cells = <2>;
reg = <0x43>;
- initial_io_dir = <0xff>;
- initial_output = <0x05>;
};
};
#include "imx7s-u-boot.dtsi"
/{
- aliases {
- mmc0 = &usdhc3;
- usb0 = &usbotg1;
- display0 = &lcdif;
- };
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc1;
+ usb0 = &usbotg1;
+ display0 = &lcdif;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&usbotg1 {
};
};
+&wdog1 {
+ bootph-pre-ram;
+};
+
&iomuxc {
pinctrl_backlight: backlight {
fsl,pins = <
dr_mode = "peripheral";
};
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
-};
-
-&pinctrl_usdhc1 {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x59
- MX7D_PAD_SD1_CLK__SD1_CLK 0x19
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
- >;
-};
-
-&iomuxc {
- pinctrl_usdhc1_gpio: usdhc1gpiogrp {
- fsl,pins = <
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
- MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
- MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
- MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
- MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
- >;
- };
-};
-
&wdog1 {
bootph-pre-ram;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- volume-up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
- volume-down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
- spi4 {
+ spi-4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
- gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
};
};
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SD1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <200000>;
+ off-on-delay-us = <20000>;
+ };
+
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
- pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
- ti,x-min = /bits/ 16 <0>;
- ti,x-max = /bits/ 16 <0>;
- ti,y-min = /bits/ 16 <0>;
- ti,y-max = /bits/ 16 <0>;
- ti,pressure-max = /bits/ 16 <0>;
- ti,x-plate-ohms = /bits/ 16 <400>;
+ pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
+ touchscreen-max-pressure = <255>;
wakeup-source;
};
};
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic: pfuze3000@8 {
+ pmic: pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
};
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_sd1_vmmc>;
wakeup-source;
keep-power-in-suspend;
status = "okay";
>;
};
+ pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
+ MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
+ MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
- MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
/ {
- aliases {
- mmc0 = &usdhc3;
- usb0 = &usbotg1;
- };
+ aliases {
+ mmc0 = &usdhc3;
+ usb0 = &usbotg1;
+ };
- chosen {
- stdout-path = &uart1;
- };
+ chosen {
+ stdout-path = &uart1;
+ };
};
&aips3 {
&gpio2 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
};
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mm-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
+ compatible = "phytec,imx8mm-phyboard-polis-rdk",
+ "phytec,imx8mm-phycore-som", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ bt_osc_32k: bt-lp-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "bt_osc_32k";
+ #clock-cells = <0>;
+ };
+
+ can_osc_40m: can-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ clock-output-names = "can_osc_40m";
+ #clock-cells = <0>;
+ };
+
+ fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0
+ 13000 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fan>;
+ #cooling-cells = <2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_CPU;
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ usdhc1_pwrseq: pwr-seq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <60>;
+ reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_en>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "CAN_EN";
+ startup-delay-us = <20>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <20000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ };
+
+ reg_vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VCC_3V3";
+ };
+};
+
+/* SPI - CAN MCP251XFD */
+&ecspi1 {
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp251xfd";
+ clocks = <&can_osc_40m>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_int>;
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ xceiver-supply = <®_can_en>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
+ "", "", "", "RESET_ETHPHY",
+ "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
+ "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "",
+ "", "", "BT_REG_ON", "WL_REG_ON",
+ "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
+ "X_SD2_CD_B", "", "", "",
+ "", "", "", "SD2_RESET_B";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "FAN", "miniPCIe_nPERST", "", "",
+ "COEX1", "COEX2";
+};
+
+&gpio5 {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "ECSPI1_SS0";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+};
+
+/* PCIe */
+&pcie0 {
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie_phy {
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ status = "okay";
+};
+
+&rv3028 {
+ trickle-resistor-ohms = <3000>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* UART - RS232/RS485 */
+&uart1 {
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* UART - Sterling-LWB Bluetooth */
+&uart2 {
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ fsl,dte-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_bt>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&bt_osc_32k>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
+ max-speed = <2000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt>;
+ shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ vddio-supply = <®_vcc_3v3>;
+ };
+};
+
+/* UART - console */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* USB */
+&usbotg1 {
+ adp-disable;
+ dr_mode = "otg";
+ over-current-active-low;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ srp-disable;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+};
+
+/* SDIO - Sterling-LWB Wifi */
+&usdhc1 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+ assigned-clock-rates = <200000000>;
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+/* SD-Card */
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_nvcc_sd2>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
+ >;
+ };
+
+ pinctrl_can_en: can-engrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
+ >;
+ };
+
+ pinctrl_can_int: can-intgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
+ >;
+ };
+
+ pinctrl_fan: fan0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_leds: leds1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
+ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
+ >;
+ };
+
+ pinctrl_uart2_bt: uart2btgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_wlan: wlangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include "imx8mm.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "PHYTEC phyCORE-i.MX8MM";
+ compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
+
+ aliases {
+ rtc0 = &rv3028;
+ rtc1 = &snvs_rtc;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ reg_vdd_3v3_s: regulator-vdd-3v3-s {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VDD_3V3_S";
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25000000 {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+/* Ethernet */
+&fec1 {
+ fsl,magic-packet;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ enet-phy-lane-no-swap;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ reg = <0>;
+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ };
+ };
+};
+
+/* SPI Flash */
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ som_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
+ "", "", "", "RESET_ETHPHY",
+ "", "", "nENABLE_FLATLINK";
+};
+
+/* I2C1 */
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default","gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "nxp,pf8121a";
+ reg = <0x08>;
+
+ regulators {
+ reg_nvcc_sd1: ldo1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "NVCC_SD1 (LDO1)";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_nvcc_sd2: ldo2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "NVCC_SD2 (LDO2)";
+ vselect-en;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_vcc_enet: ldo3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <1500000>;
+ regulator-name = "VCC_ENET_2V5 (LDO3)";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_vdda_1v8: ldo4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1500000>;
+ regulator-name = "VDDA_1V8 (LDO4)";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-min-microvolt = <1500000>;
+ regulator-suspend-max-microvolt = <1500000>;
+ };
+ };
+
+ reg_soc_vdda_phy: buck1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <400000>;
+ regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-min-microvolt = <400000>;
+ regulator-suspend-max-microvolt = <400000>;
+ };
+ };
+
+ reg_vdd_gpu_dram: buck2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-name = "VDD_GPU_DRAM (BUCK2)";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1000000>;
+ regulator-suspend-min-microvolt = <1000000>;
+ };
+ };
+
+ reg_vdd_gpu: buck3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <400000>;
+ regulator-name = "VDD_VPU (BUCK3)";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_vdd_mipi: buck4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <900000>;
+ regulator-name = "VDD_MIPI_0P9 (BUCK4)";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_vdd_arm: buck5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <400000>;
+ regulator-name = "VDD_ARM (BUCK5)";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_vdd_1v8: buck6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "VDD_1V8 (BUCK6)";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1800000>;
+ regulator-suspend-min-microvolt = <1800000>;
+ };
+ };
+
+ reg_nvcc_dram: buck7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
+ };
+
+ reg_vsnvs: vsnvs {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
+ };
+ };
+ };
+
+ sn65dsi83: bridge@2d {
+ compatible = "ti,sn65dsi83";
+ enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sn65dsi83>;
+ reg = <0x2d>;
+ status = "disabled";
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x51>;
+ vcc-supply = <®_vdd_3v3_s>;
+ };
+
+ rv3028: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ reg = <0x52>;
+ };
+};
+
+/* EMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ keep-power-in-suspend;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ non-removable;
+ status = "okay";
+};
+
+/* Watchdog */
+&wdog1 {
+ fsl,ext-reset-output;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
+ >;
+ };
+
+ pinctrl_sn65dsi83: sn65dsi83grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
+ >;
+ };
+};
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
+
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
};
&gpio4 {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
+
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
};
&gpio4 {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
+ power-domains = <&pgc_otg1>;
};
usbphynop2: usbphynop2 {
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
+ power-domains = <&pgc_otg2>;
};
soc: soc@0 {
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
reg = <0x30330000 0x10000>;
};
- gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
+ gpr: syscon@30340000 {
+ compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@410 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mm-anatop", "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
pgc_otg1: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
- power-domains = <&pgc_hsiomix>;
};
pgc_otg2: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
- power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@4 {
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ lcdif: lcdif@32e00000 {
+ compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
+ reg = <0x32e00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+ clock-names = "pix", "axi", "disp_axi";
+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_AXI>,
+ <&clk IMX8MM_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_SYS_PLL2_1000M>,
+ <&clk IMX8MM_SYS_PLL1_800M>;
+ assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
+ status = "disabled";
+
+ port {
+ lcdif_to_dsim: endpoint {
+ remote-endpoint = <&dsim_from_lcdif>;
+ };
+ };
+ };
+
+ mipi_dsi: dsi@32e10000 {
+ compatible = "fsl,imx8mm-mipi-dsim";
+ reg = <0x32e10000 0x400>;
+ clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "bus_clk", "sclk_mipi";
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+ <&clk IMX8MM_CLK_24M>;
+ assigned-clock-rates = <266000000>, <24000000>;
+ samsung,pll-clock-frequency = <24000000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsim_from_lcdif: endpoint {
+ remote-endpoint = <&lcdif_to_dsim>;
+ };
+ };
+ };
+ };
+
csi: csi@32e20000 {
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
reg = <0x32e20000 0x1000>;
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
- <&clk IMX8MM_CLK_CSI1_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
- <&clk IMX8MM_SYS_PLL2_1000M>;
+ assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
+
clock-frequency = <333000000>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
};
usbotg1: usb@32e40000 {
- compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
- power-domains = <&pgc_otg1>;
+ power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
usbotg2: usb@32e50000 {
- compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
- power-domains = <&pgc_otg2>;
+ power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc2: usbmisc@32e50200 {
- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e50200 0x200>;
};
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
- gpmi: nand-controller@33002000{
+ gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
- 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
+ <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ status = "disabled";
+ };
+
+ pcie0_ep: pcie-ep@33800000 {
+ compatible = "fsl,imx8mm-pcie-ep";
+ reg = <0x33800000 0x400000>,
+ <0x18000000 0x8000000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
status = "disabled";
};
};
&i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_pmic {
};
&eeprom_som {
- bootph-pre-ram;
+ bootph-all;
};
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
sai2: sai@30020000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
sai3: sai@30030000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
sai5: sai@30050000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
sai6: sai@30060000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
sai7: sai@300b0000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
reg = <0x30330000 0x10000>;
};
- gpr: iomuxc-gpr@30340000 {
+ gpr: syscon@30340000 {
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id@410 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
- "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
pgc_otg1: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_OTG1>;
- power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@2 {
#size-cells = <1>;
ranges;
+ lcdif: lcdif@32e00000 {
+ compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
+ reg = <0x32e00000 0x10000>;
+ clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
+ clock-names = "pix", "axi", "disp_axi";
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
+ status = "disabled";
+
+ port {
+ lcdif_to_dsim: endpoint {
+ remote-endpoint = <&dsim_from_lcdif>;
+ };
+ };
+ };
+
+ mipi_dsi: dsi@32e10000 {
+ compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
+ reg = <0x32e10000 0x400>;
+ clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>;
+ clock-names = "bus_clk", "sclk_mipi";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsim_from_lcdif: endpoint {
+ remote-endpoint = <&lcdif_to_dsim>;
+ };
+ };
+ };
+ };
+
+ isi: isi@32e20000 {
+ compatible = "fsl,imx8mn-isi";
+ reg = <0x32e20000 0x8000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+ clock-names = "axi", "apb";
+ fsl,blk-ctrl = <&disp_blk_ctrl>;
+ power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ isi_in: endpoint {
+ remote-endpoint = <&mipi_csi_out>;
+ };
+ };
+ };
+ };
+
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
"lcdif-axi", "lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk";
+ assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>,
+ <&clk IMX8MN_CLK_DISP_PIXEL>,
+ <&clk IMX8MN_CLK_DISP_AXI>,
+ <&clk IMX8MN_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+ <&clk IMX8MN_CLK_24M>,
+ <&clk IMX8MN_VIDEO_PLL1_OUT>,
+ <&clk IMX8MN_SYS_PLL2_1000M>,
+ <&clk IMX8MN_SYS_PLL1_800M>;
+ assigned-clock-rates = <266000000>,
+ <24000000>,
+ <594000000>,
+ <500000000>,
+ <200000000>;
#power-domain-cells = <1>;
};
+ mipi_csi: mipi-csi@32e30000 {
+ compatible = "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e30000 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
+ assigned-clock-rates = <333000000>;
+ clock-frequency = <333000000>;
+ clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_CAMERA_PIXEL>,
+ <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csi_out: endpoint {
+ remote-endpoint = <&isi_in>;
+ };
+ };
+ };
+ };
+
usbotg1: usb@32e40000 {
- compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
+ compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
- power-domains = <&pgc_otg1>;
+ power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
- compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
+ compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
+ power-domains = <&pgc_otg1>;
};
};
};
};
-&eqos {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
&gpio1 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <18 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <19 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
};
&gpio5 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2021 NXP
+ * Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&crypto {
+ bootph-pre-ram;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <100000>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+ bootph-pre-ram;
+};
+
+&pmic {
+ bootph-pre-ram;
+
+ regulators {
+ bootph-pre-ram;
+ };
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&uart2 {
+ bootph-pre-ram;
+};
+
+&sec_jr0 {
+ bootph-pre-ram;
+};
+
+&sec_jr1 {
+ bootph-pre-ram;
+};
+
+&sec_jr2 {
+ bootph-pre-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
+
+&usdhc3 {
+ bootph-pre-ram;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Ideas on Board Oy
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
+
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Polyhex Debix Model A i.MX8MPlus board";
+ compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-connection-type = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 { /* RTL8211E */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <20>;
+ reset-deassert-us = <200000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ };
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart2 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+/* SD Card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
+ MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
+ MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c6: i2c6grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
+ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirqgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
};
};
+&pinctrl_i2c1 {
+ bootph-all;
+};
+
+&pinctrl_pmic {
+ bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-all;
+};
+
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
};
&i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&i2c2 {
&wdog1 {
bootph-pre-ram;
};
-
-ðphy0 {
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- reset-delay-us = <15000>;
- reset-post-delay-us = <100000>;
-};
-
-&fec {
- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <15>;
- phy-reset-post-delay = <100>;
-};
-
-
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
+&gpio1 {
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
+};
+
&gpio4 {
dio_1 {
gpio-hog;
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};
reset-post-delay-us = <300000>;
};
+&gpio1 {
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
+};
+
&gpio4 {
dio_1 {
gpio-hog;
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};
clock-output-names = "clk_ext4";
};
+ funnel {
+ /*
+ * non-configurable funnel don't show up on the AMBA
+ * bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-static-funnel";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ca_funnel_in_port0: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ca_funnel_in_port1: endpoint {
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ca_funnel_in_port2: endpoint {
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ca_funnel_in_port3: endpoint {
+ remote-endpoint = <&etm3_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+
+ ca_funnel_out_port0: endpoint {
+ remote-endpoint = <&hugo_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
+ etm0: etm@28440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28440000 0x1000>;
+ cpu = <&A53_0>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm1: etm@28540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28540000 0x1000>;
+ cpu = <&A53_1>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm2: etm@28640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28640000 0x1000>;
+ cpu = <&A53_2>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm3: etm@28740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28740000 0x1000>;
+ cpu = <&A53_3>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm3_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port3>;
+ };
+ };
+ };
+ };
+
+ funnel@28c03000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x28c03000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hugo_funnel_in_port0: endpoint {
+ remote-endpoint = <&ca_funnel_out_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hugo_funnel_in_port1: endpoint {
+ /* M7 input */
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ hugo_funnel_in_port2: endpoint {
+ /* DSP input */
+ };
+ };
+ /* the other input ports are not connect to anything */
+ };
+
+ out-ports {
+ port {
+ hugo_funnel_out_port0: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ etf@28c04000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c04000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&hugo_funnel_out_port0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ };
+
+ etr@28c06000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c06000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
- regmap =<&snvs>;
+ regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
- <&clk IMX8MP_CLK_GIC>,
- <&clk IMX8MP_CLK_AUDIO_AHB>,
- <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
- <&clk IMX8MP_AUDIO_PLL1>,
- <&clk IMX8MP_AUDIO_PLL2>;
+ <&clk IMX8MP_CLK_GIC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL2_500M>,
- <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
+ <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
- <500000000>,
- <400000000>,
- <800000000>,
- <393216000>,
- <361267200>;
+ <500000000>;
};
src: reset-controller@30390000 {
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_audio: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_AXI>;
+ assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
+ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <400000000>,
+ <600000000>;
+ };
+
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
pgc_vpumix: power-domain@19 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
- clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
+ clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_vpu_g1: power-domain@20 {
};
};
+ aips5: bus@30c00000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ spba-bus@30c00000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ reg = <0x30c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sai1: sai@30c10000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c10000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai2: sai@30c20000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c20000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai3: sai@30c30000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c30000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai5: sai@30c50000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c50000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai6: sai@30c60000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c60000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai7: sai@30c80000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c80000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ easrc: easrc@30c90000 {
+ compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
+ reg = <0x30c90000 0x10000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
+ clock-names = "mem";
+ dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
+ <&sdma2 18 23 0> , <&sdma2 19 23 0>,
+ <&sdma2 20 23 0> , <&sdma2 21 23 0>,
+ <&sdma2 22 23 0> , <&sdma2 23 23 0>;
+ dma-names = "ctx0_rx", "ctx0_tx",
+ "ctx1_rx", "ctx1_tx",
+ "ctx2_rx", "ctx2_tx",
+ "ctx3_rx", "ctx3_tx";
+ firmware-name = "imx/easrc/easrc-imx8mn.bin";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-format = <2>;
+ status = "disabled";
+ };
+
+ micfil: audio-controller@30ca0000 {
+ compatible = "fsl,imx8mp-micfil";
+ reg = <0x30ca0000 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
+ <&clk IMX8MP_AUDIO_PLL1_OUT>,
+ <&clk IMX8MP_AUDIO_PLL2_OUT>,
+ <&clk IMX8MP_CLK_EXT3>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "pll11k", "clkext3";
+ dmas = <&sdma2 24 25 0x80000000>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ };
+
+ sdma3: dma-controller@30e00000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e00000 0x10000>;
+ #dma-cells = <3>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ sdma2: dma-controller@30e10000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e10000 0x10000>;
+ #dma-cells = <3>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ audio_blk_ctrl: clock-controller@30e20000 {
+ compatible = "fsl,imx8mp-audio-blk-ctrl";
+ reg = <0x30e20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_SAI1>,
+ <&clk IMX8MP_CLK_SAI2>,
+ <&clk IMX8MP_CLK_SAI3>,
+ <&clk IMX8MP_CLK_SAI5>,
+ <&clk IMX8MP_CLK_SAI6>,
+ <&clk IMX8MP_CLK_SAI7>;
+ clock-names = "ahb",
+ "sai1", "sai2", "sai3",
+ "sai5", "sai6", "sai7";
+ power-domains = <&pgc_audio>;
+ };
+ };
+
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
#size-cells = <1>;
ranges;
+ isi_0: isi@32e00000 {
+ compatible = "fsl,imx8mp-isi";
+ reg = <0x32e00000 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "axi", "apb";
+ fsl,blk-ctrl = <&media_blk_ctrl>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ isi_in_0: endpoint {
+ remote-endpoint = <&mipi_csi_0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ isi_in_1: endpoint {
+ remote-endpoint = <&mipi_csi_1_out>;
+ };
+ };
+ };
+ };
+
+ dewarp: dwe@32e30000 {
+ compatible = "nxp,imx8mp-dw100";
+ reg = <0x32e30000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "axi", "ahb";
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
+ };
+
+ mipi_csi_0: csi@32e40000 {
+ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e40000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <500000000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csi_0_out: endpoint {
+ remote-endpoint = <&isi_in_0>;
+ };
+ };
+ };
+ };
+
+ mipi_csi_1: csi@32e50000 {
+ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e50000 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <266000000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <266000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csi_1_out: endpoint {
+ remote-endpoint = <&isi_in_1>;
+ };
+ };
+ };
+ };
+
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
- <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
+ <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
* Copyright 2022 NXP
*/
+#include "imx93-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
phy-reset-post-delay = <100>;
};
-&eqos {
- compatible = "fsl,imx-eqos";
-};
-
ðphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ ddr-1d-imem-fw {
+ filename = "lpddr4_imem_1d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_dmem_1d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-2d-imem-fw {
+ filename = "lpddr4_imem_2d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_dmem_2d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ u-boot-container {
+ filename = "u-boot-container.bin";
+
+ mkimage {
+ args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
+
+ blob {
+ filename = "u-boot.bin";
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ align-size = <0x400>;
+ align = <0x400>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot-container.bin";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+#include "imx93-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ aliases {
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+ðphy1 {
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&s4muap {
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+/*
+ * The two nodes below won't be needed once nxp,pca9451a
+ * support is added to the Linux kernel.
+ */
+&iomuxc {
+ pinctrl_lpi2c3: lpi2c3grp {
+ bootph-pre-ram;
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+};
+
+&lpi2c3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-1 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ pmic@25 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+
+ regulators {
+ bootph-pre-ram;
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+/dts-v1/;
+
+#include "imx93-var-som.dtsi"
+
+/{
+ model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
+ compatible = "variscite,var-som-mx93-symphony",
+ "variscite,var-som-mx93", "fsl,imx93";
+
+ aliases {
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ /*
+ * Needed only for Symphony <= v1.5
+ */
+ reg_fec_phy: regulator-fec-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <20000>;
+ gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
+ enable-active-high;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ethosu_mem: ethosu-region@88000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x0 0x88000000 0x0 0x8000000>;
+ };
+
+ vdev0vring0: vdev0vring0@87ee0000 {
+ reg = <0 0x87ee0000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@87ee8000 {
+ reg = <0 0x87ee8000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@87ef0000 {
+ reg = <0 0x87ef0000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@87ef8000 {
+ reg = <0 0x87ef8000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@2021f000 {
+ reg = <0 0x2021f000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@87f00000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x87f00000 0 0x100000>;
+ no-map;
+ };
+
+ ele_reserved: ele-reserved@87de0000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x87de0000 0 0x100000>;
+ no-map;
+ };
+ };
+};
+
+/* Use external instead of internal RTC*/
+&bbnsm_rtc {
+ status = "disabled";
+};
+
+&eqos {
+ mdio {
+ ethphy1: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <5>;
+ qca,disable-smarteee;
+ eee-broken-1000t;
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ vddio-supply = <&vddio1>;
+
+ vddio1: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ phy-supply = <®_fec_phy>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
+ MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
+ >;
+ };
+
+ pinctrl_pca9534: pca9534grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
+ pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
+ scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* DS1337 RTC module */
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+&lpi2c5 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+ pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
+ pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
+ scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9534>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ wakeup-source;
+ };
+};
+
+/* Console */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
+ clock-names = "ipg", "per";
+ status = "okay";
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+ no-sdio;
+ no-mmc;
+};
+
+/* Watchdog */
+&wdog3 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ model = "Variscite VAR-SOM-MX93 module";
+ compatible = "variscite,var-som-mx93", "fsl,imx93";
+
+ mmc_pwrseq: mmc-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+ <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+ };
+
+ reg_eqos_phy: regulator-eqos-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eqos_phy>;
+ regulator-name = "eth_phy_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100000>;
+ regulator-always-on;
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ phy-supply = <®_eqos_phy>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <1000000>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_reg_eqos_phy: regeqosgrp {
+ fsl,pins = <
+ MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
};
dmss: bus@48000000 {
- compatible = "simple-mfd";
+ bootph-all;
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
+ bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
};
dmsc: system-controller@44043000 {
+ bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
+ bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
secure_proxy_sa3: mailbox@43600000 {
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
};
main_pmx0: pinctrl@f4000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
};
main_esm: esm@420000 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
+ bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
};
mcu_esm: esm@4100000 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ fw-init-baudrate = <3000000>;
+ };
};
vddc-supply = <®_1v2_dsi>;
vddmipi-supply = <®_1v2_dsi>;
vddio-supply = <®_1v8_dsi>;
+ status = "disabled";
dsi_bridge_ports: ports {
#address-cells = <1>;
&cbass_wakeup {
wkup_conf: syscon@43000000 {
+ bootph-all;
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
+ bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
cbass_main: bus@f0000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
cbass_mcu: bus@4000000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
};
cbass_wakeup: bus@b00000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
-#include "k3-am625-sk-binman.dtsi"
+#include "k3-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
- memory@80000000 {
- bootph-all;
- };
-
/* Keep the LEDs on by default to indicate life */
leds {
- bootph-all;
led-0 {
default-state = "on";
- bootph-all;
};
led-1 {
default-state = "on";
- bootph-all;
};
led-2 {
default-state = "on";
- bootph-all;
};
led-3 {
default-state = "on";
- bootph-all;
};
led-4 {
default-state = "on";
- bootph-all;
};
};
};
-&cbass_main {
- bootph-all;
-};
-
&main_timer0 {
clock-frequency = <25000000>;
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
-&dmsc {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
};
&dmsc {
- bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&wkup_conf {
- bootph-all;
-};
-
-&chipid {
- bootph-all;
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&console_pins_default {
- bootph-all;
-};
-
-&cbass_mcu {
- bootph-all;
-};
-
-&cbass_wakeup {
- bootph-all;
-};
-
-&mcu_pmx0 {
- bootph-all;
-};
-
-&main_i2c0 {
- bootph-all;
-};
-
-&local_i2c_pins_default {
- bootph-all;
-};
-
-&gpio0_pins_default {
- bootph-all;
-};
-
-&main_gpio0 {
- bootph-all;
-};
-
-&main_gpio1 {
- bootph-all;
-};
-
-&sdhci0 {
- /* EMMC */
- bootph-all;
-};
-
-&emmc_pins_default {
- bootph-all;
-};
-
&sd_pins_default {
- bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
>;
};
-&tps65219 {
- bootph-all;
-};
-
-&sdhci1 {
- bootph-all;
-};
-
-#ifdef CONFIG_TARGET_AM625_A53_EVM
+#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
+#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
-&spl_am625_sk_dtb {
- filename = SPL_AM625_BEAGLEPLAY_DTB;
-};
-
-&am625_sk_dtb {
- filename = AM625_BEAGLEPLAY_DTB;
-};
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
-&spl_am625_sk_dtb_unsigned {
- filename = SPL_AM625_BEAGLEPLAY_DTB;
-};
+ ti-spl_unsigned {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-beagleplay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ spl_am625_bp_dtb_unsigned: blob {
+ filename = SPL_AM625_BEAGLEPLAY_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-beagleplay";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
-&am625_sk_dtb_unsigned {
- filename = AM625_BEAGLEPLAY_DTB;
+ u-boot_unsigned {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for AM625 board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = UBOOT_NODTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-beagleplay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ am625_bp_dtb_unsigned: blob {
+ filename = AM625_BEAGLEPLAY_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-beagleplay";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
};
-
#endif
};
memory@80000000 {
+ bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
ramoops: ramoops@9ca00000 {
compatible = "ramoops";
- reg = <0x00 0x9c700000 0x00 0x00100000>;
+ reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
};
vsys_5v0: regulator-1 {
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
vdd_3v3: regulator-2 {
/* output of TLV62595DMQR-U12 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
vdd_3v3_sd: regulator-4 {
/* output of TPS22918DBVR-U21 */
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
};
vdd_sd_dv: regulator-5 {
+ bootph-all;
compatible = "regulator-gpio";
regulator-name = "sd_hs200_switch";
pinctrl-names = "default";
};
leds {
+ bootph-all;
compatible = "gpio-leds";
led-0 {
+ bootph-all;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
};
led-1 {
+ bootph-all;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
function = LED_FUNCTION_DISK_ACTIVITY;
};
led-2 {
+ bootph-all;
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
};
led-3 {
+ bootph-all;
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_LAN;
};
led-4 {
+ bootph-all;
gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
};
&main_pmx0 {
gpio0_pins_default: gpio0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
};
vdd_sd_dv_pins_default: vdd-sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
};
local_i2c_pins_default: local-i2c-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
};
emmc_pins_default: emmc-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
};
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
};
console_pins_default: console-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
};
&main_gpio0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
};
&main_gpio1 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_gpio_pins_default>;
gpio-line-names = "", "", "", "", "", /* 0-4 */
};
&main_i2c0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&local_i2c_pins_default>;
clock-frequency = <400000>;
};
tps65219: pmic@30 {
+ bootph-all;
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
};
&sdhci0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
&sdhci1 {
/* SD/MMC */
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
};
&main_uart0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
+
+ mcu {
+ compatible = "ti,cc1352p7";
+ reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
+ vdds-supply = <&vdd_3v3>;
+ };
};
&dss {
ti,secure-host;
};
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
};
};
-&main_esm {
- bootph-pre-ram;
-};
-
&main_pktdma {
ti,sci = <&dm_tifs>;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};
+
+&binman {
+ tiboot3-am62x-gp-evm.bin {
+ filename = "tiboot3-am62x-gp-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+ combined;
+ dm-data;
+ content-sbl = <&u_boot_spl_unsigned>;
+ load = <0x43c00000>;
+ content-sysfw = <&ti_fs_gp>;
+ load-sysfw = <0x40000>;
+ content-sysfw-data = <&combined_tifs_cfg_gp>;
+ load-sysfw-data = <0x67000>;
+ content-dm-data = <&combined_dm_cfg_gp>;
+ load-dm-data = <0x43c3a800>;
+ sw-rev = <1>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_gp: ti-fs-gp.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+};
ti,secure-host;
};
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
-&main_esm {
- bootph-pre-ram;
-};
-
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
};
};
-&wkup_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_uart1_pins_default {
- bootph-pre-ram;
-};
-
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- bootph-pre-ram;
+ status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- bootph-pre-ram;
+ status = "okay";
};
&ospi0 {
#ifdef CONFIG_TARGET_AM625_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Board";
};
fdt-0 {
/ {
chosen {
- stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
-
- aliases {
- mmc1 = &sdhci1;
- };
-
- memory@80000000 {
- bootph-all;
- };
-};
-
-&main_conf {
- bootph-all;
-};
-
-&cbass_main {
- bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
-&dmsc {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
-&wkup_conf {
- bootph-all;
-};
-
-&chipid {
- bootph-all;
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&main_uart0_pins_default {
- bootph-all;
-};
-
-&cbass_mcu {
- bootph-all;
-};
-
-&cbass_wakeup {
- bootph-all;
-};
-
-&mcu_pmx0 {
- bootph-all;
-};
-
-&sdhci1 {
- bootph-all;
-};
-
-&main_mmc1_pins_default {
- bootph-all;
-};
-
-&fss {
- bootph-all;
-};
-
-&ospi0_pins_default {
- bootph-all;
-};
-
-&ospi0 {
- bootph-all;
-
- flash@0 {
- bootph-all;
-
- partitions {
- bootph-all;
-
- partition@3fc0000 {
- bootph-all;
- };
- };
- };
-};
-
-&inta_main_dmss {
- bootph-all;
};
&main_bcdma {
bootph-all;
};
-&cpsw3g_mdio {
- bootph-all;
-};
-
-&cpsw3g_phy0 {
- bootph-all;
-};
-
-&cpsw3g_phy1 {
- bootph-all;
-};
-
-&main_rgmii1_pins_default {
- bootph-all;
-};
-
-&main_rgmii2_pins_default {
- bootph-all;
-};
-
-&phy_gmii_sel {
- bootph-all;
-};
-
-&cpsw3g {
- bootph-all;
- ethernet-ports {
- bootph-all;
- };
-};
-
-&cpsw_port1 {
- bootph-all;
-};
-
&cpsw_port2 {
status = "disabled";
};
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
vcc_5v0: regulator-1 {
/* Output of LM34936 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
+ bootph-all;
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
&main_pmx0 {
main_rgmii2_pins_default: main-rgmii2-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
};
ospi0_pins_default: ospi0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_gpio1 {
+ bootph-all;
+};
+
&main_i2c1 {
+ bootph-all;
exp1: gpio@22 {
+ bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
};
};
+&fss {
+ bootph-all;
+};
+
&ospi0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
+ bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
cdns,read-delay = <4>;
partitions {
+ bootph-all;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
partition@3fc0000 {
+ bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
- * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
+ * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
- */
+*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
+
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
#define DDRSS_CTL_39_DATA 0x00000000
-#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_40_DATA 0x00000A1C
#define DDRSS_CTL_41_DATA 0x00000000
-#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_42_DATA 0x00000A1C
#define DDRSS_CTL_43_DATA 0x00000000
#define DDRSS_CTL_44_DATA 0x05000804
#define DDRSS_CTL_45_DATA 0x00000B00
#define DDRSS_CTL_46_DATA 0x09090004
-#define DDRSS_CTL_47_DATA 0x00000204
+#define DDRSS_CTL_47_DATA 0x00000304
#define DDRSS_CTL_48_DATA 0x00370008
#define DDRSS_CTL_49_DATA 0x09090024
-#define DDRSS_CTL_50_DATA 0x00001910
+#define DDRSS_CTL_50_DATA 0x00002110
#define DDRSS_CTL_51_DATA 0x00370008
#define DDRSS_CTL_52_DATA 0x09090024
-#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_53_DATA 0x09002110
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x0400036D
#define DDRSS_CTL_56_DATA 0x09092004
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_207_DATA 0x00000000
#define DDRSS_CTL_208_DATA 0x00000024
-#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_209_DATA 0x0000001A
#define DDRSS_CTL_210_DATA 0x00000000
#define DDRSS_CTL_211_DATA 0x00000024
-#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_212_DATA 0x0000001A
#define DDRSS_CTL_213_DATA 0x00000000
#define DDRSS_CTL_214_DATA 0x00000004
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_216_DATA 0x00000000
#define DDRSS_CTL_217_DATA 0x00000024
-#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_218_DATA 0x0000001A
#define DDRSS_CTL_219_DATA 0x00000000
#define DDRSS_CTL_220_DATA 0x00000024
-#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_221_DATA 0x0000001A
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
-#define DDRSS_CTL_254_DATA 0x46004646
-#define DDRSS_CTL_255_DATA 0x00002746
-#define DDRSS_CTL_256_DATA 0x00000027
-#define DDRSS_CTL_257_DATA 0x00000027
-#define DDRSS_CTL_258_DATA 0x00000027
-#define DDRSS_CTL_259_DATA 0x00000027
-#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_254_DATA 0x44004444
+#define DDRSS_CTL_255_DATA 0x00004D44
+#define DDRSS_CTL_256_DATA 0x0000004D
+#define DDRSS_CTL_257_DATA 0x0000004D
+#define DDRSS_CTL_258_DATA 0x0000004D
+#define DDRSS_CTL_259_DATA 0x0000004D
+#define DDRSS_CTL_260_DATA 0x0000004D
#define DDRSS_CTL_261_DATA 0x00000000
#define DDRSS_CTL_262_DATA 0x00000000
-#define DDRSS_CTL_263_DATA 0x0000000F
-#define DDRSS_CTL_264_DATA 0x0000000F
-#define DDRSS_CTL_265_DATA 0x0000000F
-#define DDRSS_CTL_266_DATA 0x0000000F
-#define DDRSS_CTL_267_DATA 0x0000000F
-#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_263_DATA 0x0000004D
+#define DDRSS_CTL_264_DATA 0x0000004D
+#define DDRSS_CTL_265_DATA 0x0000004D
+#define DDRSS_CTL_266_DATA 0x0000004D
+#define DDRSS_CTL_267_DATA 0x0000004D
+#define DDRSS_CTL_268_DATA 0x0000004D
#define DDRSS_CTL_269_DATA 0x00000000
#define DDRSS_CTL_270_DATA 0x00001000
#define DDRSS_CTL_271_DATA 0x00000015
#define DDRSS_CTL_371_DATA 0x01000101
#define DDRSS_CTL_372_DATA 0x01010001
#define DDRSS_CTL_373_DATA 0x00010101
-#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_374_DATA 0x01070703
#define DDRSS_CTL_375_DATA 0x05020201
#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
-#define DDRSS_CTL_378_DATA 0x000B030E
-#define DDRSS_CTL_379_DATA 0x000B0310
-#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_378_DATA 0x0009030E
+#define DDRSS_CTL_379_DATA 0x00090312
+#define DDRSS_CTL_380_DATA 0x09090806
#define DDRSS_CTL_381_DATA 0x01000000
#define DDRSS_CTL_382_DATA 0x03020301
#define DDRSS_CTL_383_DATA 0x04000102
#define DDRSS_CTL_399_DATA 0x00003690
#define DDRSS_CTL_400_DATA 0x00007940
#define DDRSS_CTL_401_DATA 0x070D0402
-#define DDRSS_CTL_402_DATA 0x00260405
+#define DDRSS_CTL_402_DATA 0x00260607
#define DDRSS_CTL_403_DATA 0x00000C20
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00003690
#define DDRSS_CTL_409_DATA 0x00007940
#define DDRSS_CTL_410_DATA 0x070D0402
-#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_411_DATA 0x00000607
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
#define DDRSS_PI_169_DATA 0x00020043
#define DDRSS_PI_170_DATA 0x02000200
#define DDRSS_PI_171_DATA 0x00000004
-#define DDRSS_PI_172_DATA 0x0000080C
-#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_172_DATA 0x00000A0C
+#define DDRSS_PI_173_DATA 0x000A1C00
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x00000059
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
-#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_187_DATA 0x05070703
#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
-#define DDRSS_PI_194_DATA 0x04020808
-#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_194_DATA 0x06020808
+#define DDRSS_PI_195_DATA 0x04040206
#define DDRSS_PI_196_DATA 0x00090031
#define DDRSS_PI_197_DATA 0x00110039
#define DDRSS_PI_198_DATA 0x00110039
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
-#define DDRSS_PI_224_DATA 0x001D0204
-#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_224_DATA 0x001F0204
+#define DDRSS_PI_225_DATA 0x72400056
#define DDRSS_PI_226_DATA 0x05000101
-#define DDRSS_PI_227_DATA 0x001D0408
-#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_227_DATA 0x001F0608
+#define DDRSS_PI_228_DATA 0x72400056
#define DDRSS_PI_229_DATA 0x05000101
-#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_230_DATA 0x00000608
#define DDRSS_PI_231_DATA 0x05040900
#define DDRSS_PI_232_DATA 0x00060900
#define DDRSS_PI_233_DATA 0x00000315
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00000000
#define DDRSS_PI_303_DATA 0x00000000
-#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_304_DATA 0x00104D4D
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
-#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_307_DATA 0x0000001A
#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
-#define DDRSS_PI_311_DATA 0x46000000
-#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_311_DATA 0x44000000
+#define DDRSS_PI_312_DATA 0x00154D4D
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
-#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_315_DATA 0x0000001A
#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
-#define DDRSS_PI_319_DATA 0x46000000
-#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_319_DATA 0x44000000
+#define DDRSS_PI_320_DATA 0x00154D4D
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00000000
#define DDRSS_PI_327_DATA 0x00000000
-#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_328_DATA 0x00104D4D
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
-#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_331_DATA 0x0000001A
#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
-#define DDRSS_PI_335_DATA 0x46000000
-#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_335_DATA 0x44000000
+#define DDRSS_PI_336_DATA 0x00154D4D
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
-#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_339_DATA 0x0000001A
#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
-#define DDRSS_PI_343_DATA 0x46000000
-#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PI_343_DATA 0x44000000
+#define DDRSS_PI_344_DATA 0x00154D4D
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_2_DATA 0x00030200
#define DDRSS_PHY_71_DATA 0x00000000
#define DDRSS_PHY_72_DATA 0x041F07FF
#define DDRSS_PHY_73_DATA 0x00000000
-#define DDRSS_PHY_74_DATA 0x01CC0B01
-#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_74_DATA 0x01FF0B01
+#define DDRSS_PHY_75_DATA 0x1003FF0B
#define DDRSS_PHY_76_DATA 0x20000140
#define DDRSS_PHY_77_DATA 0x07FF0200
#define DDRSS_PHY_78_DATA 0x0000DD01
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
-#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_90_DATA 0x06B60340
#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x04050000
#define DDRSS_PHY_93_DATA 0x00000504
#define DDRSS_PHY_327_DATA 0x00000000
#define DDRSS_PHY_328_DATA 0x041F07FF
#define DDRSS_PHY_329_DATA 0x00000000
-#define DDRSS_PHY_330_DATA 0x01CC0B01
-#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_330_DATA 0x01FF0B01
+#define DDRSS_PHY_331_DATA 0x1003FF0B
#define DDRSS_PHY_332_DATA 0x20000140
#define DDRSS_PHY_333_DATA 0x07FF0200
#define DDRSS_PHY_334_DATA 0x0000DD01
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
-#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_346_DATA 0x06B60340
#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x04050000
#define DDRSS_PHY_349_DATA 0x00000504
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
-#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_544_DATA 0x020002FF
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
-#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_800_DATA 0x020002FF
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
-#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1056_DATA 0x020002FF
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
#define DDRSS_PHY_1384_DATA 0x00000300
#define DDRSS_PHY_1385_DATA 0x00000300
#define DDRSS_PHY_1386_DATA 0x00000300
-#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1387_DATA 0x31833F77
#define DDRSS_PHY_1388_DATA 0x00000000
-#define DDRSS_PHY_1389_DATA 0x0C000DFF
-#define DDRSS_PHY_1390_DATA 0x30000DFF
-#define DDRSS_PHY_1391_DATA 0x3F0DFF11
-#define DDRSS_PHY_1392_DATA 0x01990000
-#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1389_DATA 0x0C000DBF
+#define DDRSS_PHY_1390_DATA 0x30000DBF
+#define DDRSS_PHY_1391_DATA 0x3F0DBF11
+#define DDRSS_PHY_1392_DATA 0x01FF0000
+#define DDRSS_PHY_1393_DATA 0x780DBFFF
#define DDRSS_PHY_1394_DATA 0x00000C11
#define DDRSS_PHY_1395_DATA 0x00018011
#define DDRSS_PHY_1396_DATA 0x0089FF00
#define DDRSS_PHY_1397_DATA 0x000C3F11
-#define DDRSS_PHY_1398_DATA 0x01990000
-#define DDRSS_PHY_1399_DATA 0x000C3F11
-#define DDRSS_PHY_1400_DATA 0x01990000
-#define DDRSS_PHY_1401_DATA 0x3F0DFF11
-#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1398_DATA 0x01FF0000
+#define DDRSS_PHY_1399_DATA 0x000C3F91
+#define DDRSS_PHY_1400_DATA 0x01FF0000
+#define DDRSS_PHY_1401_DATA 0x3F0DBF11
+#define DDRSS_PHY_1402_DATA 0x01FF0000
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
#define DDRSS_PHY_1405_DATA 0x20040004
ti,secure-host;
};
-&main_esm {
- bootph-pre-ram;
-};
-
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
#include "k3-binman.dtsi"
-&custmpk_pem {
- filename = "../../ti/keys/custMpk.pem";
-};
-
-&dkey_pem {
- filename = "../../ti/keys/ti-degenerate-key.pem";
-};
-
-#ifndef CONFIG_ARM64
-
-&bcfg_yaml {
- schema = "../../ti/common/schema.yaml";
-};
-
-&pcfg_yaml {
- schema = "../../ti/common/schema.yaml";
-};
-
-&rcfg_yaml {
- schema = "../../ti/common/schema.yaml";
-};
-
-&scfg_yaml {
- schema = "../../ti/common/schema.yaml";
-};
-
-/* combined-tifs-cfg */
-
-&bcfg_yaml_tifs {
- schema = "../../ti/common/schema.yaml";
-};
-
-&pcfg_yaml_tifs {
- schema = "../../ti/common/schema.yaml";
-};
-
-&rcfg_yaml_tifs {
- schema = "../../ti/common/schema.yaml";
-};
-
-&scfg_yaml_tifs {
- schema = "../../ti/common/schema.yaml";
-};
-
-/* combined-dm-cfg */
-
-&pcfg_yaml_dm {
- schema = "../../ti/common/schema.yaml";
-};
-
-&rcfg_yaml_dm {
- schema = "../../ti/common/schema.yaml";
-};
-
-/* combined-sysfw-cfg */
-
-&bcfg_yaml_sysfw {
- schema = "../../ti/common/schema.yaml";
-};
-
-&pcfg_yaml_sysfw {
- schema = "../../ti/common/schema.yaml";
-};
-
-&rcfg_yaml_sysfw {
- schema = "../../ti/common/schema.yaml";
-};
-
-&scfg_yaml_sysfw {
- schema = "../../ti/common/schema.yaml";
-};
-
-#endif /* CONFIG_ARM64 */
-
#ifdef CONFIG_TARGET_VERDIN_AM62_R5
&binman {
#ifdef CONFIG_TARGET_VERDIN_AM62_A53
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define VERDIN_AM62_DTB "u-boot.dtb"
&binman {
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot fot AM625 Verdin Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Verdin Board";
};
fdt-0 {
};
};
-&cbass_main {
- bootph-all;
-
- timer@2400000 {
- clock-frequency = <25000000>;
- bootph-all;
- };
-};
-
-&cbass_mcu {
- bootph-all;
-};
-
-&cbass_wakeup {
- bootph-all;
-};
-
-&chipid {
- bootph-all;
+&main_timer0 {
+ clock-frequency = <25000000>;
};
&main_bcdma {
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
};
&main_pktdma {
};
&dmsc {
- bootph-all;
-
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&dmss {
- bootph-all;
-};
-
&fss {
bootph-all;
};
-&k3_clks {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
&main_gpio0 {
bootph-all;
};
};
};
-&main_pmx0 {
- bootph-all;
-};
-
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
bootph-all;
bootph-all;
};
-&mcu_pmx0 {
- bootph-all;
-};
-
&pinctrl_ctrl_sleep_moci {
bootph-all;
};
status = "disabled";
};
-&secure_proxy_main {
- bootph-all;
-};
-
&verdin_ctrl_sleep_moci {
bootph-all;
};
-&wkup_conf {
- bootph-all;
-};
-
/* Verdin UART_2 */
&wkup_uart0 {
bootph-all;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
dmss: bus@48000000 {
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <6 70 34>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
};
dmsc: system-controller@44043000 {
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
};
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
status = "disabled";
};
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ status = "disabled";
+ };
+
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
no-1-8-v;
status = "disabled";
};
+
+ usbss0: dwc3-usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>;
+ clocks = <&k3_clks 161 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: dwc3-usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>;
+ clocks = <&k3_clks 162 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster1: mailbox@29010000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29010000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ main_mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&k3_clks 125 0>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 125 0>;
+ assigned-clock-parents = <&k3_clks 125 2>;
+ };
+
+ main_rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&k3_clks 126 0>;
+ power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 126 0>;
+ assigned-clock-parents = <&k3_clks 126 2>;
+ };
+
+ main_rti2: watchdog@e020000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e020000 0x00 0x100>;
+ clocks = <&k3_clks 127 0>;
+ power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 127 0>;
+ assigned-clock-parents = <&k3_clks 127 2>;
+ };
+
+ main_rti3: watchdog@e030000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e030000 0x00 0x100>;
+ clocks = <&k3_clks 128 0>;
+ power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 128 0>;
+ assigned-clock-parents = <&k3_clks 128 2>;
+ };
+
+ main_rti4: watchdog@e040000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e040000 0x00 0x100>;
+ clocks = <&k3_clks 205 0>;
+ power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 205 0>;
+ assigned-clock-parents = <&k3_clks 205 2>;
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp0: audio-controller@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 190 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 190 0>;
+ assigned-clock-parents = <&k3_clks 190 2>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: audio-controller@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 191 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 191 0>;
+ assigned-clock-parents = <&k3_clks 191 2>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: audio-controller@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 192 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 192 0>;
+ assigned-clock-parents = <&k3_clks 192 2>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
status = "disabled";
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
clock-names = "fck";
status = "disabled";
};
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ status = "disabled";
+ };
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x04201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <24>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ mcu_rti0: watchdog@4880000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x04880000 0x00 0x100>;
+ clocks = <&k3_clks 131 0>;
+ power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 131 0>;
+ assigned-clock-parents = <&k3_clks 131 2>;
+ /* Tightly coupled to M4F */
+ status = "reserved";
+ };
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM62Ax board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM62Ax Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM62Ax board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM62Ax Board";
};
fdt-0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-source;
status = "disabled";
};
+
+ wkup_rti0: watchdog@2b000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2b000000 0x00 0x100>;
+ clocks = <&k3_clks 132 0>;
+ power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 132 0>;
+ assigned-clock-parents = <&k3_clks 132 2>;
+ /* Used by DM firmware */
+ status = "reserved";
+ };
+
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
+
+ #include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial0 = &wkup_uart0;
- serial3 = &main_uart1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
};
a53_0: a53@0 {
ti,secure-host;
};
-&cbass_main {
- sa3_secproxy: secproxy@44880000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg = <0x00 0x44880000 0x00 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- bootph-pre-ram;
- };
+&secure_proxy_sa3 {
+ /* Needed for initial handshake with ROM */
+ status = "okay";
+ bootph-pre-ram;
+};
+&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
- <&sa3_secproxy 0>;
+ <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
-&mcu_pmx0 {
- status = "okay";
+&wkup_uart0_pins_default {
bootph-pre-ram;
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
- >;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&main_uart1_pins_default {
bootph-pre-ram;
- main_uart1_pins_default: main-uart1-pins-default {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
- >;
- bootph-pre-ram;
- };
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "k3-am62a-sk-binman.dtsi"
+
/ {
chosen {
stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
-&cbass_main{
- bootph-pre-ram;
+&main_timer0 {
+ bootph-all;
+};
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x00 0x2400000 0x00 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
+&cbass_main {
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_uart1 {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&exp1 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&vdd_mmc1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&cpsw_port1 {
+ bootph-all;
};
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
+ compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
+ serial0 = &wkup_uart0;
serial2 = &main_uart0;
+ serial3 = &main_uart1;
mmc1 = &sdhci1;
};
regulator-boot-on;
};
- vcc_3v3_sys: regulator-2 {
+ vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
+ regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
+ vcc_3v3_sys: regulator-4 {
+ /* output of TPS222965DSGT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
default-state = "off";
};
};
+
+ tlv320_mclk: clk-0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ };
+
+ codec_audio: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM62Ax-SKEVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&tlv320_mclk>;
+ };
+ };
+};
+
+&mcu_pmx0 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
+ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
+ AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
+ AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
+ >;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
+ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
+ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
+ AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
+ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
>;
};
- usr_led_pins_default: usr-led-pins-default {
+ usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+ AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+ AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+ AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+ AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+ AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+ AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+ AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+ AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
+ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
+ AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ status = "okay";
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
+ >;
+ };
+};
+
+&mcu_gpio0 {
+ status = "okay";
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+
+ typec_pd0: usb-power-controller@3f {
+ compatible = "ti,tps6598x";
+ reg = <0x3f>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ self-powered;
+ data-role = "dual";
+ power-role = "sink";
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
+ };
+ };
+ };
+ };
+
+ tps659312: pmic@48 {
+ compatible = "ti,tps6593-q1";
+ reg = <0x48>;
+ ti,primary-pmic;
+ system-power-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&mcu_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ buck123-supply = <&vcc_3v3_sys>;
+ buck4-supply = <&vcc_3v3_sys>;
+ buck5-supply = <&vcc_3v3_sys>;
+ ldo1-supply = <&vcc_3v3_sys>;
+ ldo2-supply = <&vcc_3v3_sys>;
+ ldo3-supply = <&buck5>;
+ ldo4-supply = <&vcc_3v3_sys>;
+
+ regulators {
+ buck123: buck123 {
+ regulator-name = "vcc_core";
+ regulator-min-microvolt = <715000>;
+ regulator-max-microvolt = <895000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-name = "vcc_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-name = "vcc_1v8_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: ldo1 {
+ regulator-name = "vddshv5_sdio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: ldo2 {
+ regulator-name = "vpp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: ldo3 {
+ regulator-name = "vcc_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: ldo4 {
+ regulator-name = "vdda_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
+
+ tlv320aic3106: audio-codec@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+
+ /* Regulators */
+ AVDD-supply = <&vcc_3v3_sys>;
+ IOVDD-supply = <&vcc_3v3_sys>;
+ DRVDD-supply = <&vcc_3v3_sys>;
+ DVDD-supply = <&buck5>;
+ };
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "reserved";
+};
+
+&usbss0 {
+ status = "okay";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ usb-role-switch;
+
+ port {
+ usb0_hs_ep: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
memory@80000000 {
+ bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
clocks = <&tlv320_mclk>;
};
};
+
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
};
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
};
main_uart1_pins_default: main-uart1-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
};
main_mmc0_pins_default: main-mmc0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
};
main_mmc1_pins_default: main-mmc1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
+
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
+ AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
+ AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
+ AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
+ AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
+ AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
+ AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
+ AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
+ >;
+ };
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
+ bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
+ bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
};
+
+ sii9022: bridge-hdmi@3b {
+ compatible = "sil,sii9022";
+ reg = <0x3b>;
+ interrupt-parent = <&exp1>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ #sound-dai-cells = <0>;
+ sil,i2s-data-lanes = < 0 >;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&sdhci0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
&sdhci1 {
/* SD/MMC */
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
};
&cpsw3g {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
+ bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw3g_mdio {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
+ bootph-all;
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+};
+
+&dss_ports {
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
#ifdef CONFIG_TARGET_AM642_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
&binman {
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
fdt-0 {
description = "k3-am642-evm";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM64 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM64 Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am642-evm";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM64 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM64 Board";
};
fdt-0 {
*/
&main_pmx0 {
- cp2102n_reset_pin_default: cp2102n-reset-pin-default {
+ cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
/ {
aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ i2c5 = &main_i2c3;
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
chosen {
stdout-path = "serial3:115200n8";
- bootargs = "earlycon=ns16550a,mmio32,0x02810000";
};
reserved-memory {
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
>;
};
- mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
>;
};
- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
+ arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
pinctrl-single,pins = <
/* (R2) WKUP_GPIO0_21 */
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
>;
};
- push_button_pins_default: push-button-pins-default {
+ push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
>;
};
- arduino_uart_pins_default: arduino-uart-pins-default {
+ arduino_uart_pins_default: arduino-uart-default-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
>;
};
- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
+ arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
>;
};
- arduino_io_oe_pins_default: arduino-io-oe-pins-default {
+ arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
/* (N4) WKUP_GPIO0_34 */
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
>;
};
- db9_com_mode_pins_default: db9-com-mode-pins-default {
+ db9_com_mode_pins_default: db9-com-mode-default-pins {
pinctrl-single,pins = <
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
>;
};
- leds_pins_default: leds-pins-default {
+ leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
/* (T2) WKUP_GPIO0_17, used as user led1 red */
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
>;
};
- mcu_spi0_pins_default: mcu-spi0-pins-default {
+ mcu_spi0_pins_default: mcu-spi0-default-pins {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
>;
};
- minipcie_pins_default: minipcie-pins-default {
+ minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
};
&main_pmx0 {
- main_uart1_pins_default: main-uart1-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
>;
};
- main_i2c3_pins_default: main-i2c3-pins-default {
+ main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
>;
};
- usb0_pins_default: usb0-pins-default {
+ usb0_pins_default: usb0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
- usb1_pins_default: usb1-pins-default {
+ usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
+ arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
>;
};
- dss_vout1_pins_default: dss-vout1-pins-default {
+ dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
>;
};
- dp_pins_default: dp-pins-default {
+ dp_pins_default: dp-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
};
&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
- ecap0_pins_default: ecap0-pins-default {
+ ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
};
&main_uart1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
-&main_uart2 {
- status = "disabled";
-};
-
&mcu_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
&wkup_gpio0 {
pinctrl-names = "default";
- pinctrl-0 = <
- &arduino_io_d2_to_d3_pins_default
- &arduino_i2c_aio_switch_pins_default
- &arduino_io_oe_pins_default
- &push_button_pins_default
- &db9_com_mode_pins_default
- >;
+ pinctrl-0 =
+ <&arduino_io_d2_to_d3_pins_default>,
+ <&arduino_i2c_aio_switch_pins_default>,
+ <&arduino_io_oe_pins_default>,
+ <&push_button_pins_default>,
+ <&db9_com_mode_pins_default>;
gpio-line-names =
/* 0..9 */
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
psu: regulator@60 {
compatible = "ti,tps62363";
- reg = <0x60>;
+ reg = <0x60>;
regulator-name = "tps62363-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
- rtc: rtc8564@51 {
+ rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
};
&mcu_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
#address-cells = <1>;
- #size-cells= <0>;
+ #size-cells = <0>;
ti,pindir-d0-out-d1-in;
};
-&tscadc0 {
- status = "disabled";
-};
-
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5>;
};
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ seboot@0 {
+ label = "seboot";
+ reg = <0x0 0x180000>; /* 1.5M */
+ };
+
+ tispl@180000 {
+ label = "tispl";
+ reg = <0x180000 0x200000>; /* 2M */
+ };
+
+ u-boot@380000 {
+ label = "u-boot";
+ reg = <0x380000 0x300000>; /* 3M */
+ };
+
+ env@680000 {
+ label = "env";
+ reg = <0x680000 0x20000>; /* 128K */
+ };
+
+ env-backup@6a0000 {
+ label = "env.backup";
+ reg = <0x6a0000 0x20000>; /* 128K */
+ };
+
+ otpcmd@6c0000 {
+ label = "otpcmd";
+ reg = <0x6c0000 0x10000>; /* 64K */
+ };
+
+ unused@6d0000 {
+ label = "unused";
+ reg = <0x6d0000 0x7b0000>; /* 7872K */
+ };
+
+ seboot-backup@e80000 {
+ label = "seboot.backup";
+ reg = <0xe80000 0x180000>; /* 1.5M */
+ };
+ };
};
};
};
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&mcu_rti1 {
memory-region = <&wdt_reset_memory_region>;
-
-};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
};
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
crypto: crypto@4e00000 {
compatible = "ti,am654-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
- <&main_udmap 0x4001>;
+ dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
+ <&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 136 1>;
+ status = "disabled"; /* Used by OP-TEE */
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x30>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ecap0: pwm@3100000 {
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@2100000 {
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@2110000 {
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
+ status = "disabled";
};
main_spi2: spi@2120000 {
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi3: spi@2130000 {
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi4: spi@2140000 {
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 23 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 23 0>;
+ assigned-clock-parents = <&k3_clks 23 1>;
+ power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 24 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 24 0>;
+ assigned-clock-parents = <&k3_clks 24 1>;
+ power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 27 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 27 0>;
+ assigned-clock-parents = <&k3_clks 27 1>;
+ power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 28 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 28 0>;
+ assigned-clock-parents = <&k3_clks 28 1>;
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 29 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 29 0>;
+ assigned-clock-parents = <&k3_clks 29 1>;
+ power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 30 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 30 0>;
+ assigned-clock-parents = <&k3_clks 30 1>;
+ power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 31 0>;
+ assigned-clocks = <&k3_clks 31 0>;
+ assigned-clock-parents = <&k3_clks 31 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 32 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 32 0>;
+ assigned-clock-parents = <&k3_clks 32 1>;
+ power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 33 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 33 0>;
+ assigned-clock-parents = <&k3_clks 33 1>;
+ power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 34 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 34 0>;
+ assigned-clock-parents = <&k3_clks 34 1>;
+ power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 25 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 25 0>;
+ assigned-clock-parents = <&k3_clks 25 1>;
+ power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 26 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 26 0>;
+ assigned-clock-parents = <&k3_clks 26 1>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
sdhci0: mmc@4f80000 {
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- pcie0_mode: pcie-mode@4060 {
- compatible = "syscon";
- reg = <0x00004060 0x4>;
- };
-
- pcie1_mode: pcie-mode@4070 {
- compatible = "syscon";
- reg = <0x00004070 0x4>;
- };
-
- pcie_devid: pcie-devid@210 {
- compatible = "syscon";
- reg = <0x00000210 0x4>;
- };
-
serdes0_clk: clock@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
- reg = <0x0000041e0 0x14>;
+ reg = <0x000041e0 0x14>;
};
- ehrpwm_tbclk: clock@4140 {
- compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
};
main_navss: bus@30800000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>,
+ <0x0 0x31080000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
main_udmap: dma-controller@31150000 {
compatible = "ti,am654-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie0_ep: pcie-ep@5500000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
- 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
+ <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie1_ep: pcie-ep@5600000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
mcasp0: mcasp@2b00000 {
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
cal: cal@6f03000 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
- <0x0 0x04a06000 0x0 0x1000>, /* vid */
- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+ <0x0 0x04a06000 0x0 0x1000>, /* vid */
+ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 67 1>,
- <&k3_clks 216 1>,
- <&k3_clks 67 2>;
+ clocks = <&k3_clks 67 1>,
+ <&k3_clks 216 1>,
+ <&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
/*
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm1: pwm@3010000 {
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm2: pwm@3020000 {
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm3: pwm@3030000 {
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm4: pwm@3040000 {
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm5: pwm@3050000 {
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
icssg0: icssg@b000000 {
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
};
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x10>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000101>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000003>;
+ };
+
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_ram: sram@41c00000 {
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_spi0: spi@40300000 {
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi1: spi@40310000 {
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi2: spi@40320000 {
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
tscadc0: tscadc@40200000 {
clocks = <&k3_clks 0 2>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
clocks = <&k3_clks 1 2>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
};
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ clocks = <&k3_clks 35 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ clocks = <&k3_clks 36 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ clocks = <&k3_clks 37 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ clocks = <&k3_clks 38 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
+ "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
};
};
- fss: fss@47000000 {
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x2a480000 0x0 0x80000>,
+ <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
+ m_can0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40528000 0x0 0x400>,
+ <0x0 0x40500000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ m_can1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40568000 0x0 0x400>,
+ <0x0 0x40540000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
ospi1: spi@47050000 {
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
-
- thermal_zones: thermal-zones {
- #include "k3-am654-industrial-thermal.dtsi"
- };
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654";
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- i2c5 = &main_i2c3;
- ethernet0 = &cpsw_port1;
- };
-
chosen { };
firmware {
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include "k3-am654-r5-base-board-u-boot.dtsi"
#include "k3-am65x-binman.dtsi"
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+};
+
+&mcu_timer0 {
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ bootph-all;
+};
+
+&vtt_supply {
+ bootph-all;
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&main_navss {
+ bootph-all;
+};
+
+&cbass_mcu {
+ bootph-all;
+};
+
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ bootph-all;
+};
+
+&mcu_udmap {
+ bootph-all;
+};
+
+&wkup_gpio0 {
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&cbass_wakeup {
+ bootph-all;
+
+ chipid@43000014 {
+ bootph-all;
+ };
+};
+
+&dmsc {
+ bootph-all;
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&wkup_vtm0 {
+ bootph-all;
+};
+
+&wkup_pmx0 {
+ bootph-all;
+};
+
+&wkup_uart0_pins_default {
+ bootph-all;
+};
+
+&ddr_vtt_pins_default {
+ bootph-all;
+};
+
+&mcu_uart0_pins_default {
+ bootph-all;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-all;
+};
+
+&mcu_fss0_ospi0_pins_default {
+ bootph-all;
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_mmc0_pins_default {
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&main_pmx1 {
+ bootph-all;
+};
+
+&sdhci0 {
+ bootph-all;
+};
+
+&sdhci1 {
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ bootph-all;
+};
+
+&vdd_mpu {
+ bootph-all;
+};
+
+&ospi0 {
+ bootph-all;
+
+ flash@0 {
+ bootph-all;
+ };
+};
+
+&dwc3_0 {
+ bootph-all;
+};
+
+&scm_conf {
+ bootph-all;
+};
+
+&fss {
+ bootph-all;
+};
+
&pru0_0 {
remoteproc-name = "pru0_0";
};
&mcu_r5fss0 {
ti,cluster-mode = <0>;
};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&main_udmap {
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x10000>,
+ <0x0 0x30c00000 0x0 0x10000>,
+ <0x0 0x30d00000 0x0 0x8000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
#include <dt-bindings/net/ti-dp83867.h>
/ {
- compatible = "ti,am654-evm", "ti,am654";
+ compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 Base Board";
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ ethernet0 = &cpsw_port1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins_default>;
- sw5 {
+ switch-5 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
};
- sw6 {
+ switch-6 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-boot-on;
};
- vcc3v3_io: fixedregulator-vcc3v3io {
+ vcc3v3_io: regulator-1 {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
vin-supply = <&evm_12v0>;
};
- vdd_mmc1_sd: fixedregulator-sd {
+ vdd_mmc1_sd: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
+
+ vtt_supply: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ };
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
- push_button_pins_default: push-button-pins-default {
+ push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
>;
};
- wkup_pca554_default: wkup-pca554-default {
+ wkup_pca554_default: wkup-pca554-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
};
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
+
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
+ >;
+ };
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
>;
};
- main_mmc0_pins_default: main-mmc0-pins-default {
+ main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
>;
};
- usb1_pins_default: usb1-pins-default {
+ usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
- ecap0_pins_default: ecap0-pins-default {
+ ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+
+ vdd_mpu: regulator@60 {
+ compatible = "ti,tps62363";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ ti,enable-vout-discharge;
+ };
+
+ gpio@38 {
+ compatible = "nxp,pca9554";
+ reg = <0x38>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
pca9554: gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
};
};
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
- #size-cells= <0>;
+ #size-cells = <0>;
ti,pindir-d0-out-d1-in;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <48000000>;
- #address-cells = <1>;
- #size-cells= <1>;
};
};
};
&tscadc0 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
status = "disabled";
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x20000>;
+ };
+
+ partition@6a0000 {
+ label = "ospi.env.backup";
+ reg = <0x6a0000 0x20000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fe0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fe0000 0x20000>;
+ };
+ };
};
};
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
phy-handle = <&phy0>;
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
&dss {
status = "disabled";
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/pinctrl/k3.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am65x-binman.dtsi"
-
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial2 = &main_uart0;
- ethernet0 = &cpsw_port1;
- usb0 = &usb0;
- usb1 = &usb1;
- spi0 = &ospi0;
- spi1 = &ospi1;
- };
-};
-
-&cbass_main{
- bootph-pre-ram;
- main_navss: bus@30800000 {
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
- bootph-pre-ram;
-
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- ti,dma-ring-reset-quirk;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
-};
-
-&cbass_wakeup {
- bootph-pre-ram;
-
- chipid@43000014 {
- bootph-pre-ram;
- };
-};
-
-&secure_proxy_main {
- bootph-pre-ram;
-};
-
-&dmsc {
- bootph-pre-ram;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
-};
-
-&k3_pds {
- bootph-pre-ram;
-};
-
-&k3_clks {
- bootph-pre-ram;
-};
-
-&k3_reset {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- bootph-pre-ram;
-
- wkup_i2c0_pins_default {
- bootph-pre-ram;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- bootph-pre-ram;
- };
-};
-
-&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_pmx1 {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- mcu-fss0-ospi0-pins-default {
- bootph-pre-ram;
- };
-};
-
-&main_uart0 {
- bootph-pre-ram;
-};
-
-&main_mmc0_pins_default {
- bootph-pre-ram;
-};
-
-&main_mmc1_pins_default {
- bootph-pre-ram;
-};
-
-&sdhci0 {
- bootph-pre-ram;
-};
-
-&sdhci1 {
- bootph-pre-ram;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
-};
-
-&wkup_i2c0 {
- bootph-pre-ram;
-};
-
-&usb1 {
- dr_mode = "peripheral";
-};
-
-&fss {
- bootph-pre-ram;
-};
-
-&ospi0 {
- bootph-pre-ram;
-
- flash@0{
- bootph-pre-ram;
- };
-};
-
-&dwc3_0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0_phy {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&scm_conf {
- bootph-pre-ram;
-};
/dts-v1/;
-#include "k3-am654.dtsi"
+#include "k3-am654-base-board.dts"
+#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {
- compatible = "ti,am654-evm", "ti,am654";
- model = "Texas Instruments AM654 R5 Base Board";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
bootph-pre-ram;
};
- vtt_supply: vtt_supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
- };
-};
-
-&cbass_main {
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-all;
- };
-};
-
-&cbass_mcu {
- mcu_secproxy: secproxy@28380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
+ clk_200mhz: dummy_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
bootph-pre-ram;
};
};
-&wkup_gpio0 {
+&secure_proxy_mcu {
+ status = "okay";
bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
+};
- clk_200mhz: dummy_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+/*
+ * timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&mcu_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes = <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 6>,
+ <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&wkup_uart0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
+ bootph-pre-ram;
};
&mcu_uart0 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
/delete-property/ power-domains;
status = "okay";
-};
-
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
- status = "okay";
+ bootph-pre-ram;
};
&wkup_vtm0 {
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- bootph-pre-ram;
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
- AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
- AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- wkup_vtt_pins_default: wkup_vtt_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
- >;
- bootph-pre-ram;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
- >;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- >;
- bootph-pre-ram;
- };
-
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- bootph-pre-ram;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
- >;
- bootph-pre-ram;
- };
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_vtt_pins_default>;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
-};
-
-&wkup_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
- bootph-pre-ram;
-
- vdd_mpu: tps62363@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "VDD_MPU";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1770000>;
- regulator-always-on;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- bootph-pre-ram;
- };
};
&ospi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- bootph-pre-ram;
- };
};
&dwc3_0 {
status = "okay";
- bootph-pre-ram;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
-&usb0_phy {
- status = "okay";
- bootph-pre-ram;
- /delete-property/ clocks;
-};
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "peripheral";
- bootph-pre-ram;
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
};
-&scm_conf {
- bootph-pre-ram;
+&usb1 {
+ dr_mode = "peripheral";
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
+ };
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
};
};
};
&main_pmx0 {
- main_mmc0_pins_default: main-mmc0-pins-default {
+ main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
ti,driver-strength-ohm = <50>;
disable-wp;
};
-
-&main_uart0 {
- status = "disabled";
-};
};
&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-pins-default {
+ main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
- main_bkey_pcie_reset: main-bkey-pcie-reset {
+ main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
>;
};
- main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
+ main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
>;
};
- main_m2_pcie_mux_control: main-m2-pcie-mux-control {
+ main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
};
&main_pmx1 {
- main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
+ main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
&main_gpio0 {
pinctrl-names = "default";
- pinctrl-0 = <
- &main_m2_pcie_mux_control
- &arduino_io_d4_to_d9_pins_default
- >;
+ pinctrl-0 =
+ <&main_m2_pcie_mux_control>,
+ <&arduino_io_d4_to_d9_pins_default>;
};
&main_gpio1 {
pinctrl-names = "default";
- pinctrl-0 = <
- &main_m2_enable_pins_default
- &main_pmx0_m2_config_pins_default
- &main_pmx1_m2_config_pins_default
- &cp2102n_reset_pin_default
- >;
+ pinctrl-0 =
+ <&main_m2_enable_pins_default>,
+ <&main_pmx0_m2_config_pins_default>,
+ <&main_pmx1_m2_config_pins_default>,
+ <&cp2102n_reset_pin_default>;
};
/*
};
itb {
filename = "sysfw-am65x_sr2-hs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&board_cfg>;
- keyfile = "custMpk.pem";
- };
- board_cfg: board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&pm_cfg>;
- keyfile = "custMpk.pem";
- };
- pm_cfg: pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&rm_cfg>;
- keyfile = "custMpk.pem";\
- };
- rm_cfg: rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&sec_cfg>;
- keyfile = "custMpk.pem";
- };
- sec_cfg: sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_template>;
};
};
itb_gp {
filename = "sysfw-am65x_sr2-gp-evm.itb";
symlink = "sysfw.itb";
+ insert-template = <&itb_unsigned_template>;
fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
images {
sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "board-cfg.bin";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "pm-cfg.bin";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "rm-cfg.bin";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sec-cfg.bin";
- };
- };
};
};
};
#ifdef CONFIG_TARGET_AM654_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM654_EVM_DTB "u-boot.dtb"
&binman {
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am654-base-board";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM65 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM65 Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM65 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM65 Board";
};
fdt-0 {
};
};
};
+
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
+ <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_usb_link: phy@2 {
+ status = "okay";
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 3>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 2 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_1_memory_region: c71-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a8000000 {
+ reg = <0x00 0xa8000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
};
reg = <0x51>;
};
};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c71_1: mbox-c71-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+&c71_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ memory-region = <&c71_1_dma_memory_region>,
+ <&c71_1_memory_region>;
+};
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "k3-security.h"
+
/ {
binman: binman {
multiple-images;
custMpk {
filename = "custMpk.pem";
custmpk_pem: blob-ext {
- filename = "../keys/custMpk.pem";
+ filename = "arch/arm/mach-k3/keys/custMpk.pem";
};
};
ti-degenerate-key {
filename = "ti-degenerate-key.pem";
dkey_pem: blob-ext {
- filename = "../keys/ti-degenerate-key.pem";
+ filename = "arch/arm/mach-k3/keys/ti-degenerate-key.pem";
};
};
};
filename = "board-cfg.bin";
bcfg_yaml: ti-board-config {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
pm-cfg {
filename = "pm-cfg.bin";
pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
sec-cfg {
filename = "sec-cfg.bin";
scfg_yaml: ti-board-config {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
combined-tifs-cfg {
ti-board-config {
bcfg_yaml_tifs: board-cfg {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_tifs: sec-cfg {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_tifs: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_tifs: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
ti-board-config {
pcfg_yaml_dm: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_dm: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
ti-board-config {
bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "arch/arm/mach-k3/schema.yaml";
+ };
+ };
+ };
+};
+
+&binman {
+ itb_template: template-5 {
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&board_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ board_cfg: board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&pm_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ pm_cfg: pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&rm_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ rm_cfg: rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&sec_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ sec_cfg: sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+
+ itb_unsigned_template: template-6 {
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_fs";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+};
+
+#else
+
+&binman {
+ ti_spl_template: template-1 {
+ filename = "tispl.bin";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ ti-secure {
+ content = <&atf>;
+ keyfile = "custMpk.pem";
+ };
+ atf: atf-bl31 {
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ ti-secure {
+ content = <&tee>;
+ keyfile = "custMpk.pem";
+ };
+ tee: tee-os {
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_spl_nodtb>;
+ keyfile = "custMpk.pem";
+
+ };
+ u_boot_spl_nodtb: blob-ext {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+
+ };
+ };
+ };
+ ti_spl_unsigned_template: template-2 {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob-ext {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+ };
+ };
+ };
+ u_boot_template: template-3 {
+ filename = "u-boot.img";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_nodtb>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_nodtb: u-boot-nodtb {
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
};
};
};
+ u_boot_unsigned_template: template-4 {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = "u-boot-nodtb.bin";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+ };
+ };
+ firewall_bg_1: template-5 {
+ control = <(FWCTRL_EN | FWCTRL_LOCK |
+ FWCTRL_BG | FWCTRL_CACHE)>;
+ permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>;
+ start_address = <0x0 0x0>;
+ end_address = <0xff 0xffffffff>;
+ };
+ firewall_bg_3: template-6 {
+ insert-template = <&firewall_bg_1>;
+ permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>,
+ <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>,
+ <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>;
+ };
+ firewall_armv8_atf_fg: template-7 {
+ control = <(FWCTRL_EN | FWCTRL_LOCK |
+ FWCTRL_CACHE)>;
+ permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD)>;
+ start_address = <0x0 0x70000000>;
+ end_address = <0x0 0x7001ffff>;
+ };
+ firewall_armv8_optee_fg: template-8 {
+ control = <(FWCTRL_EN | FWCTRL_LOCK |
+ FWCTRL_CACHE)>;
+ permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD)>;
+ start_address = <0x0 0x9e800000>;
+ end_address = <0x0 0x9fffffff>;
+ };
+
};
#endif
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
+ auth-in-place = <0xa02>;
+
+ firewall-257-0 {
+ /* cpu_0_cpu_0_msmc Background Firewall */
+ insert-template = <&firewall_bg_1>;
+ id = <257>;
+ region = <0>;
+ };
+
+ firewall-257-1 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <257>;
+ region = <1>;
+ };
+
+ /* firewall-4760-0 {
+ * nb_slv0__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-4760-1 {
+ /* nb_slv0__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <4760>;
+ region = <1>;
+ };
+
+ /* firewall-4761-0 {
+ * nb_slv1__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-4761-1 {
+ /* nb_slv1__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <4761>;
+ region = <1>;
+ };
};
};
tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
+ auth-in-place = <0xa02>;
+
+ /* cpu_0_cpu_0_msmc region 0 and 1 configured
+ * during ATF Firewalling
+ */
+
+ firewall-257-2 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <257>;
+ region = <2>;
+ };
+
+ firewall-4762-0 {
+ /* nb_slv2__mem0 Background Firewall - 0 */
+ insert-template = <&firewall_bg_3>;
+ id = <4762>;
+ region = <0>;
+ };
+
+ firewall-4762-1 {
+ /* nb_slv2__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <4762>;
+ region = <1>;
+ };
+
+ firewall-4763-0 {
+ /* nb_slv3__mem0 Background Firewall - 0 */
+ insert-template = <&firewall_bg_3>;
+ id = <4763>;
+ region = <0>;
+ };
+
+ firewall-4763-1 {
+ /* nb_slv3__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <4763>;
+ region = <1>;
+ };
};
};
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
-
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J7200 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J7200 Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = SPL_NODTB;
- };
- };
-
fdt-1 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J7200 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J7200 Board";
};
fdt-1 {
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
+ assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-binman.dtsi"
+
+/ {
+ memory@80000000 {
+ bootph-all;
+ };
+
+ /* Keep the LEDs on by default to indicate life */
+ leds {
+ bootph-all;
+ led-0 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-1 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-2 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-3 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-4 {
+ default-state = "on";
+ bootph-all;
+ };
+ };
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&main_navss {
+ bootph-all;
+};
+
+&cbass_mcu_wakeup {
+ bootph-all;
+
+ chipid@43000014 {
+ bootph-all;
+ };
+};
+
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ bootph-all;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&dmsc {
+ bootph-all;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-all;
+ };
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&wkup_pmx0 {
+ bootph-all;
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_sdhci0 {
+ bootph-all;
+};
+
+&main_sdhci1 {
+ bootph-all;
+ sdhci-caps-mask = <0x00000007 0x00000000>;
+ /delete-property/ cd-gpios;
+ /delete-property/ cd-debounce-delay-ms;
+ /delete-property/ ti,fails-without-test-cd;
+ /delete-property/ no-1-8-v;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&mcu_cpsw {
+ bootph-all;
+};
+
+&davinci_mdio {
+ bootph-all;
+};
+
+&phy0 {
+ bootph-all;
+};
+
+&serdes2 {
+ bootph-all;
+};
+
+&serdes_ln_ctrl {
+ bootph-all;
+};
+
+&serdes2_usb_link {
+ bootph-all;
+};
+
+&usb_serdes_mux {
+ bootph-all;
+};
+
+&serdes_wiz2 {
+ bootph-all;
+};
+
+&main_usbss1_pins_default {
+ bootph-all;
+};
+
+&mcu_usbss1_pins_default {
+ bootph-all;
+};
+
+&usbss1 {
+ bootph-all;
+};
+
+&usb1 {
+ bootph-all;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ bootph-all;
+};
+
+#ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+
+ ti-spl_unsigned {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob-ext {
+ filename = SPL_NODTB;
+ };
+ };
+
+ fdt-0 {
+ description = "k3-j721e-beagleboneai64";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = SPL_J721E_BBAI64_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j721e-beagleboneai64";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+
+ u-boot_unsigned {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for j721e board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = UBOOT_NODTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-j721e-beagleboneai64";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = J721E_BBAI64_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j721e-beagleboneai64";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+/ {
+ compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
+ model = "BeagleBoard.org BeagleBone AI-64";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &main_i2c6;
+ i2c2 = &main_i2c2;
+ i2c3 = &main_i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_pwr_pins_default>;
+
+ button-1 {
+ label = "BOOT";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led-0 {
+ gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc0";
+ };
+
+ led-2 {
+ gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CPU;
+ linux,default-trigger = "cpu";
+ };
+
+ led-3 {
+ gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc1";
+ };
+
+ led-4 {
+ gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_WLAN;
+ default-state = "off";
+ };
+ };
+
+ evm_12v0: regulator-0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-1 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-2 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwr_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: regulator-4 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ dp_pwr_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_3v3_en_pins_default>;
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ led_pins_default: led-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
+ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ sd_pwr_en_pins_default: sd-pwr-en-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
+ >;
+ };
+
+ dp0_pins_default: dp0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
+ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
+ J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
+ J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
+ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
+ J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
+ J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ main_i2c6_pins_default: main-i2c6-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+ J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
+ J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
+ >;
+ };
+
+ csi0_gpio_pins_default: csi0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ >;
+ };
+
+ csi1_gpio_pins_default: csi1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ >;
+ };
+
+ pcie1_rst_pins_default: pcie1-rst-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ eeprom_wp_pins_default: eeprom-wp-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
+ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
+ J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
+ J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
+ J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
+ J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
+ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
+ >;
+ };
+
+ mikro_bus_pins_default: mikro-bus-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
+ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
+
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
+
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ sw_pwr_pins_default: sw-pwr-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_usbss1_pins_default: mcu-usbss1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by TIFS firmware. */
+ status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&main_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ status = "okay";
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ status = "okay";
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c2 {
+ /* BBB Header: P9.19 and P9.20 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+ /* BBB Header: P9.24 and P9.26 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c6 {
+ /* BBB Header: P9.17 and P9.18 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c6_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eeprom_wp_pins_default>;
+ };
+};
+
+&wkup_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
+ <&mikro_bus_pins_default>;
+};
+
+&main_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
+};
+
+&main_gpio1 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ status = "okay";
+ /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6>;
+ };
+};
+
+&tscadc1 {
+ status = "okay";
+ /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
+ adc {
+ ti,adc-channels = <0>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
+ <&k3_clks 152 4>, /* VP 2 pixel clock */
+ <&k3_clks 152 9>, /* VP 3 pixel clock */
+ <&k3_clks 152 13>; /* VP 4 pixel clock */
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_rst_pins_default>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ status = "okay";
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
};
itb {
filename = "sysfw-j721e_sr1_1-hs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&board_cfg>;
- keyfile = "custMpk.pem";
- };
- board_cfg: board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
-
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&pm_cfg>;
- keyfile = "custMpk.pem";
- };
- pm_cfg: pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&rm_cfg>;
- keyfile = "custMpk.pem";
- };
- rm_cfg: rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&sec_cfg>;
- keyfile = "custMpk.pem";
- };
- sec_cfg: sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_template>;
};
};
};
itb_fs {
filename = "sysfw-j721e_sr2-hs-fs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin_fs";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
-
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_unsigned_template>;
};
};
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
+ insert-template = <&itb_unsigned_template>;
+
fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
images {
sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "board-cfg.bin";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "pm-cfg.bin";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "rm-cfg.bin";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sec-cfg.bin";
- };
- };
};
};
};
#ifdef CONFIG_TARGET_J721E_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_EVM_DTB "u-boot.dtb"
#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
+ auth-in-place = <0xa02>;
+
+ firewall-257-0 {
+ /* cpu_0_cpu_0_msmc Background Firewall */
+ insert-template = <&firewall_bg_1>;
+ id = <257>;
+ region = <0>;
+ };
+
+ firewall-257-1 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <257>;
+ region = <1>;
+ };
+
+ firewall-284-0 {
+ /* dru_0_msmc Background Firewall */
+ insert-template = <&firewall_bg_3>;
+ id = <284>;
+ region = <0>;
+ };
+
+ firewall-284-1 {
+ /* dru_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <284>;
+ region = <1>;
+ };
+
+ /* firewall-4760-0 {
+ * nb_slv0__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-4760-1 {
+ /* nb_slv0__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <4760>;
+ region = <1>;
+ };
+
+ /* firewall-4761-0 {
+ * nb_slv1__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-4761-1 {
+ /* nb_slv1__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <4761>;
+ region = <1>;
+ };
+
};
};
tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
+ auth-in-place = <0xa02>;
+
+ /* cpu_0_cpu_0_msmc region 0 and 1 configured
+ * during ATF Firewalling
+ */
+
+ firewall-257-2 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <257>;
+ region = <2>;
+ };
+
+ /* dru_0_msmc region 0 and 1 configured
+ * during ATF Firewalling
+ */
+
+ firewall-284-2 {
+ /* dru_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <284>;
+ region = <2>;
+ };
+
+ firewall-4762-0 {
+ /* nb_slv2__mem0 Background Firewall */
+ insert-template = <&firewall_bg_3>;
+ id = <4762>;
+ region = <0>;
+ };
+
+ firewall-4762-1 {
+ /* nb_slv2__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <4762>;
+ region = <1>;
+ };
+
+ firewall-4763-0 {
+ /* nb_slv3__mem0 Background Firewall */
+ insert-template = <&firewall_bg_3>;
+ id = <4763>;
+ region = <0>;
+ };
+
+ firewall-4763-1 {
+ /* nb_slv3__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <4763>;
+ region = <1>;
+ };
};
};
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
-
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
images {
uboot {
- description = "U-Boot for j721e board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721E Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for j721e board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721E Board";
};
fdt-0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.1
+ * This file was generated on 02/08/2023
+ * Part Number: Kingston Q3222PM1WDGTK-U
+ * Configuration: LPDDR4-3200, wrDBI enabled, j721e-SK latencies
+ * Also common for:
+ * * Part Number: Samsung K4FBE3D4HM-MGC @ LPDDR4-3200 (instead of 3700)
+ */
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
+
+#define DDRSS_CTL_00_DATA 0x00000B00
+#define DDRSS_CTL_01_DATA 0x00000000
+#define DDRSS_CTL_02_DATA 0x00000000
+#define DDRSS_CTL_03_DATA 0x00000000
+#define DDRSS_CTL_04_DATA 0x00000000
+#define DDRSS_CTL_05_DATA 0x00000000
+#define DDRSS_CTL_06_DATA 0x00000000
+#define DDRSS_CTL_07_DATA 0x00002AF8
+#define DDRSS_CTL_08_DATA 0x0001ADAF
+#define DDRSS_CTL_09_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x0000006E
+#define DDRSS_CTL_11_DATA 0x0004E200
+#define DDRSS_CTL_12_DATA 0x0030D400
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000C80
+#define DDRSS_CTL_15_DATA 0x0004E200
+#define DDRSS_CTL_16_DATA 0x0030D400
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000C80
+#define DDRSS_CTL_19_DATA 0x01010000
+#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_21_DATA 0x02010000
+#define DDRSS_CTL_22_DATA 0x00020100
+#define DDRSS_CTL_23_DATA 0x0000000B
+#define DDRSS_CTL_24_DATA 0x0000001C
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x03020200
+#define DDRSS_CTL_28_DATA 0x00004040
+#define DDRSS_CTL_29_DATA 0x00100000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x040C0000
+#define DDRSS_CTL_35_DATA 0x0E380E38
+#define DDRSS_CTL_36_DATA 0x00050804
+#define DDRSS_CTL_37_DATA 0x09040008
+#define DDRSS_CTL_38_DATA 0x14000304
+#define DDRSS_CTL_39_DATA 0x15480068
+#define DDRSS_CTL_40_DATA 0x14004220
+#define DDRSS_CTL_41_DATA 0x15480068
+#define DDRSS_CTL_42_DATA 0x20004220
+#define DDRSS_CTL_43_DATA 0x000A0A09
+#define DDRSS_CTL_44_DATA 0x0400078A
+#define DDRSS_CTL_45_DATA 0x17100D04
+#define DDRSS_CTL_46_DATA 0x0C00DB60
+#define DDRSS_CTL_47_DATA 0x17100D0C
+#define DDRSS_CTL_48_DATA 0x0C00DB60
+#define DDRSS_CTL_49_DATA 0x0203040C
+#define DDRSS_CTL_50_DATA 0x21040500
+#define DDRSS_CTL_51_DATA 0x08222122
+#define DDRSS_CTL_52_DATA 0x14000E0A
+#define DDRSS_CTL_53_DATA 0x03010A0A
+#define DDRSS_CTL_54_DATA 0x01010003
+#define DDRSS_CTL_55_DATA 0x04424208
+#define DDRSS_CTL_56_DATA 0x04252504
+#define DDRSS_CTL_57_DATA 0x00002525
+#define DDRSS_CTL_58_DATA 0x00010100
+#define DDRSS_CTL_59_DATA 0x03010000
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_61_DATA 0x000000CE
+#define DDRSS_CTL_62_DATA 0x000001C0
+#define DDRSS_CTL_63_DATA 0x00001858
+#define DDRSS_CTL_64_DATA 0x000001C0
+#define DDRSS_CTL_65_DATA 0x00001858
+#define DDRSS_CTL_66_DATA 0x00000005
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00700012
+#define DDRSS_CTL_69_DATA 0x00700304
+#define DDRSS_CTL_70_DATA 0x00400304
+#define DDRSS_CTL_71_DATA 0x00120103
+#define DDRSS_CTL_72_DATA 0x000C0005
+#define DDRSS_CTL_73_DATA 0x2408000C
+#define DDRSS_CTL_74_DATA 0x05050124
+#define DDRSS_CTL_75_DATA 0x0301030A
+#define DDRSS_CTL_76_DATA 0x03170C08
+#define DDRSS_CTL_77_DATA 0x0C080301
+#define DDRSS_CTL_78_DATA 0x00010317
+#define DDRSS_CTL_79_DATA 0x00100010
+#define DDRSS_CTL_80_DATA 0x01CC01CC
+#define DDRSS_CTL_81_DATA 0x01CC01CC
+#define DDRSS_CTL_82_DATA 0x03050505
+#define DDRSS_CTL_83_DATA 0x03010303
+#define DDRSS_CTL_84_DATA 0x18080C08
+#define DDRSS_CTL_85_DATA 0x03030C03
+#define DDRSS_CTL_86_DATA 0x18080C08
+#define DDRSS_CTL_87_DATA 0x03030C03
+#define DDRSS_CTL_88_DATA 0x03010000
+#define DDRSS_CTL_89_DATA 0x00010000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x01000000
+#define DDRSS_CTL_93_DATA 0x80104002
+#define DDRSS_CTL_94_DATA 0x00000000
+#define DDRSS_CTL_95_DATA 0x00040005
+#define DDRSS_CTL_96_DATA 0x00000000
+#define DDRSS_CTL_97_DATA 0x00050000
+#define DDRSS_CTL_98_DATA 0x00000004
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x00040005
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00003380
+#define DDRSS_CTL_103_DATA 0x00003380
+#define DDRSS_CTL_104_DATA 0x00003380
+#define DDRSS_CTL_105_DATA 0x00003380
+#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_107_DATA 0x00000000
+#define DDRSS_CTL_108_DATA 0x000005A2
+#define DDRSS_CTL_109_DATA 0x00061600
+#define DDRSS_CTL_110_DATA 0x00061600
+#define DDRSS_CTL_111_DATA 0x00061600
+#define DDRSS_CTL_112_DATA 0x00061600
+#define DDRSS_CTL_113_DATA 0x00061600
+#define DDRSS_CTL_114_DATA 0x00000000
+#define DDRSS_CTL_115_DATA 0x0000AA68
+#define DDRSS_CTL_116_DATA 0x00061600
+#define DDRSS_CTL_117_DATA 0x00061600
+#define DDRSS_CTL_118_DATA 0x00061600
+#define DDRSS_CTL_119_DATA 0x00061600
+#define DDRSS_CTL_120_DATA 0x00061600
+#define DDRSS_CTL_121_DATA 0x00000000
+#define DDRSS_CTL_122_DATA 0x0000AA68
+#define DDRSS_CTL_123_DATA 0x00000000
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x00000000
+#define DDRSS_CTL_126_DATA 0x00000000
+#define DDRSS_CTL_127_DATA 0x00000000
+#define DDRSS_CTL_128_DATA 0x00000000
+#define DDRSS_CTL_129_DATA 0x00000000
+#define DDRSS_CTL_130_DATA 0x00000000
+#define DDRSS_CTL_131_DATA 0x08030500
+#define DDRSS_CTL_132_DATA 0x00030803
+#define DDRSS_CTL_133_DATA 0x0A090000
+#define DDRSS_CTL_134_DATA 0x0A090701
+#define DDRSS_CTL_135_DATA 0x0900000E
+#define DDRSS_CTL_136_DATA 0x0907010A
+#define DDRSS_CTL_137_DATA 0x00000E0A
+#define DDRSS_CTL_138_DATA 0x07010A09
+#define DDRSS_CTL_139_DATA 0x000E0A09
+#define DDRSS_CTL_140_DATA 0x07000401
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x08080000
+#define DDRSS_CTL_149_DATA 0x01000000
+#define DDRSS_CTL_150_DATA 0x800000C0
+#define DDRSS_CTL_151_DATA 0x800000C0
+#define DDRSS_CTL_152_DATA 0x800000C0
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00001500
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000001
+#define DDRSS_CTL_157_DATA 0x00000002
+#define DDRSS_CTL_158_DATA 0x0000100E
+#define DDRSS_CTL_159_DATA 0x00000000
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x00000000
+#define DDRSS_CTL_162_DATA 0x00000000
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x000B0000
+#define DDRSS_CTL_165_DATA 0x000E0006
+#define DDRSS_CTL_166_DATA 0x000E0404
+#define DDRSS_CTL_167_DATA 0x00A00140
+#define DDRSS_CTL_168_DATA 0x0C0C0190
+#define DDRSS_CTL_169_DATA 0x01400190
+#define DDRSS_CTL_170_DATA 0x019000A0
+#define DDRSS_CTL_171_DATA 0x01900C0C
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x2DD40084
+#define DDRSS_CTL_176_DATA 0xAB002DD4
+#define DDRSS_CTL_177_DATA 0x0000ABAB
+#define DDRSS_CTL_178_DATA 0x45450000
+#define DDRSS_CTL_179_DATA 0x27272745
+#define DDRSS_CTL_180_DATA 0x0F0F0F00
+#define DDRSS_CTL_181_DATA 0x1D000000
+#define DDRSS_CTL_182_DATA 0x00841D1D
+#define DDRSS_CTL_183_DATA 0x2DD42DD4
+#define DDRSS_CTL_184_DATA 0xABABAB00
+#define DDRSS_CTL_185_DATA 0x00000000
+#define DDRSS_CTL_186_DATA 0x27454545
+#define DDRSS_CTL_187_DATA 0x0F002727
+#define DDRSS_CTL_188_DATA 0x00000F0F
+#define DDRSS_CTL_189_DATA 0x1D1D1D00
+#define DDRSS_CTL_190_DATA 0x00000020
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000001
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x01000000
+#define DDRSS_CTL_195_DATA 0x00000001
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x02000000
+#define DDRSS_CTL_207_DATA 0x01080101
+#define DDRSS_CTL_208_DATA 0x00000000
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000000
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000000
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000000
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000000
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00001000
+#define DDRSS_CTL_223_DATA 0x006403E8
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x15110000
+#define DDRSS_CTL_228_DATA 0x00040C18
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00030000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x01000200
+#define DDRSS_CTL_258_DATA 0x00370040
+#define DDRSS_CTL_259_DATA 0x00020008
+#define DDRSS_CTL_260_DATA 0x00400100
+#define DDRSS_CTL_261_DATA 0x00300640
+#define DDRSS_CTL_262_DATA 0x01000200
+#define DDRSS_CTL_263_DATA 0x06400040
+#define DDRSS_CTL_264_DATA 0x00000030
+#define DDRSS_CTL_265_DATA 0x00500003
+#define DDRSS_CTL_266_DATA 0x01000050
+#define DDRSS_CTL_267_DATA 0x03030303
+#define DDRSS_CTL_268_DATA 0x01010000
+#define DDRSS_CTL_269_DATA 0x00000202
+#define DDRSS_CTL_270_DATA 0x00000FFF
+#define DDRSS_CTL_271_DATA 0x1FFF1000
+#define DDRSS_CTL_272_DATA 0x01FF0000
+#define DDRSS_CTL_273_DATA 0x000101FF
+#define DDRSS_CTL_274_DATA 0x0FFF0B00
+#define DDRSS_CTL_275_DATA 0x01010001
+#define DDRSS_CTL_276_DATA 0x01010101
+#define DDRSS_CTL_277_DATA 0x01180101
+#define DDRSS_CTL_278_DATA 0x00030000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000000
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00040101
+#define DDRSS_CTL_287_DATA 0x04010100
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x03030300
+#define DDRSS_CTL_291_DATA 0x00000101
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00000000
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x01000000
+#define DDRSS_CTL_314_DATA 0x00020201
+#define DDRSS_CTL_315_DATA 0x01000101
+#define DDRSS_CTL_316_DATA 0x01010001
+#define DDRSS_CTL_317_DATA 0x00010101
+#define DDRSS_CTL_318_DATA 0x05080803
+#define DDRSS_CTL_319_DATA 0x0C081818
+#define DDRSS_CTL_320_DATA 0x0009030C
+#define DDRSS_CTL_321_DATA 0x090B030F
+#define DDRSS_CTL_322_DATA 0x090B0306
+#define DDRSS_CTL_323_DATA 0x0B090006
+#define DDRSS_CTL_324_DATA 0x0100000B
+#define DDRSS_CTL_325_DATA 0x06030601
+#define DDRSS_CTL_326_DATA 0x00000003
+#define DDRSS_CTL_327_DATA 0x00000000
+#define DDRSS_CTL_328_DATA 0x00010000
+#define DDRSS_CTL_329_DATA 0x00280D00
+#define DDRSS_CTL_330_DATA 0x00000001
+#define DDRSS_CTL_331_DATA 0x00030001
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x01000000
+#define DDRSS_CTL_341_DATA 0x00000001
+#define DDRSS_CTL_342_DATA 0x00010100
+#define DDRSS_CTL_343_DATA 0x03030000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x000556AA
+#define DDRSS_CTL_361_DATA 0x000AAAAA
+#define DDRSS_CTL_362_DATA 0x000AA955
+#define DDRSS_CTL_363_DATA 0x00055555
+#define DDRSS_CTL_364_DATA 0x000B3133
+#define DDRSS_CTL_365_DATA 0x0004CD33
+#define DDRSS_CTL_366_DATA 0x0004CECC
+#define DDRSS_CTL_367_DATA 0x000B32CC
+#define DDRSS_CTL_368_DATA 0x00010300
+#define DDRSS_CTL_369_DATA 0x03000100
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00010000
+#define DDRSS_CTL_378_DATA 0x00000404
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x00000000
+#define DDRSS_CTL_384_DATA 0x00000000
+#define DDRSS_CTL_385_DATA 0x00000000
+#define DDRSS_CTL_386_DATA 0x00000000
+#define DDRSS_CTL_387_DATA 0x33331B00
+#define DDRSS_CTL_388_DATA 0x000A0000
+#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_390_DATA 0x00000200
+#define DDRSS_CTL_391_DATA 0x00000200
+#define DDRSS_CTL_392_DATA 0x00000200
+#define DDRSS_CTL_393_DATA 0x00000200
+#define DDRSS_CTL_394_DATA 0x000004D4
+#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_396_DATA 0x00000204
+#define DDRSS_CTL_397_DATA 0x000030B0
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00009210
+#define DDRSS_CTL_403_DATA 0x0001E6E0
+#define DDRSS_CTL_404_DATA 0x00000A10
+#define DDRSS_CTL_405_DATA 0x000030B0
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00009210
+#define DDRSS_CTL_411_DATA 0x0001E6E0
+#define DDRSS_CTL_412_DATA 0x02020A10
+#define DDRSS_CTL_413_DATA 0x03030202
+#define DDRSS_CTL_414_DATA 0x00000022
+#define DDRSS_CTL_415_DATA 0x00000000
+#define DDRSS_CTL_416_DATA 0x00000000
+#define DDRSS_CTL_417_DATA 0x00001403
+#define DDRSS_CTL_418_DATA 0x000007D0
+#define DDRSS_CTL_419_DATA 0x00000000
+#define DDRSS_CTL_420_DATA 0x00000000
+#define DDRSS_CTL_421_DATA 0x00030000
+#define DDRSS_CTL_422_DATA 0x0007001F
+#define DDRSS_CTL_423_DATA 0x0016002E
+#define DDRSS_CTL_424_DATA 0x0016002E
+#define DDRSS_CTL_425_DATA 0x00000000
+#define DDRSS_CTL_426_DATA 0x00000000
+#define DDRSS_CTL_427_DATA 0x02000000
+#define DDRSS_CTL_428_DATA 0x01000404
+#define DDRSS_CTL_429_DATA 0x07160716
+#define DDRSS_CTL_430_DATA 0x00000105
+#define DDRSS_CTL_431_DATA 0x00010101
+#define DDRSS_CTL_432_DATA 0x00010101
+#define DDRSS_CTL_433_DATA 0x00010001
+#define DDRSS_CTL_434_DATA 0x00000101
+#define DDRSS_CTL_435_DATA 0x02000201
+#define DDRSS_CTL_436_DATA 0x02010000
+#define DDRSS_CTL_437_DATA 0x00000200
+#define DDRSS_CTL_438_DATA 0x1E060000
+#define DDRSS_CTL_439_DATA 0x0000011E
+#define DDRSS_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS_CTL_442_DATA 0x00000000
+#define DDRSS_CTL_443_DATA 0x00000000
+#define DDRSS_CTL_444_DATA 0x00000000
+#define DDRSS_CTL_445_DATA 0x00000000
+#define DDRSS_CTL_446_DATA 0x00000000
+#define DDRSS_CTL_447_DATA 0x00000000
+#define DDRSS_CTL_448_DATA 0x00000000
+#define DDRSS_CTL_449_DATA 0x00000000
+#define DDRSS_CTL_450_DATA 0x00000000
+#define DDRSS_CTL_451_DATA 0x00000000
+#define DDRSS_CTL_452_DATA 0x00000000
+#define DDRSS_CTL_453_DATA 0x00000000
+#define DDRSS_CTL_454_DATA 0x00000000
+#define DDRSS_CTL_455_DATA 0x00000000
+#define DDRSS_CTL_456_DATA 0x00000000
+#define DDRSS_CTL_457_DATA 0x00000000
+#define DDRSS_CTL_458_DATA 0x00000000
+
+#define DDRSS_PI_00_DATA 0x00000B00
+#define DDRSS_PI_01_DATA 0x00000000
+#define DDRSS_PI_02_DATA 0x00000000
+#define DDRSS_PI_03_DATA 0x00000000
+#define DDRSS_PI_04_DATA 0x00000000
+#define DDRSS_PI_05_DATA 0x00000101
+#define DDRSS_PI_06_DATA 0x00640000
+#define DDRSS_PI_07_DATA 0x00000001
+#define DDRSS_PI_08_DATA 0x00000000
+#define DDRSS_PI_09_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_14_DATA 0x0800000F
+#define DDRSS_PI_15_DATA 0x00000103
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010100
+#define DDRSS_PI_27_DATA 0x00280A00
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00003200
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x000F0F00
+#define DDRSS_PI_46_DATA 0x00000019
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x00030000
+#define DDRSS_PI_55_DATA 0x0F000000
+#define DDRSS_PI_56_DATA 0x00000017
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x00020805
+#define DDRSS_PI_63_DATA 0x01000404
+#define DDRSS_PI_64_DATA 0x00000000
+#define DDRSS_PI_65_DATA 0x00000000
+#define DDRSS_PI_66_DATA 0x00000100
+#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_68_DATA 0x00340000
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00080100
+#define DDRSS_PI_74_DATA 0x02000200
+#define DDRSS_PI_75_DATA 0x01000100
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x02000200
+#define DDRSS_PI_78_DATA 0x00000200
+#define DDRSS_PI_79_DATA 0x00000000
+#define DDRSS_PI_80_DATA 0x00000000
+#define DDRSS_PI_81_DATA 0x00000000
+#define DDRSS_PI_82_DATA 0x00000000
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x02010000
+#define DDRSS_PI_93_DATA 0x00080003
+#define DDRSS_PI_94_DATA 0x00080000
+#define DDRSS_PI_95_DATA 0x00000001
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x0000AA00
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x00000000
+#define DDRSS_PI_100_DATA 0x00010000
+#define DDRSS_PI_101_DATA 0x00000000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000008
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000002
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000000
+#define DDRSS_PI_137_DATA 0x0000000A
+#define DDRSS_PI_138_DATA 0x00000019
+#define DDRSS_PI_139_DATA 0x00000100
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00000401
+#define DDRSS_PI_160_DATA 0x00000000
+#define DDRSS_PI_161_DATA 0x00010000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x20200200
+#define DDRSS_PI_164_DATA 0x00000034
+#define DDRSS_PI_165_DATA 0x00000058
+#define DDRSS_PI_166_DATA 0x00020058
+#define DDRSS_PI_167_DATA 0x02000200
+#define DDRSS_PI_168_DATA 0x380E0C04
+#define DDRSS_PI_169_DATA 0x0010380E
+#define DDRSS_PI_170_DATA 0x000000CE
+#define DDRSS_PI_171_DATA 0x000001C0
+#define DDRSS_PI_172_DATA 0x00001858
+#define DDRSS_PI_173_DATA 0x000001C0
+#define DDRSS_PI_174_DATA 0x04001858
+#define DDRSS_PI_175_DATA 0x01010404
+#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_177_DATA 0x00150015
+#define DDRSS_PI_178_DATA 0x01000100
+#define DDRSS_PI_179_DATA 0x00000100
+#define DDRSS_PI_180_DATA 0x00000000
+#define DDRSS_PI_181_DATA 0x01010101
+#define DDRSS_PI_182_DATA 0x00000101
+#define DDRSS_PI_183_DATA 0x00000000
+#define DDRSS_PI_184_DATA 0x00000000
+#define DDRSS_PI_185_DATA 0x10040000
+#define DDRSS_PI_186_DATA 0x0A0A0210
+#define DDRSS_PI_187_DATA 0x00040402
+#define DDRSS_PI_188_DATA 0x000D0035
+#define DDRSS_PI_189_DATA 0x001C0044
+#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_191_DATA 0x01010101
+#define DDRSS_PI_192_DATA 0x0003000E
+#define DDRSS_PI_193_DATA 0x00030190
+#define DDRSS_PI_194_DATA 0x01000190
+#define DDRSS_PI_195_DATA 0x000F000F
+#define DDRSS_PI_196_DATA 0x01910100
+#define DDRSS_PI_197_DATA 0x01000191
+#define DDRSS_PI_198_DATA 0x01910191
+#define DDRSS_PI_199_DATA 0x32103200
+#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_201_DATA 0x0A070601
+#define DDRSS_PI_202_DATA 0x180F090D
+#define DDRSS_PI_203_DATA 0x180F0911
+#define DDRSS_PI_204_DATA 0x0000C011
+#define DDRSS_PI_205_DATA 0x00C01000
+#define DDRSS_PI_206_DATA 0x00C01000
+#define DDRSS_PI_207_DATA 0x00021000
+#define DDRSS_PI_208_DATA 0x001E000E
+#define DDRSS_PI_209_DATA 0x001E0190
+#define DDRSS_PI_210_DATA 0x00110190
+#define DDRSS_PI_211_DATA 0x32000056
+#define DDRSS_PI_212_DATA 0x00000301
+#define DDRSS_PI_213_DATA 0x005A0030
+#define DDRSS_PI_214_DATA 0x03013212
+#define DDRSS_PI_215_DATA 0x00003000
+#define DDRSS_PI_216_DATA 0x3212005A
+#define DDRSS_PI_217_DATA 0x09000301
+#define DDRSS_PI_218_DATA 0x04010504
+#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_220_DATA 0x0A032001
+#define DDRSS_PI_221_DATA 0x21250D0A
+#define DDRSS_PI_222_DATA 0x00002216
+#define DDRSS_PI_223_DATA 0x4800C570
+#define DDRSS_PI_224_DATA 0x17182006
+#define DDRSS_PI_225_DATA 0x21250D10
+#define DDRSS_PI_226_DATA 0x00002216
+#define DDRSS_PI_227_DATA 0x4800C570
+#define DDRSS_PI_228_DATA 0x17182006
+#define DDRSS_PI_229_DATA 0x00019C10
+#define DDRSS_PI_230_DATA 0x00001018
+#define DDRSS_PI_231_DATA 0x000030B0
+#define DDRSS_PI_232_DATA 0x0001E6E0
+#define DDRSS_PI_233_DATA 0x000030B0
+#define DDRSS_PI_234_DATA 0x0001E6E0
+#define DDRSS_PI_235_DATA 0x01CC0010
+#define DDRSS_PI_236_DATA 0x030301CC
+#define DDRSS_PI_237_DATA 0x002AF803
+#define DDRSS_PI_238_DATA 0x0001ADAF
+#define DDRSS_PI_239_DATA 0x00000005
+#define DDRSS_PI_240_DATA 0x0000006E
+#define DDRSS_PI_241_DATA 0x00000010
+#define DDRSS_PI_242_DATA 0x0004E200
+#define DDRSS_PI_243_DATA 0x0001ADAF
+#define DDRSS_PI_244_DATA 0x00000005
+#define DDRSS_PI_245_DATA 0x00000C80
+#define DDRSS_PI_246_DATA 0x000001CC
+#define DDRSS_PI_247_DATA 0x0004E200
+#define DDRSS_PI_248_DATA 0x0001ADAF
+#define DDRSS_PI_249_DATA 0x00000005
+#define DDRSS_PI_250_DATA 0x00000C80
+#define DDRSS_PI_251_DATA 0x010001CC
+#define DDRSS_PI_252_DATA 0x00370040
+#define DDRSS_PI_253_DATA 0x00010008
+#define DDRSS_PI_254_DATA 0x06400040
+#define DDRSS_PI_255_DATA 0x00010030
+#define DDRSS_PI_256_DATA 0x06400040
+#define DDRSS_PI_257_DATA 0x00000330
+#define DDRSS_PI_258_DATA 0x00500050
+#define DDRSS_PI_259_DATA 0x08040404
+#define DDRSS_PI_260_DATA 0x00000055
+#define DDRSS_PI_261_DATA 0x55083C5A
+#define DDRSS_PI_262_DATA 0x5A000000
+#define DDRSS_PI_263_DATA 0x0055083C
+#define DDRSS_PI_264_DATA 0x3C5A0000
+#define DDRSS_PI_265_DATA 0x00005508
+#define DDRSS_PI_266_DATA 0x0C3C5A00
+#define DDRSS_PI_267_DATA 0x080F0E0D
+#define DDRSS_PI_268_DATA 0x000B0A09
+#define DDRSS_PI_269_DATA 0x00030201
+#define DDRSS_PI_270_DATA 0x01000000
+#define DDRSS_PI_271_DATA 0x04020201
+#define DDRSS_PI_272_DATA 0x00080804
+#define DDRSS_PI_273_DATA 0x00000000
+#define DDRSS_PI_274_DATA 0x00000000
+#define DDRSS_PI_275_DATA 0x45AB0084
+#define DDRSS_PI_276_DATA 0x001D0F27
+#define DDRSS_PI_277_DATA 0x45AB2DD4
+#define DDRSS_PI_278_DATA 0x001D0F27
+#define DDRSS_PI_279_DATA 0x45AB2DD4
+#define DDRSS_PI_280_DATA 0x001D0F27
+#define DDRSS_PI_281_DATA 0x45AB0084
+#define DDRSS_PI_282_DATA 0x001D0F27
+#define DDRSS_PI_283_DATA 0x45AB2DD4
+#define DDRSS_PI_284_DATA 0x001D0F27
+#define DDRSS_PI_285_DATA 0x45AB2DD4
+#define DDRSS_PI_286_DATA 0x001D0F27
+#define DDRSS_PI_287_DATA 0x45AB0084
+#define DDRSS_PI_288_DATA 0x001D0F27
+#define DDRSS_PI_289_DATA 0x45AB2DD4
+#define DDRSS_PI_290_DATA 0x001D0F27
+#define DDRSS_PI_291_DATA 0x45AB2DD4
+#define DDRSS_PI_292_DATA 0x001D0F27
+#define DDRSS_PI_293_DATA 0x45AB0084
+#define DDRSS_PI_294_DATA 0x001D0F27
+#define DDRSS_PI_295_DATA 0x45AB2DD4
+#define DDRSS_PI_296_DATA 0x001D0F27
+#define DDRSS_PI_297_DATA 0x45AB2DD4
+#define DDRSS_PI_298_DATA 0x001D0F27
+#define DDRSS_PI_299_DATA 0x00000000
+
+#define DDRSS_PHY_00_DATA 0x000004F0
+#define DDRSS_PHY_01_DATA 0x00000000
+#define DDRSS_PHY_02_DATA 0x00030200
+#define DDRSS_PHY_03_DATA 0x00000000
+#define DDRSS_PHY_04_DATA 0x00000000
+#define DDRSS_PHY_05_DATA 0x01030000
+#define DDRSS_PHY_06_DATA 0x00010000
+#define DDRSS_PHY_07_DATA 0x01030004
+#define DDRSS_PHY_08_DATA 0x01000000
+#define DDRSS_PHY_09_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01000001
+#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_13_DATA 0x000800C0
+#define DDRSS_PHY_14_DATA 0x060100CC
+#define DDRSS_PHY_15_DATA 0x00030066
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000301
+#define DDRSS_PHY_18_DATA 0x0000AAAA
+#define DDRSS_PHY_19_DATA 0x00005555
+#define DDRSS_PHY_20_DATA 0x0000B5B5
+#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_22_DATA 0x00005656
+#define DDRSS_PHY_23_DATA 0x0000A9A9
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B5B5
+#define DDRSS_PHY_26_DATA 0x00000000
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x2A000000
+#define DDRSS_PHY_29_DATA 0x00000808
+#define DDRSS_PHY_30_DATA 0x0F000000
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
+#define DDRSS_PHY_34_DATA 0x00000000
+#define DDRSS_PHY_35_DATA 0x00000000
+#define DDRSS_PHY_36_DATA 0x55555555
+#define DDRSS_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x00005555
+#define DDRSS_PHY_41_DATA 0x01000100
+#define DDRSS_PHY_42_DATA 0x00800180
+#define DDRSS_PHY_43_DATA 0x00000001
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000104
+#define DDRSS_PHY_67_DATA 0x00000120
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x00000000
+#define DDRSS_PHY_75_DATA 0x00000001
+#define DDRSS_PHY_76_DATA 0x07FF0000
+#define DDRSS_PHY_77_DATA 0x0080081F
+#define DDRSS_PHY_78_DATA 0x00081020
+#define DDRSS_PHY_79_DATA 0x04010000
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00000000
+#define DDRSS_PHY_83_DATA 0x00000100
+#define DDRSS_PHY_84_DATA 0x01BB0B01
+#define DDRSS_PHY_85_DATA 0x1003BB0B
+#define DDRSS_PHY_86_DATA 0x20000140
+#define DDRSS_PHY_87_DATA 0x07FF0200
+#define DDRSS_PHY_88_DATA 0x0000DD01
+#define DDRSS_PHY_89_DATA 0x10100303
+#define DDRSS_PHY_90_DATA 0x10101010
+#define DDRSS_PHY_91_DATA 0x10101010
+#define DDRSS_PHY_92_DATA 0x00021010
+#define DDRSS_PHY_93_DATA 0x00100010
+#define DDRSS_PHY_94_DATA 0x00100010
+#define DDRSS_PHY_95_DATA 0x00100010
+#define DDRSS_PHY_96_DATA 0x00100010
+#define DDRSS_PHY_97_DATA 0x00050010
+#define DDRSS_PHY_98_DATA 0x51517041
+#define DDRSS_PHY_99_DATA 0x31C06000
+#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_101_DATA 0x00C0C001
+#define DDRSS_PHY_102_DATA 0x0B0A0001
+#define DDRSS_PHY_103_DATA 0x10001000
+#define DDRSS_PHY_104_DATA 0x0C073E42
+#define DDRSS_PHY_105_DATA 0x0F0C2D01
+#define DDRSS_PHY_106_DATA 0x01000140
+#define DDRSS_PHY_107_DATA 0x0C000420
+#define DDRSS_PHY_108_DATA 0x00000198
+#define DDRSS_PHY_109_DATA 0x0A0000D0
+#define DDRSS_PHY_110_DATA 0x00030200
+#define DDRSS_PHY_111_DATA 0x02800000
+#define DDRSS_PHY_112_DATA 0x80800000
+#define DDRSS_PHY_113_DATA 0x000B2010
+#define DDRSS_PHY_114_DATA 0x76543210
+#define DDRSS_PHY_115_DATA 0x00000008
+#define DDRSS_PHY_116_DATA 0x02800280
+#define DDRSS_PHY_117_DATA 0x02800280
+#define DDRSS_PHY_118_DATA 0x02800280
+#define DDRSS_PHY_119_DATA 0x02800280
+#define DDRSS_PHY_120_DATA 0x00000280
+#define DDRSS_PHY_121_DATA 0x0000A000
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00A000A0
+#define DDRSS_PHY_128_DATA 0x00A000A0
+#define DDRSS_PHY_129_DATA 0x00A000A0
+#define DDRSS_PHY_130_DATA 0x011900A0
+#define DDRSS_PHY_131_DATA 0x01A00004
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00080200
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x20202000
+#define DDRSS_PHY_137_DATA 0x20202020
+#define DDRSS_PHY_138_DATA 0xF0F02020
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x000004F0
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01000001
+#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_269_DATA 0x000800C0
+#define DDRSS_PHY_270_DATA 0x060100CC
+#define DDRSS_PHY_271_DATA 0x00030066
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000301
+#define DDRSS_PHY_274_DATA 0x0000AAAA
+#define DDRSS_PHY_275_DATA 0x00005555
+#define DDRSS_PHY_276_DATA 0x0000B5B5
+#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_278_DATA 0x00005656
+#define DDRSS_PHY_279_DATA 0x0000A9A9
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B5B5
+#define DDRSS_PHY_282_DATA 0x00000000
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x2A000000
+#define DDRSS_PHY_285_DATA 0x00000808
+#define DDRSS_PHY_286_DATA 0x0F000000
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
+#define DDRSS_PHY_290_DATA 0x00000000
+#define DDRSS_PHY_291_DATA 0x00000000
+#define DDRSS_PHY_292_DATA 0x55555555
+#define DDRSS_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x00005555
+#define DDRSS_PHY_297_DATA 0x01000100
+#define DDRSS_PHY_298_DATA 0x00800180
+#define DDRSS_PHY_299_DATA 0x00000000
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000104
+#define DDRSS_PHY_323_DATA 0x00000120
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x00000000
+#define DDRSS_PHY_331_DATA 0x00000001
+#define DDRSS_PHY_332_DATA 0x07FF0000
+#define DDRSS_PHY_333_DATA 0x0080081F
+#define DDRSS_PHY_334_DATA 0x00081020
+#define DDRSS_PHY_335_DATA 0x04010000
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00000000
+#define DDRSS_PHY_339_DATA 0x00000100
+#define DDRSS_PHY_340_DATA 0x01BB0B01
+#define DDRSS_PHY_341_DATA 0x1003BB0B
+#define DDRSS_PHY_342_DATA 0x20000140
+#define DDRSS_PHY_343_DATA 0x07FF0200
+#define DDRSS_PHY_344_DATA 0x0000DD01
+#define DDRSS_PHY_345_DATA 0x10100303
+#define DDRSS_PHY_346_DATA 0x10101010
+#define DDRSS_PHY_347_DATA 0x10101010
+#define DDRSS_PHY_348_DATA 0x00021010
+#define DDRSS_PHY_349_DATA 0x00100010
+#define DDRSS_PHY_350_DATA 0x00100010
+#define DDRSS_PHY_351_DATA 0x00100010
+#define DDRSS_PHY_352_DATA 0x00100010
+#define DDRSS_PHY_353_DATA 0x00050010
+#define DDRSS_PHY_354_DATA 0x51517041
+#define DDRSS_PHY_355_DATA 0x31C06000
+#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_357_DATA 0x00C0C001
+#define DDRSS_PHY_358_DATA 0x0B0A0001
+#define DDRSS_PHY_359_DATA 0x10001000
+#define DDRSS_PHY_360_DATA 0x0C073E42
+#define DDRSS_PHY_361_DATA 0x0F0C2D01
+#define DDRSS_PHY_362_DATA 0x01000140
+#define DDRSS_PHY_363_DATA 0x0C000420
+#define DDRSS_PHY_364_DATA 0x00000198
+#define DDRSS_PHY_365_DATA 0x0A0000D0
+#define DDRSS_PHY_366_DATA 0x00030200
+#define DDRSS_PHY_367_DATA 0x02800000
+#define DDRSS_PHY_368_DATA 0x80800000
+#define DDRSS_PHY_369_DATA 0x000B2010
+#define DDRSS_PHY_370_DATA 0x76543210
+#define DDRSS_PHY_371_DATA 0x00000008
+#define DDRSS_PHY_372_DATA 0x02800280
+#define DDRSS_PHY_373_DATA 0x02800280
+#define DDRSS_PHY_374_DATA 0x02800280
+#define DDRSS_PHY_375_DATA 0x02800280
+#define DDRSS_PHY_376_DATA 0x00000280
+#define DDRSS_PHY_377_DATA 0x0000A000
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00A000A0
+#define DDRSS_PHY_384_DATA 0x00A000A0
+#define DDRSS_PHY_385_DATA 0x00A000A0
+#define DDRSS_PHY_386_DATA 0x011900A0
+#define DDRSS_PHY_387_DATA 0x01A00004
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00080200
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x20202000
+#define DDRSS_PHY_393_DATA 0x20202020
+#define DDRSS_PHY_394_DATA 0xF0F02020
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x000004F0
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x01000001
+#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_525_DATA 0x000800C0
+#define DDRSS_PHY_526_DATA 0x060100CC
+#define DDRSS_PHY_527_DATA 0x00030066
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000301
+#define DDRSS_PHY_530_DATA 0x0000AAAA
+#define DDRSS_PHY_531_DATA 0x00005555
+#define DDRSS_PHY_532_DATA 0x0000B5B5
+#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_534_DATA 0x00005656
+#define DDRSS_PHY_535_DATA 0x0000A9A9
+#define DDRSS_PHY_536_DATA 0x0000A9A9
+#define DDRSS_PHY_537_DATA 0x0000B5B5
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x2A000000
+#define DDRSS_PHY_541_DATA 0x00000808
+#define DDRSS_PHY_542_DATA 0x0F000000
+#define DDRSS_PHY_543_DATA 0x00000F0F
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
+#define DDRSS_PHY_546_DATA 0x00000000
+#define DDRSS_PHY_547_DATA 0x00000000
+#define DDRSS_PHY_548_DATA 0x55555555
+#define DDRSS_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x00005555
+#define DDRSS_PHY_553_DATA 0x01000100
+#define DDRSS_PHY_554_DATA 0x00800180
+#define DDRSS_PHY_555_DATA 0x00000001
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000104
+#define DDRSS_PHY_579_DATA 0x00000120
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000001
+#define DDRSS_PHY_588_DATA 0x07FF0000
+#define DDRSS_PHY_589_DATA 0x0080081F
+#define DDRSS_PHY_590_DATA 0x00081020
+#define DDRSS_PHY_591_DATA 0x04010000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000100
+#define DDRSS_PHY_596_DATA 0x01BB0B01
+#define DDRSS_PHY_597_DATA 0x1003BB0B
+#define DDRSS_PHY_598_DATA 0x20000140
+#define DDRSS_PHY_599_DATA 0x07FF0200
+#define DDRSS_PHY_600_DATA 0x0000DD01
+#define DDRSS_PHY_601_DATA 0x10100303
+#define DDRSS_PHY_602_DATA 0x10101010
+#define DDRSS_PHY_603_DATA 0x10101010
+#define DDRSS_PHY_604_DATA 0x00021010
+#define DDRSS_PHY_605_DATA 0x00100010
+#define DDRSS_PHY_606_DATA 0x00100010
+#define DDRSS_PHY_607_DATA 0x00100010
+#define DDRSS_PHY_608_DATA 0x00100010
+#define DDRSS_PHY_609_DATA 0x00050010
+#define DDRSS_PHY_610_DATA 0x51517041
+#define DDRSS_PHY_611_DATA 0x31C06000
+#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_613_DATA 0x00C0C001
+#define DDRSS_PHY_614_DATA 0x0B0A0001
+#define DDRSS_PHY_615_DATA 0x10001000
+#define DDRSS_PHY_616_DATA 0x0C073E42
+#define DDRSS_PHY_617_DATA 0x0F0C2D01
+#define DDRSS_PHY_618_DATA 0x01000140
+#define DDRSS_PHY_619_DATA 0x0C000420
+#define DDRSS_PHY_620_DATA 0x00000198
+#define DDRSS_PHY_621_DATA 0x0A0000D0
+#define DDRSS_PHY_622_DATA 0x00030200
+#define DDRSS_PHY_623_DATA 0x02800000
+#define DDRSS_PHY_624_DATA 0x80800000
+#define DDRSS_PHY_625_DATA 0x000B2010
+#define DDRSS_PHY_626_DATA 0x76543210
+#define DDRSS_PHY_627_DATA 0x00000008
+#define DDRSS_PHY_628_DATA 0x02800280
+#define DDRSS_PHY_629_DATA 0x02800280
+#define DDRSS_PHY_630_DATA 0x02800280
+#define DDRSS_PHY_631_DATA 0x02800280
+#define DDRSS_PHY_632_DATA 0x00000280
+#define DDRSS_PHY_633_DATA 0x0000A000
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00A000A0
+#define DDRSS_PHY_640_DATA 0x00A000A0
+#define DDRSS_PHY_641_DATA 0x00A000A0
+#define DDRSS_PHY_642_DATA 0x011900A0
+#define DDRSS_PHY_643_DATA 0x01A00004
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00080200
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x20202000
+#define DDRSS_PHY_649_DATA 0x20202020
+#define DDRSS_PHY_650_DATA 0xF0F02020
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x000004F0
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x01000001
+#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_781_DATA 0x000800C0
+#define DDRSS_PHY_782_DATA 0x060100CC
+#define DDRSS_PHY_783_DATA 0x00030066
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000301
+#define DDRSS_PHY_786_DATA 0x0000AAAA
+#define DDRSS_PHY_787_DATA 0x00005555
+#define DDRSS_PHY_788_DATA 0x0000B5B5
+#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_790_DATA 0x00005656
+#define DDRSS_PHY_791_DATA 0x0000A9A9
+#define DDRSS_PHY_792_DATA 0x0000A9A9
+#define DDRSS_PHY_793_DATA 0x0000B5B5
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x2A000000
+#define DDRSS_PHY_797_DATA 0x00000808
+#define DDRSS_PHY_798_DATA 0x0F000000
+#define DDRSS_PHY_799_DATA 0x00000F0F
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
+#define DDRSS_PHY_802_DATA 0x00000000
+#define DDRSS_PHY_803_DATA 0x00000000
+#define DDRSS_PHY_804_DATA 0x55555555
+#define DDRSS_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x00005555
+#define DDRSS_PHY_809_DATA 0x01000100
+#define DDRSS_PHY_810_DATA 0x00800180
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000104
+#define DDRSS_PHY_835_DATA 0x00000120
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000001
+#define DDRSS_PHY_844_DATA 0x07FF0000
+#define DDRSS_PHY_845_DATA 0x0080081F
+#define DDRSS_PHY_846_DATA 0x00081020
+#define DDRSS_PHY_847_DATA 0x04010000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000100
+#define DDRSS_PHY_852_DATA 0x01BB0B01
+#define DDRSS_PHY_853_DATA 0x1003BB0B
+#define DDRSS_PHY_854_DATA 0x20000140
+#define DDRSS_PHY_855_DATA 0x07FF0200
+#define DDRSS_PHY_856_DATA 0x0000DD01
+#define DDRSS_PHY_857_DATA 0x10100303
+#define DDRSS_PHY_858_DATA 0x10101010
+#define DDRSS_PHY_859_DATA 0x10101010
+#define DDRSS_PHY_860_DATA 0x00021010
+#define DDRSS_PHY_861_DATA 0x00100010
+#define DDRSS_PHY_862_DATA 0x00100010
+#define DDRSS_PHY_863_DATA 0x00100010
+#define DDRSS_PHY_864_DATA 0x00100010
+#define DDRSS_PHY_865_DATA 0x00050010
+#define DDRSS_PHY_866_DATA 0x51517041
+#define DDRSS_PHY_867_DATA 0x31C06000
+#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_869_DATA 0x00C0C001
+#define DDRSS_PHY_870_DATA 0x0B0A0001
+#define DDRSS_PHY_871_DATA 0x10001000
+#define DDRSS_PHY_872_DATA 0x0C073E42
+#define DDRSS_PHY_873_DATA 0x0F0C2D01
+#define DDRSS_PHY_874_DATA 0x01000140
+#define DDRSS_PHY_875_DATA 0x0C000420
+#define DDRSS_PHY_876_DATA 0x00000198
+#define DDRSS_PHY_877_DATA 0x0A0000D0
+#define DDRSS_PHY_878_DATA 0x00030200
+#define DDRSS_PHY_879_DATA 0x02800000
+#define DDRSS_PHY_880_DATA 0x80800000
+#define DDRSS_PHY_881_DATA 0x000B2010
+#define DDRSS_PHY_882_DATA 0x76543210
+#define DDRSS_PHY_883_DATA 0x00000008
+#define DDRSS_PHY_884_DATA 0x02800280
+#define DDRSS_PHY_885_DATA 0x02800280
+#define DDRSS_PHY_886_DATA 0x02800280
+#define DDRSS_PHY_887_DATA 0x02800280
+#define DDRSS_PHY_888_DATA 0x00000280
+#define DDRSS_PHY_889_DATA 0x0000A000
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00A000A0
+#define DDRSS_PHY_896_DATA 0x00A000A0
+#define DDRSS_PHY_897_DATA 0x00A000A0
+#define DDRSS_PHY_898_DATA 0x011900A0
+#define DDRSS_PHY_899_DATA 0x01A00004
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00080200
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x20202000
+#define DDRSS_PHY_905_DATA 0x20202020
+#define DDRSS_PHY_906_DATA 0xF0F02020
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x00543210
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x00000000
+#define DDRSS_PHY_1062_DATA 0x00000000
+#define DDRSS_PHY_1063_DATA 0x00000000
+#define DDRSS_PHY_1064_DATA 0x000305FF
+#define DDRSS_PHY_1065_DATA 0x00030000
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x00000300
+#define DDRSS_PHY_1069_DATA 0x00000300
+#define DDRSS_PHY_1070_DATA 0x00000300
+#define DDRSS_PHY_1071_DATA 0x42080010
+#define DDRSS_PHY_1072_DATA 0x0000803E
+#define DDRSS_PHY_1073_DATA 0x00000001
+#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1075_DATA 0x00008000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00050000
+#define DDRSS_PHY_1285_DATA 0x04000000
+#define DDRSS_PHY_1286_DATA 0x00000055
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00002001
+#define DDRSS_PHY_1292_DATA 0x0000400F
+#define DDRSS_PHY_1293_DATA 0x50020028
+#define DDRSS_PHY_1294_DATA 0x01010000
+#define DDRSS_PHY_1295_DATA 0x80080001
+#define DDRSS_PHY_1296_DATA 0x10200000
+#define DDRSS_PHY_1297_DATA 0x00000008
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x01090E00
+#define DDRSS_PHY_1300_DATA 0x00040101
+#define DDRSS_PHY_1301_DATA 0x0000010F
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1304_DATA 0x00000000
+#define DDRSS_PHY_1305_DATA 0x01010000
+#define DDRSS_PHY_1306_DATA 0x01080402
+#define DDRSS_PHY_1307_DATA 0x01200F02
+#define DDRSS_PHY_1308_DATA 0x00194280
+#define DDRSS_PHY_1309_DATA 0x00000004
+#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1311_DATA 0x00000000
+#define DDRSS_PHY_1312_DATA 0x00000000
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x01000000
+#define DDRSS_PHY_1318_DATA 0x00000705
+#define DDRSS_PHY_1319_DATA 0x00000054
+#define DDRSS_PHY_1320_DATA 0x00030820
+#define DDRSS_PHY_1321_DATA 0x00010820
+#define DDRSS_PHY_1322_DATA 0x00010820
+#define DDRSS_PHY_1323_DATA 0x00010820
+#define DDRSS_PHY_1324_DATA 0x00010820
+#define DDRSS_PHY_1325_DATA 0x00010820
+#define DDRSS_PHY_1326_DATA 0x00010820
+#define DDRSS_PHY_1327_DATA 0x00010820
+#define DDRSS_PHY_1328_DATA 0x00010820
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000074
+#define DDRSS_PHY_1331_DATA 0x00000400
+#define DDRSS_PHY_1332_DATA 0x00000108
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x03000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x04102006
+#define DDRSS_PHY_1343_DATA 0x00041020
+#define DDRSS_PHY_1344_DATA 0x01C98C98
+#define DDRSS_PHY_1345_DATA 0x3F400000
+#define DDRSS_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1347_DATA 0x0000001F
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00010000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x76543210
+#define DDRSS_PHY_1357_DATA 0x00010198
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00040700
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000002
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00080000
+#define DDRSS_PHY_1375_DATA 0x000007FF
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x000FFFFF
+#define DDRSS_PHY_1383_DATA 0x000FFFFF
+#define DDRSS_PHY_1384_DATA 0x0000FFFF
+#define DDRSS_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS_PHY_1386_DATA 0x030FFFFF
+#define DDRSS_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS_PHY_1388_DATA 0x0000FFFF
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x0001F7C0
+#define DDRSS_PHY_1394_DATA 0x00000003
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00001142
+#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1398_DATA 0x01000080
+#define DDRSS_PHY_1399_DATA 0x03900390
+#define DDRSS_PHY_1400_DATA 0x03900390
+#define DDRSS_PHY_1401_DATA 0x00000390
+#define DDRSS_PHY_1402_DATA 0x00000390
+#define DDRSS_PHY_1403_DATA 0x00000390
+#define DDRSS_PHY_1404_DATA 0x00000390
+#define DDRSS_PHY_1405_DATA 0x00000005
+#define DDRSS_PHY_1406_DATA 0x01813FFF
+#define DDRSS_PHY_1407_DATA 0x000000FF
+#define DDRSS_PHY_1408_DATA 0x0C000DFF
+#define DDRSS_PHY_1409_DATA 0x30000DFF
+#define DDRSS_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS_PHY_1411_DATA 0x000100F0
+#define DDRSS_PHY_1412_DATA 0x780DFFFF
+#define DDRSS_PHY_1413_DATA 0x00007E31
+#define DDRSS_PHY_1414_DATA 0x000CBF11
+#define DDRSS_PHY_1415_DATA 0x01FF0010
+#define DDRSS_PHY_1416_DATA 0x000CBF11
+#define DDRSS_PHY_1417_DATA 0x01FF0010
+#define DDRSS_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS_PHY_1419_DATA 0x01FF00F0
+#define DDRSS_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS_PHY_1421_DATA 0x01FF00F0
+#define DDRSS_PHY_1422_DATA 0x20040006
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-j721e-beagleboneai64.dts"
+#include "k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi"
+#include "k3-j721e-ddr.dtsi"
+
+#include "k3-j721e-beagleboneai64-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clock-rates = <2000000000>, <200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_mcu 6>,
+ <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 5>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&mcu_timer0 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
+ bootph-pre-ram;
+ };
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+&wkup_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+ bootph-pre-ram;
+};
+
+&binman {
+ tiboot3-j721e-gp-evm.bin {
+ filename = "tiboot3-j721e-gp-evm.bin";
+ symlink = "tiboot3.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>;
+ core = "public";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ };
+
+ sysfw_gp {
+ filename = "sysfw.bin_gp";
+ ti-secure-rom {
+ content = <&ti_fs>;
+ core = "secure";
+ load = <0x40000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ ti_fs: ti-fs.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ itb_gp {
+ filename = "sysfw-j721e-gp-evm.itb";
+ symlink = "sysfw.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_gp";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "board-cfg.bin";
+ };
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "pm-cfg.bin";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "rm-cfg.bin";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sec-cfg.bin";
+ };
+ };
+ };
+ };
+ };
+};
#ifdef CONFIG_TARGET_J721S2_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721S2_EVM_DTB "u-boot.dtb"
#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
+ auth-in-place = <0xa02>;
+
+ firewall-257-0 {
+ /* cpu_0_cpu_0_msmc Background Firewall */
+ insert-template = <&firewall_bg_1>;
+ id = <257>;
+ region = <0>;
+ };
+
+ firewall-257-1 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <257>;
+ region = <1>;
+ };
+
+ firewall-284-0 {
+ /* dru_0_msmc Background Firewall */
+ insert-template = <&firewall_bg_3>;
+ id = <284>;
+ region = <0>;
+ };
+
+ firewall-284-1 {
+ /* dru_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <284>;
+ region = <1>;
+ };
+
+ /* firewall-5140-0 {
+ * nb_slv0__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-5140-1 {
+ /* nb_slv0__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <5140>;
+ region = <1>;
+ };
+
+ /* firewall-5140-0 {
+ * nb_slv1__mem0 Background Firewall
+ * Already configured by the secure entity
+ * };
+ */
+
+ firewall-5141-1 {
+ /* nb_slv1__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_atf_fg>;
+ id = <5141>;
+ region = <1>;
+ };
+
};
};
tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
+ auth-in-place = <0xa02>;
+
+ firewall-257-2 {
+ /* cpu_0_cpu_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <257>;
+ region = <2>;
+ };
+
+ firewall-284-2 {
+ /* dru_0_msmc Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <284>;
+ region = <2>;
+ };
+
+ firewall-5142-0 {
+ /* nb_slv2__mem0 Background Firewall - 0 */
+ insert-template = <&firewall_bg_3>;
+ id = <5142>;
+ region = <0>;
+ };
+
+ firewall-5142-1 {
+ /* nb_slv2__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <5142>;
+ region = <1>;
+ };
+
+ firewall-5143-0 {
+ /* nb_slv3__mem0 Background Firewall - 0 */
+ insert-template = <&firewall_bg_3>;
+ id = <5143>;
+ region = <0>;
+ };
+
+ firewall-5143-1 {
+ /* nb_slv3__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <5143>;
+ region = <1>;
+ };
+
+ firewall-5144-0 {
+ /* nb_slv4__mem0 Background Firewall - 0 */
+ insert-template = <&firewall_bg_3>;
+ id = <5144>;
+ region = <0>;
+ };
+
+ firewall-5144-1 {
+ /* nb_slv4__mem0 Foreground Firewall */
+ insert-template = <&firewall_armv8_optee_fg>;
+ id = <5144>;
+ region = <1>;
+ };
+
};
};
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
+ dm: ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J721S2 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721S2 Board";
};
fdt-0 {
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
- blob-ext {
+ ti-dm {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J721S2 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721S2 Board";
};
fdt-0 {
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
+ main_bcdma_csi: dma-controller@311a0000 {
+ compatible = "ti,j721s2-dmss-bcdma-csi";
+ reg = <0x00 0x311a0000 0x00 0x100>,
+ <0x00 0x35d00000 0x00 0x20000>,
+ <0x00 0x35c00000 0x00 0x10000>,
+ <0x00 0x35e00000 0x00 0x80000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <3>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <225>;
+ ti,sci-rm-range-rchan = <0x21>;
+ ti,sci-rm-range-tchan = <0x22>;
+ status = "disabled";
+ };
+
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
dss_ports: ports {
};
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5c00000 0x00010000>,
+ <0x5c10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <279>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 279 1>;
+ firmware-name = "j721s2-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5d00000 0x00010000>,
+ <0x5d10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <280>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 280 1>;
+ firmware-name = "j721s2-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@5e00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+ <0x5f00000 0x00 0x5f00000 0x20000>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@5e00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5e00000 0x00010000>,
+ <0x5e10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <281>;
+ ti,sci-proc-ids = <0x08 0xff>;
+ resets = <&k3_reset 281 1>;
+ firmware-name = "j721s2-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@5f00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5f00000 0x00010000>,
+ <0x5f10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <282>;
+ ti,sci-proc-ids = <0x09 0xff>;
+ resets = <&k3_reset 282 1>;
+ firmware-name = "j721s2-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <8>;
+ ti,sci-proc-ids = <0x30 0xff>;
+ resets = <&k3_reset 8 1>;
+ firmware-name = "j721s2-c71_0-fw";
+ status = "disabled";
+ };
+
+ c71_1: dsp@65800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x65800000 0x00 0x00080000>,
+ <0x00 0x65e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <11>;
+ ti,sci-proc-ids = <0x31 0xff>;
+ resets = <&k3_reset 11 1>;
+ firmware-name = "j721s2-c71_1-fw";
+ status = "disabled";
+ };
+
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x700000 0x00 0x1000>;
+ ti,esm-pins = <688>, <689>;
+ bootph-pre-ram;
+ };
+
+ watchdog0: watchdog@2200000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2200000 0x00 0x100>;
+ clocks = <&k3_clks 286 1>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 286 1>;
+ assigned-clock-parents = <&k3_clks 286 5>;
+ };
+
+ watchdog1: watchdog@2210000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2210000 0x00 0x100>;
+ clocks = <&k3_clks 287 1>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 287 1>;
+ assigned-clock-parents = <&k3_clks 287 5>;
+ };
+
+ /*
+ * The following RTI instances are coupled with MCU R5Fs, c7x and
+ * GPU so keeping them reserved as these will be used by their
+ * respective firmware
+ */
+ watchdog2: watchdog@22f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x22f0000 0x00 0x100>;
+ clocks = <&k3_clks 290 1>;
+ power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 290 1>;
+ assigned-clock-parents = <&k3_clks 290 5>;
+ /* reserved for GPU */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@2300000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2300000 0x00 0x100>;
+ clocks = <&k3_clks 288 1>;
+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 288 1>;
+ assigned-clock-parents = <&k3_clks 288 5>;
+ /* reserved for C7X_0 */
+ status = "reserved";
+ };
+
+ watchdog4: watchdog@2310000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2310000 0x00 0x100>;
+ clocks = <&k3_clks 289 1>;
+ power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 289 1>;
+ assigned-clock-parents = <&k3_clks 289 5>;
+ /* reserved for C7X_1 */
+ status = "reserved";
+ };
+
+ watchdog5: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 291 1>;
+ power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 291 1>;
+ assigned-clock-parents = <&k3_clks 291 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog6: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 292 1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 292 1>;
+ assigned-clock-parents = <&k3_clks 292 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
+ watchdog7: watchdog@23e0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23e0000 0x00 0x100>;
+ clocks = <&k3_clks 293 1>;
+ power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 293 1>;
+ assigned-clock-parents = <&k3_clks 293 5>;
+ /* reserved for MAIN_R5F1_0 */
+ status = "reserved";
+ };
+
+ watchdog8: watchdog@23f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23f0000 0x00 0x100>;
+ clocks = <&k3_clks 294 1>;
+ power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 294 1>;
+ assigned-clock-parents = <&k3_clks 294 5>;
+ /* reserved for MAIN_R5F1_1 */
+ status = "reserved";
+ };
};
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41000000 0x00010000>,
+ <0x41010000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <284>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 284 1>;
+ firmware-name = "j721s2-mcu-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41400000 0x00010000>,
+ <0x41410000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <285>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 285 1>;
+ firmware-name = "j721s2-mcu-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
+
+ wkup_esm: esm@42080000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x42080000 0x00 0x1000>;
+ ti,esm-pins = <63>;
+ bootph-pre-ram;
+ };
+
+ /*
+ * The 2 RTI instances are couple with MCU R5Fs so keeping them
+ * reserved as these will be used by their respective firmware
+ */
+ mcu_watchdog0: watchdog@40600000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40600000 0x00 0x100>;
+ clocks = <&k3_clks 295 1>;
+ power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 295 1>;
+ assigned-clock-parents = <&k3_clks 295 5>;
+ /* reserved for MCU_R5F0_0 */
+ status = "reserved";
+ };
+
+ mcu_watchdog1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40610000 0x00 0x100>;
+ clocks = <&k3_clks 296 1>;
+ power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 296 1>;
+ assigned-clock-parents = <&k3_clks 296 5>;
+ /* reserved for MCU_R5F0_1 */
+ status = "reserved";
+ };
};
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_1_memory_region: c71-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a8000000 {
+ reg = <0x00 0xa8000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
mux0: mux-controller {
cdns,read-delay = <4>;
};
};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c71_1: mbox-c71-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+&c71_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ memory-region = <&c71_1_dma_memory_region>,
+ <&c71_1_memory_region>;
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef DTS_ARM64_TI_K3_FIREWALL_H
+#define DTS_ARM64_TI_K3_FIREWALL_H
+
+#define FWPRIVID_ALL 0xc3
+#define FWPRIVID_ARMV8 1
+#define FWPRIVID_SHIFT 16
+
+#define FWCTRL_EN 0xA
+#define FWCTRL_LOCK (1 << 4)
+#define FWCTRL_BG (1 << 8)
+#define FWCTRL_CACHE (1 << 9)
+
+#define FWPERM_SECURE_PRIV_WRITE (1 << 0)
+#define FWPERM_SECURE_PRIV_READ (1 << 1)
+#define FWPERM_SECURE_PRIV_CACHEABLE (1 << 2)
+#define FWPERM_SECURE_PRIV_DEBUG (1 << 3)
+
+#define FWPERM_SECURE_PRIV_RWCD (FWPERM_SECURE_PRIV_READ | \
+ FWPERM_SECURE_PRIV_WRITE | \
+ FWPERM_SECURE_PRIV_CACHEABLE | \
+ FWPERM_SECURE_PRIV_DEBUG)
+
+#define FWPERM_SECURE_USER_WRITE (1 << 4)
+#define FWPERM_SECURE_USER_READ (1 << 5)
+#define FWPERM_SECURE_USER_CACHEABLE (1 << 6)
+#define FWPERM_SECURE_USER_DEBUG (1 << 7)
+
+#define FWPERM_SECURE_USER_RWCD (FWPERM_SECURE_USER_READ | \
+ FWPERM_SECURE_USER_WRITE | \
+ FWPERM_SECURE_USER_CACHEABLE | \
+ FWPERM_SECURE_USER_DEBUG)
+
+#define FWPERM_NON_SECURE_PRIV_WRITE (1 << 8)
+#define FWPERM_NON_SECURE_PRIV_READ (1 << 9)
+#define FWPERM_NON_SECURE_PRIV_CACHEABLE (1 << 10)
+#define FWPERM_NON_SECURE_PRIV_DEBUG (1 << 11)
+
+#define FWPERM_NON_SECURE_PRIV_RWCD (FWPERM_NON_SECURE_PRIV_READ | \
+ FWPERM_NON_SECURE_PRIV_WRITE | \
+ FWPERM_NON_SECURE_PRIV_CACHEABLE | \
+ FWPERM_NON_SECURE_PRIV_DEBUG)
+
+#define FWPERM_NON_SECURE_USER_WRITE (1 << 12)
+#define FWPERM_NON_SECURE_USER_READ (1 << 13)
+#define FWPERM_NON_SECURE_USER_CACHEABLE (1 << 14)
+#define FWPERM_NON_SECURE_USER_DEBUG (1 << 15)
+
+#define FWPERM_NON_SECURE_USER_RWCD (FWPERM_NON_SECURE_USER_READ | \
+ FWPERM_NON_SECURE_USER_WRITE | \
+ FWPERM_NON_SECURE_USER_CACHEABLE | \
+ FWPERM_NON_SECURE_USER_DEBUG)
+
+#endif
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
- update-button {
+ button-update {
label = "update";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1300000>;
pinctrl-names = "default";
status = "okay";
- gd25lq128: spi-flash@0 {
+ gd25lq128: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
no-map;
};
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
reusable;
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
reg = <0x14 0x10>;
};
- eth_mac: eth_mac@34 {
+ eth_mac: eth-mac@34 {
reg = <0x34 0x10>;
};
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
- scpi_dvfs: scpi_clocks@0 {
+ scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
- reg = <0x0 0x0 0x0 0x100>;
+ reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
- hwrng: rng {
+ hwrng: rng@0 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x800>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x72000 0x0 0x800>;
- interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x74000 0x0 0x800>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
/* Bluetooth on AP6212 */
&uart_A {
- status = "disabled";
+ status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&wifi_32k>;
+ clock-names = "lpo";
+ vbat-supply = <&vddio_ao3v3>;
+ vddio-supply = <&vddio_ao18>;
+ host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ };
};
/* 40-pin CON1 */
};
};
-&gpio_ao {
- /*
- * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- hog-0 {
- gpio-hog;
- gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
};
&usb1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ hub@1 {
+ /* Genesys Logic GL852G USB 2.0 hub */
+ compatible = "usb5e3,610";
+ reg = <1>;
+ vdd-supply = <&p5v0>;
+ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ };
};
};
&gpio_intc {
- compatible = "amlogic,meson-gpio-intc",
- "amlogic,meson-gxbb-gpio-intc";
+ compatible = "amlogic,meson-gxbb-gpio-intc",
+ "amlogic,meson-gpio-intc";
status = "okay";
};
};
};
+ spi_idle_high_pins: spi-idle-high-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-up;
+ };
+ };
+
+ spi_idle_low_pins: spi-idle-low-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-down;
+ };
+ };
+
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
- w25q32: spi-flash@0 {
+ w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
};
&efuse {
- bt_mac: bt_mac@6 {
+ bt_mac: bt-mac@6 {
reg = <0x6 0x6>;
};
- wifi_mac: wifi_mac@C {
+ wifi_mac: wifi-mac@c {
reg = <0xc 0x6>;
};
};
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
+
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
};
&uart_C {
pinctrl-names = "default";
pinctrl-0 = <&i2c_b_pins>;
- pcf8563: pcf8563@51 {
+ pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
};
&sd_emmc_a {
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&uart_A {
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
+ max-frequency = <100000000>;
};
/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
- nor_4u1: spi-flash@0 {
+ nor_4u1: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
};
&usb2_phy0 {
- pinctrl-names = "default";
phy-supply = <&vcc5v>;
};
/dts-v1/;
#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905X) P212 Development Board";
+ dio2133: analog-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "AU2";
+ VCC-supply = <&hdmi_5v>;
+ enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ };
+
cvbs-connector {
compatible = "composite-video-connector";
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "S905X-P212";
+ audio-aux-devs = <&dio2133>;
+ audio-widgets = "Line", "Lineout";
+ audio-routing = "AU2 INL", "ACODEC LOLN",
+ "AU2 INR", "ACODEC LORN",
+ "Lineout", "AU2 OUTL",
+ "Lineout", "AU2 OUTR";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+
+ codec-1 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddio_ao18>;
+ status = "okay";
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
};
/* SD card */
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
/* This is connected to the Bluetooth module: */
&uart_A {
status = "okay";
};
&gpio_intc {
- compatible = "amlogic,meson-gpio-intc",
- "amlogic,meson-gxl-gpio-intc";
+ compatible = "amlogic,meson-gxl-gpio-intc",
+ "amlogic,meson-gpio-intc";
status = "okay";
};
};
};
+ spi_idle_high_pins: spi-idle-high-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-up;
+ };
+ };
+
+ spi_idle_low_pins: spi-idle-low-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-down;
+ };
+ };
+
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
};
};
- eth-phy-mux {
- compatible = "mdio-mux-mmioreg", "mdio-mux";
+ eth_phy_mux: mdio@558 {
+ reg = <0x0 0x558 0x0 0xc>;
+ compatible = "amlogic,gxl-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0x55c 0x0 0x4>;
- mux-mask = <0xffffffff>;
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "ref";
mdio-parent-bus = <&mdio0>;
- internal_mdio: mdio@e40908ff {
- reg = <0xe40908ff>;
+ external_mdio: mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ internal_mdio: mdio@1 {
+ reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
max-speed = <100>;
};
};
-
- external_mdio: mdio@2009087f {
- reg = <0x2009087f>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
};
};
gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
&gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
/* Dummy RPM values since fan is optional */
- gpio-fan,speed-map = <0 0
- 1 1
- 2 2
- 3 3>;
+ gpio-fan,speed-map =
+ <0 0>,
+ <1 1>,
+ <2 2>,
+ <3 3>;
#cooling-cells = <2>;
};
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
#size-cells = <0>;
bus-width = <4>;
- max-frequency = <60000000>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
non-removable;
disable-wp;
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
- w25q32: spi-flash@0 {
+ w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <100>;
button-power {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2023 BayLibre Inc.
+ */
+
+#include <dt-bindings/input/input.h>
+
+&pwrap {
+ mt6357_pmic: pmic {
+ compatible = "mediatek,mt6357";
+
+ regulators {
+ mt6357_vproc_reg: buck-vproc {
+ regulator-name = "vproc";
+ regulator-min-microvolt = <518750>;
+ regulator-max-microvolt = <1312500>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <220>;
+ regulator-always-on;
+ };
+
+ mt6357_vcore_reg: buck-vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <518750>;
+ regulator-max-microvolt = <1312500>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <220>;
+ regulator-always-on;
+ };
+
+ mt6357_vmodem_reg: buck-vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <220>;
+ };
+
+ mt6357_vs1_reg: buck-vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <220>;
+ regulator-always-on;
+ };
+
+ mt6357_vpa_reg: buck-vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-ramp-delay = <50000>;
+ regulator-enable-ramp-delay = <220>;
+ };
+
+ mt6357_vfe28_reg: ldo-vfe28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vxo22_reg: ldo-vxo22 {
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-enable-ramp-delay = <110>;
+ };
+
+ mt6357_vrf18_reg: ldo-vrf18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <110>;
+ };
+
+ mt6357_vrf12_reg: ldo-vrf12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <110>;
+ };
+
+ mt6357_vefuse_reg: ldo-vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcn33_bt_reg: ldo-vcn33-bt {
+ regulator-name = "vcn33-bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
+ regulator-name = "vcn33-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcn28_reg: ldo-vcn28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcn18_reg: ldo-vcn18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcama_reg: ldo-vcama {
+ regulator-name = "vcama";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcamd_reg: ldo-vcamd {
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vcamio_reg: ldo-vcamio18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vldo28_reg: ldo-vldo28 {
+ regulator-name = "vldo28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vsram_others_reg: ldo-vsram-others {
+ regulator-name = "vsram-others";
+ regulator-min-microvolt = <518750>;
+ regulator-max-microvolt = <1312500>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <110>;
+ regulator-always-on;
+ };
+
+ mt6357_vsram_proc_reg: ldo-vsram-proc {
+ regulator-name = "vsram-proc";
+ regulator-min-microvolt = <518750>;
+ regulator-max-microvolt = <1312500>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <110>;
+ regulator-always-on;
+ };
+
+ mt6357_vaux18_reg: ldo-vaux18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vaud28_reg: ldo-vaud28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vaud28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vio28_reg: ldo-vio28 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vio18_reg: ldo-vio18 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ };
+
+ mt6357_vdram_reg: ldo-vdram {
+ regulator-name = "vdram";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <3300>;
+ };
+
+ mt6357_vmc_reg: ldo-vmc {
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <44>;
+ };
+
+ mt6357_vmch_reg: ldo-vmch {
+ regulator-name = "vmch";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <44>;
+ };
+
+ mt6357_vemc_reg: ldo-vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <44>;
+ regulator-always-on;
+ };
+
+ mt6357_vsim1_reg: ldo-vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vsim2_reg: ldo-vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6357_vibr_reg: ldo-vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <44>;
+ };
+
+ mt6357_vusb33_reg: ldo-vusb33 {
+ regulator-name = "vusb33";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+ };
+
+ rtc {
+ compatible = "mediatek,mt6357-rtc";
+ };
+
+ keys {
+ compatible = "mediatek,mt6357-keys";
+
+ key-power {
+ linux,keycodes = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ key-home {
+ linux,keycodes = <KEY_HOME>;
+ wakeup-source;
+ };
+
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2022 BayLibre, SAS.
+ * Authors:
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
+#include "mt8365.dtsi"
+#include "mt6357.dtsi"
+
+/ {
+ model = "MediaTek MT8365 Open Platform EVK";
+ compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys>;
+
+ key-volume-up {
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x30000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&cpu0 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+ðernet {
+ pinctrl-0 = <ðernet_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy>;
+ phy-mode = "rmii";
+ /*
+ * Ethernet and HDMI (DSI0) are sharing pins.
+ * Only one can be enabled at a time and require the physical switch
+ * SW2101 to be set on LAN position
+ * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
+ */
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc0 {
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x12012>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <&mt6357_vemc_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
+ max-frequency = <200000000>;
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ vmmc-supply = <&mt6357_vmch_reg>;
+ vqmmc-supply = <&mt6357_vmc_reg>;
+ status = "okay";
+};
+
+&mt6357_pmic {
+ interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+&pio {
+ ethernet_pins: ethernet-pins {
+ phy_reset_pins {
+ pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
+ };
+
+ rmii_pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
+ <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
+ <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
+ <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
+ <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
+ <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
+ <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
+ <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
+ <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
+ <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
+ <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
+ <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
+ <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
+ <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
+ <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
+ <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
+ };
+ };
+
+ gpio_keys: gpio-keys-pins {
+ pins {
+ pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins {
+ pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
+ <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ ds-pins {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ cd-pins {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
+ <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
+ <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
+ <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ id-pins {
+ pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ usb0-vbus-pins {
+ pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
+ output-high;
+ };
+
+ usb1-vbus-pins {
+ pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
+ output-high;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pins {
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
+ <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ssusb {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ pinctrl-0 = <&usb_pins>;
+ pinctrl-names = "default";
+ usb-role-switch;
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
+ type = "micro";
+ vbus-supply = <&usb_otg_vbus>;
+ };
+};
+
+&usb_host {
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) 2018 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+
+/ {
+ compatible = "mediatek,mt8365";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <650000>;
+ };
+
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-microvolt = <668750>;
+ };
+
+ opp-987000000 {
+ opp-hz = /bits/ 64 <987000000>;
+ opp-microvolt = <687500>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <706250>;
+ };
+
+ opp-1125000000 {
+ opp-hz = /bits/ 64 <1125000000>;
+ opp-microvolt = <725000>;
+ };
+
+ opp-1216000000 {
+ opp-hz = /bits/ 64 <1216000000>;
+ opp-microvolt = <750000>;
+ };
+
+ opp-1308000000 {
+ opp-hz = /bits/ 64 <1308000000>;
+ opp-microvolt = <775000>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <800000>;
+ };
+
+ opp-1466000000 {
+ opp-hz = /bits/ 64 <1466000000>;
+ opp-microvolt = <825000>;
+ };
+
+ opp-1533000000 {
+ opp-hz = /bits/ 64 <1533000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp-1633000000 {
+ opp-hz = /bits/ 64 <1633000000>;
+ opp-microvolt = <887500>;
+ };
+
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <912500>;
+ };
+
+ opp-1767000000 {
+ opp-hz = /bits/ 64 <1767000000>;
+ opp-microvolt = <937500>;
+ };
+
+ opp-1834000000 {
+ opp-hz = /bits/ 64 <1834000000>;
+ opp-microvolt = <962500>;
+ };
+
+ opp-1917000000 {
+ opp-hz = /bits/ 64 <1917000000>;
+ opp-microvolt = <993750>;
+ };
+
+ opp-2001000000 {
+ opp-hz = /bits/ 64 <2001000000>;
+ opp-microvolt = <1025000>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_MCDI: cpu-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010001>;
+ entry-latency-us = <300>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_MCDI: cluster-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010001>;
+ entry-latency-us = <350>;
+ exit-latency-us = <250>;
+ min-residency-us = <1200>;
+ };
+
+ CLUSTER_DPIDLE: cluster-dpidle {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010004>;
+ entry-latency-us = <300>;
+ exit-latency-us = <800>;
+ min-residency-us = <3300>;
+ };
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x10000>, /* GICD */
+ <0 0x0c080000 0 0x80000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8365-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8365-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ syscfg_pctl: syscfg-pctl@10005000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8365-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT8365_POWER_DOMAIN_MM {
+ reg = <MT8365_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&mmsys CLK_MM_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_MM_SMI_COMM0>,
+ <&mmsys CLK_MM_MM_SMI_COMM1>,
+ <&mmsys CLK_MM_MM_SMI_LARB0>;
+ clock-names = "mm", "mm-0", "mm-1",
+ "mm-2", "mm-3";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,infracfg-nao = <&infracfg_nao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@MT8365_POWER_DOMAIN_CAM {
+ reg = <MT8365_POWER_DOMAIN_CAM>;
+ clocks = <&camsys CLK_CAM_LARB2>,
+ <&camsys CLK_CAM_SENIF>,
+ <&camsys CLK_CAMSV0>,
+ <&camsys CLK_CAMSV1>,
+ <&camsys CLK_CAM_FDVT>,
+ <&camsys CLK_CAM_WPE>;
+ clock-names = "cam-0", "cam-1",
+ "cam-2", "cam-3",
+ "cam-4", "cam-5";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,smi = <&smi_common>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_VDEC {
+ reg = <MT8365_POWER_DOMAIN_VDEC>;
+ #power-domain-cells = <0>;
+ mediatek,smi = <&smi_common>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_VENC {
+ reg = <MT8365_POWER_DOMAIN_VENC>;
+ #power-domain-cells = <0>;
+ mediatek,smi = <&smi_common>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_APU {
+ reg = <MT8365_POWER_DOMAIN_APU>;
+ clocks = <&infracfg CLK_IFR_APU_AXI>,
+ <&apu CLK_APU_IPU_CK>,
+ <&apu CLK_APU_AXI>,
+ <&apu CLK_APU_JTAG>,
+ <&apu CLK_APU_IF_CK>,
+ <&apu CLK_APU_EDMA>,
+ <&apu CLK_APU_AHB>;
+ clock-names = "apu", "apu-0",
+ "apu-1", "apu-2",
+ "apu-3", "apu-4",
+ "apu-5";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,smi = <&smi_common>;
+ };
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_CONN {
+ reg = <MT8365_POWER_DOMAIN_CONN>;
+ clocks = <&topckgen CLK_TOP_CONN_32K>,
+ <&topckgen CLK_TOP_CONN_26M>;
+ clock-names = "conn", "conn1";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_MFG {
+ reg = <MT8365_POWER_DOMAIN_MFG>;
+ clocks = <&topckgen CLK_TOP_MFG_SEL>;
+ clock-names = "mfg";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_AUDIO {
+ reg = <MT8365_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_IFR_AUDIO>,
+ <&infracfg CLK_IFR_AUD_26M_BK>;
+ clock-names = "audio", "audio1", "audio2";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8365_POWER_DOMAIN_DSP {
+ reg = <MT8365_POWER_DOMAIN_DSP>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_DSP_26M>;
+ clock-names = "dsp", "dsp1";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8365-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
+ keypad: keypad@10010000 {
+ compatible = "mediatek,mt6779-keypad";
+ reg = <0 0x10010000 0 0x1000>;
+ wakeup-source;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk26m>;
+ clock-names = "kpd";
+ status = "disabled";
+ };
+
+ mcucfg: syscon@10200000 {
+ compatible = "mediatek,mt8365-mcucfg", "syscon";
+ reg = <0 0x10200000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt8365-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
+ #iommu-cells = <1>;
+ };
+
+ infracfg_nao: infracfg@1020e000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x1020e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_IFR_TRNG>;
+ clock-names = "rng";
+ };
+
+ apdma: dma-controller@11000280 {
+ compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000280 0 0x80>,
+ <0 0x11000300 0 0x80>,
+ <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt8365-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_PWM_HCLK>,
+ <&infracfg CLK_IFR_PWM>,
+ <&infracfg CLK_IFR_PWM1>,
+ <&infracfg CLK_IFR_PWM2>,
+ <&infracfg CLK_IFR_PWM3>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
+ reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
+ reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_IFR_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ i2c3: i2c@1100f000 {
+ compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
+ reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: usb@11200000 {
+ compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>,
+ <&infracfg CLK_IFR_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11c60000 0 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
+ <&infracfg CLK_IFR_MSDC2_HCLK>,
+ <&infracfg CLK_IFR_MSDC2_SRC>,
+ <&infracfg CLK_IFR_MSDC2_BK>,
+ <&infracfg CLK_IFR_AP_MSDC0>;
+ clock-names = "source", "hclk", "source_cg",
+ "bus_clk", "sys_cg";
+ status = "disabled";
+ };
+
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
+ u3phy: t-phy@11cc0000 {
+ compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11cc0000 0x9000>;
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@1000 {
+ reg = <0x1000 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8365-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8365-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_MM_SMI_COMM0>,
+ <&mmsys CLK_MM_MM_SMI_COMM1>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8365-smi-larb",
+ "mediatek,mt8186-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ mediatek,larb-id = <0>;
+ };
+
+ camsys: syscon@15000000 {
+ compatible = "mediatek,mt8365-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt8365-smi-larb",
+ "mediatek,mt8186-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
+ <&camsys CLK_CAM_LARB2>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
+ mediatek,larb-id = <2>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8365-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb3: larb@16010000 {
+ compatible = "mediatek,mt8365-smi-larb",
+ "mediatek,mt8186-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
+ mediatek,larb-id = <3>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8365-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb1: larb@17010000 {
+ compatible = "mediatek,mt8365-smi-larb",
+ "mediatek,mt8186-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
+ mediatek,larb-id = <1>;
+ };
+
+ apu: syscon@19020000 {
+ compatible = "mediatek,mt8365-apu", "syscon";
+ reg = <0 0x19020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ #clock-cells = <0>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x100>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&system_clk>;
+ clock-names = "clk13m";
+ };
+};
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
- spi1: spi@201000 {
+ host_intf: host_intf@9f000 {
+ compatible = "nuvoton,npcm845-host-intf";
+ reg = <0x9f000 0x1000>;
+ type = "espi";
+ ioaddr = <0x4e>;
+ channel-support = <0xf>;
+ syscon = <&gcr>;
+ };
+
+ pspi: spi@201000 {
compatible = "nuvoton,npcm845-pspi";
reg = <0x201000 0x1000>;
pinctrl-names = "default";
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
/dts-v1/;
+
+#include <dt-bindings/phy/nuvoton,npcm-usbphy.h>
#include "nuvoton-npcm845.dtsi"
#include "nuvoton-npcm845-pincfg.dtsi"
spi1 = &fiu1;
spi3 = &fiu3;
spi4 = &fiux;
- spi5 = &spi1;
+ spi5 = &pspi;
usb0 = &udc0;
usb1 = &ehci1;
- usb2 = &ehci2;
+ usb2 = &udc8;
};
chosen {
reg = <0x0 0x0 0x0 0x40000000>;
};
+ tpm@0 {
+ compatible = "microsoft,ftpm";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
vsbr2: vsbr2 {
compatible = "regulator-npcm845";
regulator-name = "vr2";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */
+ phy-supply = <&vsbr2>;
+ phy-supply-microvolt = <1800000>;
status = "okay";
};
status = "okay";
};
-&spi1 {
+&pspi {
status = "okay";
};
&udc0 {
status = "okay";
- phys = <&usbphy1 0>;
+ phys = <&usbphy1 NPCM_UDC0_7>;
};
&sdhci0 {
&ehci1 {
status = "okay";
- phys = <&usbphy2 3>;
+ phys = <&usbphy2 NPCM_USBH1>;
};
-&ehci2 {
+&udc8 {
status = "okay";
- phys = <&usbphy3 4>;
+ phys = <&usbphy3 NPCM_UDC8>;
};
&rng {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <3>;
- resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
+ resets = <&rstc4 NPCM8XX_RESET_USBPHY3>;
status = "disabled";
};
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "imx8mm.dtsi"
-
-/ {
- model = "PHYTEC phyCORE-i.MX8MM";
- compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart3;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <100>;
- off-on-delay-us = <12000>;
- };
-};
-
-/* ethernet */
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- phy-reset-duration = <1>;
- phy-reset-post-delay = <1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- enet-phy-lane-no-swap;
- };
- };
-};
-
-/* SPI nor flash */
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- flash0: norflash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- };
-};
-
-/* i2c eeprom */
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- /* M24C32-D */
- i2c_eeprom: eeprom@51 {
- compatible = "atmel,24c32";
- reg = <0x51>;
- u-boot,i2c-offset-len = <2>;
- };
-
- /* M24C32-D Identification page */
- i2c_eeprom_id: eeprom@59 {
- compatible = "atmel,24c32";
- reg = <0x59>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-/* debug console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* sd-card */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-/* watchdog */
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1grp-gpio {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
bootph-all;
};
+&dsi {
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+ clock-names = "pclk", "px_clk", "ref";
+};
+
&gpioa {
bootph-all;
};
bootph-all;
};
+<dc {
+ bootph-all;
+
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>;
+};
+
&pinctrl {
bootph-all;
};
};
- panel-dsi@0 {
+ panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
status = "okay";
port {
- ltdc_out_dsi: endpoint@0 {
+ ltdc_out_dsi: endpoint {
remote-endpoint = <&dsi_in>;
};
};
};
};
};
+ };
+};
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
-
- status = "okay";
- bootph-all;
+<dc {
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ bootph-all;
- ports {
- port@0 {
- dp_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
+ ports {
+ port@0 {
+ dp_out: endpoint {
+ remote-endpoint = <&dsi_in>;
};
};
};
status = "okay";
};
+<dc {
+ status = "okay";
+};
+
&rtc {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2023
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ pinctrl0 = &pinctrl;
+ pinctrl1 = &pinctrl_z;
+ };
+
+ firmware {
+ optee {
+ bootph-all;
+ };
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ bootph-all;
+ };
+
+ soc@0 {
+ bootph-all;
+ };
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
+&syscfg {
+ bootph-all;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ arm_wdt: watchdog {
+ compatible = "arm,smc-wdt";
+ arm,smc-id = <0xb200005a>;
+ status = "disabled";
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ intc: interrupt-controller@4ac00000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0x0 0x4ac10000 0x0 0x1000>,
+ <0x0 0x4ac20000 0x0 0x2000>,
+ <0x0 0x4ac40000 0x0 0x2000>,
+ <0x0 0x4ac60000 0x0 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges = <0x0 0x0 0x0 0x80000000>;
+
+ rifsc: rifsc-bus@42080000 {
+ compatible = "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ status = "disabled";
+ };
+ };
+
+ syscfg: syscon@44230000 {
+ compatible = "st,stm32mp25-syscfg", "syscon";
+ reg = <0x44230000 0x10000>;
+ };
+
+ pinctrl: pinctrl@44240000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-pinctrl";
+ ranges = <0 0x44240000 0xa0400>;
+ pins-are-numbered;
+
+ gpioa: gpio@44240000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@44250000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@44260000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@44270000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x30000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@44280000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@44290000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x50000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@442a0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x60000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@442b0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x70000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@442c0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@442d0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x90000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@442e0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa0000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pinctrl@46200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@46200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp251.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp253.dtsi"
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp255.dtsi"
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ */
+
+#include "stm32mp25-u-boot.dtsi"
+
+&usart2 {
+ bootph-all;
+};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
+ compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
+
+ aliases {
+ serial0 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fw@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ no-map;
+ };
+ };
+};
+
+&arm_wdt {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AI>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@442d0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@442e0000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AK>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AL>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
- phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
- allwinner,rx-delay-ps = <3100>;
- allwinner,tx-delay-ps = <700>;
status = "okay";
};
};
&emac0 {
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ phy-mode = "rgmii";
phy-supply = <®_dcdce>;
};
};
&emac0 {
+ allwinner,tx-delay-ps = <700>;
+ phy-mode = "rgmii-rxid";
phy-supply = <®_dldo1>;
};
clock-frequency = <100000>;
};
- nvec@7000c500 {
+ i2c@7000c500 {
compatible = "nvidia,nvec";
- reg = <0x7000c500 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+
+ /delete-property/ #address-cells;
+ /delete-property/ #size-cells;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+
clock-frequency = <80000>;
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
- clocks = <&tegra_car TEGRA20_CLK_I2C3>,
- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 67>;
- reset-names = "i2c";
+
+ status = "okay";
};
i2c@7000d000 {
power-supply = <&vdd_bl_reg>;
pwms = <&pwm 0 5000000>;
- brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
- default-brightness-level = <10>;
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <2>;
backlight-boot-off;
};
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr1_pc1",
+ "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pclk_pb3 {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_dc0_pn6",
+ "lcd_cs1_n_pw0",
+ "lcd_sdin_pz2",
+ "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat5_pd0 {
+ nvidia,pins = "sdmmc3_dat5_pd0";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad14_ph6",
+ "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad2_pg2 {
+ nvidia,pins = "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad4_pg4 {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad8_ph0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad9_ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad11_ph3 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_adv_n_pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad15_ph7 {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_dqs_pi2 {
+ nvidia,pins = "gmi_dqs_pi2",
+ "pu2",
+ "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_rst_n_pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_iordy_pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs7_n_pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_a16_pj7 {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data3_po4 {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_fs_pp4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row6_pr6 {
+ nvidia,pins = "kb_row6_pr6",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3",
+ "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu0 {
+ nvidia,pins = "pu0",
+ "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck_pu7 {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2",
+ "spi2_miso_px1",
+ "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_cs0_n_px3 {
+ nvidia,pins = "spi2_cs0_n_px3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_cs0_n_px6";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_wr_n_pz3 {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pbb0 {
+ nvidia,pins = "pbb0",
+ "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7",
+ "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n_pcc3 {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l2_rst_n_pcc6 {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ drive_gma {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
uarta: serial@70006000 {
status = "okay";
};
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
compatible = "asus,grouper", "nvidia,tegra30";
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
i2c@7000d000 {
pmic: max77663@3c {
compatible = "maxim,max77663";
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
compatible = "asus,grouper", "nvidia,tegra30";
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
i2c@7000d000 {
/* Texas Instruments TPS659110 PMIC */
pmic: tps65911@2d {
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
};
};
model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
compatible = "asus,tilapia", "nvidia,tegra30";
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
i2c@7000d000 {
pmic: max77663@3c {
compatible = "maxim,max77663";
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1_clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cd {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_wp {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC2 pinmux */
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d5_pl3",
+ "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3_clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive_sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc_i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hotplug_i2c {
+ nvidia,pins = "pu4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi_cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hdmi_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb_txd_rts {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uartb_rxd_cts {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uartc_rxd_cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc_txd_rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap_i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_dout {
+ nvidia,pins = "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* sensors pinmux */
+ nct_irq {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Asus EC pinmux */
+ ec_irqs {
+ nvidia,pins = "kb_row10_ps2",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ec_reqs {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* memory type bootstrap */
+ mem_boostraps {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex_l2_rst_n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l0_rst_n_pdd1",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l2_clkreq_n {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_wake_n_pdd3",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6",
+ "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_sck_px2 {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a16_pj7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_a18_pb1 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a19_pk7 {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3",
+ "lcd_pwr1_pc1",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs1_n_pw0",
+ "lcd_dc0_pn6",
+ "lcd_sck_pz4",
+ "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_cs0_n_pn4 {
+ nvidia,pins = "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col1_pq1 {
+ nvidia,pins = "kb_row1_pr1",
+ "kb_row3_pr3",
+ "kb_row9_ps1",
+ "kb_row11_ps3",
+ "kb_row14_ps6",
+ "kb_col6_pq6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row12_ps4",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* GPIO keys pinmux */
+ power_key {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vol_keys {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bluetooth */
+ bt_shutdown {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt_dev_wake {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_host_wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_hsync_pd7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2",
+ "vi_d0_pt4", "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_rst_n_pi4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* USB2 VBUS control */
+ usb2_vbus_control {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* PWM pinmux */
+ pwm_0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_2 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* S/PDIF pinmux */
+ spdif_out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sys_clk_req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5",
+ "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* P1801-T specific pinmux */
+ lcd_pwr2 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_m1 {
+ nvidia,pins = "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ key_mode {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ splashtop {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "nand_alt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ w8_detect {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "nand_alt";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ tp_vendor {
+ nvidia,pins = "kb_row6_pr6",
+ "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ tp_power {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
uarta: serial@70006000 {
status = "okay";
};
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDD */
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Mini USB port */
usb2: usb@7d004000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
};
+ usb-phy@7d004000 {
+ status = "okay";
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
model = "ASUS Transformer Prime TF201";
compatible = "asus,tf201", "nvidia,tegra30";
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
usb-phy@7d008000 {
/delete-property/ nvidia,xcvr-setup-use-fuses;
nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
output-low;
};
};
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
};
/ {
model = "ASUS Transformer Pad 3G TF300TG";
compatible = "asus,tf300tg", "nvidia,tegra30";
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ };
+
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
};
/ {
model = "ASUS Transformer Pad LTE TF300TL";
compatible = "asus,tf300tl", "nvidia,tegra30";
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* TF300TL specific pinmux reconfiguration */
+
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_vsync_pv7 {
+ nvidia,pins = "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap1_dout_pn2 {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ };
+
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
};
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1_clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cd {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_wp {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC2 pinmux */
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d5_pl3",
+ "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3_clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc_i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hotplug_i2c {
+ nvidia,pins = "pu4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi_cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hdmi_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb_txd_rts {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uartb_rxd_cts {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uartc_rxd_cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc_txd_rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap_i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_din {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_dout {
+ nvidia,pins = "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ i2s4 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ nct_irq {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hall {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Asus EC pinmux */
+ ec_irqs {
+ nvidia,pins = "kb_row10_ps2",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ec_reqs {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Memory type bootstrap */
+ mem_boostraps {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex_l2_rst_n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l0_rst_n_pdd1",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l2_clkreq_n {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_wake_n_pdd3",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3",
+ "lcd_pwr1_pc1",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs1_n_pw0",
+ "lcd_m1_pw1",
+ "lcd_dc0_pn6",
+ "lcd_sck_pz4",
+ "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_cs0_n_pn4 {
+ nvidia,pins = "lcd_sdout_pn5",
+ "lcd_wr_n_pz3",
+ "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb_col0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_row1_pr1",
+ "kb_row3_pr3",
+ "kb_row6_pr6",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row11_ps3",
+ "kb_row14_ps6",
+ "kb_col6_pq6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col5 {
+ nvidia,pins = "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* GPIO keys pinmux */
+ power_key {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vol_keys {
+ nvidia,pins = "kb_col3_pq3",
+ "kb_col4_pq4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bluetooth */
+ bt_shutdown {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt_dev_wake {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_host_wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_hsync_pd7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2",
+ "vi_d0_pt4", "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_rst_n_pi4",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Vibrator control */
+ vibrator {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PWM pinmux */
+ pwm_0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_2 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs_n {
+ nvidia,pins = "gmi_cs4_n_pk2",
+ "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Spdif pinmux */
+ spdif_out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_sync {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sys_clk_req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5",
+ "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ drive_sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
uarta: serial@70006000 {
status = "okay";
};
regulator-name = "vdd_1v2_backlight";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
vcore_lcd: vdd2 {
regulator-name = "vcore_lcd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
};
vdd_1v8_vio: vddio {
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
};
};
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
/delete-node/ host1x@50000000;
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
/delete-node/ panel;
};
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1_clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc1_cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc1_cd {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc1_wp {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC2 pinmux */
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d5_pl3",
+ "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,io-reset = <0>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3_clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc4_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc4_rst_n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ drive_sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ gen2_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ ddc_i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ hotplug_i2c {
+ nvidia,pins = "pu4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi_cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ hdmi_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb_txd_rts {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uartb_rxd_cts {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uartc_rxd_cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ uartc_txd_rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap_i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap_i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_fs {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_dout {
+ nvidia,pins = "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap_i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ nct_irq {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Asus EC pinmux */
+ ec_irqs {
+ nvidia,pins = "kb_row10_ps2",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ec_reqs {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Memory type bootstrap */
+ mem_boostraps {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex_l2_rst_n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l0_rst_n_pdd1",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l2_clkreq_n {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_wake_n_pdd3",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6",
+ "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ hp_detect {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ mic_detect {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a16_pj7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_a18_pb1 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_a19_pk7 {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3",
+ "lcd_pwr1_pc1",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs1_n_pw0",
+ "lcd_m1_pw1",
+ "lcd_dc0_pn6",
+ "lcd_sck_pz4",
+ "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_cs0_n_pn4 {
+ nvidia,pins = "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col1_pq1 {
+ nvidia,pins = "kb_row1_pr1",
+ "kb_row3_pr3",
+ "kb_row6_pr6",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row11_ps3",
+ "kb_row14_ps6",
+ "kb_col6_pq6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row12_ps4",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,io-reset = <0>;
+ };
+
+ /* GPIO keys pinmux */
+ power_key {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vol_keys {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bluetooth */
+ bt_shutdown {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ bt_dev_wake {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ bt_host_wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_hsync_pd7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,io-reset = <0>;
+ };
+
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2",
+ "vi_d0_pt4", "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_rst_n_pi4",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Vibrator control */
+ vibrator {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PWM pimnmux */
+ pwm_0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_2 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Spdif pinmux */
+ spdif_out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spdif_in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <0>;
+ nvidia,io-reset = <0>;
+ };
+
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sys_clk_req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5",
+ "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
uarta: serial@70006000 {
status = "okay";
};
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDD */
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* PORT A */
+ clk_32k_out {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_uart_cts {
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_aic3008_i2s {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wifi_sdio_clock {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wifi_sdio_command {
+ nvidia,pins = "sdmmc3_cmd_pa7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT B */
+ mdm_imc_uart {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_3v3_en {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wifi_sdio_data {
+ nvidia,pins = "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT C */
+ bt_uart_rts {
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mdm_ap2bb_rst_pwrdwn {
+ nvidia,pins = "lcd_pwr1_pc1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cam_spi_clk_do {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rxd_pc3";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ per_sensor_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_ap2bb_slave_wakeup {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_int {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT D */
+ sdmmc3_data {
+ nvidia,pins = "sdmmc3_dat5_pd0",
+ "sdmmc3_dat4_pd1";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_1v8_en {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat6_pd3 {
+ nvidia,pins = "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT E */
+ mhl_usb_sel {
+ nvidia,pins = "lcd_d0_pe0";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_d1_pe1 {
+ nvidia,pins = "lcd_d1_pe1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ peh_cap_int {
+ nvidia,pins = "lcd_d2_pe2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_1v2_en {
+ nvidia,pins = "lcd_d3_pe3",
+ "lcd_d4_pe4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_lcm_1v8_en {
+ nvidia,pins = "lcd_d5_pe5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mhl_rst {
+ nvidia,pins = "lcd_d6_pe6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ peh_vibrator_on {
+ nvidia,pins = "lcd_d7_pe7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT F */
+ cam_vcm_2v85_pwr {
+ nvidia,pins = "lcd_d8_pf0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_d9_d13 {
+ nvidia,pins = "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_cam2_core_1v8_en {
+ nvidia,pins = "lcd_d14_pf6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys_pmu_msecure {
+ nvidia,pins = "lcd_d15_pf7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT G */
+ bootstraps {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT H */
+ haptic_pwm {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad9 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad10 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dsp_tp_rst {
+ nvidia,pins = "gmi_ad11_ph3",
+ "gmi_ad12_ph4",
+ "gmi_ad13_ph5",
+ "gmi_ad14_ph6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad15 {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT I */
+ gmi_wr_n {
+ nvidia,pins = "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_cs6_n_pi3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_rst_n_pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sim_detect {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ peh_gyr_int {
+ nvidia,pins = "gmi_cs7_n_pi6",
+ "gmi_wait_pi7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT J */
+ mdm_bb2ap_host_wakeup {
+ nvidia,pins = "gmi_cs0_n_pj0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_lcm_de {
+ nvidia,pins = "lcd_de_pj1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ peh_comp_int {
+ nvidia,pins = "gmi_cs1_n_pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_hsync {
+ nvidia,pins = "lcd_hsync_pj3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_ap_usb_uart_oe {
+ nvidia,pins = "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mcam_spi_di_cs0 {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_tx {
+ nvidia,pins = "gmi_a16_pj7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT K */
+ gmi_adv_n {
+ nvidia,pins = "gmi_adv_n_pk0",
+ "gmi_clk_pk1",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs4_n {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs3_n {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spdif_out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_rts {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT L */
+ port_l {
+ nvidia,pins = "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d4_pl2",
+ "vi_d5_pl3",
+ "vi_d6_pl4",
+ "vi_d7_pl5",
+ "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT M */
+ dsp_lcd_id {
+ nvidia,pins = "lcd_d16_pm0",
+ "lcd_d17_pm1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ front_cam_rst {
+ nvidia,pins = "lcd_d18_pm2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_v_dcin_modem_en {
+ nvidia,pins = "lcd_d19_pm3",
+ "lcd_d20_pm4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ nfc_pins {
+ nvidia,pins = "lcd_d21_pm5",
+ "lcd_d22_pm6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cam_vaa_2v85_en {
+ nvidia,pins = "lcd_d23_pm7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT N */
+ mdm_ap2bb_rst_host_pwr {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mdm_bb_fatal_int {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_cs0_n {
+ nvidia,pins = "lcd_cs0_n_pn4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_sdout {
+ nvidia,pins = "lcd_sdout_pn5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_lcd_rst {
+ nvidia,pins = "lcd_dc0_pn6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mhl_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT O */
+ ap_usb_uart_sel {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bsp_ap_debug_tx {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bsp_ap_debug_rx {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data2 {
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ con_wifi_irq {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "hsi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ per_gsensor_int {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data5_data6 {
+ nvidia,pins = "ulpi_data5_po6",
+ "ulpi_data6_po7";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT P */
+ aud_ap_pcm {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_btpcm {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_ext {
+ nvidia,pins = "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT Q */
+ port_q {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col6_pq6",
+ "kb_col7_pq7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT R */
+ raw_intr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ per_torch_en {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gyro_pwr {
+ nvidia,pins = "kb_row2_pr2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ haptic_en {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row4_row5 {
+ nvidia,pins = "kb_row4_pr4",
+ "kb_row5_pr5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_id {
+ nvidia,pins = "kb_row6_pr6",
+ "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT S */
+ dsp_vol_up {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ con_usb_id_1 {
+ nvidia,pins = "kb_row9_ps1",
+ "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ port_s {
+ nvidia,pins = "kb_row11_ps3",
+ "kb_row12_ps4",
+ "kb_row13_ps5",
+ "kb_row14_ps6",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT T */
+ dsp_tw_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ per_emmc_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT U */
+ con_bt_en {
+ nvidia,pins = "pu0", "pu1", "pu2",
+ "pu3", "pu4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ per_capsensor_int_cpu {
+ nvidia,pins = "pu5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_ap_kpdpwr {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT V */
+ mdm_bb2ap_suspend_req {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_tp_att {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ con_wifi_en {
+ nvidia,pins = "pv2", "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_ddc {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ crt_hsync {
+ nvidia,pins = "crt_hsync_pv6";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ crt_vsync {
+ nvidia,pins = "crt_vsync_pv7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT W */
+ pwr_chg_stat {
+ nvidia,pins = "lcd_cs1_n_pw0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_bl_pwm_cpu {
+ nvidia,pins = "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ aud_hp_det {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dsp_vol_down {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_mclk {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_aic3008_rst {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ con_bt_tx {
+ nvidia,pins = "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ con_bt_rx {
+ nvidia,pins = "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT X */
+ aud_spi_do {
+ nvidia,pins = "spi2_mosi_px0",
+ "spi2_sck_px2",
+ "spi2_cs0_n_px3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ aud_spi_di {
+ nvidia,pins = "spi2_miso_px1";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_mosi {
+ nvidia,pins = "spi1_mosi_px4";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_chg_int {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_cs0_n {
+ nvidia,pins = "spi1_cs0_n_px6";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ audio_mclk_en {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT Y */
+ led_drv_en_trig {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_3v3_en {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ peh_v_srio_1v8_en {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_remo_tx {
+ nvidia,pins = "sdmmc1_dat3_py4";
+ nvidia,function = "uarte";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ aud_remo_rx {
+ nvidia,pins = "sdmmc1_dat2_py5";
+ nvidia,function = "uarte";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ nfc_irq {
+ nvidia,pins = "sdmmc1_dat1_py6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ testpoint1 {
+ nvidia,pins = "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT Z */
+ aud_remo_oe {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ testpoint2 {
+ nvidia,pins = "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mdm_usb_uart_oe {
+ nvidia,pins = "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_wr_n {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_sck {
+ nvidia,pins = "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sys_clk_req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sys_pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT AA */
+ bsp_emmc {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT BB */
+ cam1_rst {
+ nvidia,pins = "pbb0";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ per_flash_en {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cam_vddio_1v8_en {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam1_vcm_pd {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_remo_pres {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ front_cam_standby {
+ nvidia,pins = "pbb7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT CC */
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_sel {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_themp_alert_int {
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bsp_emmc_resout {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bsp_emmc_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ aud_dock_out_en {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT DD */
+ /* PORT EE */
+ clk3_out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ raw_intr1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk1_req {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi_cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
uarta: serial@70006000 {
status = "okay";
};
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
};
};
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
mmc1 = &sdmmc3; /* uSD slot */
};
+ pinmux@70000868 {
+ state_default: pinmux {
+ /* WLAN SDIO pinmux */
+ host_wlan_wake {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GNSS UART-B pinmux */
+ uartb_rxd {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb_txd {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps_reset {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* MicroSD pinmux */
+ sdmmc3_clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_data {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ microsd_detect {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ volume_up {
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ current_alert_irq {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* AUDIO pinmux */
+ sub_mic_ldo {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
sdmmc3: sdhci@78000400 {
status = "okay";
bus-width = <4>;
};
};
+ pinmux@70000868 {
+ state_default: pinmux {
+ /* GNSS UART-B pinmux */
+ uartb_cts_rxd {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb_rts_txd {
+ nvidia,pins = "uart2_rts_n_pj6",
+ "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps_reset {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ volume_up {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ memo_key {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ current_alert_irq {
+ nvidia,pins = "spi1_cs0_n_px6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Panel pinmux */
+ panel_vdd {
+ nvidia,pins = "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AUDIO pinmux */
+ sub_mic_ldo {
+ nvidia,pins = "gmi_dqs_pi2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Modem pinmux */
+ usim_detect {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
panel: panel {
compatible = "hitachi,tx13d100vm0eaa";
};
};
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* WLAN SDIO pinmux */
+ sdmmc1_clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wlan_reset {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ wlan_host_wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GNSS UART-B pinmux */
+ gps_pwr_en {
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps_ldo_en {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps_clk_ref {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Bluetooth UART-C pinmux */
+ uartc_cts_rxd {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc_rts_txd {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_reset {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_dev_wake {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_host_wake {
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt_pcm_dap4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* EMMC pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_data {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_reset {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ gen2_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ ddc_i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+
+ mhl_i2c {
+ nvidia,pins = "kb_col6_pq6",
+ "kb_col7_pq7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ power_key {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ volume_down {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ sen_vdd {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ proxi_vdd {
+ nvidia,pins = "spi2_miso_px1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sen_vio {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ nct_irq {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bat_irq {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ charger_irq {
+ nvidia,pins = "gmi_cs1_n_pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mpu_irq {
+ nvidia,pins = "gmi_ad12_ph4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ compass_irq {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ light_irq {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* LED pinmux */
+ backlight_en {
+ nvidia,pins = "lcd_dc0_pn6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ flash_led_en {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ keypad_led {
+ nvidia,pins = "kb_row2_pr2",
+ "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* NFC pinmux */
+ nfc_irq {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ nfc_ven {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ nfc_firm {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* DC pinmux */
+ lcd_pwr {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr1_pc1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_wr_n {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_id {
+ nvidia,pins = "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pclk {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_rgb_blue {
+ nvidia,pins = "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_rgb_green {
+ nvidia,pins = "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_rgb_red {
+ nvidia,pins = "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bridge pinmux */
+ bridge_reset {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rgb_ic_en {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bridge_clk {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ rgb_bridge {
+ nvidia,pins = "lcd_sdin_pz2",
+ "lcd_sdout_pn5",
+ "lcd_cs0_n_pn4",
+ "lcd_sck_pz4";
+ nvidia,function = "spi5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Panel pinmux */
+ panel_reset {
+ nvidia,pins = "lcd_cs1_n_pw0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ panel_vio {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Touchscreen pinmux */
+ touch_vdd {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch_vio {
+ nvidia,pins = "spi1_mosi_px4";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch_int_n {
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ touch_rst_n {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch_maker_id {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MHL pinmux */
+ mhl_vio {
+ nvidia,pins = "pv2";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_rst_n {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl_int {
+ nvidia,pins = "crt_vsync_pv7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mhl_sel {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* AUDIO pinmux */
+ hp_detect {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hp_hook {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ear_mic_en {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ audio_irq {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ audio_mclk {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MUIC pinmux */
+ muic_irq {
+ nvidia,pins = "gmi_cs0_n_pj0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ muic_dp2t {
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ muic_usif {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ifx_usb_vbus_en {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcb_rev {
+ nvidia,pins = "gmi_wait_pi7",
+ "gmi_rst_n_pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Camera pinmux */
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_pmic_en {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ front_cam_rst {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ front_cam_vio {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear_cam_rst {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear_cam_eprom_pr {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear_cam_vcm_pwdn {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Haptic pinmux */
+ haptic_en {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ haptic_osc {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Modem pinmux */
+ cp2ap_ack1_host_active {
+ nvidia,pins = "pu5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cp2ap_ack2_host_wakeup {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ap2cp_ack2_suspend_req {
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ap2cp_ack1_slave_wakeup {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ cp_kkp {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cp_crash_irq {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ap2cp_uarta_tx_ipc {
+ nvidia,pins = "pu0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ap2cp_uarta_rx_ipc {
+ nvidia,pins = "pu1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ fota_ap_cts_cp_rts {
+ nvidia,pins = "pu2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ fota_ap_rts_cp_cts {
+ nvidia,pins = "pu3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ modem_enable {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "hsi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ modem_reset {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap_i2s2 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_i2c {
+ nvidia,pins = "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive_uart3 {
+ nvidia,pins = "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive_gmi {
+ nvidia,pins = "drive_at3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+ };
+
uartd: serial@70006300 {
status = "okay";
};
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&avdd_3v3_periph>;
+ };
+
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
ethernet_phy: ethernet-phy@1 {
reg = <1>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
- device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
- device_type = "ethernet-phy";
};
};
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */
- #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
- compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
- reg = <0x6c>;
- /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
- /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
- };
+ /* u39 8T49N240 */
};
i2c@3 { /* PMBUS2_INA226 */
#address-cells = <1>;
/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
- clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */
- #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
- compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
- reg = <0x60>;
- /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
- /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
-
- };
-
+ /* u39 8T49N240 - pcie clocking 3 */
};
};
};
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
usbhub0: usb-hub { /* u36 */
i2c-bus = <&i2c1>;
compatible = "microchip,usb5744";
compatible = "microchip,usb2244";
reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_0 {
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
usbhub0: usb-hub { /* u43 */
i2c-bus = <&usbhub_i2c0>;
compatible = "microchip,usb5744";
compatible = "microchip,usb2244";
reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_0 {
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
usbhub0: usb-hub { /* u43 */
i2c-bus = <&usbhub_i2c0>;
compatible = "microchip,usb5744";
compatible = "microchip,usb2244";
reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_0 {
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+#if 0
usbhub: usb5744 { /* u43 */
compatible = "microchip,usb5744";
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_0 {
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
usb5744: usb-hub { /* u43 */
status = "okay";
compatible = "microchip,usb5744";
i2c-bus = <&i2c1>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_0 {
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
+ compatible = "xlnx,zynqmp-ipi-dest-mailbox";
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
-#include <linux/kconfig.h>
#include <fsl_ddrc_version.h>
#ifndef __ASSEMBLY__
#ifndef __FSL_SERDES_H__
#define __FSL_SERDES_H__
-#include <config.h>
-
#ifdef CONFIG_FSL_LSCH3
enum srds_prtcl {
/*
extern unsigned long boot_pointer[];
void build_info(void);
+int ahab_close(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
int imx8_power_domain_lookup_name(const char *name,
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
+void set_arm_core_max_clk(void);
int configure_intpll(enum ccm_clk_src pll, u32 freq);
#ifndef __FSL_SERDES_H
#define __FSL_SERDES_H
-#include <config.h>
-
enum srds_prtcl {
/*
* Nobody will check whether the device 'NONE' has been configured,
* Register base addresses for i.MX28
*/
#elif defined(CONFIG_MX28)
-#define MXS_ICOL_BASE 0x80000000
+#define MXS_ICOLL_BASE 0x80000000
#define MXS_HSADC_BASE 0x80002000
#define MXS_APBH_BASE 0x80004000
#define MXS_PERFMON_BASE 0x80006000
#ifndef _CPU_H
#define _CPU_H
+#include <asm/arch/omap.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
- uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
- uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
+ struct clk_pll_simple plld2; /* _PLLD2_BASE_0, 0x4B8 */
uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DISPLAY2,
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
- CLOCK_ID_DISPLAY2, /* placeholder */
CLOCK_ID_NONE = -1,
};
PERIPH_ID_UART3,
/* 56 */
- PERIPH_ID_RESERVED56,
+ PERIPH_ID_MIPI_CAL,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
u32 mc_emem_adr_cfg; /* offset 0x54 */
u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
- u32 reserved3[12]; /* offset 0x60 - 0x8C */
+ u32 reserved3[4]; /* offset 0x60 - 0x6C */
+ u32 mc_security_cfg0; /* offset 0x70 */
+ u32 mc_security_cfg1; /* offset 0x74 */
+ u32 reserved4[6]; /* offset 0x7C - 0x8C */
u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
- u32 reserved4[338]; /* offset 0x100 - 0x644 */
+ u32 reserved5[74]; /* offset 0x100 - 0x224 */
+ u32 mc_smmu_translation_enable_0; /* offset 0x228 */
+ u32 mc_smmu_translation_enable_1; /* offset 0x22C */
+ u32 mc_smmu_translation_enable_2; /* offset 0x230 */
+ u32 mc_smmu_translation_enable_3; /* offset 0x234 */
+ u32 mc_smmu_afi_asid; /* offset 0x238 */
+ u32 mc_smmu_avpc_asid; /* offset 0x23C */
+ u32 mc_smmu_dc_asid; /* offset 0x240 */
+ u32 mc_smmu_dcb_asid; /* offset 0x244 */
+ u32 reserved6[2]; /* offset 0x248 - 0x24C */
+ u32 mc_smmu_hc_asid; /* offset 0x250 */
+ u32 mc_smmu_hda_asid; /* offset 0x254 */
+ u32 mc_smmu_isp_asid; /* offset 0x258 */
+ u32 reserved7[2]; /* offset 0x25C - 0x260 */
+ u32 mc_smmu_mpe_asid; /* offset 0x264 */
+ u32 mc_smmu_nv_asid; /* offset 0x268 */
+ u32 mc_smmu_nv2_asid; /* offset 0x26C */
+ u32 mc_smmu_ppcs_asid; /* offset 0x270 */
+ u32 reserved8[1]; /* offset 0x274 */
+ u32 mc_smmu_sata_asid; /* offset 0x278 */
+ u32 mc_smmu_vde_asid; /* offset 0x27C */
+ u32 mc_smmu_vi_asid; /* offset 0x280 */
+ u32 reserved9[241]; /* offset 0x284 - 0x644 */
u32 mc_video_protect_bom; /* offset 0x648 */
u32 mc_video_protect_size_mb; /* offset 0x64c */
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
PMUX_FUNC_COUNT,
};
+static const char * const tegra_pinctrl_to_pingrp[] = {
+ [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
+ [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
+ [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
+ [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
+ [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
+ [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
+ [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
+ [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
+ [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
+ [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
+ [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
+ [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
+ [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
+ [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
+ [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
+ [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
+ [PMUX_PINGRP_PV0] = "pv0",
+ [PMUX_PINGRP_PV1] = "pv1",
+ [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
+ [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
+ [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
+ [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
+ [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
+ [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
+ [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
+ [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
+ [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
+ [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
+ [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
+ [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
+ [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
+ [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
+ [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
+ [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
+ [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
+ [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
+ [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
+ [PMUX_PINGRP_PU0] = "pu0",
+ [PMUX_PINGRP_PU1] = "pu1",
+ [PMUX_PINGRP_PU2] = "pu2",
+ [PMUX_PINGRP_PU3] = "pu3",
+ [PMUX_PINGRP_PU4] = "pu4",
+ [PMUX_PINGRP_PU5] = "pu5",
+ [PMUX_PINGRP_PU6] = "pu6",
+ [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
+ [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
+ [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
+ [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
+ [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
+ [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
+ [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
+ [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
+ [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
+ [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
+ [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
+ [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
+ [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
+ [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
+ [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
+ [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
+ [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
+ [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
+ [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
+ [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
+ [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
+ [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
+ [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
+ [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
+ [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
+ [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
+ [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
+ [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
+ [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
+ [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
+ [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
+ [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
+ [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
+ [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
+ [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
+ [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
+ [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
+ [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
+ [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
+ [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
+ [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
+ [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
+ [PMUX_PINGRP_GMI_DQS_P_PJ3] = "gmi_dqs_p_pj3",
+ [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
+ [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
+ [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
+ [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
+ [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
+ [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
+ [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
+ [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
+ [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
+ [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
+ [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
+ [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
+ [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
+ [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
+ [PMUX_PINGRP_PCC1] = "pcc1",
+ [PMUX_PINGRP_PBB0] = "pbb0",
+ [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
+ [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
+ [PMUX_PINGRP_PBB3] = "pbb3",
+ [PMUX_PINGRP_PBB4] = "pbb4",
+ [PMUX_PINGRP_PBB5] = "pbb5",
+ [PMUX_PINGRP_PBB6] = "pbb6",
+ [PMUX_PINGRP_PBB7] = "pbb7",
+ [PMUX_PINGRP_PCC2] = "pcc2",
+ [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
+ [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
+ [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
+ [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
+ [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
+ [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
+ [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
+ [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
+ [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
+ [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
+ [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
+ [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
+ [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
+ [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
+ [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
+ [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
+ [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
+ [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
+ [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
+ [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
+ [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
+ [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
+ [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
+ [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
+ [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
+ [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_PINGRP_OWR] = "owr",
+ [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
+ [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
+ [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
+ [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
+ [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
+ [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
+ [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
+ [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
+ [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
+ [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
+ [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
+ [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
+ [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
+ [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
+ [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
+ [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
+ [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
+ [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
+ [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
+ [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
+ [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
+ [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
+ [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
+ [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
+ [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
+ [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
+ [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
+ [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
+ [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
+ [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
+ [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
+ [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
+ [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
+ [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
+ [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
+ [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
+ [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
+};
+
+static const char * const tegra_pinctrl_to_drvgrp[] = {
+ [PMUX_DRVGRP_AO1] = "drive_ao1",
+ [PMUX_DRVGRP_AO2] = "drive_ao2",
+ [PMUX_DRVGRP_AT1] = "drive_at1",
+ [PMUX_DRVGRP_AT2] = "drive_at2",
+ [PMUX_DRVGRP_AT3] = "drive_at3",
+ [PMUX_DRVGRP_AT4] = "drive_at4",
+ [PMUX_DRVGRP_AT5] = "drive_at5",
+ [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
+ [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
+ [PMUX_DRVGRP_DAP1] = "drive_dap1",
+ [PMUX_DRVGRP_DAP2] = "drive_dap2",
+ [PMUX_DRVGRP_DAP3] = "drive_dap3",
+ [PMUX_DRVGRP_DAP4] = "drive_dap4",
+ [PMUX_DRVGRP_DBG] = "drive_dbg",
+ [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
+ [PMUX_DRVGRP_SPI] = "drive_spi",
+ [PMUX_DRVGRP_UAA] = "drive_uaa",
+ [PMUX_DRVGRP_UAB] = "drive_uab",
+ [PMUX_DRVGRP_UART2] = "drive_uart2",
+ [PMUX_DRVGRP_UART3] = "drive_uart3",
+ [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
+ [PMUX_DRVGRP_DDC] = "drive_ddc",
+ [PMUX_DRVGRP_GMA] = "drive_gma",
+ [PMUX_DRVGRP_GME] = "drive_gme",
+ [PMUX_DRVGRP_GMF] = "drive_gmf",
+ [PMUX_DRVGRP_GMG] = "drive_gmg",
+ [PMUX_DRVGRP_GMH] = "drive_gmh",
+ [PMUX_DRVGRP_OWR] = "drive_owr",
+ [PMUX_DRVGRP_UDA] = "drive_uda",
+ [PMUX_DRVGRP_DEV3] = "drive_dev3",
+ [PMUX_DRVGRP_CEC] = "drive_cec",
+ [PMUX_DRVGRP_AT6] = "drive_at6",
+ [PMUX_DRVGRP_DAP5] = "drive_dap5",
+ [PMUX_DRVGRP_USB_VBUS_EN] = "drive_usb_vbus_en",
+ [PMUX_DRVGRP_AO3] = "drive_ao3",
+ [PMUX_DRVGRP_HV0] = "drive_hv0",
+ [PMUX_DRVGRP_SDIO4] = "drive_sdio4",
+ [PMUX_DRVGRP_AO0] = "drive_ao0",
+};
+
+static const char * const tegra_pinctrl_to_func[] = {
+ [PMUX_FUNC_DEFAULT] = "default",
+ [PMUX_FUNC_BLINK] = "blink",
+ [PMUX_FUNC_CEC] = "cec",
+ [PMUX_FUNC_CLDVFS] = "cldvfs",
+ [PMUX_FUNC_CLK] = "clk",
+ [PMUX_FUNC_CLK12] = "clk12",
+ [PMUX_FUNC_CPU] = "cpu",
+ [PMUX_FUNC_DAP] = "dap",
+ [PMUX_FUNC_DAP1] = "dap1",
+ [PMUX_FUNC_DAP2] = "dap2",
+ [PMUX_FUNC_DEV3] = "dev3",
+ [PMUX_FUNC_DISPLAYA] = "displaya",
+ [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
+ [PMUX_FUNC_DISPLAYB] = "displayb",
+ [PMUX_FUNC_DTV] = "dtv",
+ [PMUX_FUNC_EMC_DLL] = "emc_dll",
+ [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
+ [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
+ [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
+ [PMUX_FUNC_GMI] = "gmi",
+ [PMUX_FUNC_GMI_ALT] = "gmi_alt",
+ [PMUX_FUNC_HDA] = "hda",
+ [PMUX_FUNC_HSI] = "hsi",
+ [PMUX_FUNC_I2C1] = "i2c1",
+ [PMUX_FUNC_I2C2] = "i2c2",
+ [PMUX_FUNC_I2C3] = "i2c3",
+ [PMUX_FUNC_I2C4] = "i2c4",
+ [PMUX_FUNC_I2CPWR] = "i2cpwr",
+ [PMUX_FUNC_I2S0] = "i2s0",
+ [PMUX_FUNC_I2S1] = "i2s1",
+ [PMUX_FUNC_I2S2] = "i2s2",
+ [PMUX_FUNC_I2S3] = "i2s3",
+ [PMUX_FUNC_I2S4] = "i2s4",
+ [PMUX_FUNC_IRDA] = "irda",
+ [PMUX_FUNC_KBC] = "kbc",
+ [PMUX_FUNC_NAND] = "nand",
+ [PMUX_FUNC_NAND_ALT] = "nand_alt",
+ [PMUX_FUNC_OWR] = "owr",
+ [PMUX_FUNC_PMI] = "pmi",
+ [PMUX_FUNC_PWM0] = "pwm0",
+ [PMUX_FUNC_PWM1] = "pwm1",
+ [PMUX_FUNC_PWM2] = "pwm2",
+ [PMUX_FUNC_PWM3] = "pwm3",
+ [PMUX_FUNC_PWRON] = "pwron",
+ [PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
+ [PMUX_FUNC_RTCK] = "rtck",
+ [PMUX_FUNC_SDMMC1] = "sdmmc1",
+ [PMUX_FUNC_SDMMC2] = "sdmmc2",
+ [PMUX_FUNC_SDMMC3] = "sdmmc3",
+ [PMUX_FUNC_SDMMC4] = "sdmmc4",
+ [PMUX_FUNC_SOC] = "soc",
+ [PMUX_FUNC_SPDIF] = "spdif",
+ [PMUX_FUNC_SPI1] = "spi1",
+ [PMUX_FUNC_SPI2] = "spi2",
+ [PMUX_FUNC_SPI3] = "spi3",
+ [PMUX_FUNC_SPI4] = "spi4",
+ [PMUX_FUNC_SPI5] = "spi5",
+ [PMUX_FUNC_SPI6] = "spi6",
+ [PMUX_FUNC_SYSCLK] = "sysclk",
+ [PMUX_FUNC_TRACE] = "trace",
+ [PMUX_FUNC_UARTA] = "uarta",
+ [PMUX_FUNC_UARTB] = "uartb",
+ [PMUX_FUNC_UARTC] = "uartc",
+ [PMUX_FUNC_UARTD] = "uartd",
+ [PMUX_FUNC_ULPI] = "ulpi",
+ [PMUX_FUNC_USB] = "usb",
+ [PMUX_FUNC_VGP1] = "vgp1",
+ [PMUX_FUNC_VGP2] = "vgp2",
+ [PMUX_FUNC_VGP3] = "vgp3",
+ [PMUX_FUNC_VGP4] = "vgp4",
+ [PMUX_FUNC_VGP5] = "vgp5",
+ [PMUX_FUNC_VGP6] = "vgp6",
+ [PMUX_FUNC_VI] = "vi",
+ [PMUX_FUNC_VI_ALT1] = "vi_alt1",
+ [PMUX_FUNC_VI_ALT3] = "vi_alt3",
+ [PMUX_FUNC_RSVD1] = "rsvd1",
+ [PMUX_FUNC_RSVD2] = "rsvd2",
+ [PMUX_FUNC_RSVD3] = "rsvd3",
+ [PMUX_FUNC_RSVD4] = "rsvd4",
+};
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
PMUX_FUNC_COUNT,
};
+static const char * const tegra_pinctrl_to_pingrp[] = {
+ [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
+ [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
+ [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
+ [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
+ [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
+ [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
+ [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
+ [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
+ [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
+ [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
+ [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
+ [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
+ [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
+ [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
+ [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
+ [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
+ [PMUX_PINGRP_PV0] = "pv0",
+ [PMUX_PINGRP_PV1] = "pv1",
+ [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
+ [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
+ [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
+ [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
+ [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
+ [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
+ [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
+ [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
+ [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
+ [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
+ [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
+ [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
+ [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
+ [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
+ [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
+ [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
+ [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
+ [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
+ [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
+ [PMUX_PINGRP_PU0] = "pu0",
+ [PMUX_PINGRP_PU1] = "pu1",
+ [PMUX_PINGRP_PU2] = "pu2",
+ [PMUX_PINGRP_PU3] = "pu3",
+ [PMUX_PINGRP_PU4] = "pu4",
+ [PMUX_PINGRP_PU5] = "pu5",
+ [PMUX_PINGRP_PU6] = "pu6",
+ [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
+ [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
+ [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
+ [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
+ [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
+ [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
+ [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
+ [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
+ [PMUX_PINGRP_PC7] = "pc7",
+ [PMUX_PINGRP_PI5] = "pi5",
+ [PMUX_PINGRP_PI7] = "pi7",
+ [PMUX_PINGRP_PK0] = "pk0",
+ [PMUX_PINGRP_PK1] = "pk1",
+ [PMUX_PINGRP_PJ0] = "pj0",
+ [PMUX_PINGRP_PJ2] = "pj2",
+ [PMUX_PINGRP_PK3] = "pk3",
+ [PMUX_PINGRP_PK4] = "pk4",
+ [PMUX_PINGRP_PK2] = "pk2",
+ [PMUX_PINGRP_PI3] = "pi3",
+ [PMUX_PINGRP_PI6] = "pi6",
+ [PMUX_PINGRP_PG0] = "pg0",
+ [PMUX_PINGRP_PG1] = "pg1",
+ [PMUX_PINGRP_PG2] = "pg2",
+ [PMUX_PINGRP_PG3] = "pg3",
+ [PMUX_PINGRP_PG4] = "pg4",
+ [PMUX_PINGRP_PG5] = "pg5",
+ [PMUX_PINGRP_PG6] = "pg6",
+ [PMUX_PINGRP_PG7] = "pg7",
+ [PMUX_PINGRP_PH0] = "ph0",
+ [PMUX_PINGRP_PH1] = "ph1",
+ [PMUX_PINGRP_PH2] = "ph2",
+ [PMUX_PINGRP_PH3] = "ph3",
+ [PMUX_PINGRP_PH4] = "ph4",
+ [PMUX_PINGRP_PH5] = "ph5",
+ [PMUX_PINGRP_PH6] = "ph6",
+ [PMUX_PINGRP_PH7] = "ph7",
+ [PMUX_PINGRP_PJ7] = "pj7",
+ [PMUX_PINGRP_PB0] = "pb0",
+ [PMUX_PINGRP_PB1] = "pb1",
+ [PMUX_PINGRP_PK7] = "pk7",
+ [PMUX_PINGRP_PI0] = "pi0",
+ [PMUX_PINGRP_PI1] = "pi1",
+ [PMUX_PINGRP_PI2] = "pi2",
+ [PMUX_PINGRP_PI4] = "pi4",
+ [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
+ [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
+ [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
+ [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
+ [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
+ [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
+ [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
+ [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
+ [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
+ [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
+ [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
+ [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
+ [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
+ [PMUX_PINGRP_PCC1] = "pcc1",
+ [PMUX_PINGRP_PBB0] = "pbb0",
+ [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
+ [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
+ [PMUX_PINGRP_PBB3] = "pbb3",
+ [PMUX_PINGRP_PBB4] = "pbb4",
+ [PMUX_PINGRP_PBB5] = "pbb5",
+ [PMUX_PINGRP_PBB6] = "pbb6",
+ [PMUX_PINGRP_PBB7] = "pbb7",
+ [PMUX_PINGRP_PCC2] = "pcc2",
+ [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
+ [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
+ [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
+ [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
+ [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
+ [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
+ [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
+ [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
+ [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
+ [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
+ [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
+ [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
+ [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
+ [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
+ [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
+ [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
+ [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
+ [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
+ [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
+ [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
+ [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
+ [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
+ [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
+ [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
+ [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
+ [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
+ [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
+ [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
+ [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
+ [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_PINGRP_OWR] = "owr",
+ [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
+ [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
+ [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
+ [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
+ [PMUX_PINGRP_DAP_MCLK1_REQ_PEE2] = "dap_mclk1_req_pee2",
+ [PMUX_PINGRP_DAP_MCLK1_PW4] = "dap_mclk1_pw4",
+ [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
+ [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
+ [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
+ [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
+ [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
+ [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
+ [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
+ [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
+ [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
+ [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
+ [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
+ [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
+ [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
+ [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
+ [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
+ [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
+ [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
+ [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
+ [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
+ [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
+ [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
+ [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
+ [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
+ [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
+ [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
+ [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
+ [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
+ [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
+ [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
+ [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
+ [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
+ [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
+ [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
+ [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
+ [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
+ [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
+ [PMUX_PINGRP_KB_ROW16_PT0] = "kb_row16_pt0",
+ [PMUX_PINGRP_KB_ROW17_PT1] = "kb_row17_pt1",
+ [PMUX_PINGRP_USB_VBUS_EN2_PFF1] = "usb_vbus_en2_pff1",
+ [PMUX_PINGRP_PFF2] = "pff2",
+ [PMUX_PINGRP_DP_HPD_PFF0] = "dp_hpd_pff0",
+};
+
+static const char * const tegra_pinctrl_to_drvgrp[] = {
+ [PMUX_DRVGRP_AO1] = "ao1",
+ [PMUX_DRVGRP_AO2] = "ao2",
+ [PMUX_DRVGRP_AT1] = "at1",
+ [PMUX_DRVGRP_AT2] = "at2",
+ [PMUX_DRVGRP_AT3] = "at3",
+ [PMUX_DRVGRP_AT4] = "at4",
+ [PMUX_DRVGRP_AT5] = "at5",
+ [PMUX_DRVGRP_CDEV1] = "cdev1",
+ [PMUX_DRVGRP_CDEV2] = "cdev2",
+ [PMUX_DRVGRP_DAP1] = "dap1",
+ [PMUX_DRVGRP_DAP2] = "dap2",
+ [PMUX_DRVGRP_DAP3] = "dap3",
+ [PMUX_DRVGRP_DAP4] = "dap4",
+ [PMUX_DRVGRP_DBG] = "dbg",
+ [PMUX_DRVGRP_SDIO3] = "sdio3",
+ [PMUX_DRVGRP_SPI] = "spi",
+ [PMUX_DRVGRP_UAA] = "uaa",
+ [PMUX_DRVGRP_UAB] = "uab",
+ [PMUX_DRVGRP_UART2] = "uart2",
+ [PMUX_DRVGRP_UART3] = "uart3",
+ [PMUX_DRVGRP_SDIO1] = "sdio1",
+ [PMUX_DRVGRP_DDC] = "ddc",
+ [PMUX_DRVGRP_GMA] = "gma",
+ [PMUX_DRVGRP_GME] = "gme",
+ [PMUX_DRVGRP_GMF] = "gmf",
+ [PMUX_DRVGRP_GMG] = "gmg",
+ [PMUX_DRVGRP_GMH] = "gmh",
+ [PMUX_DRVGRP_OWR] = "owr",
+ [PMUX_DRVGRP_UDA] = "uda",
+ [PMUX_DRVGRP_GPV] = "gpv",
+ [PMUX_DRVGRP_DEV3] = "dev3",
+ [PMUX_DRVGRP_CEC] = "cec",
+ [PMUX_DRVGRP_AT6] = "at6",
+ [PMUX_DRVGRP_DAP5] = "dap5",
+ [PMUX_DRVGRP_USB_VBUS_EN] = "usb_vbus_en",
+ [PMUX_DRVGRP_AO3] = "ao3",
+ [PMUX_DRVGRP_AO0] = "ao0",
+ [PMUX_DRVGRP_HV0] = "hv0",
+ [PMUX_DRVGRP_SDIO4] = "sdio4",
+ [PMUX_DRVGRP_AO4] = "ao4",
+};
+
+static const char * const tegra_pinctrl_to_func[] = {
+ [PMUX_FUNC_DEFAULT] = "default",
+ [PMUX_FUNC_BLINK] = "blink",
+ [PMUX_FUNC_CCLA] = "ccla",
+ [PMUX_FUNC_CEC] = "cec",
+ [PMUX_FUNC_CLDVFS] = "cldvfs",
+ [PMUX_FUNC_CLK] = "clk",
+ [PMUX_FUNC_CLK12] = "clk12",
+ [PMUX_FUNC_CPU] = "cpu",
+ [PMUX_FUNC_CSI] = "csi",
+ [PMUX_FUNC_DAP] = "dap",
+ [PMUX_FUNC_DAP1] = "dap1",
+ [PMUX_FUNC_DAP2] = "dap2",
+ [PMUX_FUNC_DEV3] = "dev3",
+ [PMUX_FUNC_DISPLAYA] = "displaya",
+ [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
+ [PMUX_FUNC_DISPLAYB] = "displayb",
+ [PMUX_FUNC_DP] = "dp",
+ [PMUX_FUNC_DSI_B] = "dsi_b",
+ [PMUX_FUNC_DTV] = "dtv",
+ [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
+ [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
+ [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
+ [PMUX_FUNC_GMI] = "gmi",
+ [PMUX_FUNC_GMI_ALT] = "gmi_alt",
+ [PMUX_FUNC_HDA] = "hda",
+ [PMUX_FUNC_HSI] = "hsi",
+ [PMUX_FUNC_I2C1] = "i2c1",
+ [PMUX_FUNC_I2C2] = "i2c2",
+ [PMUX_FUNC_I2C3] = "i2c3",
+ [PMUX_FUNC_I2C4] = "i2c4",
+ [PMUX_FUNC_I2CPWR] = "i2cpwr",
+ [PMUX_FUNC_I2S0] = "i2s0",
+ [PMUX_FUNC_I2S1] = "i2s1",
+ [PMUX_FUNC_I2S2] = "i2s2",
+ [PMUX_FUNC_I2S3] = "i2s3",
+ [PMUX_FUNC_I2S4] = "i2s4",
+ [PMUX_FUNC_IRDA] = "irda",
+ [PMUX_FUNC_KBC] = "kbc",
+ [PMUX_FUNC_OWR] = "owr",
+ [PMUX_FUNC_PE] = "pe",
+ [PMUX_FUNC_PE0] = "pe0",
+ [PMUX_FUNC_PE1] = "pe1",
+ [PMUX_FUNC_PMI] = "pmi",
+ [PMUX_FUNC_PWM0] = "pwm0",
+ [PMUX_FUNC_PWM1] = "pwm1",
+ [PMUX_FUNC_PWM2] = "pwm2",
+ [PMUX_FUNC_PWM3] = "pwm3",
+ [PMUX_FUNC_PWRON] = "pwron",
+ [PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
+ [PMUX_FUNC_RTCK] = "rtck",
+ [PMUX_FUNC_SATA] = "sata",
+ [PMUX_FUNC_SDMMC1] = "sdmmc1",
+ [PMUX_FUNC_SDMMC2] = "sdmmc2",
+ [PMUX_FUNC_SDMMC3] = "sdmmc3",
+ [PMUX_FUNC_SDMMC4] = "sdmmc4",
+ [PMUX_FUNC_SOC] = "soc",
+ [PMUX_FUNC_SPDIF] = "spdif",
+ [PMUX_FUNC_SPI1] = "spi1",
+ [PMUX_FUNC_SPI2] = "spi2",
+ [PMUX_FUNC_SPI3] = "spi3",
+ [PMUX_FUNC_SPI4] = "spi4",
+ [PMUX_FUNC_SPI5] = "spi5",
+ [PMUX_FUNC_SPI6] = "spi6",
+ [PMUX_FUNC_SYS] = "sys",
+ [PMUX_FUNC_TMDS] = "tmds",
+ [PMUX_FUNC_TRACE] = "trace",
+ [PMUX_FUNC_UARTA] = "uarta",
+ [PMUX_FUNC_UARTB] = "uartb",
+ [PMUX_FUNC_UARTC] = "uartc",
+ [PMUX_FUNC_UARTD] = "uartd",
+ [PMUX_FUNC_ULPI] = "ulpi",
+ [PMUX_FUNC_USB] = "usb",
+ [PMUX_FUNC_VGP1] = "vgp1",
+ [PMUX_FUNC_VGP2] = "vgp2",
+ [PMUX_FUNC_VGP3] = "vgp3",
+ [PMUX_FUNC_VGP4] = "vgp4",
+ [PMUX_FUNC_VGP5] = "vgp5",
+ [PMUX_FUNC_VGP6] = "vgp6",
+ [PMUX_FUNC_VI] = "vi",
+ [PMUX_FUNC_VI_ALT1] = "vi_alt1",
+ [PMUX_FUNC_VI_ALT3] = "vi_alt3",
+ [PMUX_FUNC_VIMCLK2] = "vimclk2",
+ [PMUX_FUNC_VIMCLK2_ALT] = "vimclk2_alt",
+ [PMUX_FUNC_RSVD1] = "rsvd1",
+ [PMUX_FUNC_RSVD2] = "rsvd2",
+ [PMUX_FUNC_RSVD3] = "rsvd3",
+ [PMUX_FUNC_RSVD4] = "rsvd4",
+};
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
PMUX_PINGRP_COUNT,
};
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_CSUS,
+ PMUX_DRVGRP_DAP1,
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_LCD1,
+ PMUX_DRVGRP_LCD2,
+ PMUX_DRVGRP_SDIO2,
+ PMUX_DRVGRP_SDIO3,
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_VI1,
+ PMUX_DRVGRP_VI2,
+ PMUX_DRVGRP_XM2A,
+ PMUX_DRVGRP_XM2C,
+ PMUX_DRVGRP_XM2D,
+ PMUX_DRVGRP_XM2CLK,
+ PMUX_DRVGRP_SDIO1 = (0x78 / 4),
+ PMUX_DRVGRP_CRT = (0x84 / 4),
+ PMUX_DRVGRP_DDC,
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GMB,
+ PMUX_DRVGRP_GMC,
+ PMUX_DRVGRP_GMD,
+ PMUX_DRVGRP_GME,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_COUNT,
+};
+
/*
* Functions which can be assigned to each of the pin groups. The values here
* bear no relation to the values programmed into pinmux registers and are
PMUX_FUNC_COUNT,
};
+static const char * const tegra_pinctrl_to_pingrp[] = {
+ /* APB_MISC_PP_TRISTATE_REG_A_0 */
+ [PMUX_PINGRP_ATA] = "ata",
+ [PMUX_PINGRP_ATB] = "atb",
+ [PMUX_PINGRP_ATC] = "atc",
+ [PMUX_PINGRP_ATD] = "atd",
+ [PMUX_PINGRP_CDEV1] = "cdev1",
+ [PMUX_PINGRP_CDEV2] = "cdev2",
+ [PMUX_PINGRP_CSUS] = "csus",
+ [PMUX_PINGRP_DAP1] = "dap1",
+
+ [PMUX_PINGRP_DAP2] = "dap2",
+ [PMUX_PINGRP_DAP3] = "dap3",
+ [PMUX_PINGRP_DAP4] = "dap4",
+ [PMUX_PINGRP_DTA] = "dta",
+ [PMUX_PINGRP_DTB] = "dtb",
+ [PMUX_PINGRP_DTC] = "dtc",
+ [PMUX_PINGRP_DTD] = "dtd",
+ [PMUX_PINGRP_DTE] = "dte",
+
+ [PMUX_PINGRP_GPU] = "gpu",
+ [PMUX_PINGRP_GPV] = "gpv",
+ [PMUX_PINGRP_I2CP] = "i2cp",
+ [PMUX_PINGRP_IRTX] = "irtx",
+ [PMUX_PINGRP_IRRX] = "irrx",
+ [PMUX_PINGRP_KBCB] = "kbcb",
+ [PMUX_PINGRP_KBCA] = "kbca",
+ [PMUX_PINGRP_PMC] = "pmc",
+
+ [PMUX_PINGRP_PTA] = "pta",
+ [PMUX_PINGRP_RM] = "rm",
+ [PMUX_PINGRP_KBCE] = "kbce",
+ [PMUX_PINGRP_KBCF] = "kbcf",
+ [PMUX_PINGRP_GMA] = "gma",
+ [PMUX_PINGRP_GMC] = "gmc",
+ [PMUX_PINGRP_SDIO1] = "sdio1",
+ [PMUX_PINGRP_OWC] = "owc",
+
+ /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
+ [PMUX_PINGRP_GME] = "gme",
+ [PMUX_PINGRP_SDC] = "sdc",
+ [PMUX_PINGRP_SDD] = "sdd",
+ [PMUX_PINGRP_RESERVED0] = "reserved0",
+ [PMUX_PINGRP_SLXA] = "slxa",
+ [PMUX_PINGRP_SLXC] = "slxc",
+ [PMUX_PINGRP_SLXD] = "slxd",
+ [PMUX_PINGRP_SLXK] = "slxk",
+
+ [PMUX_PINGRP_SPDI] = "spdi",
+ [PMUX_PINGRP_SPDO] = "spdo",
+ [PMUX_PINGRP_SPIA] = "spia",
+ [PMUX_PINGRP_SPIB] = "spib",
+ [PMUX_PINGRP_SPIC] = "spic",
+ [PMUX_PINGRP_SPID] = "spid",
+ [PMUX_PINGRP_SPIE] = "spie",
+ [PMUX_PINGRP_SPIF] = "spif",
+
+ [PMUX_PINGRP_SPIG] = "spig",
+ [PMUX_PINGRP_SPIH] = "spih",
+ [PMUX_PINGRP_UAA] = "uaa",
+ [PMUX_PINGRP_UAB] = "uab",
+ [PMUX_PINGRP_UAC] = "uac",
+ [PMUX_PINGRP_UAD] = "uad",
+ [PMUX_PINGRP_UCA] = "uca",
+ [PMUX_PINGRP_UCB] = "ucb",
+
+ [PMUX_PINGRP_RESERVED1] = "reserved1",
+ [PMUX_PINGRP_ATE] = "ate",
+ [PMUX_PINGRP_KBCC] = "kbcc",
+ [PMUX_PINGRP_RESERVED2] = "reserved2",
+ [PMUX_PINGRP_RESERVED3] = "reserved3",
+ [PMUX_PINGRP_GMB] = "gmb",
+ [PMUX_PINGRP_GMD] = "gmd",
+ [PMUX_PINGRP_DDC] = "ddc",
+
+ /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
+ [PMUX_PINGRP_LD0] = "ld0",
+ [PMUX_PINGRP_LD1] = "ld1",
+ [PMUX_PINGRP_LD2] = "ld2",
+ [PMUX_PINGRP_LD3] = "ld3",
+ [PMUX_PINGRP_LD4] = "ld4",
+ [PMUX_PINGRP_LD5] = "ld5",
+ [PMUX_PINGRP_LD6] = "ld6",
+ [PMUX_PINGRP_LD7] = "ld7",
+
+ [PMUX_PINGRP_LD8] = "ld8",
+ [PMUX_PINGRP_LD9] = "ld9",
+ [PMUX_PINGRP_LD10] = "ld10",
+ [PMUX_PINGRP_LD11] = "ld11",
+ [PMUX_PINGRP_LD12] = "ld12",
+ [PMUX_PINGRP_LD13] = "ld13",
+ [PMUX_PINGRP_LD14] = "ld14",
+ [PMUX_PINGRP_LD15] = "ld15",
+
+ [PMUX_PINGRP_LD16] = "ld16",
+ [PMUX_PINGRP_LD17] = "ld17",
+ [PMUX_PINGRP_LHP0] = "lhp0",
+ [PMUX_PINGRP_LHP1] = "lhp1",
+ [PMUX_PINGRP_LHP2] = "lhp2",
+ [PMUX_PINGRP_LVP0] = "lvp0",
+ [PMUX_PINGRP_LVP1] = "lvp1",
+ [PMUX_PINGRP_HDINT] = "hdint",
+
+ [PMUX_PINGRP_LM0] = "lm0",
+ [PMUX_PINGRP_LM1] = "lm1",
+ [PMUX_PINGRP_LVS] = "lvs",
+ [PMUX_PINGRP_LSC0] = "lsc0",
+ [PMUX_PINGRP_LSC1] = "lsc1",
+ [PMUX_PINGRP_LSCK] = "lsck",
+ [PMUX_PINGRP_LDC] = "ldc",
+ [PMUX_PINGRP_LCSN] = "lcsn",
+
+ /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
+ [PMUX_PINGRP_LSPI] = "lspi",
+ [PMUX_PINGRP_LSDA] = "lsda",
+ [PMUX_PINGRP_LSDI] = "lsdi",
+ [PMUX_PINGRP_LPW0] = "lpw0",
+ [PMUX_PINGRP_LPW1] = "lpw1",
+ [PMUX_PINGRP_LPW2] = "lpw2",
+ [PMUX_PINGRP_LDI] = "ldi",
+ [PMUX_PINGRP_LHS] = "lhs",
+
+ [PMUX_PINGRP_LPP] = "lpp",
+ [PMUX_PINGRP_RESERVED4] = "reserved4",
+ [PMUX_PINGRP_KBCD] = "kbcd",
+ [PMUX_PINGRP_GPU7] = "gpu7",
+ [PMUX_PINGRP_DTF] = "dtf",
+ [PMUX_PINGRP_UDA] = "uda",
+ [PMUX_PINGRP_CRTP] = "crtp",
+ [PMUX_PINGRP_SDB] = "sdb",
+
+ /* these pin groups only have pullup and pull down control */
+ [PMUX_PINGRP_CK32] = "ck32",
+ [PMUX_PINGRP_DDRC] = "ddrc",
+ [PMUX_PINGRP_PMCA] = "pmca",
+ [PMUX_PINGRP_PMCB] = "pmcb",
+ [PMUX_PINGRP_PMCC] = "pmcc",
+ [PMUX_PINGRP_PMCD] = "pmcd",
+ [PMUX_PINGRP_PMCE] = "pmce",
+ [PMUX_PINGRP_XM2C] = "xm2c",
+ [PMUX_PINGRP_XM2D] = "xm2d",
+};
+
+static const char * const tegra_pinctrl_to_drvgrp[] = {
+ [PMUX_DRVGRP_AO1] = "drive_ao1",
+ [PMUX_DRVGRP_AO2] = "drive_ao2",
+ [PMUX_DRVGRP_AT1] = "drive_at1",
+ [PMUX_DRVGRP_AT2] = "drive_at2",
+ [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
+ [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
+ [PMUX_DRVGRP_CSUS] = "drive_csus",
+ [PMUX_DRVGRP_DAP1] = "drive_dap1",
+ [PMUX_DRVGRP_DAP2] = "drive_dap2",
+ [PMUX_DRVGRP_DAP3] = "drive_dap3",
+ [PMUX_DRVGRP_DAP4] = "drive_dap4",
+ [PMUX_DRVGRP_DBG] = "drive_dbg",
+ [PMUX_DRVGRP_LCD1] = "drive_lcd1",
+ [PMUX_DRVGRP_LCD2] = "drive_lcd2",
+ [PMUX_DRVGRP_SDIO2] = "drive_sdio2",
+ [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
+ [PMUX_DRVGRP_SPI] = "drive_spi",
+ [PMUX_DRVGRP_UAA] = "drive_uaa",
+ [PMUX_DRVGRP_UAB] = "drive_uab",
+ [PMUX_DRVGRP_UART2] = "drive_uart2",
+ [PMUX_DRVGRP_UART3] = "drive_uart3",
+ [PMUX_DRVGRP_VI1] = "drive_vi1",
+ [PMUX_DRVGRP_VI2] = "drive_vi2",
+ [PMUX_DRVGRP_XM2A] = "drive_xm2a",
+ [PMUX_DRVGRP_XM2C] = "drive_xm2c",
+ [PMUX_DRVGRP_XM2D] = "drive_xm2d",
+ [PMUX_DRVGRP_XM2CLK] = "drive_xm2clk",
+ [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
+ [PMUX_DRVGRP_CRT] = "drive_crt",
+ [PMUX_DRVGRP_DDC] = "drive_ddc",
+ [PMUX_DRVGRP_GMA] = "drive_gma",
+ [PMUX_DRVGRP_GMB] = "drive_gmb",
+ [PMUX_DRVGRP_GMC] = "drive_gmc",
+ [PMUX_DRVGRP_GMD] = "drive_gmd",
+ [PMUX_DRVGRP_GME] = "drive_gme",
+ [PMUX_DRVGRP_OWR] = "drive_owr",
+ [PMUX_DRVGRP_UDA] = "drive_uda",
+};
+
+static const char * const tegra_pinctrl_to_func[] = {
+ [PMUX_FUNC_DEFAULT] = "default",
+ [PMUX_FUNC_AHB_CLK] = "ahb_clk",
+ [PMUX_FUNC_APB_CLK] = "apb_clk",
+ [PMUX_FUNC_AUDIO_SYNC] = "audio_sync",
+ [PMUX_FUNC_CRT] = "crt",
+ [PMUX_FUNC_DAP1] = "dap1",
+ [PMUX_FUNC_DAP2] = "dap2",
+ [PMUX_FUNC_DAP3] = "dap3",
+ [PMUX_FUNC_DAP4] = "dap4",
+ [PMUX_FUNC_DAP5] = "dap5",
+ [PMUX_FUNC_DISPA] = "dispa",
+ [PMUX_FUNC_DISPB] = "dispb",
+ [PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
+ [PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
+ [PMUX_FUNC_GMI] = "gmi",
+ [PMUX_FUNC_GMI_INT] = "gmi_int",
+ [PMUX_FUNC_HDMI] = "hdmi",
+ [PMUX_FUNC_I2C] = "i2c",
+ [PMUX_FUNC_I2C2] = "i2c2",
+ [PMUX_FUNC_I2C3] = "i2c3",
+ [PMUX_FUNC_IDE] = "ide",
+ [PMUX_FUNC_KBC] = "kbc",
+ [PMUX_FUNC_MIO] = "mio",
+ [PMUX_FUNC_MIPI_HS] = "mipi_hs",
+ [PMUX_FUNC_NAND] = "nand",
+ [PMUX_FUNC_OSC] = "osc",
+ [PMUX_FUNC_OWR] = "owr",
+ [PMUX_FUNC_PCIE] = "pcie",
+ [PMUX_FUNC_PLLA_OUT] = "plla_out",
+ [PMUX_FUNC_PLLC_OUT1] = "pllc_out1",
+ [PMUX_FUNC_PLLM_OUT1] = "pllm_out1",
+ [PMUX_FUNC_PLLP_OUT2] = "pllp_out2",
+ [PMUX_FUNC_PLLP_OUT3] = "pllp_out3",
+ [PMUX_FUNC_PLLP_OUT4] = "pllp_out4",
+ [PMUX_FUNC_PWM] = "pwm",
+ [PMUX_FUNC_PWR_INTR] = "pwr_intr",
+ [PMUX_FUNC_PWR_ON] = "pwr_on",
+ [PMUX_FUNC_RTCK] = "rtck",
+ [PMUX_FUNC_SDIO1] = "sdio1",
+ [PMUX_FUNC_SDIO2] = "sdio2",
+ [PMUX_FUNC_SDIO3] = "sdio3",
+ [PMUX_FUNC_SDIO4] = "sdio4",
+ [PMUX_FUNC_SFLASH] = "sflash",
+ [PMUX_FUNC_SPDIF] = "spdif",
+ [PMUX_FUNC_SPI1] = "spi1",
+ [PMUX_FUNC_SPI2] = "spi2",
+ [PMUX_FUNC_SPI2_ALT] = "spi2_alt",
+ [PMUX_FUNC_SPI3] = "spi3",
+ [PMUX_FUNC_SPI4] = "spi4",
+ [PMUX_FUNC_TRACE] = "trace",
+ [PMUX_FUNC_TWC] = "twc",
+ [PMUX_FUNC_UARTA] = "uarta",
+ [PMUX_FUNC_UARTB] = "uartb",
+ [PMUX_FUNC_UARTC] = "uartc",
+ [PMUX_FUNC_UARTD] = "uartd",
+ [PMUX_FUNC_UARTE] = "uarte",
+ [PMUX_FUNC_ULPI] = "ulpi",
+ [PMUX_FUNC_VI] = "vi",
+ [PMUX_FUNC_VI_SENSOR_CLK] = "vi_sensor_clk",
+ [PMUX_FUNC_XIO] = "xio",
+ [PMUX_FUNC_RSVD1] = "rsvd1",
+ [PMUX_FUNC_RSVD2] = "rsvd2",
+ [PMUX_FUNC_RSVD3] = "rsvd3",
+ [PMUX_FUNC_RSVD4] = "rsvd4",
+};
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#include <asm/arch-tegra/pinmux.h>
PMUX_FUNC_COUNT,
};
+static const char * const tegra_pinctrl_to_pingrp[] = {
+ [PMUX_PINGRP_SDMMC1_CLK_PM0] = "sdmmc1_clk_pm0",
+ [PMUX_PINGRP_SDMMC1_CMD_PM1] = "sdmmc1_cmd_pm1",
+ [PMUX_PINGRP_SDMMC1_DAT3_PM2] = "sdmmc1_dat3_pm2",
+ [PMUX_PINGRP_SDMMC1_DAT2_PM3] = "sdmmc1_dat2_pm3",
+ [PMUX_PINGRP_SDMMC1_DAT1_PM4] = "sdmmc1_dat1_pm4",
+ [PMUX_PINGRP_SDMMC1_DAT0_PM5] = "sdmmc1_dat0_pm5",
+ [PMUX_PINGRP_SDMMC3_CLK_PP0] = "sdmmc3_clk_pp0",
+ [PMUX_PINGRP_SDMMC3_CMD_PP1] = "sdmmc3_cmd_pp1",
+ [PMUX_PINGRP_SDMMC3_DAT0_PP5] = "sdmmc3_dat0_pp5",
+ [PMUX_PINGRP_SDMMC3_DAT1_PP4] = "sdmmc3_dat1_pp4",
+ [PMUX_PINGRP_SDMMC3_DAT2_PP3] = "sdmmc3_dat2_pp3",
+ [PMUX_PINGRP_SDMMC3_DAT3_PP2] = "sdmmc3_dat3_pp2",
+ [PMUX_PINGRP_PEX_L0_RST_N_PA0] = "pex_l0_rst_n_pa0",
+ [PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1] = "pex_l0_clkreq_n_pa1",
+ [PMUX_PINGRP_PEX_WAKE_N_PA2] = "pex_wake_n_pa2",
+ [PMUX_PINGRP_PEX_L1_RST_N_PA3] = "pex_l1_rst_n_pa3",
+ [PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4] = "pex_l1_clkreq_n_pa4",
+ [PMUX_PINGRP_SATA_LED_ACTIVE_PA5] = "sata_led_active_pa5",
+ [PMUX_PINGRP_SPI1_MOSI_PC0] = "spi1_mosi_pc0",
+ [PMUX_PINGRP_SPI1_MISO_PC1] = "spi1_miso_pc1",
+ [PMUX_PINGRP_SPI1_SCK_PC2] = "spi1_sck_pc2",
+ [PMUX_PINGRP_SPI1_CS0_PC3] = "spi1_cs0_pc3",
+ [PMUX_PINGRP_SPI1_CS1_PC4] = "spi1_cs1_pc4",
+ [PMUX_PINGRP_SPI2_MOSI_PB4] = "spi2_mosi_pb4",
+ [PMUX_PINGRP_SPI2_MISO_PB5] = "spi2_miso_pb5",
+ [PMUX_PINGRP_SPI2_SCK_PB6] = "spi2_sck_pb6",
+ [PMUX_PINGRP_SPI2_CS0_PB7] = "spi2_cs0_pb7",
+ [PMUX_PINGRP_SPI2_CS1_PDD0] = "spi2_cs1_pdd0",
+ [PMUX_PINGRP_SPI4_MOSI_PC7] = "spi4_mosi_pc7",
+ [PMUX_PINGRP_SPI4_MISO_PD0] = "spi4_miso_pd0",
+ [PMUX_PINGRP_SPI4_SCK_PC5] = "spi4_sck_pc5",
+ [PMUX_PINGRP_SPI4_CS0_PC6] = "spi4_cs0_pc6",
+ [PMUX_PINGRP_QSPI_SCK_PEE0] = "qspi_sck_pee0",
+ [PMUX_PINGRP_QSPI_CS_N_PEE1] = "qspi_cs_n_pee1",
+ [PMUX_PINGRP_QSPI_IO0_PEE2] = "qspi_io0_pee2",
+ [PMUX_PINGRP_QSPI_IO1_PEE3] = "qspi_io1_pee3",
+ [PMUX_PINGRP_QSPI_IO2_PEE4] = "qspi_io2_pee4",
+ [PMUX_PINGRP_QSPI_IO3_PEE5] = "qspi_io3_pee5",
+ [PMUX_PINGRP_DMIC1_CLK_PE0] = "dmic1_clk_pe0",
+ [PMUX_PINGRP_DMIC1_DAT_PE1] = "dmic1_dat_pe1",
+ [PMUX_PINGRP_DMIC2_CLK_PE2] = "dmic2_clk_pe2",
+ [PMUX_PINGRP_DMIC2_DAT_PE3] = "dmic2_dat_pe3",
+ [PMUX_PINGRP_DMIC3_CLK_PE4] = "dmic3_clk_pe4",
+ [PMUX_PINGRP_DMIC3_DAT_PE5] = "dmic3_dat_pe5",
+ [PMUX_PINGRP_GEN1_I2C_SCL_PJ1] = "gen1_i2c_scl_pj1",
+ [PMUX_PINGRP_GEN1_I2C_SDA_PJ0] = "gen1_i2c_sda_pj0",
+ [PMUX_PINGRP_GEN2_I2C_SCL_PJ2] = "gen2_i2c_scl_pj2",
+ [PMUX_PINGRP_GEN2_I2C_SDA_PJ3] = "gen2_i2c_sda_pj3",
+ [PMUX_PINGRP_GEN3_I2C_SCL_PF0] = "gen3_i2c_scl_pf0",
+ [PMUX_PINGRP_GEN3_I2C_SDA_PF1] = "gen3_i2c_sda_pf1",
+ [PMUX_PINGRP_CAM_I2C_SCL_PS2] = "cam_i2c_scl_ps2",
+ [PMUX_PINGRP_CAM_I2C_SDA_PS3] = "cam_i2c_sda_ps3",
+ [PMUX_PINGRP_PWR_I2C_SCL_PY3] = "pwr_i2c_scl_py3",
+ [PMUX_PINGRP_PWR_I2C_SDA_PY4] = "pwr_i2c_sda_py4",
+ [PMUX_PINGRP_UART1_TX_PU0] = "uart1_tx_pu0",
+ [PMUX_PINGRP_UART1_RX_PU1] = "uart1_rx_pu1",
+ [PMUX_PINGRP_UART1_RTS_PU2] = "uart1_rts_pu2",
+ [PMUX_PINGRP_UART1_CTS_PU3] = "uart1_cts_pu3",
+ [PMUX_PINGRP_UART2_TX_PG0] = "uart2_tx_pg0",
+ [PMUX_PINGRP_UART2_RX_PG1] = "uart2_rx_pg1",
+ [PMUX_PINGRP_UART2_RTS_PG2] = "uart2_rts_pg2",
+ [PMUX_PINGRP_UART2_CTS_PG3] = "uart2_cts_pg3",
+ [PMUX_PINGRP_UART3_TX_PD1] = "uart3_tx_pd1",
+ [PMUX_PINGRP_UART3_RX_PD2] = "uart3_rx_pd2",
+ [PMUX_PINGRP_UART3_RTS_PD3] = "uart3_rts_pd3",
+ [PMUX_PINGRP_UART3_CTS_PD4] = "uart3_cts_pd4",
+ [PMUX_PINGRP_UART4_TX_PI4] = "uart4_tx_pi4",
+ [PMUX_PINGRP_UART4_RX_PI5] = "uart4_rx_pi5",
+ [PMUX_PINGRP_UART4_RTS_PI6] = "uart4_rts_pi6",
+ [PMUX_PINGRP_UART4_CTS_PI7] = "uart4_cts_pi7",
+ [PMUX_PINGRP_DAP1_FS_PB0] = "dap1_fs_pb0",
+ [PMUX_PINGRP_DAP1_DIN_PB1] = "dap1_din_pb1",
+ [PMUX_PINGRP_DAP1_DOUT_PB2] = "dap1_dout_pb2",
+ [PMUX_PINGRP_DAP1_SCLK_PB3] = "dap1_sclk_pb3",
+ [PMUX_PINGRP_DAP2_FS_PAA0] = "dap2_fs_paa0",
+ [PMUX_PINGRP_DAP2_DIN_PAA2] = "dap2_din_paa2",
+ [PMUX_PINGRP_DAP2_DOUT_PAA3] = "dap2_dout_paa3",
+ [PMUX_PINGRP_DAP2_SCLK_PAA1] = "dap2_sclk_paa1",
+ [PMUX_PINGRP_DAP4_FS_PJ4] = "dap4_fs_pj4",
+ [PMUX_PINGRP_DAP4_DIN_PJ5] = "dap4_din_pj5",
+ [PMUX_PINGRP_DAP4_DOUT_PJ6] = "dap4_dout_pj6",
+ [PMUX_PINGRP_DAP4_SCLK_PJ7] = "dap4_sclk_pj7",
+ [PMUX_PINGRP_CAM1_MCLK_PS0] = "cam1_mclk_ps0",
+ [PMUX_PINGRP_CAM2_MCLK_PS1] = "cam2_mclk_ps1",
+ [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
+ [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_PINGRP_CLK_32K_OUT_PY5] = "clk_32k_out_py5",
+ [PMUX_PINGRP_BATT_BCL] = "batt_bcl",
+ [PMUX_PINGRP_CLK_REQ] = "clk_req",
+ [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
+ [PMUX_PINGRP_SHUTDOWN] = "shutdown",
+ [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_PINGRP_AUD_MCLK_PBB0] = "aud_mclk_pbb0",
+ [PMUX_PINGRP_DVFS_PWM_PBB1] = "dvfs_pwm_pbb1",
+ [PMUX_PINGRP_DVFS_CLK_PBB2] = "dvfs_clk_pbb2",
+ [PMUX_PINGRP_GPIO_X1_AUD_PBB3] = "gpio_x1_aud_pbb3",
+ [PMUX_PINGRP_GPIO_X3_AUD_PBB4] = "gpio_x3_aud_pbb4",
+ [PMUX_PINGRP_PCC7] = "pcc7",
+ [PMUX_PINGRP_HDMI_CEC_PCC0] = "hdmi_cec_pcc0",
+ [PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1] = "hdmi_int_dp_hpd_pcc1",
+ [PMUX_PINGRP_SPDIF_OUT_PCC2] = "spdif_out_pcc2",
+ [PMUX_PINGRP_SPDIF_IN_PCC3] = "spdif_in_pcc3",
+ [PMUX_PINGRP_USB_VBUS_EN0_PCC4] = "usb_vbus_en0_pcc4",
+ [PMUX_PINGRP_USB_VBUS_EN1_PCC5] = "usb_vbus_en1_pcc5",
+ [PMUX_PINGRP_DP_HPD0_PCC6] = "dp_hpd0_pcc6",
+ [PMUX_PINGRP_WIFI_EN_PH0] = "wifi_en_ph0",
+ [PMUX_PINGRP_WIFI_RST_PH1] = "wifi_rst_ph1",
+ [PMUX_PINGRP_WIFI_WAKE_AP_PH2] = "wifi_wake_ap_ph2",
+ [PMUX_PINGRP_AP_WAKE_BT_PH3] = "ap_wake_bt_ph3",
+ [PMUX_PINGRP_BT_RST_PH4] = "bt_rst_ph4",
+ [PMUX_PINGRP_BT_WAKE_AP_PH5] = "bt_wake_ap_ph5",
+ [PMUX_PINGRP_AP_WAKE_NFC_PH7] = "ap_wake_nfc_ph7",
+ [PMUX_PINGRP_NFC_EN_PI0] = "nfc_en_pi0",
+ [PMUX_PINGRP_NFC_INT_PI1] = "nfc_int_pi1",
+ [PMUX_PINGRP_GPS_EN_PI2] = "gps_en_pi2",
+ [PMUX_PINGRP_GPS_RST_PI3] = "gps_rst_pi3",
+ [PMUX_PINGRP_CAM_RST_PS4] = "cam_rst_ps4",
+ [PMUX_PINGRP_CAM_AF_EN_PS5] = "cam_af_en_ps5",
+ [PMUX_PINGRP_CAM_FLASH_EN_PS6] = "cam_flash_en_ps6",
+ [PMUX_PINGRP_CAM1_PWDN_PS7] = "cam1_pwdn_ps7",
+ [PMUX_PINGRP_CAM2_PWDN_PT0] = "cam2_pwdn_pt0",
+ [PMUX_PINGRP_CAM1_STROBE_PT1] = "cam1_strobe_pt1",
+ [PMUX_PINGRP_LCD_TE_PY2] = "lcd_te_py2",
+ [PMUX_PINGRP_LCD_BL_PWM_PV0] = "lcd_bl_pwm_pv0",
+ [PMUX_PINGRP_LCD_BL_EN_PV1] = "lcd_bl_en_pv1",
+ [PMUX_PINGRP_LCD_RST_PV2] = "lcd_rst_pv2",
+ [PMUX_PINGRP_LCD_GPIO1_PV3] = "lcd_gpio1_pv3",
+ [PMUX_PINGRP_LCD_GPIO2_PV4] = "lcd_gpio2_pv4",
+ [PMUX_PINGRP_AP_READY_PV5] = "ap_ready_pv5",
+ [PMUX_PINGRP_TOUCH_RST_PV6] = "touch_rst_pv6",
+ [PMUX_PINGRP_TOUCH_CLK_PV7] = "touch_clk_pv7",
+ [PMUX_PINGRP_MODEM_WAKE_AP_PX0] = "modem_wake_ap_px0",
+ [PMUX_PINGRP_TOUCH_INT_PX1] = "touch_int_px1",
+ [PMUX_PINGRP_MOTION_INT_PX2] = "motion_int_px2",
+ [PMUX_PINGRP_ALS_PROX_INT_PX3] = "als_prox_int_px3",
+ [PMUX_PINGRP_TEMP_ALERT_PX4] = "temp_alert_px4",
+ [PMUX_PINGRP_BUTTON_POWER_ON_PX5] = "button_power_on_px5",
+ [PMUX_PINGRP_BUTTON_VOL_UP_PX6] = "button_vol_up_px6",
+ [PMUX_PINGRP_BUTTON_VOL_DOWN_PX7] = "button_vol_down_px7",
+ [PMUX_PINGRP_BUTTON_SLIDE_SW_PY0] = "button_slide_sw_py0",
+ [PMUX_PINGRP_BUTTON_HOME_PY1] = "button_home_py1",
+ [PMUX_PINGRP_PA6] = "pa6",
+ [PMUX_PINGRP_PE6] = "pe6",
+ [PMUX_PINGRP_PE7] = "pe7",
+ [PMUX_PINGRP_PH6] = "ph6",
+ [PMUX_PINGRP_PK0] = "pk0",
+ [PMUX_PINGRP_PK1] = "pk1",
+ [PMUX_PINGRP_PK2] = "pk2",
+ [PMUX_PINGRP_PK3] = "pk3",
+ [PMUX_PINGRP_PK4] = "pk4",
+ [PMUX_PINGRP_PK5] = "pk5",
+ [PMUX_PINGRP_PK6] = "pk6",
+ [PMUX_PINGRP_PK7] = "pk7",
+ [PMUX_PINGRP_PL0] = "pl0",
+ [PMUX_PINGRP_PL1] = "pl1",
+ [PMUX_PINGRP_PZ0] = "pz0",
+ [PMUX_PINGRP_PZ1] = "pz1",
+ [PMUX_PINGRP_PZ2] = "pz2",
+ [PMUX_PINGRP_PZ3] = "pz3",
+ [PMUX_PINGRP_PZ4] = "pz4",
+ [PMUX_PINGRP_PZ5] = "pz5",
+};
+
+static const char * const tegra_pinctrl_to_drvgrp[] = {
+ [PMUX_DRVGRP_ALS_PROX_INT] = "als_prox_int",
+ [PMUX_DRVGRP_AP_READY] = "ap_ready",
+ [PMUX_DRVGRP_AP_WAKE_BT] = "ap_wake_bt",
+ [PMUX_DRVGRP_AP_WAKE_NFC] = "ap_wake_nfc",
+ [PMUX_DRVGRP_AUD_MCLK] = "aud_mclk",
+ [PMUX_DRVGRP_BATT_BCL] = "batt_bcl",
+ [PMUX_DRVGRP_BT_RST] = "bt_rst",
+ [PMUX_DRVGRP_BT_WAKE_AP] = "bt_wake_ap",
+ [PMUX_DRVGRP_BUTTON_HOME] = "button_home",
+ [PMUX_DRVGRP_BUTTON_POWER_ON] = "button_power_on",
+ [PMUX_DRVGRP_BUTTON_SLIDE_SW] = "button_slide_sw",
+ [PMUX_DRVGRP_BUTTON_VOL_DOWN] = "button_vol_down",
+ [PMUX_DRVGRP_BUTTON_VOL_UP] = "button_vol_up",
+ [PMUX_DRVGRP_CAM1_MCLK] = "cam1_mclk",
+ [PMUX_DRVGRP_CAM1_PWDN] = "cam1_pwdn",
+ [PMUX_DRVGRP_CAM1_STROBE] = "cam1_strobe",
+ [PMUX_DRVGRP_CAM2_MCLK] = "cam2_mclk",
+ [PMUX_DRVGRP_CAM2_PWDN] = "cam2_pwdn",
+ [PMUX_DRVGRP_CAM_AF_EN] = "cam_af_en",
+ [PMUX_DRVGRP_CAM_FLASH_EN] = "cam_flash_en",
+ [PMUX_DRVGRP_CAM_I2C_SCL] = "cam_i2c_scl",
+ [PMUX_DRVGRP_CAM_I2C_SDA] = "cam_i2c_sda",
+ [PMUX_DRVGRP_CAM_RST] = "cam_rst",
+ [PMUX_DRVGRP_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_DRVGRP_CLK_32K_OUT] = "clk_32k_out",
+ [PMUX_DRVGRP_CLK_REQ] = "clk_req",
+ [PMUX_DRVGRP_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_DRVGRP_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_DRVGRP_DAP1_DIN] = "dap1_din",
+ [PMUX_DRVGRP_DAP1_DOUT] = "dap1_dout",
+ [PMUX_DRVGRP_DAP1_FS] = "dap1_fs",
+ [PMUX_DRVGRP_DAP1_SCLK] = "dap1_sclk",
+ [PMUX_DRVGRP_DAP2_DIN] = "dap2_din",
+ [PMUX_DRVGRP_DAP2_DOUT] = "dap2_dout",
+ [PMUX_DRVGRP_DAP2_FS] = "dap2_fs",
+ [PMUX_DRVGRP_DAP2_SCLK] = "dap2_sclk",
+ [PMUX_DRVGRP_DAP4_DIN] = "dap4_din",
+ [PMUX_DRVGRP_DAP4_DOUT] = "dap4_dout",
+ [PMUX_DRVGRP_DAP4_FS] = "dap4_fs",
+ [PMUX_DRVGRP_DAP4_SCLK] = "dap4_sclk",
+ [PMUX_DRVGRP_DMIC1_CLK] = "dmic1_clk",
+ [PMUX_DRVGRP_DMIC1_DAT] = "dmic1_dat",
+ [PMUX_DRVGRP_DMIC2_CLK] = "dmic2_clk",
+ [PMUX_DRVGRP_DMIC2_DAT] = "dmic2_dat",
+ [PMUX_DRVGRP_DMIC3_CLK] = "dmic3_clk",
+ [PMUX_DRVGRP_DMIC3_DAT] = "dmic3_dat",
+ [PMUX_DRVGRP_DP_HPD0] = "dp_hpd0",
+ [PMUX_DRVGRP_DVFS_CLK] = "dvfs_clk",
+ [PMUX_DRVGRP_DVFS_PWM] = "dvfs_pwm",
+ [PMUX_DRVGRP_GEN1_I2C_SCL] = "gen1_i2c_scl",
+ [PMUX_DRVGRP_GEN1_I2C_SDA] = "gen1_i2c_sda",
+ [PMUX_DRVGRP_GEN2_I2C_SCL] = "gen2_i2c_scl",
+ [PMUX_DRVGRP_GEN2_I2C_SDA] = "gen2_i2c_sda",
+ [PMUX_DRVGRP_GEN3_I2C_SCL] = "gen3_i2c_scl",
+ [PMUX_DRVGRP_GEN3_I2C_SDA] = "gen3_i2c_sda",
+ [PMUX_DRVGRP_PA6] = "pa6",
+ [PMUX_DRVGRP_PCC7] = "pcc7",
+ [PMUX_DRVGRP_PE6] = "pe6",
+ [PMUX_DRVGRP_PE7] = "pe7",
+ [PMUX_DRVGRP_PH6] = "ph6",
+ [PMUX_DRVGRP_PK0] = "pk0",
+ [PMUX_DRVGRP_PK1] = "pk1",
+ [PMUX_DRVGRP_PK2] = "pk2",
+ [PMUX_DRVGRP_PK3] = "pk3",
+ [PMUX_DRVGRP_PK4] = "pk4",
+ [PMUX_DRVGRP_PK5] = "pk5",
+ [PMUX_DRVGRP_PK6] = "pk6",
+ [PMUX_DRVGRP_PK7] = "pk7",
+ [PMUX_DRVGRP_PL0] = "pl0",
+ [PMUX_DRVGRP_PL1] = "pl1",
+ [PMUX_DRVGRP_PZ0] = "pz0",
+ [PMUX_DRVGRP_PZ1] = "pz1",
+ [PMUX_DRVGRP_PZ2] = "pz2",
+ [PMUX_DRVGRP_PZ3] = "pz3",
+ [PMUX_DRVGRP_PZ4] = "pz4",
+ [PMUX_DRVGRP_PZ5] = "pz5",
+ [PMUX_DRVGRP_GPIO_X1_AUD] = "gpio_x1_aud",
+ [PMUX_DRVGRP_GPIO_X3_AUD] = "gpio_x3_aud",
+ [PMUX_DRVGRP_GPS_EN] = "gps_en",
+ [PMUX_DRVGRP_GPS_RST] = "gps_rst",
+ [PMUX_DRVGRP_HDMI_CEC] = "hdmi_cec",
+ [PMUX_DRVGRP_HDMI_INT_DP_HPD] = "hdmi_int_dp_hpd",
+ [PMUX_DRVGRP_JTAG_RTCK] = "jtag_rtck",
+ [PMUX_DRVGRP_LCD_BL_EN] = "lcd_bl_en",
+ [PMUX_DRVGRP_LCD_BL_PWM] = "lcd_bl_pwm",
+ [PMUX_DRVGRP_LCD_GPIO1] = "lcd_gpio1",
+ [PMUX_DRVGRP_LCD_GPIO2] = "lcd_gpio2",
+ [PMUX_DRVGRP_LCD_RST] = "lcd_rst",
+ [PMUX_DRVGRP_LCD_TE] = "lcd_te",
+ [PMUX_DRVGRP_MODEM_WAKE_AP] = "modem_wake_ap",
+ [PMUX_DRVGRP_MOTION_INT] = "motion_int",
+ [PMUX_DRVGRP_NFC_EN] = "nfc_en",
+ [PMUX_DRVGRP_NFC_INT] = "nfc_int",
+ [PMUX_DRVGRP_PEX_L0_CLKREQ_N] = "pex_l0_clkreq_n",
+ [PMUX_DRVGRP_PEX_L0_RST_N] = "pex_l0_rst_n",
+ [PMUX_DRVGRP_PEX_L1_CLKREQ_N] = "pex_l1_clkreq_n",
+ [PMUX_DRVGRP_PEX_L1_RST_N] = "pex_l1_rst_n",
+ [PMUX_DRVGRP_PEX_WAKE_N] = "pex_wake_n",
+ [PMUX_DRVGRP_PWR_I2C_SCL] = "pwr_i2c_scl",
+ [PMUX_DRVGRP_PWR_I2C_SDA] = "pwr_i2c_sda",
+ [PMUX_DRVGRP_PWR_INT_N] = "pwr_int_n",
+ [PMUX_DRVGRP_QSPI_SCK] = "qspi_sck",
+ [PMUX_DRVGRP_SATA_LED_ACTIVE] = "sata_led_active",
+ [PMUX_DRVGRP_SDMMC1] = "sdmmc1",
+ [PMUX_DRVGRP_SDMMC2] = "sdmmc2",
+ [PMUX_DRVGRP_SDMMC3] = "sdmmc3",
+ [PMUX_DRVGRP_SDMMC4] = "sdmmc4",
+ [PMUX_DRVGRP_SHUTDOWN] = "shutdown",
+ [PMUX_DRVGRP_SPDIF_IN] = "spdif_in",
+ [PMUX_DRVGRP_SPDIF_OUT] = "spdif_out",
+ [PMUX_DRVGRP_SPI1_CS0] = "spi1_cs0",
+ [PMUX_DRVGRP_SPI1_CS1] = "spi1_cs1",
+ [PMUX_DRVGRP_SPI1_MISO] = "spi1_miso",
+ [PMUX_DRVGRP_SPI1_MOSI] = "spi1_mosi",
+ [PMUX_DRVGRP_SPI1_SCK] = "spi1_sck",
+ [PMUX_DRVGRP_SPI2_CS0] = "spi2_cs0",
+ [PMUX_DRVGRP_SPI2_CS1] = "spi2_cs1",
+ [PMUX_DRVGRP_SPI2_MISO] = "spi2_miso",
+ [PMUX_DRVGRP_SPI2_MOSI] = "spi2_mosi",
+ [PMUX_DRVGRP_SPI2_SCK] = "spi2_sck",
+ [PMUX_DRVGRP_SPI4_CS0] = "spi4_cs0",
+ [PMUX_DRVGRP_SPI4_MISO] = "spi4_miso",
+ [PMUX_DRVGRP_SPI4_MOSI] = "spi4_mosi",
+ [PMUX_DRVGRP_SPI4_SCK] = "spi4_sck",
+ [PMUX_DRVGRP_TEMP_ALERT] = "temp_alert",
+ [PMUX_DRVGRP_TOUCH_CLK] = "touch_clk",
+ [PMUX_DRVGRP_TOUCH_INT] = "touch_int",
+ [PMUX_DRVGRP_TOUCH_RST] = "touch_rst",
+ [PMUX_DRVGRP_UART1_CTS] = "uart1_cts",
+ [PMUX_DRVGRP_UART1_RTS] = "uart1_rts",
+ [PMUX_DRVGRP_UART1_RX] = "uart1_rx",
+ [PMUX_DRVGRP_UART1_TX] = "uart1_tx",
+ [PMUX_DRVGRP_UART2_CTS] = "uart2_cts",
+ [PMUX_DRVGRP_UART2_RTS] = "uart2_rts",
+ [PMUX_DRVGRP_UART2_RX] = "uart2_rx",
+ [PMUX_DRVGRP_UART2_TX] = "uart2_tx",
+ [PMUX_DRVGRP_UART3_CTS] = "uart3_cts",
+ [PMUX_DRVGRP_UART3_RTS] = "uart3_rts",
+ [PMUX_DRVGRP_UART3_RX] = "uart3_rx",
+ [PMUX_DRVGRP_UART3_TX] = "uart3_tx",
+ [PMUX_DRVGRP_UART4_CTS] = "uart4_cts",
+ [PMUX_DRVGRP_UART4_RTS] = "uart4_rts",
+ [PMUX_DRVGRP_UART4_RX] = "uart4_rx",
+ [PMUX_DRVGRP_UART4_TX] = "uart4_tx",
+ [PMUX_DRVGRP_USB_VBUS_EN0] = "usb_vbus_en0",
+ [PMUX_DRVGRP_USB_VBUS_EN1] = "usb_vbus_en1",
+ [PMUX_DRVGRP_WIFI_EN] = "wifi_en",
+ [PMUX_DRVGRP_WIFI_RST] = "wifi_rst",
+ [PMUX_DRVGRP_WIFI_WAKE_AP] = "wifi_wake_ap",
+};
+
+static const char * const tegra_pinctrl_to_func[] = {
+ [PMUX_FUNC_DEFAULT] = "default",
+ [PMUX_FUNC_AUD] = "aud",
+ [PMUX_FUNC_BCL] = "bcl",
+ [PMUX_FUNC_BLINK] = "blink",
+ [PMUX_FUNC_CCLA] = "ccla",
+ [PMUX_FUNC_CEC] = "cec",
+ [PMUX_FUNC_CLDVFS] = "cldvfs",
+ [PMUX_FUNC_CLK] = "clk",
+ [PMUX_FUNC_CORE] = "core",
+ [PMUX_FUNC_CPU] = "cpu",
+ [PMUX_FUNC_DISPLAYA] = "displaya",
+ [PMUX_FUNC_DISPLAYB] = "displayb",
+ [PMUX_FUNC_DMIC1] = "dmic1",
+ [PMUX_FUNC_DMIC2] = "dmic2",
+ [PMUX_FUNC_DMIC3] = "dmic3",
+ [PMUX_FUNC_DP] = "dp",
+ [PMUX_FUNC_DTV] = "dtv",
+ [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
+ [PMUX_FUNC_I2C1] = "i2c1",
+ [PMUX_FUNC_I2C2] = "i2c2",
+ [PMUX_FUNC_I2C3] = "i2c3",
+ [PMUX_FUNC_I2CPMU] = "i2cpmu",
+ [PMUX_FUNC_I2CVI] = "i2cvi",
+ [PMUX_FUNC_I2S1] = "i2s1",
+ [PMUX_FUNC_I2S2] = "i2s2",
+ [PMUX_FUNC_I2S3] = "i2s3",
+ [PMUX_FUNC_I2S4A] = "i2s4a",
+ [PMUX_FUNC_I2S4B] = "i2s4b",
+ [PMUX_FUNC_I2S5A] = "i2s5a",
+ [PMUX_FUNC_I2S5B] = "i2s5b",
+ [PMUX_FUNC_IQC0] = "iqc0",
+ [PMUX_FUNC_IQC1] = "iqc1",
+ [PMUX_FUNC_JTAG] = "jtag",
+ [PMUX_FUNC_PE] = "pe",
+ [PMUX_FUNC_PE0] = "pe0",
+ [PMUX_FUNC_PE1] = "pe1",
+ [PMUX_FUNC_PMI] = "pmi",
+ [PMUX_FUNC_PWM0] = "pwm0",
+ [PMUX_FUNC_PWM1] = "pwm1",
+ [PMUX_FUNC_PWM2] = "pwm2",
+ [PMUX_FUNC_PWM3] = "pwm3",
+ [PMUX_FUNC_QSPI] = "qspi",
+ [PMUX_FUNC_SATA] = "sata",
+ [PMUX_FUNC_SDMMC1] = "sdmmc1",
+ [PMUX_FUNC_SDMMC3] = "sdmmc3",
+ [PMUX_FUNC_SHUTDOWN] = "shutdown",
+ [PMUX_FUNC_SOC] = "soc",
+ [PMUX_FUNC_SOR0] = "sor0",
+ [PMUX_FUNC_SOR1] = "sor1",
+ [PMUX_FUNC_SPDIF] = "spdif",
+ [PMUX_FUNC_SPI1] = "spi1",
+ [PMUX_FUNC_SPI2] = "spi2",
+ [PMUX_FUNC_SPI3] = "spi3",
+ [PMUX_FUNC_SPI4] = "spi4",
+ [PMUX_FUNC_SYS] = "sys",
+ [PMUX_FUNC_TOUCH] = "touch",
+ [PMUX_FUNC_UART] = "uart",
+ [PMUX_FUNC_UARTA] = "uarta",
+ [PMUX_FUNC_UARTB] = "uartb",
+ [PMUX_FUNC_UARTC] = "uartc",
+ [PMUX_FUNC_UARTD] = "uartd",
+ [PMUX_FUNC_USB] = "usb",
+ [PMUX_FUNC_VGP1] = "vgp1",
+ [PMUX_FUNC_VGP2] = "vgp2",
+ [PMUX_FUNC_VGP3] = "vgp3",
+ [PMUX_FUNC_VGP4] = "vgp4",
+ [PMUX_FUNC_VGP5] = "vgp5",
+ [PMUX_FUNC_VGP6] = "vgp6",
+ [PMUX_FUNC_VIMCLK] = "vimclk",
+ [PMUX_FUNC_VIMCLK2] = "vimclk2",
+ [PMUX_FUNC_RSVD0] = "rsvd0",
+ [PMUX_FUNC_RSVD1] = "rsvd1",
+ [PMUX_FUNC_RSVD2] = "rsvd2",
+ [PMUX_FUNC_RSVD3] = "rsvd3",
+};
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DISPLAY2,
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
- CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
CLOCK_ID_NONE = -1,
};
PMUX_FUNC_COUNT,
};
+static const char * const tegra_pinctrl_to_pingrp[] = {
+ [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
+ [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
+ [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
+ [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
+ [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
+ [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
+ [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
+ [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
+ [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
+ [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
+ [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
+ [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
+ [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
+ [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
+ [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
+ [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
+ [PMUX_PINGRP_PV0] = "pv0",
+ [PMUX_PINGRP_PV1] = "pv1",
+ [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
+ [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
+ [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
+ [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
+ [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
+ [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
+ [PMUX_PINGRP_PV2] = "pv2",
+ [PMUX_PINGRP_PV3] = "pv3",
+ [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
+ [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
+ [PMUX_PINGRP_LCD_PWR1_PC1] = "lcd_pwr1_pc1",
+ [PMUX_PINGRP_LCD_PWR2_PC6] = "lcd_pwr2_pc6",
+ [PMUX_PINGRP_LCD_SDIN_PZ2] = "lcd_sdin_pz2",
+ [PMUX_PINGRP_LCD_SDOUT_PN5] = "lcd_sdout_pn5",
+ [PMUX_PINGRP_LCD_WR_N_PZ3] = "lcd_wr_n_pz3",
+ [PMUX_PINGRP_LCD_CS0_N_PN4] = "lcd_cs0_n_pn4",
+ [PMUX_PINGRP_LCD_DC0_PN6] = "lcd_dc0_pn6",
+ [PMUX_PINGRP_LCD_SCK_PZ4] = "lcd_sck_pz4",
+ [PMUX_PINGRP_LCD_PWR0_PB2] = "lcd_pwr0_pb2",
+ [PMUX_PINGRP_LCD_PCLK_PB3] = "lcd_pclk_pb3",
+ [PMUX_PINGRP_LCD_DE_PJ1] = "lcd_de_pj1",
+ [PMUX_PINGRP_LCD_HSYNC_PJ3] = "lcd_hsync_pj3",
+ [PMUX_PINGRP_LCD_VSYNC_PJ4] = "lcd_vsync_pj4",
+ [PMUX_PINGRP_LCD_D0_PE0] = "lcd_d0_pe0",
+ [PMUX_PINGRP_LCD_D1_PE1] = "lcd_d1_pe1",
+ [PMUX_PINGRP_LCD_D2_PE2] = "lcd_d2_pe2",
+ [PMUX_PINGRP_LCD_D3_PE3] = "lcd_d3_pe3",
+ [PMUX_PINGRP_LCD_D4_PE4] = "lcd_d4_pe4",
+ [PMUX_PINGRP_LCD_D5_PE5] = "lcd_d5_pe5",
+ [PMUX_PINGRP_LCD_D6_PE6] = "lcd_d6_pe6",
+ [PMUX_PINGRP_LCD_D7_PE7] = "lcd_d7_pe7",
+ [PMUX_PINGRP_LCD_D8_PF0] = "lcd_d8_pf0",
+ [PMUX_PINGRP_LCD_D9_PF1] = "lcd_d9_pf1",
+ [PMUX_PINGRP_LCD_D10_PF2] = "lcd_d10_pf2",
+ [PMUX_PINGRP_LCD_D11_PF3] = "lcd_d11_pf3",
+ [PMUX_PINGRP_LCD_D12_PF4] = "lcd_d12_pf4",
+ [PMUX_PINGRP_LCD_D13_PF5] = "lcd_d13_pf5",
+ [PMUX_PINGRP_LCD_D14_PF6] = "lcd_d14_pf6",
+ [PMUX_PINGRP_LCD_D15_PF7] = "lcd_d15_pf7",
+ [PMUX_PINGRP_LCD_D16_PM0] = "lcd_d16_pm0",
+ [PMUX_PINGRP_LCD_D17_PM1] = "lcd_d17_pm1",
+ [PMUX_PINGRP_LCD_D18_PM2] = "lcd_d18_pm2",
+ [PMUX_PINGRP_LCD_D19_PM3] = "lcd_d19_pm3",
+ [PMUX_PINGRP_LCD_D20_PM4] = "lcd_d20_pm4",
+ [PMUX_PINGRP_LCD_D21_PM5] = "lcd_d21_pm5",
+ [PMUX_PINGRP_LCD_D22_PM6] = "lcd_d22_pm6",
+ [PMUX_PINGRP_LCD_D23_PM7] = "lcd_d23_pm7",
+ [PMUX_PINGRP_LCD_CS1_N_PW0] = "lcd_cs1_n_pw0",
+ [PMUX_PINGRP_LCD_M1_PW1] = "lcd_m1_pw1",
+ [PMUX_PINGRP_LCD_DC1_PD2] = "lcd_dc1_pd2",
+ [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
+ [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
+ [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
+ [PMUX_PINGRP_CRT_HSYNC_PV6] = "crt_hsync_pv6",
+ [PMUX_PINGRP_CRT_VSYNC_PV7] = "crt_vsync_pv7",
+ [PMUX_PINGRP_VI_D0_PT4] = "vi_d0_pt4",
+ [PMUX_PINGRP_VI_D1_PD5] = "vi_d1_pd5",
+ [PMUX_PINGRP_VI_D2_PL0] = "vi_d2_pl0",
+ [PMUX_PINGRP_VI_D3_PL1] = "vi_d3_pl1",
+ [PMUX_PINGRP_VI_D4_PL2] = "vi_d4_pl2",
+ [PMUX_PINGRP_VI_D5_PL3] = "vi_d5_pl3",
+ [PMUX_PINGRP_VI_D6_PL4] = "vi_d6_pl4",
+ [PMUX_PINGRP_VI_D7_PL5] = "vi_d7_pl5",
+ [PMUX_PINGRP_VI_D8_PL6] = "vi_d8_pl6",
+ [PMUX_PINGRP_VI_D9_PL7] = "vi_d9_pl7",
+ [PMUX_PINGRP_VI_D10_PT2] = "vi_d10_pt2",
+ [PMUX_PINGRP_VI_D11_PT3] = "vi_d11_pt3",
+ [PMUX_PINGRP_VI_PCLK_PT0] = "vi_pclk_pt0",
+ [PMUX_PINGRP_VI_MCLK_PT1] = "vi_mclk_pt1",
+ [PMUX_PINGRP_VI_VSYNC_PD6] = "vi_vsync_pd6",
+ [PMUX_PINGRP_VI_HSYNC_PD7] = "vi_hsync_pd7",
+ [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
+ [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
+ [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
+ [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
+ [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
+ [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
+ [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
+ [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
+ [PMUX_PINGRP_PU0] = "pu0",
+ [PMUX_PINGRP_PU1] = "pu1",
+ [PMUX_PINGRP_PU2] = "pu2",
+ [PMUX_PINGRP_PU3] = "pu3",
+ [PMUX_PINGRP_PU4] = "pu4",
+ [PMUX_PINGRP_PU5] = "pu5",
+ [PMUX_PINGRP_PU6] = "pu6",
+ [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
+ [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
+ [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
+ [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
+ [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
+ [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
+ [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
+ [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
+ [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
+ [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
+ [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
+ [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
+ [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
+ [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
+ [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
+ [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
+ [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
+ [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
+ [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
+ [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
+ [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
+ [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
+ [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
+ [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
+ [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
+ [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
+ [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
+ [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
+ [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
+ [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
+ [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
+ [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
+ [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
+ [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
+ [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
+ [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
+ [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
+ [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
+ [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
+ [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
+ [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
+ [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
+ [PMUX_PINGRP_GMI_DQS_PI2] = "gmi_dqs_pi2",
+ [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
+ [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
+ [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
+ [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
+ [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
+ [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
+ [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
+ [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
+ [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
+ [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
+ [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
+ [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
+ [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
+ [PMUX_PINGRP_SDMMC4_RST_N_PCC3] = "sdmmc4_rst_n_pcc3",
+ [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
+ [PMUX_PINGRP_PCC1] = "pcc1",
+ [PMUX_PINGRP_PBB0] = "pbb0",
+ [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
+ [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
+ [PMUX_PINGRP_PBB3] = "pbb3",
+ [PMUX_PINGRP_PBB4] = "pbb4",
+ [PMUX_PINGRP_PBB5] = "pbb5",
+ [PMUX_PINGRP_PBB6] = "pbb6",
+ [PMUX_PINGRP_PBB7] = "pbb7",
+ [PMUX_PINGRP_PCC2] = "pcc2",
+ [PMUX_PINGRP_JTAG_RTCK_PU7] = "jtag_rtck_pu7",
+ [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
+ [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
+ [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
+ [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
+ [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
+ [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
+ [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
+ [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
+ [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
+ [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
+ [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
+ [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
+ [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
+ [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
+ [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
+ [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
+ [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
+ [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
+ [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
+ [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
+ [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
+ [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
+ [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
+ [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
+ [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
+ [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
+ [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
+ [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
+ [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
+ [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_PINGRP_OWR] = "owr",
+ [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
+ [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
+ [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
+ [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
+ [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
+ [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
+ [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
+ [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
+ [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
+ [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
+ [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
+ [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
+ [PMUX_PINGRP_SPI2_MOSI_PX0] = "spi2_mosi_px0",
+ [PMUX_PINGRP_SPI2_MISO_PX1] = "spi2_miso_px1",
+ [PMUX_PINGRP_SPI2_CS0_N_PX3] = "spi2_cs0_n_px3",
+ [PMUX_PINGRP_SPI2_SCK_PX2] = "spi2_sck_px2",
+ [PMUX_PINGRP_SPI1_MOSI_PX4] = "spi1_mosi_px4",
+ [PMUX_PINGRP_SPI1_SCK_PX5] = "spi1_sck_px5",
+ [PMUX_PINGRP_SPI1_CS0_N_PX6] = "spi1_cs0_n_px6",
+ [PMUX_PINGRP_SPI1_MISO_PX7] = "spi1_miso_px7",
+ [PMUX_PINGRP_SPI2_CS1_N_PW2] = "spi2_cs1_n_pw2",
+ [PMUX_PINGRP_SPI2_CS2_N_PW3] = "spi2_cs2_n_pw3",
+ [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
+ [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
+ [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
+ [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
+ [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
+ [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
+ [PMUX_PINGRP_SDMMC3_DAT4_PD1] = "sdmmc3_dat4_pd1",
+ [PMUX_PINGRP_SDMMC3_DAT5_PD0] = "sdmmc3_dat5_pd0",
+ [PMUX_PINGRP_SDMMC3_DAT6_PD3] = "sdmmc3_dat6_pd3",
+ [PMUX_PINGRP_SDMMC3_DAT7_PD4] = "sdmmc3_dat7_pd4",
+ [PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0] = "pex_l0_prsnt_n_pdd0",
+ [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
+ [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
+ [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
+ [PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4] = "pex_l1_prsnt_n_pdd4",
+ [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
+ [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
+ [PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7] = "pex_l2_prsnt_n_pdd7",
+ [PMUX_PINGRP_PEX_L2_RST_N_PCC6] = "pex_l2_rst_n_pcc6",
+ [PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7] = "pex_l2_clkreq_n_pcc7",
+ [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
+};
+
+static const char * const tegra_pinctrl_to_drvgrp[] = {
+ [PMUX_DRVGRP_AO1] = "drive_ao1",
+ [PMUX_DRVGRP_AO2] = "drive_ao2",
+ [PMUX_DRVGRP_AT1] = "drive_at1",
+ [PMUX_DRVGRP_AT2] = "drive_at2",
+ [PMUX_DRVGRP_AT3] = "drive_at3",
+ [PMUX_DRVGRP_AT4] = "drive_at4",
+ [PMUX_DRVGRP_AT5] = "drive_at5",
+ [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
+ [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
+ [PMUX_DRVGRP_CSUS] = "drive_csus",
+ [PMUX_DRVGRP_DAP1] = "drive_dap1",
+ [PMUX_DRVGRP_DAP2] = "drive_dap2",
+ [PMUX_DRVGRP_DAP3] = "drive_dap3",
+ [PMUX_DRVGRP_DAP4] = "drive_dap4",
+ [PMUX_DRVGRP_DBG] = "drive_dbg",
+ [PMUX_DRVGRP_LCD1] = "drive_lcd1",
+ [PMUX_DRVGRP_LCD2] = "drive_lcd2",
+ [PMUX_DRVGRP_SDIO2] = "drive_sdio2",
+ [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
+ [PMUX_DRVGRP_SPI] = "drive_spi",
+ [PMUX_DRVGRP_UAA] = "drive_uaa",
+ [PMUX_DRVGRP_UAB] = "drive_uab",
+ [PMUX_DRVGRP_UART2] = "drive_uart2",
+ [PMUX_DRVGRP_UART3] = "drive_uart3",
+ [PMUX_DRVGRP_VI1] = "drive_vi1",
+ [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
+ [PMUX_DRVGRP_CRT] = "drive_crt",
+ [PMUX_DRVGRP_DDC] = "drive_ddc",
+ [PMUX_DRVGRP_GMA] = "drive_gma",
+ [PMUX_DRVGRP_GMB] = "drive_gmb",
+ [PMUX_DRVGRP_GMC] = "drive_gmc",
+ [PMUX_DRVGRP_GMD] = "drive_gmd",
+ [PMUX_DRVGRP_GME] = "drive_gme",
+ [PMUX_DRVGRP_GMF] = "drive_gmf",
+ [PMUX_DRVGRP_GMG] = "drive_gmg",
+ [PMUX_DRVGRP_GMH] = "drive_gmh",
+ [PMUX_DRVGRP_OWR] = "drive_owr",
+ [PMUX_DRVGRP_UDA] = "drive_uda",
+ [PMUX_DRVGRP_GPV] = "drive_gpv",
+ [PMUX_DRVGRP_DEV3] = "drive_dev3",
+ [PMUX_DRVGRP_CEC] = "drive_cec",
+};
+
+static const char * const tegra_pinctrl_to_func[] = {
+ [PMUX_FUNC_DEFAULT] = "default",
+ [PMUX_FUNC_BLINK] = "blink",
+ [PMUX_FUNC_CEC] = "cec",
+ [PMUX_FUNC_CLK_12M_OUT] = "clk_12m_out",
+ [PMUX_FUNC_CLK_32K_IN] = "clk_32k_in",
+ [PMUX_FUNC_CORE_PWR_REQ] = "core_pwr_req",
+ [PMUX_FUNC_CPU_PWR_REQ] = "cpu_pwr_req",
+ [PMUX_FUNC_CRT] = "crt",
+ [PMUX_FUNC_DAP] = "dap",
+ [PMUX_FUNC_DDR] = "ddr",
+ [PMUX_FUNC_DEV3] = "dev3",
+ [PMUX_FUNC_DISPLAYA] = "displaya",
+ [PMUX_FUNC_DISPLAYB] = "displayb",
+ [PMUX_FUNC_DTV] = "dtv",
+ [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
+ [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
+ [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
+ [PMUX_FUNC_GMI] = "gmi",
+ [PMUX_FUNC_GMI_ALT] = "gmi_alt",
+ [PMUX_FUNC_HDA] = "hda",
+ [PMUX_FUNC_HDCP] = "hdcp",
+ [PMUX_FUNC_HDMI] = "hdmi",
+ [PMUX_FUNC_HSI] = "hsi",
+ [PMUX_FUNC_I2C1] = "i2c1",
+ [PMUX_FUNC_I2C2] = "i2c2",
+ [PMUX_FUNC_I2C3] = "i2c3",
+ [PMUX_FUNC_I2C4] = "i2c4",
+ [PMUX_FUNC_I2CPWR] = "i2cpwr",
+ [PMUX_FUNC_I2S0] = "i2s0",
+ [PMUX_FUNC_I2S1] = "i2s1",
+ [PMUX_FUNC_I2S2] = "i2s2",
+ [PMUX_FUNC_I2S3] = "i2s3",
+ [PMUX_FUNC_I2S4] = "i2s4",
+ [PMUX_FUNC_INVALID] = "invalid",
+ [PMUX_FUNC_KBC] = "kbc",
+ [PMUX_FUNC_MIO] = "mio",
+ [PMUX_FUNC_NAND] = "nand",
+ [PMUX_FUNC_NAND_ALT] = "nand_alt",
+ [PMUX_FUNC_OWR] = "owr",
+ [PMUX_FUNC_PCIE] = "pcie",
+ [PMUX_FUNC_PWM0] = "pwm0",
+ [PMUX_FUNC_PWM1] = "pwm1",
+ [PMUX_FUNC_PWM2] = "pwm2",
+ [PMUX_FUNC_PWM3] = "pwm3",
+ [PMUX_FUNC_PWR_INT_N] = "pwr_int_n",
+ [PMUX_FUNC_RTCK] = "rtck",
+ [PMUX_FUNC_SATA] = "sata",
+ [PMUX_FUNC_SDMMC1] = "sdmmc1",
+ [PMUX_FUNC_SDMMC2] = "sdmmc2",
+ [PMUX_FUNC_SDMMC3] = "sdmmc3",
+ [PMUX_FUNC_SDMMC4] = "sdmmc4",
+ [PMUX_FUNC_SPDIF] = "spdif",
+ [PMUX_FUNC_SPI1] = "spi1",
+ [PMUX_FUNC_SPI2] = "spi2",
+ [PMUX_FUNC_SPI2_ALT] = "spi2_alt",
+ [PMUX_FUNC_SPI3] = "spi3",
+ [PMUX_FUNC_SPI4] = "spi4",
+ [PMUX_FUNC_SPI5] = "spi5",
+ [PMUX_FUNC_SPI6] = "spi6",
+ [PMUX_FUNC_SYSCLK] = "sysclk",
+ [PMUX_FUNC_TEST] = "test",
+ [PMUX_FUNC_TRACE] = "trace",
+ [PMUX_FUNC_UARTA] = "uarta",
+ [PMUX_FUNC_UARTB] = "uartb",
+ [PMUX_FUNC_UARTC] = "uartc",
+ [PMUX_FUNC_UARTD] = "uartd",
+ [PMUX_FUNC_UARTE] = "uarte",
+ [PMUX_FUNC_ULPI] = "ulpi",
+ [PMUX_FUNC_VGP1] = "vgp1",
+ [PMUX_FUNC_VGP2] = "vgp2",
+ [PMUX_FUNC_VGP3] = "vgp3",
+ [PMUX_FUNC_VGP4] = "vgp4",
+ [PMUX_FUNC_VGP5] = "vgp5",
+ [PMUX_FUNC_VGP6] = "vgp6",
+ [PMUX_FUNC_VI] = "vi",
+ [PMUX_FUNC_VI_ALT1] = "vi_alt1",
+ [PMUX_FUNC_VI_ALT2] = "vi_alt2",
+ [PMUX_FUNC_VI_ALT3] = "vi_alt3",
+ [PMUX_FUNC_RSVD1] = "rsvd1",
+ [PMUX_FUNC_RSVD2] = "rsvd2",
+ [PMUX_FUNC_RSVD3] = "rsvd3",
+ [PMUX_FUNC_RSVD4] = "rsvd4",
+};
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
* assembler source.
*/
-#include <config.h>
#include <asm/unified.h>
/*
#include <config.h>
-#include <asm/types.h>
#include <linux/types.h>
/* Architecture-specific global data */
#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
u32 sdhc_clk;
#endif
-
+#if CONFIG_IS_ENABLED(ACPI)
+ ulong table_start; /* Start address of ACPI tables */
+ ulong table_end; /* End address of ACPI tables */
+ ulong table_start_high; /* Start address of high ACPI tables */
+ ulong table_end_high; /* End address of high ACPI tables */
+#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_per_clk;
#endif
#ifndef __ASM_SECURE_H
#define __ASM_SECURE_H
-#include <config.h>
#include <asm/global_data.h>
#define __secure __section("._secure.text")
#ifndef __ASM_ARM_STRING_H
#define __ASM_ARM_STRING_H
-#include <config.h>
-
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
};
#endif
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
-#endif
-
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
#endif /* CONFIG_ARM64 */
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
+#endif
+
#ifndef __ASSEMBLY__
/**
* save_boot_params() - Save boot parameters before starting reset sequence
*/
#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <command.h>
#include <cpu_func.h>
* DIFFERENCE: Instead of calling prep and go at the end
* they are called if subcommand is equal 0.
*/
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* No need for those on ARM */
if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
return -1;
#include <cpu_func.h>
#include <efi_loader.h>
#include <irq_func.h>
+#include <semihosting.h>
#include <asm/global_data.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/ptrace.h>
regs->ARM_pc = pc | (regs->ARM_pc & PCMASK);
}
+/*
+ * Try to "emulate" a semihosting call in the event that we don't have a
+ * debugger attached.
+ */
+static bool smh_emulate_trap(struct pt_regs *regs)
+{
+ if (regs->ARM_cpsr & T_BIT) {
+ u16 *insn = (u16 *)(regs->ARM_pc - 2);
+
+ if (*insn != SMH_T32_SVC)
+ return false;
+ } else {
+ u32 *insn = (u32 *)(regs->ARM_pc - 4);
+
+ if (*insn != SMH_A32_SVC)
+ return false;
+ }
+
+ /* Avoid future semihosting calls */
+ disable_semihosting();
+
+ /* Just pretend the call failed */
+ regs->ARM_r0 = -1;
+ return true;
+}
+
void do_undefined_instruction (struct pt_regs *pt_regs)
{
efi_restore_gd();
void do_software_interrupt (struct pt_regs *pt_regs)
{
+ if (CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) &&
+ smh_emulate_trap(pt_regs))
+ return;
+
efi_restore_gd();
printf ("software interrupt\n");
fixup_pc(pt_regs, -4);
#elif defined(CONFIG_SYS_THUMB_BUILD)
svc #0xab
#else
+#if CONFIG_SYS_ARM_ARCH < 7
+ /* Before the ARMv7 exception model, svc (swi) clobbers lr */
+ mov r2, lr
+#endif
svc #0x123456
#endif
#if defined(CONFIG_ARM64)
ret
+#elif CONFIG_SYS_ARM_ARCH < 7
+ bx r2
#else
bx lr
#endif
movs pc, lr @ jump to next instruction & switch modes.
.endm
+ .macro get_bad_stack_swi
+ sub r13, r13, #4 @ space on current stack for scratch reg.
+ str r0, [r13] @ save R0's value.
+ ldr r0, IRQ_STACK_START_IN @ get data regions start
+ str lr, [r0] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r0, #4] @ save spsr in position 1 of saved stack
+ ldr lr, [r0] @ restore lr
+ ldr r0, [r13] @ restore r0
+ add r13, r13, #4 @ pop stack entry
+ .endm
+
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.align 5
software_interrupt:
- get_bad_stack
+ get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
+#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ movs pc, lr @ return & move spsr_svc into cpsr
+#endif
.align 5
prefetch_abort:
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2400000000,
+ .phys = 0x2400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2480000000,
+ .phys = 0x2480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x2580000000,
#ifndef __DM365_LOWLEVEL_H
#define __DM365_LOWLEVEL_H
-#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define __ASM_ARCH_PINMUX_DEFS_H
#include <asm/arch/davinci_misc.h>
-#include <config.h>
/* SPI0 pin muxer settings */
extern const struct pinmux_config spi0_pins_base[3];
#ifndef _ORIGEN_SETUP_H
#define _ORIGEN_SETUP_H
-#include <config.h>
#include <asm/arch/cpu.h>
/* Bus Configuration Register Address */
#ifndef _SMDK5250_SETUP_H
#define _SMDK5250_SETUP_H
-#include <config.h>
#include <asm/arch/dmc.h>
#define NOT_AVAILABLE 0
bool "Support i.MX HAB features"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
select FSL_CAAM if HAS_CAAM
+ select SPL_DRIVERS_MISC if SPL
imply CMD_DEKBLOB if HAS_CAAM
help
This option enables the support for secure boot (HAB).
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
DEPFILE_EXISTS := 0
+else ifeq ($(CONFIG_ARCH_IMX9), y)
+IMAGE_TYPE := imx8image
+DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
endif
ifeq ($(CONFIG_ARCH_IMX9), y)
-SPL:
+
+quiet_cmd_imx9_check = CHECK $@
+cmd_imx9_check = $(srctree)/tools/imx9_image.sh $@
+
+SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout u-boot-container.cfgout FORCE
+
+MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
+flash.bin: MKIMAGEOUTPUT = flash.log
+
+spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+ $(call if_changed,imx9_check)
+
+spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
+
+u-boot-container.cfgout: $(IMX_CONTAINER_CFG) FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+ $(call if_changed,imx9_check)
+
+flash.bin: spl/u-boot-spl-ddr.bin container.cfgout FORCE
+ $(call if_changed,mkimage)
endif
else
return 0;
}
+int ahab_close(void)
+{
+ int err;
+ u16 lc;
+
+ err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
+ if (err != SC_ERR_NONE) {
+ printf("Error in get lifecycle\n");
+ return -EIO;
+ }
+
+ if (lc != 0x20) {
+ puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n");
+ display_life_cycle(lc);
+ return -EPERM;
+ }
+
+ err = sc_seco_forward_lifecycle(-1, 16);
+ if (err != SC_ERR_NONE) {
+ printf("Error in forward lifecycle to OEM closed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
static int confirm_close(void)
{
puts("Warning: Please ensure your sample is in NXP closed state, "
{
int confirmed = argc >= 2 && !strcmp(argv[1], "-y");
int err;
- u16 lc;
if (!confirmed && !confirm_close())
return -EACCES;
- err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
+ err = ahab_close();
if (err) {
- printf("Error in get lifecycle\n");
- return -EIO;
- }
-
- if (lc != 0x20) {
- puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n");
- display_life_cycle(lc);
- return -EPERM;
- }
-
- err = sc_seco_forward_lifecycle(-1, 16);
- if (err) {
- printf("Error in forward lifecycle to OEM closed\n");
- return -EIO;
+ printf("Change to OEM closed failed\n");
+ return err;
}
printf("Change to OEM closed successfully\n");
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+config TARGET_IMX8MP_DEBIX_MODEL_A
+ bool "Polyhex i.MX8M Plus Debix Model A SBC"
+ select BINMAN
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
select BINMAN
select IMX8M_LPDDR4
config TARGET_IMX8MN_VAR_SOM
- bool "imx8mn_var_som"
+ bool "Variscite imx8mn_var_som"
select BINMAN
select IMX8MN
select SUPPORT_SPL
source "board/mntre/imx8mq_reform2/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
+source "board/polyhex/imx8mp_debix_model_a/Kconfig"
source "board/purism/librem5/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
+ PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
return 0;
}
+#else
+static int imx8mp_fec_interface_init(struct udevice *dev,
+ phy_interface_t interface_type,
+ bool mx8mp)
+{
+ return 0;
+}
#endif
int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
enum env_location env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
- enum env_location env_loc = ENVL_UNKNOWN;
if (prio)
- return env_loc;
+ return ENVL_UNKNOWN;
switch (dev) {
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
case QSPI_BOOT:
- env_loc = ENVL_SPI_FLASH;
- break;
-#endif
-#ifdef CONFIG_ENV_IS_IN_MMC
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_NOWHERE;
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
- env_loc = ENVL_MMC;
- break;
-#endif
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ return ENVL_NOWHERE;
default:
-#if defined(CONFIG_ENV_IS_NOWHERE)
- env_loc = ENVL_NOWHERE;
-#endif
- break;
+ return ENVL_NOWHERE;
}
-
- return env_loc;
}
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
+ select BINMAN
select IMX93
+config TARGET_IMX93_VAR_SOM
+ bool "imx93_var_som"
+ select BINMAN
+ select IMX93
+ select IMX9_LPDDR4X
+
endchoice
source "board/freescale/imx93_evk/Kconfig"
+source "board/variscite/imx93_var_som/Kconfig"
endif
#include <linux/bitops.h>
#include <linux/delay.h>
#include <log.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
}
+#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS)
+static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ clrbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK |
+ BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ setbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_MII |
+ BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RMII |
+ BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ setbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII |
+ BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#else
+static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ return 0;
+}
+#endif
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ if (IS_ENABLED(CONFIG_IMX93) &&
+ IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
+ device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
+ return imx93_eqos_interface_init(dev, interface_type);
+
+ return -EINVAL;
+}
+
int set_clk_enet(enum enet_freq type)
{
u32 div;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Mathieu Othacehe <m.othacehe@gmail.com>
+ */
+
+BOOT_FROM SD 0x400
+SOC_TYPE IMX9
+CONTAINER
+IMAGE A55 bl31.bin 0x204E0000
+IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
\ No newline at end of file
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Mathieu Othacehe <m.othacehe@gmail.com>
+ */
+
+BOOT_FROM SD 0x400
+SOC_TYPE IMX9
+APPEND mx93a0-ahab-container.img
+CONTAINER
+IMAGE A55 u-boot-spl-ddr.bin 0x2049A000
\ No newline at end of file
select DM_GPIO
select DM_MMC
select PCI
- select DM_SCSI
+ select SCSI
select VIDEO
select OF_CONTROL
select SUPPORT_SPL
}
static ulong spl_romapi_read_seekable(struct spl_load_info *load,
- ulong sector, ulong count,
+ ulong offset, ulong byte,
void *buf)
{
- u32 pagesize = *(u32 *)load->priv;
- ulong byte = count * pagesize;
- u32 offset;
-
- offset = sector * pagesize;
-
- return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize;
+ return spl_romapi_raw_seekable_read(offset, byte, buf);
}
static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
struct spl_load_info load;
memset(&load, 0, sizeof(load));
- load.bl_len = pagesize;
+ spl_set_bl_len(&load, pagesize);
load.read = spl_romapi_read_seekable;
- load.priv = &pagesize;
- return spl_load_simple_fit(spl_image, &load, offset / pagesize, header);
+ return spl_load_simple_fit(spl_image, &load, offset, header);
} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
valid_container_hdr((void *)header)) {
struct spl_load_info load;
memset(&load, 0, sizeof(load));
- load.bl_len = pagesize;
+ spl_set_bl_len(&load, pagesize);
load.read = spl_romapi_read_seekable;
- load.priv = &pagesize;
- ret = spl_load_imx_container(spl_image, &load, offset / pagesize);
+ ret = spl_load_imx_container(spl_image, &load, offset);
} else {
/* TODO */
puts("Can't support legacy image\n");
ss.pagesize = pagesize;
memset(&load, 0, sizeof(load));
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_romapi_read_stream;
load.priv = &ss;
printf("ROM download failure %d\n", imagesize);
memset(&load, 0, sizeof(load));
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_ram_load_read;
if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
#ifndef _PINCTRL_SNAPDRAGON_H
#define _PINCTRL_SNAPDRAGON_H
-#include <common.h>
-
struct msm_pinctrl_data {
int pin_count;
int functions_count;
endchoice
+if SOC_K3_J721E
+config SOC_K3_J721E_J7200
+ bool "TI's K3 based J7200 SoC variant Family Support"
+endif
+
config SYS_SOC
default "k3"
Use this option to set the index of the serial device to be used
for the early console during SPL execution.
-config K3_LOAD_SYSFW
- bool
- depends on SPL
-
-config K3_SYSFW_IMAGE_NAME
- string "File name of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default "sysfw.itb"
- help
- Filename of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a filesystem.
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
- hex "MMC sector to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- default 0x3600
- help
- Address on the MMC to load the combined System Firmware and
- configuration image tree blob from, when the MMC is being used
- in raw mode. Units: MMC sectors (1 sector = 512 bytes).
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
- hex "MMC partition to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- default 2
- help
- Partition on the MMC to the combined System Firmware and configuration
- image tree blob from, when the MMC is being used in raw mode.
-
-config K3_SYSFW_IMAGE_SIZE_MAX
- int "Amount of memory dynamically allocated for loading SYSFW blob"
- depends on K3_LOAD_SYSFW
- default 280000
- help
- Amount of memory (in bytes) reserved through dynamic allocation at
- runtime for loading the combined System Firmware and configuration image
- tree blob. Keep it as tight as possible, as this directly affects the
- overall SPL memory footprint.
-
-config K3_SYSFW_IMAGE_SPI_OFFS
- hex "SPI offset of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default 0x6C0000
- help
- Offset of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a SPI flash memory.
-
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
- depends on SPL && CPU_V7R
+ depends on CPU_V7R
help
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
help
SWRV for X509 certificate used for boot images
-source "board/ti/am65x/Kconfig"
-source "board/ti/am64x/Kconfig"
-source "board/ti/am62x/Kconfig"
-source "board/ti/am62ax/Kconfig"
-source "board/ti/j721e/Kconfig"
-source "board/siemens/iot2050/Kconfig"
-source "board/ti/j721s2/Kconfig"
-source "board/toradex/verdin-am62/Kconfig"
+if CPU_V7R
+source "arch/arm/mach-k3/r5/Kconfig"
+endif
+
+source "arch/arm/mach-k3/am65x/Kconfig"
+source "arch/arm/mach-k3/am64x/Kconfig"
+source "arch/arm/mach-k3/am62x/Kconfig"
+source "arch/arm/mach-k3/am62ax/Kconfig"
+source "arch/arm/mach-k3/j721e/Kconfig"
+source "arch/arm/mach-k3/j721s2/Kconfig"
+
endif
# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
-obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o security.o
if (ret)
panic("DRAM init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
switch (bootmode) {
case BOOT_DEVICE_EMMC:
- if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
- if (spl_mmc_emmc_boot_partition(mmc))
- return MMCSD_MODE_EMMCBOOT;
- return MMCSD_MODE_FS;
- }
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+ return MMCSD_MODE_EMMCBOOT;
if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM62A7
+
+choice
+ prompt "K3 AM62Ax based boards"
+ optional
+
+config TARGET_AM62A7_A53_EVM
+ bool "TI K3 based AM62A7 EVM running on A53"
+ select ARM64
+ select BINMAN
+ imply BOARD
+ imply SPL_BOARD
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM62A7_R5_EVM
+ bool "TI K3 based AM62A7 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/am62ax/Kconfig"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM625
+
+choice
+ prompt "K3 AM62x based boards"
+ optional
+
+config TARGET_AM625_A53_EVM
+ bool "TI K3 based AM625 EVM running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_AM625_R5_EVM
+ bool "TI K3 based AM625 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+config TARGET_VERDIN_AM62_A53
+ bool "Toradex Verdin AM62 running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_VERDIN_AM62_R5
+ bool "Toradex Verdin AM62 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+source "board/beagle/beagleplay/Kconfig"
+source "board/ti/am62x/Kconfig"
+source "board/toradex/verdin-am62/Kconfig"
+
+endif
* Dave Gerlach <d-gerlach@ti.com>
*/
-#include <common.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/io.h>
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM642
+
+choice
+ prompt "K3 AM64 based boards"
+ optional
+
+config TARGET_AM642_A53_EVM
+ bool "TI K3 based AM642 EVM running on A53"
+ select ARM64
+ select BINMAN
+ imply BOARD
+ imply SPL_BOARD
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM642_R5_EVM
+ bool "TI K3 based AM642 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/am64x/Kconfig"
+
+endif
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <fdt_support.h>
#include <init.h>
#include <asm/global_data.h>
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM654
+
+choice
+ prompt "K3 AM65 based boards"
+ optional
+
+config TARGET_AM654_A53_EVM
+ bool "TI K3 based AM654 EVM running on A53"
+ select ARM64
+ select SYS_DISABLE_DCACHE_OPS
+ select BOARD_LATE_INIT
+ select BINMAN
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM654_R5_EVM
+ bool "TI K3 based AM654 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select K3_AM654_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_IOT2050_A53
+ bool "IOT2050 running on A53"
+ depends on SOC_K3_AM654
+ select ARM64
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+ help
+ This builds U-Boot for the IOT2050 devices.
+
+endchoice
+
+source "board/ti/am65x/Kconfig"
+source "board/siemens/iot2050/Kconfig"
+
+endif
*
*/
-#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
-#ifdef CONFIG_SOC_K3_AM654
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
-
-/* ToDo: Add 64bit IO */
-struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
+struct mm_region k3_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0x20000000UL,
+ .size = 0x1e780000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
- .size = 0x02100000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xa2100000UL,
- .phys = 0xa2100000UL,
- .size = 0x5df00000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x500000000UL,
- .phys = 0x500000000UL,
- .size = 0x400000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = am654_mem_map;
-#endif /* CONFIG_SOC_K3_AM654 */
-
-#ifdef CONFIG_SOC_K3_J721E
-
-#ifdef CONFIG_TARGET_J721E_A72_EVM
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
-
-/* ToDo: Add 64bit IO */
-struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x20000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xa0000000UL,
- .phys = 0xa0000000UL,
- .size = 0x1bc00000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_NON_SHARE
- }, {
- .virt = 0xbbc00000UL,
- .phys = 0xbbc00000UL,
- .size = 0x44400000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x500000000UL,
- .phys = 0x500000000UL,
- .size = 0x400000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x4d80000000UL,
- .phys = 0x4d80000000UL,
- .size = 0x0002000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = j721e_mem_map;
-#endif /* CONFIG_TARGET_J721E_A72_EVM */
-
-#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
-
-/* ToDo: Add 64bit IO */
-struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x20000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xa0000000UL,
- .phys = 0xa0000000UL,
- .size = 0x04800000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_NON_SHARE
- }, {
- .virt = 0xa4800000UL,
- .phys = 0xa4800000UL,
- .size = 0x5b800000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x500000000UL,
- .phys = 0x500000000UL,
- .size = 0x400000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = j7200_mem_map;
-#endif /* CONFIG_TARGET_J7200_A72_EVM */
-
-#endif /* CONFIG_SOC_K3_J721E */
-
-#ifdef CONFIG_SOC_K3_J721S2
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
-
-/* ToDo: Add 64bit IO */
-struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x500000000UL,
- .phys = 0x500000000UL,
- .size = 0x400000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = j721s2_mem_map;
-
-#endif /* CONFIG_SOC_K3_J721S2 */
-
-#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
-
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
-
-/* ToDo: Add 64bit IO */
-struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x1E780000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xA0000000UL,
- .phys = 0xA0000000UL,
- .size = 0x60000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
-
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x500000000UL,
- .phys = 0x500000000UL,
- .size = 0x400000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = am62_mem_map;
-#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
-
-#ifdef CONFIG_SOC_K3_AM642
-
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
-
-/* ToDo: Add 64bit IO */
-struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x1E800000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xA0000000UL,
- .phys = 0xA0000000UL,
.size = 0x60000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}
};
-struct mm_region *mem_map = am64_mem_map;
-#endif /* CONFIG_SOC_K3_AM642 */
+struct mm_region *mem_map = k3_mem_map;
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
+#include <config.h>
#include <cpu_func.h>
#include <image.h>
#include <init.h>
}
}
-void spl_enable_dcache(void)
+void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
gd->arch.tlb_addr + gd->arch.tlb_size);
gd->relocaddr = gd->arch.tlb_addr;
- dcache_enable();
+ enable_caches();
#endif
}
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
-void spl_enable_dcache(void);
+void spl_enable_cache(void);
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
-#include <config.h>
-
/* Clock Defines */
#define V_OSCK 24000000
#define V_SCLK V_OSCK
#ifndef __ASM_ARCH_J721E_HARDWARE_H
#define __ASM_ARCH_J721E_HARDWARE_H
-#include <config.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
#ifndef __ASM_ARCH_J721S2_HARDWARE_H
#define __ASM_ARCH_J721S2_HARDWARE_H
-#include <config.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_J721E
+
+choice
+ prompt "K3 J721E based boards"
+ optional
+
+config TARGET_J721E_A72_EVM
+ bool "TI K3 based J721E EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721E_R5_EVM
+ bool "TI K3 based J721E EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_J7200_A72_EVM
+ bool "TI K3 based J7200 EVM running on A72"
+ select ARM64
+ select SOC_K3_J721E_J7200
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J7200_R5_EVM
+ bool "TI K3 based J7200 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/beagle/beagleboneai64/Kconfig"
+source "board/ti/j721e/Kconfig"
+
+endif
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
- return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
+ if (spl_mmc_emmc_boot_partition(mmc))
+ return MMCSD_MODE_EMMCBOOT;
+ return MMCSD_MODE_FS;
+ }
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
+ return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_J721S2
+
+choice
+ prompt "K3 J721S2 based boards"
+ optional
+
+config TARGET_J721S2_A72_EVM
+ bool "TI K3 based J721S2 EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721S2_R5_EVM
+ bool "TI K3 based J721S2 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/j721s2/Kconfig"
+
+endif
* David Huang <d-huang@ti.com>
*/
-#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
/* Support for the various EVM / SK families */
--- /dev/null
+config K3_LOAD_SYSFW
+ bool
+
+config K3_SYSFW_IMAGE_NAME
+ string "File name of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default "sysfw.itb"
+ help
+ Filename of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a filesystem.
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+ hex "MMC sector to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default 0x3600
+ help
+ Address on the MMC to load the combined System Firmware and
+ configuration image tree blob from, when the MMC is being used
+ in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+ hex "MMC partition to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 2
+ help
+ Partition on the MMC to the combined System Firmware and configuration
+ image tree blob from, when the MMC is being used in raw mode.
+
+config K3_SYSFW_IMAGE_SIZE_MAX
+ int "Amount of memory dynamically allocated for loading SYSFW blob"
+ depends on K3_LOAD_SYSFW
+ default 280000
+ help
+ Amount of memory (in bytes) reserved through dynamic allocation at
+ runtime for loading the combined System Firmware and configuration image
+ tree blob. Keep it as tight as possible, as this directly affects the
+ overall SPL memory footprint.
+
+config K3_SYSFW_IMAGE_SPI_OFFS
+ hex "SPI offset of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default 0x6C0000
+ help
+ Offset of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a SPI flash memory.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+
+obj-y += lowlevel_init.o
+obj-y += r5_mpu.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
+endif
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <common.h>
#include <asm/arch/hardware.h>
#include "common.h"
PSC_DEV(161, &soc_lpsc_list[5]),
PSC_DEV(162, &soc_lpsc_list[6]),
PSC_DEV(75, &soc_lpsc_list[7]),
+ PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
PSC_DEV(166, &soc_lpsc_list[9]),
"hsdiv4_16fft_main_0_hsdivout0_clk",
};
+static const char * const main_pll8_sel_extwave_out0_parents[] = {
+ "pllfracf_ssmod_16fft_main_8_foutvcop_clk",
+ "hsdiv0_16fft_main_8_hsdivout0_clk",
+};
+
static const char * const mcu_obsclk_outmux_out0_parents[] = {
"mcu_obsclk_div_out0",
"gluelogic_hfosc0_clkout",
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
+ CLK_MUX("main_pll8_sel_extwave_out0", main_pll8_sel_extwave_out0_parents, 2, 0x688040, 0, 1, 0),
CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0),
CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(323, 0, "main_pll8_sel_extwave_out0"),
+ DEV_CLK(323, 1, "pllfracf_ssmod_16fft_main_8_foutvcop_clk"),
+ DEV_CLK(323, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
};
const struct ti_k3_clk_platdata j7200_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 109,
+ .clk_list_cnt = ARRAY_SIZE(clk_list),
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 129,
+ .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
+#include <config.h>
#include <asm/io.h>
#include <linux/kernel.h>
-#include "common.h"
+#include <asm/armv7_mpu.h>
struct mpu_region_config k3_mpu_regions[16] = {
/*
* Andreas Dannenberg <dannenberg@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <image.h>
#include <log.h>
#include <spi_flash.h>
#include <asm/io.h>
-#include "common.h"
+#include "../common.h"
DECLARE_GLOBAL_DATA_PTR;
*/
#include <asm/io.h>
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
#include <linux/bitops.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
+#include <vsprintf.h>
#include <command.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
+#include <config.h>
#include <command.h>
#include <image.h>
#include <mach/mon.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <command.h>
#include <asm/arch/mon.h>
#include <asm/arch/psc_defs.h>
#include <cpu_func.h>
#include <env.h>
#include <asm/io.h>
-#include <common.h>
+#include <vsprintf.h>
#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
* (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <log.h>
+#include <string.h>
#include <i2c.h>
#include <ddr_spd.h>
#ifndef __ASM_ARCH_MUX_K2G_H
#define __ASM_ARCH_MUX_K2G_H
-#include <common.h>
#include <asm/io.h>
#define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000)
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <ns16550.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <env.h>
#include <init.h>
#include <asm/io.h>
#include <hang.h>
#include <image.h>
#include <asm/unaligned.h>
-#include <common.h>
#include <command.h>
#include <mach/mon.h>
#include <spl.h>
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <asm/arch/msmc.h>
struct mpax {
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8365
+ bool "MediaTek MT8365 SoC"
+ select ARM64
+ help
+ The MediaTek MT8365 is a ARM64-based SoC with a quad-core Cortex-A53.
+ It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
+ I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
default "mt7986" if TARGET_MT7986
default "mt7988" if TARGET_MT7988
default "mt8183" if TARGET_MT8183
+ default "mt8365" if TARGET_MT8365
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8365) += mt8365/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Copyright (C) 2023 BayLibre, SAS
+ * Author: Julien Masson <jmasson@baylibre.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+ struct udevice *wdt;
+
+ if (IS_ENABLED(CONFIG_PSCI_RESET)) {
+ psci_system_reset();
+ } else {
+ uclass_first_device(UCLASS_WDT, &wdt);
+ if (wdt)
+ wdt_expire_now(wdt, 0);
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8365\n");
+ return 0;
+}
return socinfo;
}
-int show_board_info(void)
+int checkboard(void)
{
unsigned int socinfo;
return 0;
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
- printf("MVEBU SATA INIT\n");
- board_ahci_enable();
- ahci_init((void __iomem *)MVEBU_SATA0_BASE);
-}
-#endif
-
#ifdef CONFIG_USB_XHCI_MVEBU
#define USB3_MAX_WINDOWS 4
#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
#ifndef _MVEBU_EFUSE_H
#define _MVEBU_EFUSE_H
-#include <common.h>
-
struct efuse_val {
union {
struct {
obj-y += abb.o
endif
-ifneq ($(CONFIG_OMAP54XX),)
-ifeq ($(CONFIG_DM_SCSI),)
-obj-y += pipe3-phy.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
-endif
-endif
-
ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
select DM_SERIAL
imply CMD_DM
-config TARGET_DRACO
- bool "Support draco"
- select BOARD_LATE_INIT
- select DM
- select DM_GPIO
- select DM_SERIAL
- select FACTORYSET
- imply CMD_DM
-
config TARGET_ETAMIN
bool "Support etamin"
select BOARD_LATE_INIT
}
#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void arch_preboot_os(void)
-{
- ahci_reset((void __iomem *)DWC_AHSATA_BASE);
-}
-#endif
-
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(const void *fit, int node, void **p_image,
size_t *p_size)
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
-source "board/ti/beagle/Kconfig"
+source "board/beagle/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_SCSI_AHCI_PLAT
- (*prcm)->cm_l3init_ocp2scp3_clkctrl,
-#endif
0
};
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
-#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
- (*prcm)->cm_l3init_sata_clkctrl,
#endif
0
};
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
- /* Enable optional functional clock for SATA */
- setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
- SATA_CLKCTRL_OPTFCLKEN_MASK);
-#endif
-
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#include <common.h>
-#include <sata.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include "pipe3-phy.h"
-
-/* PLLCTRL Registers */
-#define PLL_STATUS 0x00000004
-#define PLL_GO 0x00000008
-#define PLL_CONFIGURATION1 0x0000000C
-#define PLL_CONFIGURATION2 0x00000010
-#define PLL_CONFIGURATION3 0x00000014
-#define PLL_CONFIGURATION4 0x00000020
-
-#define PLL_REGM_MASK 0x001FFE00
-#define PLL_REGM_SHIFT 9
-#define PLL_REGM_F_MASK 0x0003FFFF
-#define PLL_REGM_F_SHIFT 0
-#define PLL_REGN_MASK 0x000001FE
-#define PLL_REGN_SHIFT 1
-#define PLL_SELFREQDCO_MASK 0x0000000E
-#define PLL_SELFREQDCO_SHIFT 1
-#define PLL_SD_MASK 0x0003FC00
-#define PLL_SD_SHIFT 10
-#define SET_PLL_GO 0x1
-#define PLL_TICOPWDN BIT(16)
-#define PLL_LDOPWDN BIT(15)
-#define PLL_LOCK 0x2
-#define PLL_IDLE 0x1
-
-/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
-
-
-#define PLL_IDLE_TIME 100 /* in milliseconds */
-#define PLL_LOCK_TIME 100 /* in milliseconds */
-
-static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
-{
- return __raw_readl(addr + offset);
-}
-
-static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
- u32 data)
-{
- __raw_writel(data, addr + offset);
-}
-
-static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
- *pipe3)
-{
- u32 rate;
- struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
-
- rate = get_sys_clk_freq();
-
- for (; dpll_map->rate; dpll_map++) {
- if (rate == dpll_map->rate)
- return &dpll_map->params;
- }
-
- printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
- __func__, rate);
- return NULL;
-}
-
-
-static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_LOCK_TIME;
-
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (val & PLL_LOCK)
- break;
- } while (--timeout);
-
- if (!(val & PLL_LOCK)) {
- printf("%s: DPLL failed to lock\n", __func__);
- return -EBUSY;
- }
-
- return 0;
-}
-
-static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
-{
- u32 val;
- struct pipe3_dpll_params *dpll_params;
-
- dpll_params = omap_pipe3_get_dpll_params(phy);
- if (!dpll_params) {
- printf("%s: Invalid DPLL parameters\n", __func__);
- return -EINVAL;
- }
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGN_MASK;
- val |= dpll_params->n << PLL_REGN_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGM_MASK;
- val |= dpll_params->m << PLL_REGM_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
- val &= ~PLL_REGM_F_MASK;
- val |= dpll_params->mf << PLL_REGM_F_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
- val &= ~PLL_SD_MASK;
- val |= dpll_params->sd << PLL_SD_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
-
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- return omap_pipe3_wait_lock(phy);
-}
-
-static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
-{
- u32 val, rate;
-
- val = readl(phy->power_reg);
-
- rate = get_sys_clk_freq();
- rate = rate/1000000;
-
- if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- }
-
- writel(val, phy->power_reg);
-}
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy)
-{
- int ret;
- u32 val;
-
- /* Program the DPLL only if not locked */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (!(val & PLL_LOCK)) {
- ret = omap_pipe3_dpll_program(phy);
- if (ret)
- return ret;
- } else {
- /* else just bring it out of IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- if (val & PLL_IDLE) {
- val &= ~PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base,
- PLL_CONFIGURATION2, val);
- ret = omap_pipe3_wait_lock(phy);
- if (ret)
- return ret;
- }
- }
-
- /* Power up the PHY */
- omap_control_phy_power(phy, 1);
-
- return 0;
-}
-
-int phy_pipe3_power_off(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_IDLE_TIME;
-
- /* Power down the PHY */
- omap_control_phy_power(phy, 0);
-
- /* Put DPLL in IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- /* wait for LDO and Oscillator to power down */
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
- break;
- } while (--timeout);
-
- if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
- printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
- __func__, val);
- return -EBUSY;
- }
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#ifndef __OMAP_PIPE3_PHY_H
-#define __OMAP_PIPE3_PHY_H
-
-struct pipe3_dpll_params {
- u16 m;
- u8 n;
- u8 freq:3;
- u8 sd;
- u32 mf;
-};
-
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-struct omap_pipe3 {
- void __iomem *pll_ctrl_base;
- void __iomem *power_reg;
- struct pipe3_dpll_map *dpll_map;
-};
-
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy);
-int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
-
-#endif /* __OMAP_PIPE3_PHY_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TI SATA platform driver
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <scsi.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sata.h>
-#include <sata.h>
-#include <asm/io.h>
-#include <asm/omap_common.h>
-#include "pipe3-phy.h"
-
-static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
- {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
- { }, /* Terminator */
-};
-
-struct omap_pipe3 sata_phy = {
- .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
- /* .power_reg is updated at runtime */
- .dpll_map = dpll_map_sata,
-};
-
-int init_sata(int dev)
-{
- int ret;
- u32 val;
-
- sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
-
- /* Power up the PHY */
- phy_pipe3_power_on(&sata_phy);
-
- /* Enable SATA module, No Idle, No Standby */
- val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
- writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
-
- ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
-
- return ret;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/* On OMAP platforms SATA provides the SCSI subsystem */
-void scsi_init(void)
-{
- init_sata(0);
- scsi_scan(1);
-}
-
-int scsi_bus_reset(struct udevice *dev)
-{
- ahci_reset((void __iomem *)DWC_AHSATA_BASE);
- ahci_init((void __iomem *)DWC_AHSATA_BASE);
-
- return 0;
-}
*
*/
+#include <mach/rmobile.h>
#include <asm/io.h>
#include <linux/libfdt.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <linux/bitops.h>
-#include <linux/kconfig.h>
#if CONFIG_IS_ENABLED(BANNER_PRINT)
#include <timestamp.h>
STM32MP157, STM32MP153 or STM32MP151
STMicroelectronics MPU with core ARMv7
dual core A7 for STM32MP157/3, monocore for STM32MP151
+
+config STM32MP25X
+ bool "Support STMicroelectronics STM32MP25x Soc"
+ select ARM64
+ select CLK_STM32MP25
+ select OF_BOARD
+ select PINCTRL_STM32
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
+ select SYS_ARCH_TIMER
+ select TFABOOT
+ imply CLK_SCMI
+ imply CMD_NVEDIT_INFO
+ imply DM_REGULATOR
+ imply DM_REGULATOR_SCMI
+ imply OPTEE
+ imply RESET_SCMI
+ imply SYSRESET_PSCI
+ imply TEE
+ imply VERSION_VARIABLE
+ help
+ Support of STMicroelectronics SOC STM32MP25x family
+ STMicroelectronics MPU with 2 * A53 core and 1 M33 core
endchoice
config NR_DRAM_BANKS
source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"
-
+source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
endif
--- /dev/null
+if STM32MP25X
+
+choice
+ prompt "STM32MP25x board select"
+ optional
+
+config TARGET_ST_STM32MP25X
+ bool "STMicroelectronics STM32MP25x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ help
+ target the STMicroelectronics board with SOC STM32MP25x
+ managed by board/st/stm32mp2
+ The difference between board are managed with devicetree
+
+endchoice
+
+config TEXT_BASE
+ default 0x84000000
+
+config PRE_CON_BUF_ADDR
+ default 0x84800000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0x87000000
+
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+ default y
+
+# debug on USART2 by default
+config DEBUG_UART_BASE
+ default 0x400e0000
+
+endif
+
+source "board/st/stm32mp2/Kconfig"
+
+endif
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-obj-y += cpu.o
obj-y += dram_init.o
obj-y += syscon.o
obj-y += bsec.o
-obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
-obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp1/
+obj-$(CONFIG_STM32MP13x) += stm32mp1/
+obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-obj-y += tzc400.o
-else
+ifndef CONFIG_SPL_BUILD
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
-obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o
endif
-
-obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
-obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_lock(u32 address, u32 otp)
+static bool bsec_read_lock(void __iomem *address, u32 otp)
{
u32 bit;
u32 bank;
bit = 1 << (otp & OTP_LOCK_MASK);
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
- return !!(readl(address + bank) & bit);
+ return !!(readl((address + bank)) & bit);
}
/**
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error, -EAGAIN or -ENOTSUPP
*/
-static u32 bsec_check_error(u32 base, u32 otp)
+static u32 bsec_check_error(void __iomem *base, u32 otp)
{
u32 bit;
u32 bank;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SR_lock(u32 base, u32 otp)
+static bool bsec_read_SR_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SP_lock(u32 base, u32 otp)
+static bool bsec_read_SP_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SW_lock(u32 base, u32 otp)
+static bool bsec_read_SW_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}
* @power: true to power up , false to power down
* Return: 0 if succeed
*/
-static int bsec_power_safmem(u32 base, bool power)
+static int bsec_power_safmem(void __iomem *base, bool power)
{
u32 val;
u32 mask;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
+static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp)
{
u32 val;
int ret;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
+static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val,
+ u32 otp)
{
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
+static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
/* check if programming of otp is locked */
if (bsec_read_SW_lock(base, otp))
* after the function the otp data is not refreshed in shadow
* Return: 0 if no error
*/
-static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
+static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
u32 ret;
bool power_up = false;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
+static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp)
{
int ret;
bool power_up = false;
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
- u32 base;
+ void __iomem *base;
};
struct stm32mp_bsec_priv {
{
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
- plat->base = (u32)dev_read_addr_ptr(dev);
+ plat->base = dev_read_addr_ptr(dev);
return 0;
}
*/
#include <common.h>
+#include <bootm.h>
#include <command.h>
#include <dfu.h>
#include <image.h>
char boot_addr_start[20];
char dtb_addr[20];
char initrd_addr[40];
- char *bootm_argv[5] = {
- "bootm", boot_addr_start, "-", dtb_addr, NULL
- };
+ char *fdt_arg, *initrd_arg;
const void *uimage = (void *)data->uimage;
const void *dtb = (void *)data->dtb;
const void *initrd = (void *)data->initrd;
+ struct bootm_info bmi;
+ fdt_arg = dtb_addr;
if (!dtb)
- bootm_argv[3] = env_get("fdtcontroladdr");
+ fdt_arg = env_get("fdtcontroladdr");
else
- snprintf(dtb_addr, sizeof(dtb_addr) - 1,
- "0x%p", dtb);
+ snprintf(dtb_addr, sizeof(dtb_addr) - 1, "0x%p", dtb);
snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
"0x%p", uimage);
+ initrd_arg = NULL;
if (initrd) {
- snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%p:0x%zx",
- initrd, data->initrd_size);
- bootm_argv[2] = initrd_addr;
+ snprintf(initrd_addr, sizeof(initrd_addr) - 1,
+ "0x%p:0x%zx", initrd, data->initrd_size);
+ initrd_arg = initrd_addr;
}
- printf("Booting kernel at %s %s %s...\n\n\n",
- boot_addr_start, bootm_argv[2], bootm_argv[3]);
+ printf("Booting kernel at %s %s %s...\n\n\n", boot_addr_start,
+ initrd_arg ?: "-", fdt_arg);
+
+ bootm_init(&bmi);
+ bmi.addr_img = boot_addr_start;
+ bmi.conf_ramdisk = initrd_arg;
+ bmi.conf_fdt = fdt_arg;
+
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(uimage) != IMAGE_FORMAT_INVALID)
- do_bootm(cmdtp, 0, 4, bootm_argv);
+ bootm_run(&bmi);
else if (IS_ENABLED(CONFIG_CMD_BOOTZ))
- do_bootz(cmdtp, 0, 4, bootm_argv);
+ bootz_run(&bmi);
}
if (data->script)
cmd_source_script(data->script, NULL, NULL);
int ret;
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- log_debug("RAM init failed: %d\n", ret);
+ /* in case there is no RAM driver, retrieve DDR size from DT */
+ if (ret == -ENODEV) {
+ return fdtdec_setup_mem_size_base();
+ } else if (ret) {
+ log_err("RAM init failed: %d\n", ret);
return ret;
}
ret = ram_get_info(dev, &ram);
log_debug("Cannot get RAM size: %d\n", ret);
return ret;
}
- log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+ log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
if (!total_size)
return gd->ram_top;
+ /*
+ * make sure U-Boot uses address space below 4GB boundaries even
+ * if the effective available memory is bigger
+ */
+ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
/* found enough not-reserved memory to relocated U-Boot */
lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, get_effective_memsize());
+ lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
/* add 8M for reserved memory for display, fdt, gd,... */
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
+#include <linux/sizes.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
+
+enum boot_device {
+ BOOT_FLASH_SD = 0x10,
+ BOOT_FLASH_SD_1 = 0x11,
+ BOOT_FLASH_SD_2 = 0x12,
+ BOOT_FLASH_SD_3 = 0x13,
+
+ BOOT_FLASH_EMMC = 0x20,
+ BOOT_FLASH_EMMC_1 = 0x21,
+ BOOT_FLASH_EMMC_2 = 0x22,
+ BOOT_FLASH_EMMC_3 = 0x23,
+
+ BOOT_FLASH_NAND = 0x30,
+ BOOT_FLASH_NAND_FMC = 0x31,
+
+ BOOT_FLASH_NOR = 0x40,
+ BOOT_FLASH_NOR_QSPI = 0x41,
+
+ BOOT_SERIAL_UART = 0x50,
+ BOOT_SERIAL_UART_1 = 0x51,
+ BOOT_SERIAL_UART_2 = 0x52,
+ BOOT_SERIAL_UART_3 = 0x53,
+ BOOT_SERIAL_UART_4 = 0x54,
+ BOOT_SERIAL_UART_5 = 0x55,
+ BOOT_SERIAL_UART_6 = 0x56,
+ BOOT_SERIAL_UART_7 = 0x57,
+ BOOT_SERIAL_UART_8 = 0x58,
+
+ BOOT_SERIAL_USB = 0x60,
+ BOOT_SERIAL_USB_OTG = 0x62,
+
+ BOOT_FLASH_SPINAND = 0x70,
+ BOOT_FLASH_SPINAND_1 = 0x71,
+};
+
+#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16)
+#define TAMP_BOOT_AUTH_SHIFT 16
+#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4)
+#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0)
+#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+
+enum forced_boot_mode {
+ BOOT_NORMAL = 0x00,
+ BOOT_FASTBOOT = 0x01,
+ BOOT_RECOVERY = 0x02,
+ BOOT_STM32PROG = 0x03,
+ BOOT_UMS_MMC0 = 0x10,
+ BOOT_UMS_MMC1 = 0x11,
+ BOOT_UMS_MMC2 = 0x12,
+};
+
#endif
/*
* Peripheral memory map
* only address used before device tree parsing
*/
+
+#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x)
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_SYSCFG_BASE 0x50020000
#define STM32_DDR_SIZE SZ_1G
#ifndef __ASSEMBLY__
-/* enumerated used to identify the SYSCON driver instance */
-enum {
- STM32MP_SYSCON_UNKNOWN,
- STM32MP_SYSCON_SYSCFG,
-};
-
/*
* enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
* - boot device = bit 8:4
#define BOOT_INSTANCE_MASK 0x0F
#define BOOT_INSTANCE_SHIFT 0
-enum boot_device {
- BOOT_FLASH_SD = 0x10,
- BOOT_FLASH_SD_1 = 0x11,
- BOOT_FLASH_SD_2 = 0x12,
- BOOT_FLASH_SD_3 = 0x13,
-
- BOOT_FLASH_EMMC = 0x20,
- BOOT_FLASH_EMMC_1 = 0x21,
- BOOT_FLASH_EMMC_2 = 0x22,
- BOOT_FLASH_EMMC_3 = 0x23,
-
- BOOT_FLASH_NAND = 0x30,
- BOOT_FLASH_NAND_FMC = 0x31,
-
- BOOT_FLASH_NOR = 0x40,
- BOOT_FLASH_NOR_QSPI = 0x41,
-
- BOOT_SERIAL_UART = 0x50,
- BOOT_SERIAL_UART_1 = 0x51,
- BOOT_SERIAL_UART_2 = 0x52,
- BOOT_SERIAL_UART_3 = 0x53,
- BOOT_SERIAL_UART_4 = 0x54,
- BOOT_SERIAL_UART_5 = 0x55,
- BOOT_SERIAL_UART_6 = 0x56,
- BOOT_SERIAL_UART_7 = 0x57,
- BOOT_SERIAL_UART_8 = 0x58,
-
- BOOT_SERIAL_USB = 0x60,
- BOOT_SERIAL_USB_OTG = 0x62,
-
- BOOT_FLASH_SPINAND = 0x70,
- BOOT_FLASH_SPINAND_1 = 0x71,
-};
-
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
-
#define TAMP_COPRO_STATE_OFF 0
#define TAMP_COPRO_STATE_INIT 1
#define TAMP_COPRO_STATE_CRUN 2
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
#endif
-#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
-#define TAMP_BOOT_MODE_SHIFT 8
-#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16)
-#define TAMP_BOOT_AUTH_SHIFT 16
-#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
-#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
-#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4)
-#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0)
-#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
-enum forced_boot_mode {
- BOOT_NORMAL = 0x00,
- BOOT_FASTBOOT = 0x01,
- BOOT_RECOVERY = 0x02,
- BOOT_STM32PROG = 0x03,
- BOOT_UMS_MMC0 = 0x10,
- BOOT_UMS_MMC1 = 0x11,
- BOOT_UMS_MMC2 = 0x12,
-};
+#if CONFIG_STM32MP25X
+#define STM32_RCC_BASE 0x44200000
+#define STM32_TAMP_BASE 0x46010000
+
+#define STM32_DDR_BASE 0x80000000
+
+#define STM32_DDR_SIZE SZ_4G
+
+/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */
+#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x))
+
+/* TAMP registers zone 3 RIF 1 (RW) at 96*/
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
+#endif /* STM32MP25X */
/* offset used for BSEC driver: misc_read and misc_write */
#define STM32_BSEC_SHADOW_OFFSET 0x0
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 60
#endif
+#ifdef CONFIG_STM32MP25X
+#define BSEC_OTP_SERIAL 5
+#define BSEC_OTP_RPN 9
+#define BSEC_OTP_PKG 246
+#endif
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* enumerated used to identify the SYSCON driver instance */
+enum {
+ STM32MP_SYSCON_UNKNOWN,
+ STM32MP_SYSCON_SYSCFG,
+};
+#endif /* __ASSEMBLY__*/
-#endif /* __ASSEMBLY__ */
#endif /* _MACH_STM32_H_ */
#define CPU_STM32MP131Fxx 0x05010EC8
#define CPU_STM32MP131Dxx 0x05010EC9
+/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
+#define CPU_STM32MP257Cxx 0x00002000
+#define CPU_STM32MP255Cxx 0x00082000
+#define CPU_STM32MP253Cxx 0x000B2004
+#define CPU_STM32MP251Cxx 0x000B3065
+#define CPU_STM32MP257Axx 0x40002E00
+#define CPU_STM32MP255Axx 0x40082E00
+#define CPU_STM32MP253Axx 0x400B2E04
+#define CPU_STM32MP251Axx 0x400B3E65
+#define CPU_STM32MP257Fxx 0x80002000
+#define CPU_STM32MP255Fxx 0x80082000
+#define CPU_STM32MP253Fxx 0x800B2004
+#define CPU_STM32MP251Fxx 0x800B3065
+#define CPU_STM32MP257Dxx 0xC0002E00
+#define CPU_STM32MP255Dxx 0xC0082E00
+#define CPU_STM32MP253Dxx 0xC00B2E04
+#define CPU_STM32MP251Dxx 0xC00B3E65
+
/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
#define CPU_DEV_STM32MP13 0x501
+#define CPU_DEV_STM32MP25 0x505
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
#define STM32MP15_PKG_AD_TFBGA257 1
#define STM32MP15_PKG_UNKNOWN 0
+/* package used for STM32MP25x */
+#define STM32MP25_PKG_CUSTOM 0
+#define STM32MP25_PKG_AL_TBGA361 3
+#define STM32MP25_PKG_AK_TBGA424 4
+#define STM32MP25_PKG_AI_TBGA436 5
+#define STM32MP25_PKG_UNKNOWN 7
+
/* Get SOC name */
#define SOC_NAME_SIZE 20
void get_soc_name(char name[SOC_NAME_SIZE]);
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+
+obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+
+obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += tzc400.o
+else
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
+endif
+
+obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+#
+# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+obj-y += arm64-mmu.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
+obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <mach/stm32.h>
+
+#define MP2_MEM_MAP_MAX 10
+
+#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
+ (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
+#error "invalid CONFIG_TEXT_BASE value"
+#endif
+
+struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
+ {
+ /* PCIe */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Peripherals: alias1 */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OSPI and FMC: memory-map area */
+ .virt = 0x60000000UL,
+ .phys = 0x60000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /*
+ * DDR = STM32_DDR_BASE / STM32_DDR_SIZE
+ * the beginning of DDR (before CONFIG_TEXT_BASE) is not
+ * mapped, protected by RIF and reserved for other firmware
+ * (OP-TEE / TF-M / Cube M33)
+ */
+ .virt = CONFIG_TEXT_BASE,
+ .phys = CONFIG_TEXT_BASE,
+ .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = stm32mp2_mem_map;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <env_internal.h>
+#include <init.h>
+#include <misc.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/system.h>
+#include <dm/device.h>
+#include <dm/lists.h>
+#include <dm/uclass.h>
+
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB alignment
+ */
+#define EARLY_TLB_SIZE 0xA000
+u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+/*
+ * initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+static void early_enable_caches(void)
+{
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ }
+ /* enable MMU (default configuration) */
+ dcache_enable();
+}
+
+/*
+ * Early system init
+ */
+int arch_cpu_init(void)
+{
+ icache_enable();
+ early_enable_caches();
+
+ return 0;
+}
+
+void enable_caches(void)
+{
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+ dcache_enable();
+}
+
+/* used when CONFIG_DISPLAY_CPUINFO is activated */
+int print_cpuinfo(void)
+{
+ char name[SOC_NAME_SIZE];
+
+ get_soc_name(name);
+ printf("CPU: %s\n", name);
+
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+/*
+ * Force data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+static uintptr_t nt_fw_dtb __section(".data");
+
+uintptr_t get_stm32mp_bl2_dtb(void)
+{
+ return nt_fw_dtb;
+}
+
+/*
+ * Save the FDT address provided by TF-A in r2 at boot time
+ * This function is called from start.S
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ nt_fw_dtb = r2;
+
+ save_boot_params_ret();
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/u-boot.h>
+
+/*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <log.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+
+/* SYSCFG register */
+#define SYSCFG_DEVICEID_OFFSET 0x6400
+#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
+#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
+#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
+#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+/* Device Part Number (RPN) = OTP9 */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(31, 0)
+
+/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
+ * - 000: Custom package
+ * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT 0
+#define PKG_MASK GENMASK(2, 0)
+
+static u32 read_deviceid(void)
+{
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+u32 get_cpu_type(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+/* Get Package options from OTP */
+u32 get_cpu_package(void)
+{
+ return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
+}
+
+int get_eth_nb(void)
+{
+ int nb_eth;
+
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ fallthrough;
+ case CPU_STM32MP257Dxx:
+ fallthrough;
+ case CPU_STM32MP257Cxx:
+ fallthrough;
+ case CPU_STM32MP257Axx:
+ nb_eth = 5; /* dual ETH with TSN support */
+ break;
+ case CPU_STM32MP253Fxx:
+ fallthrough;
+ case CPU_STM32MP253Dxx:
+ fallthrough;
+ case CPU_STM32MP253Cxx:
+ fallthrough;
+ case CPU_STM32MP253Axx:
+ nb_eth = 2; /* dual ETH */
+ break;
+ case CPU_STM32MP251Fxx:
+ fallthrough;
+ case CPU_STM32MP251Dxx:
+ fallthrough;
+ case CPU_STM32MP251Cxx:
+ fallthrough;
+ case CPU_STM32MP251Axx:
+ nb_eth = 1; /* single ETH */
+ break;
+ default:
+ nb_eth = 0;
+ break;
+ }
+
+ return nb_eth;
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ char *cpu_s, *cpu_r, *package;
+
+ cpu_s = "????";
+ cpu_r = "?";
+ package = "??";
+ if (get_cpu_dev() == CPU_DEV_STM32MP25) {
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ cpu_s = "257F";
+ break;
+ case CPU_STM32MP257Dxx:
+ cpu_s = "257D";
+ break;
+ case CPU_STM32MP257Cxx:
+ cpu_s = "257C";
+ break;
+ case CPU_STM32MP257Axx:
+ cpu_s = "257A";
+ break;
+ case CPU_STM32MP255Fxx:
+ cpu_s = "255F";
+ break;
+ case CPU_STM32MP255Dxx:
+ cpu_s = "255D";
+ break;
+ case CPU_STM32MP255Cxx:
+ cpu_s = "255C";
+ break;
+ case CPU_STM32MP255Axx:
+ cpu_s = "255A";
+ break;
+ case CPU_STM32MP253Fxx:
+ cpu_s = "253F";
+ break;
+ case CPU_STM32MP253Dxx:
+ cpu_s = "253D";
+ break;
+ case CPU_STM32MP253Cxx:
+ cpu_s = "253C";
+ break;
+ case CPU_STM32MP253Axx:
+ cpu_s = "253A";
+ break;
+ case CPU_STM32MP251Fxx:
+ cpu_s = "251F";
+ break;
+ case CPU_STM32MP251Dxx:
+ cpu_s = "251D";
+ break;
+ case CPU_STM32MP251Cxx:
+ cpu_s = "251C";
+ break;
+ case CPU_STM32MP251Axx:
+ cpu_s = "251A";
+ break;
+ default:
+ cpu_s = "25??";
+ break;
+ }
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ default:
+ break;
+ }
+ /* PACKAGE */
+ switch (get_cpu_package()) {
+ case STM32MP25_PKG_CUSTOM:
+ package = "XX";
+ break;
+ case STM32MP25_PKG_AL_TBGA361:
+ package = "AL";
+ break;
+ case STM32MP25_PKG_AK_TBGA424:
+ package = "AK";
+ break;
+ case STM32MP25_PKG_AI_TBGA436:
+ package = "AI";
+ break;
+ default:
+ break;
+ }
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
+}
#include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = {
- { .compatible = "st,stm32mp157-syscfg",
- .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ }
};
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-#include <linux/kconfig.h>
/*
* The DRAM controller structure on H6 is similar to the ones on A23/A80:
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-#include <linux/kconfig.h>
enum {
MBUS_QOS_LOWEST = 0,
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
#include <linux/delay.h>
-#include <linux/kconfig.h>
static void mctl_phy_init(u32 val)
{
struct spl_load_info load;
debug("Found FIT image\n");
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spi_load_read;
ret = spl_load_simple_fit(spl_image, &load,
load_offset, header);
config TEGRA_MC
bool
-config TEGRA_PINCTRL
- bool
-
config TEGRA_PMC
bool
select OF_CONTROL
select SPI
select SYSRESET
- select SPL_SYSRESET if SPL
select SYSRESET_TEGRA
imply CMD_DM
imply CRC32_VERIFY
bool "Tegra 32-bit common options"
select BINMAN
select CPU_V7A
+ select PINCTRL
+ select PINCTRL_TEGRA
select SPL
select SPL_BOARD_INIT if SPL
+ select SPL_DM if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_PINCTRL_TEGRA if SPL
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
+ select SPL_SYSRESET if SPL
select SUPPORT_SPL
select TIMER
select TEGRA_CLKRST
select TEGRA_GP_PADCTRL
select TEGRA_MC
select TEGRA_NO_BPMP
- select TEGRA_PINCTRL
select TEGRA_PMC
select TEGRA_TIMER
config TEGRA210
bool "Tegra210 family"
select GICV2
+ select PINCTRL
+ select PINCTRL_TEGRA
select TIMER
select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST
select TEGRA_GP_PADCTRL
select TEGRA_MC
select TEGRA_NO_BPMP
- select TEGRA_PINCTRL
select TEGRA_PMC
select TEGRA_PMC_SECURE
select TEGRA_TIMER
USB controller when U-Boot boots to avoid leaving a stale USB device
present.
+config TEGRA_SUPPORT_NON_SECURE
+ bool "Support executing U-Boot in non-secure (NS) mode"
+ depends on TEGRA114 || TEGRA124
+ help
+ Certain impossible actions will be skipped if the CPU is in NS mode,
+ such as ARM architectural timer initialization.
+
config CI_UDC_HAS_HOSTPC
def_bool y
depends on CI_UDC && !TEGRA20
choice
prompt "UART to use for console"
- depends on TEGRA_PINCTRL
+ depends on PINCTRL_TEGRA
default TEGRA_ENABLE_UARTA
config TEGRA_ENABLE_UARTA
obj-y += cache.o
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o
-obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
#include <asm/arch/funcmux.h>
#endif
#if IS_ENABLED(CONFIG_TEGRA_MC)
}
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
-#if !defined(CONFIG_TEGRA124)
-#error tegra_cpu_is_non_secure has only been validated on Tegra124
-#endif
bool tegra_cpu_is_non_secure(void)
{
/*
return 0;
}
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
void board_init_uart_f(void)
{
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
#include <init.h>
#include <log.h>
#include <ns16550.h>
+#include <power/regulator.h>
#include <usb.h>
#include <asm/global_data.h>
#include <asm/io.h>
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#endif
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
+
+ /* Set up boot-on regulators */
+ regulators_enable_boot_on(_DEBUG);
+
return nvidia_board_init();
}
struct clk_pll_simple *simple_pll = NULL;
u32 misc_data, data;
- if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
pll = get_pll(clkid);
- } else {
+ else
simple_pll = clock_get_simple_pll(clkid);
- if (!simple_pll) {
- debug("%s: Uknown simple PLL %d\n", __func__, clkid);
- return 0;
- }
+
+ if (!simple_pll && !pll) {
+ log_err("Unknown PLL id %d\n", clkid);
+ return 0;
}
/*
unsigned clock_get_rate(enum clock_id clkid)
{
- struct clk_pll *pll;
+ struct clk_pll *pll = NULL;
+ struct clk_pll_simple *simple_pll = NULL;
u32 base, divm;
u64 parent_rate, rate;
struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
if (clkid == CLOCK_ID_CLK_M)
return clk_m_get_rate(parent_rate);
- pll = get_pll(clkid);
- if (!pll)
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+ pll = get_pll(clkid);
+ else
+ simple_pll = clock_get_simple_pll(clkid);
+
+ if (!simple_pll && !pll) {
+ log_err("Unknown PLL id %d\n", clkid);
return 0;
- base = readl(&pll->pll_base);
+ }
+
+ if (pll)
+ base = readl(&pll->pll_base);
+ else
+ base = readl(&simple_pll->pll_base);
rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
{
u32 base_reg, misc_reg;
- struct clk_pll *pll;
+ struct clk_pll *pll = NULL;
+ struct clk_pll_simple *simple_pll = NULL;
struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
- pll = get_pll(clkid);
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+ pll = get_pll(clkid);
+ else
+ simple_pll = clock_get_simple_pll(clkid);
- base_reg = readl(&pll->pll_base);
+ if (!simple_pll && !pll) {
+ log_err("Unknown PLL id %d\n", clkid);
+ return 0;
+ }
+
+ if (pll)
+ base_reg = readl(&pll->pll_base);
+ else
+ base_reg = readl(&simple_pll->pll_base);
/* Set BYPASS, m, n and p to PLL_BASE */
base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
}
base_reg |= PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
+ if (pll)
+ writel(base_reg, &pll->pll_base);
+ else
+ writel(base_reg, &simple_pll->pll_base);
/* Set cpcon (KCP) to PLL_MISC */
- misc_reg = readl(&pll->pll_misc);
+ if (pll)
+ misc_reg = readl(&pll->pll_misc);
+ else
+ misc_reg = readl(&simple_pll->pll_misc);
+
misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
misc_reg |= cpcon << pllinfo->kcp_shift;
- writel(misc_reg, &pll->pll_misc);
+ if (pll)
+ writel(misc_reg, &pll->pll_misc);
+ else
+ writel(misc_reg, &simple_pll->pll_misc);
/* Enable PLL */
base_reg |= PLL_ENABLE_MASK;
- writel(base_reg, &pll->pll_base);
+ if (pll)
+ writel(base_reg, &pll->pll_base);
+ else
+ writel(base_reg, &simple_pll->pll_base);
/* Disable BYPASS */
base_reg &= ~PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
+ if (pll)
+ writel(base_reg, &pll->pll_base);
+ else
+ writel(base_reg, &simple_pll->pll_base);
return 0;
}
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
+#ifndef CONFIG_TEGRA20
+ pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2);
+#endif
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
obj-$(CONFIG_SPL_BUILD) += cpu.o
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
PERIPHC_UART3,
/* 56 */
- NONE(RESERVED56),
+ NONE(MIPI_CAL),
PERIPHC_EMC,
NONE(USB2),
NONE(USB3),
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+ .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
};
/*
case PERIPH_ID_RESERVED35:
case PERIPH_ID_RESERVED43:
case PERIPH_ID_RESERVED45:
- case PERIPH_ID_RESERVED56:
case PERIPH_ID_RESERVED76:
case PERIPH_ID_RESERVED77:
case PERIPH_ID_RESERVED78:
case TEGRA114_CLK_PLL_D:
case TEGRA114_CLK_PLL_D_OUT0:
return CLOCK_ID_DISPLAY;
+ case TEGRA114_CLK_PLL_D2:
+ case TEGRA114_CLK_PLL_D2_OUT0:
+ return CLOCK_ID_DISPLAY2;
case TEGRA114_CLK_PLL_X:
return CLOCK_ID_XCPU;
case TEGRA114_CLK_PLL_E_OUT0:
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
}
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DISPLAY2:
+ return &clkrst->plld2;
+ default:
+ return NULL;
+ }
+}
+
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- if (clkid == CLOCK_ID_DP)
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DP:
return &clkrst->plldp;
-
- return NULL;
+ default:
+ return NULL;
+ }
}
struct periph_clk_init periph_clk_init_table[] = {
-D__LINUX_ARM_ARCH__=4
CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
obj-$(CONFIG_TEGRA_PMU) += pmu.o
return 0;
}
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ default:
+ return NULL;
+ }
+}
+
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
#
obj-y += clock.o
-obj-y += funcmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
return 0;
}
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ default:
+ return NULL;
+ }
+}
+
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
-obj-y += clock.o funcmux.o pinmux.o
+obj-y += clock.o
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+ .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
};
/*
case TEGRA30_CLK_PLL_D:
case TEGRA30_CLK_PLL_D_OUT0:
return CLOCK_ID_DISPLAY;
+ case TEGRA30_CLK_PLL_D2:
+ case TEGRA30_CLK_PLL_D2_OUT0:
+ return CLOCK_ID_DISPLAY2;
case TEGRA30_CLK_PLL_X:
return CLOCK_ID_XCPU;
case TEGRA30_CLK_PLL_E:
return 0;
}
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ switch (clkid) {
+ case CLOCK_ID_XCPU:
+ case CLOCK_ID_EPCI:
+ case CLOCK_ID_SFROM32KHZ:
+ return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DISPLAY2:
+ return &clkrst->plld2;
+ default:
+ return NULL;
+ }
+}
+
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
#define _TEGRA_XUSB_PADCTL_COMMON_H_
-#include <common.h>
#include <fdtdec.h>
#include <dm/ofnode.h>
DECLARE_GLOBAL_DATA_PTR;
-static const char * const clk_names[clk_max] = {
- "armpll", "ddrpll", "iopll",
- "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
- "ddr2x", "ddr3x", "dci",
- "lqspi", "smc", "pcap", "gem0", "gem1",
- "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
- "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
- "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
- "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
- "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
- "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
- "smc_aper", "swdt", "dbg_trc", "dbg_apb"
-};
-
/**
* set_cpu_clk_info() - Setup clock information
*
return 0;
}
-
-/**
- * soc_clk_dump() - Print clock frequencies
- * Returns zero on success
- *
- * Implementation for the clk dump command.
- */
-int soc_clk_dump(void)
-{
- struct udevice *dev;
- int i, ret;
-
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(zynq_clk), &dev);
- if (ret)
- return ret;
-
- printf("clk\t\tfrequency\n");
- for (i = 0; i < clk_max; i++) {
- const char *name = clk_names[i];
- if (name) {
- struct clk clk;
- unsigned long rate;
-
- clk.id = i;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- return ret;
-
- rate = clk_get_rate(&clk);
-
- clk_free(&clk);
-
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO))
- printf("%10s%20s\n", name, "unknown");
- else
- printf("%10s%20lu\n", name, rate);
- }
- }
-
- return 0;
-}
#define _PSU_INIT_GPL_H_
#include <asm/io.h>
-#include <common.h>
int mask_pollonvalue(unsigned long add, u32 mask, u32 value);
#ifndef __CACHE_H
#define __CACHE_H
+#include <config.h>
+
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
defined(CONFIG_MCF52x2)
#define CFG_CF_V2
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef fsl_mcdmafec_h
-#define fsl_mcdmafec_h
-
-/* Re-use of the definitions */
-#include <asm/fec.h>
-
-typedef struct fecdma {
- u32 rsvd0; /* 0x000 */
- u32 eir; /* 0x004 */
- u32 eimr; /* 0x008 */
- u32 rsvd1[6]; /* 0x00C - 0x023 */
- u32 ecr; /* 0x024 */
- u32 rsvd2[6]; /* 0x028 - 0x03F */
- u32 mmfr; /* 0x040 */
- u32 mscr; /* 0x044 */
- u32 rsvd3[7]; /* 0x048 - 0x063 */
- u32 mibc; /* 0x064 */
- u32 rsvd4[7]; /* 0x068 - 0x083 */
- u32 rcr; /* 0x084 */
- u32 rhr; /* 0x088 */
- u32 rsvd5[14]; /* 0x08C - 0x0C3 */
- u32 tcr; /* 0x0C4 */
- u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
- u32 palr; /* 0x0E4 */
- u32 paur; /* 0x0E8 */
- u32 opd; /* 0x0EC */
- u32 rsvd7[10]; /* 0x0F0 - 0x117 */
- u32 iaur; /* 0x118 */
- u32 ialr; /* 0x11C */
- u32 gaur; /* 0x120 */
- u32 galr; /* 0x124 */
- u32 rsvd8[7]; /* 0x128 - 0x143 */
- u32 tfwr; /* 0x144 */
- u32 rsvd9[14]; /* 0x148 - 0x17F */
- u32 fmc; /* 0x180 */
- u32 rfdr; /* 0x184 */
- u32 rfsr; /* 0x188 */
- u32 rfcr; /* 0x18C */
- u32 rlrfp; /* 0x190 */
- u32 rlwfp; /* 0x194 */
- u32 rfar; /* 0x198 */
- u32 rfrp; /* 0x19C */
- u32 rfwp; /* 0x1A0 */
- u32 tfdr; /* 0x1A4 */
- u32 tfsr; /* 0x1A8 */
- u32 tfcr; /* 0x1AC */
- u32 tlrfp; /* 0x1B0 */
- u32 tlwfp; /* 0x1B4 */
- u32 tfar; /* 0x1B8 */
- u32 tfrp; /* 0x1BC */
- u32 tfwp; /* 0x1C0 */
- u32 frst; /* 0x1C4 */
- u32 ctcwr; /* 0x1C8 */
-} fecdma_t;
-
-struct fec_info_dma {
- int index;
- u32 iobase;
- u32 pinmux;
- u32 miibase;
- int phy_addr;
- int dup_spd;
- char *phy_name;
- int phyname_init;
- cbd_t *rxbd; /* Rx BD */
- cbd_t *txbd; /* Tx BD */
- uint rx_idx;
- uint tx_idx;
- char *txbuf;
- int initialized;
- struct fec_info_dma *next;
- u16 rx_task; /* DMA receive Task Number */
- u16 tx_task; /* DMA Transmit Task Number */
- u16 rx_pri; /* DMA Receive Priority */
- u16 tx_pri; /* DMA Transmit Priority */
- u16 rx_init; /* DMA Receive Initiator */
- u16 tx_init; /* DMA Transmit Initiator */
- u16 used_tbd_idx; /* next transmit BD to clean */
- u16 clean_tbd_num; /* the number of available transmit BDs */
- int to_loop;
- struct mii_dev *bus;
-};
-
-/* Bit definitions and macros for IEVENT */
-#define FEC_EIR_TXERR (0x00040000)
-#define FEC_EIR_RXERR (0x00020000)
-#undef FEC_EIR_CLEAR_ALL
-#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
-
-/* Bit definitions and macros for R_HASH */
-#define FEC_RHASH_FCE_DC (0x80000000)
-#define FEC_RHASH_MULTCAST (0x40000000)
-#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
-
-/* Bit definitions and macros for FEC_TFWR */
-#undef FEC_TFWR_X_WMRK
-#undef FEC_TFWR_X_WMRK_64
-#undef FEC_TFWR_X_WMRK_128
-#undef FEC_TFWR_X_WMRK_192
-
-#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
-#define FEC_TFWR_X_WMRK_64 (0x00)
-#define FEC_TFWR_X_WMRK_128 (0x01)
-#define FEC_TFWR_X_WMRK_192 (0x02)
-#define FEC_TFWR_X_WMRK_256 (0x03)
-#define FEC_TFWR_X_WMRK_320 (0x04)
-#define FEC_TFWR_X_WMRK_384 (0x05)
-#define FEC_TFWR_X_WMRK_448 (0x06)
-#define FEC_TFWR_X_WMRK_512 (0x07)
-#define FEC_TFWR_X_WMRK_576 (0x08)
-#define FEC_TFWR_X_WMRK_640 (0x09)
-#define FEC_TFWR_X_WMRK_704 (0x0A)
-#define FEC_TFWR_X_WMRK_768 (0x0B)
-#define FEC_TFWR_X_WMRK_832 (0x0C)
-#define FEC_TFWR_X_WMRK_896 (0x0D)
-#define FEC_TFWR_X_WMRK_960 (0x0E)
-#define FEC_TFWR_X_WMRK_1024 (0x0F)
-
-/* FIFO definitions */
-/* Bit definitions and macros for FSTAT */
-#define FIFO_STAT_IP (0x80000000)
-#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
-#define FIFO_STAT_FAE (0x00800000)
-#define FIFO_STAT_RXW (0x00400000)
-#define FIFO_STAT_UF (0x00200000)
-#define FIFO_STAT_OF (0x00100000)
-#define FIFO_STAT_FR (0x00080000)
-#define FIFO_STAT_FULL (0x00040000)
-#define FIFO_STAT_ALARM (0x00020000)
-#define FIFO_STAT_EMPTY (0x00010000)
-
-/* Bit definitions and macros for FCTRL */
-#define FIFO_CTRL_WCTL (0x40000000)
-#define FIFO_CTRL_WFR (0x20000000)
-#define FIFO_CTRL_FRAME (0x08000000)
-#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
-#define FIFO_CTRL_IPMASK (0x00800000)
-#define FIFO_CTRL_FAEMASK (0x00400000)
-#define FIFO_CTRL_RXWMASK (0x00200000)
-#define FIFO_CTRL_UFMASK (0x00100000)
-#define FIFO_CTRL_OFMASK (0x00080000)
-
-#endif /* fsl_mcdmafec_h */
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-#include <config.h>
-
/* Architecture-specific global data */
struct arch_global_data {
#ifdef CONFIG_SYS_I2C_FSL
unsigned long sdhc_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
- u32 sdhc_per_clk;
+ unsigned long sdhc_per_clk;
#endif
};
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
-#ifdef CONFIG_FSLDMAFEC
-#define FEC0_RX_TASK 0
-#define FEC0_TX_TASK 1
-#define FEC0_RX_PRIORITY 6
-#define FEC0_TX_PRIORITY 7
-#define FEC0_RX_INIT 16
-#define FEC0_TX_INIT 17
-#define FEC1_RX_TASK 2
-#define FEC1_TX_TASK 3
-#define FEC1_RX_PRIORITY 6
-#define FEC1_TX_PRIORITY 7
-#define FEC1_RX_INIT 30
-#define FEC1_TX_INIT 31
-#endif
-
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <bootm.h>
#include <bootstage.h>
#include <command.h>
#include <env.h>
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024);
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int ret;
struct bd_info *kbd;
void (*kernel) (struct bd_info *, ulong, ulong, ulong, ulong);
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
+#if defined(CONFIG_MCFFEC)
static int fec_get_node(int fec_idx)
{
char fec_alias[5] = {"fec"};
return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
}
-#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
+#endif //CONFIG_MCFFEC
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <config.h>
+#include <cpu_func.h>
#include <init.h>
#include <watchdog.h>
#include <command.h>
return 0;
}
+
+void reset_cpu(void)
+{
+ /* TODO: Refactor all the do_reset calls to be reset_cpu() instead */
+ do_reset(NULL, 0, 0, NULL);
+}
* Yasushi SHOJI <yashi@atmark-techno.com>
*/
+#include <bootm.h>
#include <bootstage.h>
#include <command.h>
#include <cpu_func.h>
}
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
images->cmdline_start = (ulong)env_get("bootargs");
/* cmdline init is the part of 'prep' and nothing to do for 'bdt' */
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*/
+#include <cpu_func.h>
#include <command.h>
#include <init.h>
#include <linux/compiler.h>
/* NOP */;
}
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+void reset_cpu(void)
{
_machine_restart();
+}
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ reset_cpu();
return 0;
}
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include <linux/types.h>
#include <asm/regdef.h>
-#include <asm/types.h>
struct octeon_eeprom_mac_addr {
u8 mac_addr_base[6];
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
BUILDIO_MEM(q, u64)
+#define __raw_readb __raw_readb
+#define __raw_readw __raw_readw
+#define __raw_readl __raw_readl
+#define __raw_readq __raw_readq
+#define __raw_writeb __raw_writeb
+#define __raw_writew __raw_writew
+#define __raw_writel __raw_writel
+#define __raw_writeq __raw_writeq
+#define readb readb
+#define readw readw
+#define readl readl
+#define readq readq
+#define writeb writeb
+#define writew writew
+#define writel writel
+#define writeq writeq
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
__BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \
} \
} \
\
-static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+static inline void reads##bwlq(const volatile void __iomem *mem, \
+ void *addr, \
unsigned int count) \
{ \
volatile type *__addr = addr; \
BUILDSTRING(b, u8)
BUILDSTRING(w, u16)
BUILDSTRING(l, u32)
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
+#define insb insb
+#define insw insw
+#define insl insl
#ifdef CONFIG_64BIT
BUILDSTRING(q, u64)
+#define readsq readsq
+#define writesq writesq
+#define insq insq
+#define outsq outsq
#endif
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <bootm.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
{
/*
* In case of legacy uImage's, relocation of FDT is already done
- * by do_bootm_states() and should not repeated in 'bootm prep'.
+ * by bootm_run_states() and should not repeated in 'bootm prep'.
*/
if (images->state & BOOTM_STATE_FDT) {
debug("## FDT already relocated\n");
{
images->initrd_start = virt_to_phys((void *)images->initrd_start);
images->initrd_end = virt_to_phys((void *)images->initrd_end);
- return image_setup_libfdt(images, images->ft_addr, images->ft_len,
- &images->lmb);
+
+ return image_setup_libfdt(images, images->ft_addr, &images->lmb);
}
static void boot_prep_linux(struct bootm_headers *images)
linux_extra);
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* No need for those on MIPS */
if (flag & BOOTM_STATE_OS_BD_T)
return -1;
return str;
}
#endif
-#ifdef CONFIG_CMD_CLK
-
-int soc_clk_dump(void)
-{
- int i;
-
- printf("PLL Speed: %lu MHz\n",
- CLK_MHZ(rate(PLLCLK)));
-
- printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
-
- printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
-
- for (i = PB1CLK; i <= PB7CLK; i++)
- printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
- CLK_MHZ(rate(i)));
-
- for (i = REF1CLK; i <= REF5CLK; i++)
- printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
- CLK_MHZ(rate(i)));
- return 0;
-}
-#endif
}
#endif
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+void reset_cpu(void)
{
disable_interrupts();
/* indirect call to go beyond 256MB limitation of toolchain */
nios2_callr(gd->arch.reset_addr);
+}
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ reset_cpu();
+
return 0;
}
#ifndef __ASM_NIOS2_GLOBALDATA_H_
#define __ASM_NIOS2_GLOBALDATA_H_
+#include <linux/types.h>
+
/* Architecture-specific global data */
struct arch_global_data {
u32 dcache_line_size;
unsigned long *p = dst;
while (count--) *p++ = inl (port);
}
+#define insb insb
+#define insw insw
+#define insl insl
static inline void outsb (unsigned long port, const void *src, unsigned long count)
{
const unsigned long *p = src;
while (count--) outl (*p++, port);
}
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/*
* Clear and set bits in one shot. These macros can be used to clear and
*/
#include <common.h>
+#include <bootm.h>
#include <cpu_func.h>
#include <env.h>
#include <image.h>
#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*kernel)(int, int, int, char *) = (void *)images->ep;
char *commandline = env_get("bootargs");
ulong initrd_start = images->rd_start;
if (images->ft_len)
of_flat_tree = images->ft_addr;
#endif
- if (!of_flat_tree && argc > 1)
- of_flat_tree = (char *)hextoul(argv[1], NULL);
+ /* TODO: Clean this up - the DT should already be set up */
+ if (!of_flat_tree && bmi->argc > 1)
+ of_flat_tree = (char *)hextoul(bmi->argv[1], NULL);
if (of_flat_tree)
initrd_end = (ulong)of_flat_tree;
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <asm-offsets.h>
#include <mpc83xx.h>
#include <system-constants.h>
#ifdef CONFIG_QE
#include <fsl_qe.h>
#endif
+#include <asm/ppc.h>
+#include <asm/fsl_lbc.h>
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/fsl_lbc.h>
#include <asm/u-boot.h>
#include "hrcw/hrcw.h"
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <display_options.h>
#include <env.h>
#include <init.h>
* Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
*/
-#include <common.h>
#include <cpu_func.h>
#include <asm/processor.h>
#include <asm/ppc.h>
* Wolfgang Denk <wd@denx.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <display_options.h>
#include <net.h>
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <init.h>
#include <watchdog.h>
* Code copied & edited from Freescale mpc85xx stuff.
*/
-#include <common.h>
#include <time.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
* MPC8xx Internal Memory Map Functions
*/
-#include <common.h>
#include <command.h>
#include <asm/global_data.h>
#include <asm/cpm_8xx.h>
#include <asm/iopin_8xx.h>
#include <asm/io.h>
+#include <asm/ppc.h>
DECLARE_GLOBAL_DATA_PTR;
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
+#include <stdio.h>
#include <irq_func.h>
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <clock_legacy.h>
#include <mpc8xx.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/immap_8xx.h>
DECLARE_GLOBAL_DATA_PTR;
* This file handles the architecture-dependent parts of hardware exceptions
*/
-#include <common.h>
+#include <vsprintf.h>
#include <asm/ptrace.h>
#include <command.h>
#include <asm/processor.h>
#ifndef __ASM_PPC_FSL_LBC_H
#define __ASM_PPC_FSL_LBC_H
-#include <config.h>
-#include <common.h>
-
#ifdef CONFIG_MPC85xx
void lbc_sdram_init(void);
#endif
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-#include <config.h>
-#include "asm/types.h"
+#include <linux/types.h>
/* Architecture-specific global data */
struct arch_global_data {
{
return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
}
+#define __raw_readb __raw_readb
+
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
}
+#define __raw_readw __raw_readw
+
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
}
+#define __raw_readl __raw_readl
+
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writeb __raw_writeb
+
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writew __raw_writew
+
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writel __raw_writel
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <cpu_func.h>
#include <env.h>
return 0;
}
-noinline int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int ret;
if (flag & BOOTM_STATE_OS_CMDLINE) {
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <command.h>
+#include <cpu_func.h>
#include <init.h>
#include <asm/global_data.h>
return 0;
}
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(void)
+{
+ /* TODO: Refactor all the do_reset calls to be reset_cpu() instead */
+ do_reset(NULL, 0, 0, NULL);
+}
+#endif
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
select SYS_CACHE_SHIFT_6
+config TARGET_XILINX_MBV
+ bool "Support AMD/Xilinx MicroBlaze V"
+
endchoice
config SYS_ICACHE_OFF
source "board/sipeed/maix/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
+source "board/xilinx/mbv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
- mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
- MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+ mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
+ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
+ MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
+
+ if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+ mcache_ctl_val |= MCACHE_CTL_IC_EN;
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
- /*
- * Check mcache_ctl.DC_COHEN, we assume this platform does
- * not support CM if the bit is hard-wired to 0.
- */
- if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
- /* Wait for DC_COHSTA bit to be set */
- while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ /*
+ * Check mcache_ctl.DC_COHEN, we assume this platform does
+ * not support CM if the bit is hard-wired to 0.
+ */
+ if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+ /* Wait for DC_COHSTA bit to be set */
+ while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+ }
}
+
+ mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+ csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
}
}
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
+#include <command.h>
#include <cpu.h>
+#include <cpu_func.h>
#include <dm.h>
#include <dm/lists.h>
#include <event.h>
+#include <hang.h>
#include <init.h>
#include <log.h>
#include <asm/encoding.h>
__weak void harts_early_init(void)
{
}
+
+#if !CONFIG_IS_ENABLED(SYSRESET)
+void reset_cpu(void)
+{
+ printf("resetting ...\n");
+
+ printf("reset not supported yet\n");
+ hang();
+}
+#endif
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
#include <config.h>
-#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
-#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
-
/ {
binman: binman {
multiple-images;
os = "U-Boot";
arch = "riscv";
compression = "none";
- load = <U64_TO_U32_H(CONFIG_TEXT_BASE)
- U64_TO_U32_L(CONFIG_TEXT_BASE)>;
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
os = "Linux";
arch = "riscv";
compression = "none";
- load = <CONFIG_TEXT_BASE>;
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
linux_blob: blob-ext {
filename = "Image";
os = "opensbi";
arch = "riscv";
compression = "none";
- load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
- U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
- entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
- U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
+ load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";
device_type = "memory";
reg = <0x0 0x40000000 0x2 0x0>;
};
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+ };
};
&osc {
#gpio-cells = <2>;
};
+ watchdog@13070000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
+ clock-names = "apb", "core";
+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+ <&syscrg JH7110_SYSRST_WDT_CORE>;
+ };
+
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "AMD MicroBlaze V 32bit";
+ compatible = "qemu,mbv", "amd,mbv";
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <102000000>;
+ cpu_0: cpu@0 {
+ compatible = "amd,mbv32", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv32imafdc";
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ clock-frequency = <102000000>;
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x20000000>;
+ };
+
+ clk102: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <102000000>;
+ };
+
+ axi: axi {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bootph-all;
+
+ axi_intc: interrupt-controller@41200000 {
+ compatible = "xlnx,xps-intc-1.00.a";
+ reg = <0x41200000 0x1000>;
+ interrupt-controller;
+ interrupt-parent = <&cpu0_intc>;
+ #interrupt-cells = <2>;
+ kind-of-intr = <0>;
+ };
+
+ xlnx_timer0: timer@41c00000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ reg = <0x41c00000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <1 2>;
+ bootph-all;
+ xlnx,one-timer-only = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&clk102>;
+ };
+
+ xlnx_timer1: timer@41c20000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ reg = <0x41c20000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <0 2>;
+ xlnx,one-timer-only = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&clk102>;
+ };
+
+ uart0: serial@40600000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ reg = <0x40600000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <2 2>;
+ bootph-all;
+ clocks = <&clk102>;
+ current-speed = <115200>;
+ xlnx,data-bits = <8>;
+ xlnx,use-parity = <0>;
+ };
+ };
+};
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
-#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc
-#define MCACHE_CTL_IC_EN_OFFSET 0
-#define MCACHE_CTL_DC_EN_OFFSET 1
-#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
-#define MCACHE_CTL_DC_COHEN_OFFSET 19
-#define MCACHE_CTL_DC_COHSTA_OFFSET 20
-
-#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
-#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
-#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
-#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
+/* mcache_ctl register */
+
+#define MCACHE_CTL_IC_EN BIT(0)
+#define MCACHE_CTL_DC_EN BIT(1)
+#define MCACHE_CTL_IC_ECCEN BIT(3)
+#define MCACHE_CTL_DC_ECCEN BIT(5)
+#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
+#define MCACHE_CTL_TLB_ECCEN BIT(18)
+#define MCACHE_CTL_DC_COHEN BIT(19)
+#define MCACHE_CTL_DC_COHSTA BIT(20)
+
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
+#define CSR_MARCHID 0xf12
#define CSR_MHARTID 0xf14
#ifndef __ASSEMBLY__
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include <linux/types.h>
#include <asm/smp.h>
#include <asm/u-boot.h>
#include <compiler.h>
ulong available_harts;
#endif
#endif
+#if CONFIG_IS_ENABLED(ACPI)
+ ulong table_start; /* Start address of ACPI tables */
+ ulong table_end; /* End address of ACPI tables */
+ ulong table_start_high; /* Start address of high ACPI tables */
+ ulong table_end_high; /* End address of high ACPI tables */
+#endif
#ifdef CONFIG_SMBIOS
ulong smbios_start; /* Start address of SMBIOS table */
#endif
#define insw(p, d, l) readsw(__io(p), d, l)
#define insl(p, d, l) readsl(__io(p), d, l)
-static inline void readsb(unsigned int *addr, void *data, int bytelen)
+static inline void readsb(const volatile void __iomem *addr, void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
}
}
-static inline void readsw(unsigned int *addr, void *data, int wordlen)
+static inline void readsw(const volatile void __iomem *addr, void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
}
}
-static inline void readsl(unsigned int *addr, void *data, int longlen)
+static inline void readsl(const volatile void __iomem *addr, void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
}
}
-static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+static inline void writesb(volatile void __iomem *addr, const void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
}
}
-static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+static inline void writesw(volatile void __iomem *addr, const void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
}
}
-static inline void writesl(unsigned int *addr, const void *data, int longlen)
+static inline void writesl(volatile void __iomem *addr, const void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
longlen--;
}
}
+
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+
#endif
#define outb_p(val, port) outb((val), (port))
#include <linux/err.h>
/* pending register */
-#define PENDING_REG(base) ((ulong)(base) + 0x1000)
+#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32))
/* enable register */
-#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32))
/* claim register */
#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
/* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
-#define FIRST_AVAILABLE_BIT 0x2
-#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
#define PLICSW_PRIORITY_BASE 0x4
-#define PLICSW_INTERRUPT_PER_HART 0x1
DECLARE_GLOBAL_DATA_PTR;
static int enable_ipi(int hart)
{
- unsigned int en;
+ u32 enable_bit = (hart + 1) % 32;
- en = FIRST_AVAILABLE_BIT << hart;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
+ writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
return 0;
}
static void init_priority_ipi(int hart_num)
{
- uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
+ u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
- for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
- writel(1, &priority[i]);
- }
+ for (int i = 0; i < hart_num; i++)
+ writel(1, &priority[i]);
- return;
+ return;
}
int riscv_init_ipi(void)
int riscv_send_ipi(int hart)
{
- unsigned int ipi = SEND_IPI_TO_HART(hart);
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
+ writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
return 0;
}
int riscv_get_ipi(int hart, int *pending)
{
- unsigned int ipi = SEND_IPI_TO_HART(hart);
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
- *pending = !!(*pending & ipi);
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
+ *pending = !!(*pending & BIT(pending_bit));
return 0;
}
*/
#include <bootstage.h>
+#include <bootm.h>
#include <command.h>
#include <dm.h>
#include <fdt_support.h>
}
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* No need for those on RISC-V */
if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
return -1;
return 0;
}
-int do_bootm_vxworks(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_vxworks(int flag, struct bootm_info *bmi)
{
- return do_bootm_linux(flag, argc, argv, images);
+ return do_bootm_linux(flag, bmi);
}
static ulong get_sp(void)
*/
#include <command.h>
-#include <hang.h>
+#include <cpu_func.h>
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- printf("resetting ...\n");
-
- printf("reset not supported yet\n");
- hang();
+ reset_cpu();
return 0;
}
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#ifndef CONFIG_SPL_BUILD
void enable_caches(void)
{
struct udevice *dev;
log_debug("ccache enable failed");
}
}
+#else
+static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
+{
+ for (uclass_find_first_device(UCLASS_CACHE, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ if (dev->driver == driver)
+ device_probe(dev);
+ }
+}
+
+void enable_caches(void)
+{
+ struct udevice *dev = NULL;
+
+ probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
+}
+#endif /* !CONFIG_SPL_BUILD */
* Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <asm/state.h>
#define LOG_CATEGORY LOGC_SANDBOX
-#include <common.h>
#include <bootstage.h>
#include <cpu_func.h>
#include <errno.h>
enable_pci_map = enable;
}
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
int dcache_status(void)
{
return 1;
return 0;
}
+int os_mktemp(char *fname, off_t size)
+{
+ int fd;
+
+ fd = mkostemp(fname, O_CLOEXEC);
+ if (fd < 0)
+ return -errno;
+
+ if (unlink(fname) < 0)
+ return -errno;
+
+ if (ftruncate(fd, size))
+ return -errno;
+
+ return fd;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
static void sandbox_sdl_poll_events(void)
{
/*
- * We don't want to include common.h in this file since it uses
+ * We don't want to include cpu_func.h in this file since it uses
* system headers. So add a declation here.
*/
extern void reset_cpu(void);
* Copyright (c) 2016 Google, Inc
*/
-#include <common.h>
#include <dm.h>
#include <hang.h>
#include <handoff.h>
* Copyright (c) 2011-2012 The Chromium OS Authors.
*/
-#include <common.h>
+#include <config.h>
#include <cli.h>
#include <command.h>
#include <efi_loader.h>
* Copyright (c) 2011-2012 The Chromium OS Authors.
*/
-#include <common.h>
-#include <autoboot.h>
#include <bloblist.h>
+#include <config.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
<&clk_sandbox 0>,
+ <&ccf 11>,
<&clk_sandbox 3>,
<&clk_sandbox 2>;
- clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
+ clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
};
clk-test2 {
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
+ #clock-cells = <1>;
};
efi-media {
compatible = "sandbox,arm-ffa";
};
};
+
+ nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sandbox,nand";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ sandbox,id = [00 e3];
+ sandbox,erasesize = <(8 * 1024)>;
+ sandbox,oobsize = <16>;
+ sandbox,pagesize = <512>;
+ sandbox,pages = <0x2000>;
+ sandbox,err-count = <1>;
+ sandbox,err-step-size = <512>;
+ };
+
+ /* MT29F64G08AKABA */
+ nand@1 {
+ reg = <1>;
+ nand-ecc-mode = "soft_bch";
+ sandbox,id = [2C 48 00 26 89 00 00 00];
+ sandbox,onfi = [
+ 4f 4e 46 49 0e 00 5a 00
+ ff 01 00 00 00 00 03 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 4d 49 43 52 4f 4e 20 20
+ 20 20 20 20 4d 54 32 39
+ 46 36 34 47 30 38 41 4b
+ 41 42 41 43 35 20 20 20
+ 2c 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 10 00 00 e0 00 00 02
+ 00 00 1c 00 80 00 00 00
+ 00 10 00 00 02 23 01 50
+ 00 01 05 01 00 00 04 00
+ 04 01 1e 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 0e 1f 00 1f 00 f4 01 ac
+ 0d 19 00 c8 00 00 00 00
+ 00 00 00 00 00 00 0a 07
+ 19 00 00 00 00 00 00 00
+ 00 00 00 00 01 00 01 00
+ 00 00 04 10 01 81 04 02
+ 02 01 1e 90 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 03 20 7d
+ ];
+ sandbox,erasesize = <(512 * 1024)>;
+ sandbox,oobsize = <224>;
+ sandbox,pagesize = <4096>;
+ sandbox,pages = <0x200000>;
+ sandbox,err-count = <3>;
+ sandbox,err-step-size = <512>;
+ };
+ };
};
#include "sandbox_pmic.dtsi"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#define nop()
#ifndef __SANDBOX_CLK_H
#define __SANDBOX_CLK_H
-#include <common.h>
#include <clk.h>
#include <dt-structs.h>
#include <linux/clk-provider.h>
SANDBOX_CLK_TEST_ID_FIXED,
SANDBOX_CLK_TEST_ID_SPI,
SANDBOX_CLK_TEST_ID_I2C,
+ SANDBOX_CLK_TEST_ID_I2C_ROOT,
SANDBOX_CLK_TEST_ID_DEVM1,
SANDBOX_CLK_TEST_ID_DEVM2,
SANDBOX_CLK_TEST_ID_DEVM_NULL,
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include <linux/types.h>
+
/* Architecture-specific global data */
struct arch_global_data {
uint8_t *ram_buf; /* emulated RAM buffer */
#ifndef __SANDBOX_ASM_IO_H
#define __SANDBOX_ASM_IO_H
+#include <linux/types.h>
+
enum sandboxio_size_t {
SB_SIZE_8,
SB_SIZE_16,
void unmap_physmem(const void *vaddr, unsigned long flags);
#define unmap_physmem unmap_physmem
-#include <asm-generic/io.h>
-
-/* For sandbox, we want addresses to point into our RAM buffer */
-static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
-{
- return map_physmem(paddr, len, MAP_WRBACK);
-}
-
-/* Remove a previous mapping */
-static inline void unmap_sysmem(const void *vaddr)
-{
- unmap_physmem(vaddr, MAP_WRBACK);
-}
-
/* Map from a pointer to our RAM buffer */
phys_addr_t map_to_sysmem(const void *ptr);
#include <iotrace.h>
#include <asm/types.h>
+#include <asm-generic/io.h>
+
+/* For sandbox, we want addresses to point into our RAM buffer */
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return map_physmem(paddr, len, MAP_WRBACK);
+}
+
+/* Remove a previous mapping */
+static inline void unmap_sysmem(const void *vaddr)
+{
+ unmap_physmem(vaddr, MAP_WRBACK);
+}
+
+/**
+ * nomap_sysmem() - pass through an address unchanged
+ *
+ * This is used to indicate an address which should NOT be mapped, e.g. in
+ * SMBIOS tables. Using this function instead of a case shows that the sandbox
+ * conversion has been done
+ */
+static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t nomap_to_sysmem(const void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
#endif
#ifndef __SANDBOX_MBOX_H
#define __SANDBOX_MBOX_H
-#include <common.h>
-
#define SANDBOX_MBOX_PING_XOR 0x12345678
struct udevice;
#ifndef __SANDBOX_POWER_DOMAIN_H
#define __SANDBOX_POWER_DOMAIN_H
-#include <common.h>
-
struct udevice;
int sandbox_power_domain_query(struct udevice *dev, unsigned long id);
#ifndef __SANDBOX_RESET_H
#define __SANDBOX_RESET_H
-#include <common.h>
-
struct udevice;
int sandbox_reset_query(struct udevice *dev, unsigned long id);
BOOT_DEVICE_CPGMAC,
BOOT_DEVICE_NOR,
BOOT_DEVICE_SPI,
+ BOOT_DEVICE_NAND,
};
/**
#ifndef __SANDBOX_STATE_H
#define __SANDBOX_STATE_H
-#include <config.h>
#include <sysreset.h>
#include <stdbool.h>
#include <linux/list.h>
* Copyright (c) 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
*/
-#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <image.h>
#include <asm/io.h>
return 0;
}
-int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
if (flag & BOOTM_STATE_OS_PREP)
return boot_prep_linux(images);
return 0;
}
+
+/* used for testing 'booti' command */
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+ bool force_reloc)
+{
+ return 0;
+}
#define LOG_CATEGORY LOGC_ARCH
-#include <common.h>
#include <fdt_support.h>
#include <log.h>
* found in the LICENSE file.
*/
-#include <common.h>
#include <efi_loader.h>
#include <irq_func.h>
#include <os.h>
* IO space access commands.
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
#include <log.h>
*/
#include <common.h>
+#include <bootm.h>
#include <command.h>
#include <env.h>
#include <image.h>
return val;
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* Linux kernel load address */
void (*kernel) (void) = (void (*)(void))images->ep;
/* empty_zero_page */
#include <cpu.h>
#include <dm.h>
#include <log.h>
+#include <mapmem.h>
#include <acpi/acpi_s3.h>
#include <acpi/acpi_table.h>
#include <asm/io.h>
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
- fadt->x_dsdt_h = 0;
+ fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
+ fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
imply X86_TSC_READ_BASE
imply USE_PREBOOT
select BINMAN if X86_64
+ select SYSINFO
+ imply SYSINFO_EXTRA
endif
*/
#include <common.h>
+#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/processor.h>
#include <asm/tables.h>
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
- fadt->x_dsdt_h = 0;
+ fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
+ fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
#include <common.h>
#include <cpu.h>
#include <dm.h>
+#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/ioapic.h>
#include <asm/mpspec.h>
header->length = sizeof(struct acpi_fadt);
header->revision = 6;
- fadt->firmware_ctrl = (u32)ctx->facs;
- fadt->dsdt = (u32)ctx->dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
fadt->minor_revision = 2;
- fadt->x_firmware_ctl_l = (u32)ctx->facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)ctx->dsdt;
- fadt->x_dsdt_h = 0;
+ fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
+ fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
header->checksum = table_compute_checksum(fadt, header->length);
SECTIONS
{
-#ifndef CONFIG_CMDLINE
- /DISCARD/ : { *(__u_boot_list_2_cmd_*) }
-#endif
-
#ifdef CONFIG_TEXT_BASE
. = CONFIG_TEXT_BASE; /* Location of bootcode in flash */
#endif
SECTIONS
{
-#ifndef CONFIG_CMDLINE
- /DISCARD/ : { *(__u_boot_list_2_cmd_*) }
-#endif
-
. = IMAGE_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
.text : {
SECTIONS
{
-#ifndef CONFIG_CMDLINE
- /DISCARD/ : { *(__u_boot_list_2_cmd_*) }
-#endif
-
. = CONFIG_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x008e0000 0x00010000>;
- bootph-all;
+ bootph-some-ram;
+ bootph-pre-ram;
};
rw-var-mrc-cache {
label = "rw-mrc-cache";
reg = <0x008f0000 0x0001000>;
- bootph-all;
+ bootph-some-ram;
+ bootph-pre-ram;
};
};
};
bootph-some-ram;
compatible = "coreboot-fb";
};
+
+ sysinfo {
+ compatible = "coreboot,sysinfo";
+ };
};
*/
int acpi_create_gnvs(struct acpi_global_nvs *gnvs);
-/**
- * acpi_get_rsdp_addr() - get ACPI RSDP table address
- *
- * This routine returns the ACPI RSDP table address in the system memory.
- *
- * @return: ACPI RSDP table address
- */
-ulong acpi_get_rsdp_addr(void);
-
/**
* arch_read_sci_irq_select() - Read the system-control interrupt number
*
#ifndef __SLIMBOOTLOADER_ARCH_H__
#define __SLIMBOOTLOADER_ARCH_H__
-#include <common.h>
#include <asm/hob.h>
/**
#ifndef __ASM_X86_DMA_MAPPING_H
#define __ASM_X86_DMA_MAPPING_H
-#include <common.h>
#include <asm/cache.h>
#include <cpu_func.h>
#include <linux/dma-direction.h>
#ifndef __ASSEMBLY__
+#include <linux/types.h>
#include <asm/processor.h>
#include <asm/mrccache.h>
__INS(b)
__INS(w)
__INS(l)
+#define insb insb
+#define insw insw
+#define insl insl
__OUTS(b)
__OUTS(w)
__OUTS(l)
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/* IO space accessors */
#define clrio(type, addr, clear) \
tcpa->platform_class = 0;
tcpa->laml = size;
- tcpa->lasa = map_to_sysmem(log);
+ tcpa->lasa = nomap_to_sysmem(log);
/* (Re)calculate length and checksum */
current = (u32)tcpa + sizeof(struct acpi_tcpa);
/* Fill the log area size and start address fields. */
tpm2->laml = tpm2_log_len;
- tpm2->lasa = map_to_sysmem(lasa);
+ tpm2->lasa = nomap_to_sysmem(lasa);
/* Calculate checksum. */
header->checksum = table_compute_checksum(tpm2, header->length);
u32 *gnvs = (u32 *)((u32)ctx->dsdt + i);
if (*gnvs == ACPI_GNVS_ADDR) {
- *gnvs = map_to_sysmem(ctx->current);
+ *gnvs = nomap_to_sysmem(ctx->current);
log_debug("Fix up global NVS in DSDT to %#08x\n",
*gnvs);
break;
memcpy(header->aslc_id, ASLC_ID, 4);
header->aslc_revision = 1;
- fadt->firmware_ctrl = (unsigned long)facs;
- fadt->dsdt = (unsigned long)dsdt;
-
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
+ fadt->x_firmware_ctrl = map_to_sysmem(facs);
+ fadt->x_dsdt = map_to_sysmem(dsdt);
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
*/
#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <command.h>
#include <efi.h>
images->os.arch == IH_ARCH_X86_64);
}
-int do_bootm_linux(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
/* No need for those on x86 */
if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
return -1;
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/coreboot_tables.h>
+#include <linux/log2.h>
DECLARE_GLOBAL_DATA_PTR;
if (!gd->arch.table_end)
gd->arch.table_end = rom_addr;
rom_addr = (ulong)bloblist_add(table->tag, size,
- table->align);
+ ilog2(table->align));
if (!rom_addr)
return log_msg_ret("bloblist", -ENOBUFS);
void outsb(unsigned long port, const void *src, unsigned long count);
void outsw(unsigned long port, const void *src, unsigned long count);
void outsl(unsigned long port, const void *src, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
#define IO_SPACE_LIMIT ~0
*/
#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <command.h>
#include <cpu_func.h>
* Boot Linux.
*/
-int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
+int do_bootm_linux(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
struct bp_tag *params, *params_start;
ulong initrd_start, initrd_end;
char *commandline = env_get("bootargs");
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
#endif
+#include <asm/csr.h>
#include <asm/global_data.h>
+#include <asm/sbi.h>
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
/*
* Miscellaneous platform dependent initializations
*/
+#if IS_ENABLED(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+ long csr_marchid = 0;
+ const long mask_64 = 0x8000;
+ const long mask_cpu = 0xff;
+ char cpu_name[10] = {};
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+ sbi_get_marchid(&csr_marchid);
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+ csr_marchid = csr_read(CSR_MARCHID);
+#endif
+ if (mask_64 & csr_marchid)
+ snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid));
+ else
+ snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
+
+ return env_set("cpu", cpu_name);
+}
+#endif
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
void spl_board_init()
{
/* enable v5l2 cache */
- enable_caches();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ enable_caches();
}
#endif
*/
#ifndef __CONFIG_BRRESETC_H__
#define __CONFIG_BRRESETC_H__
-#include <common.h>
int br_resetc_regget(u8 reg, u8 *dst);
int br_resetc_regset(u8 reg, u8 val);
#ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
#define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
-#include <common.h>
-
enum cznic_a3720_board {
BOARD_UNDEFINED = 0x0,
BOARD_TURRIS_MOX = 0x1,
}
}
-int show_board_info(void)
+int checkboard(void)
{
int i, ret, board_version, ram_size, is_sd;
const char *pub_key, *model;
return 0;
}
-int show_board_info(void)
+int checkboard(void)
{
char serial[17];
int err;
writel(0x1, (void *)CRM_SWRESET);
}
+/*
+ * Ethernet configuration
+ */
+#define ETH0_BASE_ADDRESS 0xFE100000
int board_eth_init(struct bd_info *bis)
{
if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
config SYS_CONFIG_NAME
default "grouper"
-config GROUPER_TPS65911
- bool "Enable support TI TPS65911 PMIC"
- select CMD_POWEROFF
-
-config GROUPER_MAX77663
- bool "Enable support MAXIM MAX77663 PMIC"
- select CMD_POWEROFF
-
endif
# Svyatoslav Ryhel <clamor95@gmail.com>
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o
-obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o
+obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
+obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
endif
obj-y += grouper.o
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
-CONFIG_GROUPER_MAX77663=y
+CONFIG_CMD_POWEROFF=y
+# CONFIG_MAX77663_GPIO is not set
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_REGULATOR_MAX77663=y
+CONFIG_SYSRESET_MAX77663=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269"
-CONFIG_GROUPER_TPS65911=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_DM_PMIC_TPS65910=y
+# CONFIG_DM_REGULATOR_TPS65910 is not set
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_SYSRESET_TPS65910=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565"
-CONFIG_GROUPER_MAX77663=y
CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # "
+CONFIG_CMD_POWEROFF=y
+# CONFIG_MAX77663_GPIO is not set
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_REGULATOR_MAX77663=y
+CONFIG_SYSRESET_MAX77663=y
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
-#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-grouper.h"
-
-#define TPS65911_I2C_ADDRESS 0x2D
-
-#define TPS65911_REG_LDO1 0x30
-#define TPS65911_REG_DEVCTRL 0x3F
-#define DEVCTRL_PWR_OFF_MASK BIT(7)
-#define DEVCTRL_DEV_ON_MASK BIT(2)
-#define DEVCTRL_DEV_OFF_MASK BIT(0)
-
-#define MAX77663_I2C_ADDRESS 0x3C
-
-#define MAX77663_REG_SD2 0x18
-#define MAX77663_REG_LDO3 0x29
-#define MAX77663_REG_ONOFF_CFG1 0x41
-#define ONOFF_PWR_OFF BIT(1)
-
-#ifdef CONFIG_CMD_POWEROFF
-#ifdef CONFIG_GROUPER_TPS65911
-int do_poweroff(struct cmd_tbl *cmdtp,
- int flag, int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
- data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif /* CONFIG_GROUPER_TPS65911 */
-
-#ifdef CONFIG_GROUPER_MAX77663
-int do_poweroff(struct cmd_tbl *cmdtp,
- int flag, int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= ONOFF_PWR_OFF;
-
- ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif /* CONFIG_GROUPER_MAX77663 */
-#endif /* CONFIG_CMD_POWEROFF */
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_config_pingrp_table(grouper_pinmux_common,
- ARRAY_SIZE(grouper_pinmux_common));
-
- pinmux_config_drvgrp_table(grouper_padctrl,
- ARRAY_SIZE(grouper_padctrl));
-}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void __maybe_unused tps65911_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
- ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-static void __maybe_unused max77663_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* 0x60 for 1.8v, bit7:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
- if (ret)
- log_debug("vdd_1v8_vio set failed: %d\n", ret);
-
- /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
-#ifdef CONFIG_GROUPER_MAX77663
- /* Bring up eMMC power on MAX PMIC */
- max77663_voltage_init();
-#endif
-
-#ifdef CONFIG_GROUPER_TPS65911
- /* Bring up eMMC power on TI PMIC */
- tps65911_voltage_init();
-#endif
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _PINMUX_CONFIG_GROUPER_H_
-#define _PINMUX_CONFIG_GROUPER_H_
-
-#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
- }
-
-#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static struct pmux_pingrp_config grouper_pinmux_common[] = {
- /* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
-
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* I2C pinmux */
- I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* HDMI-CEC pinmux */
- DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, DOWN, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_STP_PY3, RSVD1, NORMAL, TRISTATE, OUTPUT),
-
- /* DAP3 pinmux */
- DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, TRISTATE, INPUT),
-
- DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PV2, OWR, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, INPUT),
-
- /* CLK2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
-
- /* LCD pinmux */
- DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
-
- /* VI-group pinmux */
- LV_PINMUX(VI_D0_PT4, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1_PD5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2_PL0, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3_PL1, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4_PL2, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5_PL3, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6_PL4, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7_PL5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8_PL6, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9_PL7, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10_PT2, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11_PT3, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK_PT0, SDMMC2, UP, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK_PT1, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC_PD7, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC_PD6, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE),
-
- /* UART-B pinmux */
- DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
-
- /* UART-C pinmux */
- DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
-
- /* U-gpio group pinmux */
- DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU6, RSVD4, NORMAL, NORMAL, INPUT),
-
- /* DAP4 pinmux */
- DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
-
- /* CLK3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PCC1, RSVD2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
-
- /* KBC keys */
- DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
-
- /* CLK */
- DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
-
- /* DAP1 pinmux */
- DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
-
- /* CLK1 pinmux */
- DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
-
- /* DAP2 pinmux */
- DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, NORMAL, NORMAL, INPUT),
-
- /* PEX pinmux */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, OUTPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS0_N_PJ0, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD0_PG0, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1_PG1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2_PG2, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3_PG3, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD6_PG6, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7_PG7, RSVD1, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10_PH2, PWM2, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD13_PH5, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD14_PH6, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD15_PH7, RSVD1, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS_PI2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_RST_N_PI4, NAND, UP, NORMAL, OUTPUT),
-};
-
-static struct pmux_drvgrp_config grouper_padctrl[] = {
- /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
- DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
- SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
-};
-#endif /* _PINMUX_CONFIG_GROUPER_H_ */
config SYS_CONFIG_NAME
default "transformer-t30"
-config TRANSFORMER_SPI_BOOT
- bool "Enable support for SPI based flash"
- select TEGRA20_SLINK
- select DM_SPI_FLASH
- select SPI_FLASH_WINBOND
- help
- Tegra 3 based Transformers with Windows RT have core
- boot sequence (BCT and EBT) on separate SPI FLASH
- memory with 4MB size.
-
endif
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
-CONFIG_TRANSFORMER_SPI_BOOT=y
CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Copyright (c) 2021, Svyatoslav Ryhel.
- */
-
-#ifndef _PINMUX_CONFIG_TRANSFORMER_H_
-#define _PINMUX_CONFIG_TRANSFORMER_H_
-
-#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
- }
-
-#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static struct pmux_pingrp_config transformer_pinmux_common[] = {
- /* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
-
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* I2C pinmux */
- I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* HDMI-CEC pinmux */
- DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, DOWN, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, TRISTATE, OUTPUT),
-
- /* DAP3 pinmux */
- DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, OUTPUT),
-
- /* CLK2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
-
- /* LCD pinmux */
- DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, TRISTATE, OUTPUT),
-
- /* VI-group pinmux */
- LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* UART-B pinmux */
- DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
-
- /* UART-C pinmux */
- DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
-
- /* U-gpio group pinmux */
- DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU4, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU6, RSVD1, DOWN, NORMAL, INPUT),
-
- /* DAP4 pinmux */
- DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
-
- /* CLK3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, TRISTATE, INPUT),
-
- DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
-
- /* KBC keys */
- DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL4_PQ4, RSVD4, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT),
-
- /* CLK */
- DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
-
- /* DAP1 pinmux */
- DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, INPUT),
-
- /* CLK1 pinmux */
- DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
-
- /* DAP2 pinmux */
- DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
-
- /* PEX pinmux */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD13_PH5, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD15_PH7, NAND, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
-};
-
-static struct pmux_pingrp_config tf700t_mipi_pinmux[] = {
- DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, TRISTATE, INPUT),
-};
-
-static struct pmux_drvgrp_config transformer_padctrl[] = {
- /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
- DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
- SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
-};
-#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
/* T30 Transformers derive from Cardhu board */
-#include <common.h>
-#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-transformer.h"
-
-#define TPS65911_I2C_ADDRESS 0x2D
-
-#define TPS65911_VDD1 0x21
-#define TPS65911_VDD1_OP 0x22
-#define TPS65911_LDO1 0x30
-#define TPS65911_LDO2 0x31
-#define TPS65911_LDO3 0x37
-#define TPS65911_LDO5 0x32
-#define TPS65911_LDO6 0x35
-
-#define TPS65911_DEVCTRL 0x3F
-#define DEVCTRL_PWR_OFF_MASK BIT(7)
-#define DEVCTRL_DEV_ON_MASK BIT(2)
-#define DEVCTRL_DEV_OFF_MASK BIT(0)
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
- data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_config_pingrp_table(transformer_pinmux_common,
- ARRAY_SIZE(transformer_pinmux_common));
-
- pinmux_config_drvgrp_table(transformer_padctrl,
- ARRAY_SIZE(transformer_padctrl));
-
- if (of_machine_is_compatible("asus,tf700t")) {
- pinmux_config_pingrp_table(tf700t_mipi_pinmux,
- ARRAY_SIZE(tf700t_mipi_pinmux));
- }
-}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void tps65911_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-
- if (of_machine_is_compatible("asus,tf600t")) {
- /* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */
- ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33);
- if (ret)
- log_debug("vdd_bl set failed: %d\n", ret);
-
- ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d);
- if (ret)
- log_debug("vdd_bl enable failed: %d\n", ret);
-
- /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11);
- if (ret)
- log_debug("vdd_mipi set failed: %d\n", ret);
- } else {
- /* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d);
- if (ret)
- log_debug("vddio_usd set failed: %d\n", ret);
- }
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up uSD and eMMC power */
- tps65911_voltage_init();
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
default "beagle"
config SYS_VENDOR
- default "ti"
+ default "beagle"
config SYS_CONFIG_NAME
default "omap3_beagle"
BEAGLE BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
-F: board/ti/beagle/
+F: board/beagle/beagle/
F: include/configs/omap3_beagle.h
F: configs/omap3_beagle_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+choice
+ prompt "BeagleBoard.org J721E/TDA4VM based BeagleBone AI-64 board"
+ optional
+
+config TARGET_J721E_A72_BEAGLEBONEAI64
+ bool "BeagleBoard.org J721E BeagleBone AI-64 running on A72"
+ select ARM64
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721E_R5_BEAGLEBONEAI64
+ bool "BeagleBoard.org J721E BeagleBone AI-64 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_J721E_A72_BEAGLEBONEAI64
+
+config SYS_BOARD
+ default "beagleboneai64"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721E_R5_BEAGLEBONEAI64
+
+config SYS_BOARD
+ default "beagleboneai64"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
--- /dev/null
+BEAGLEBONE-AI64 BOARD
+M: Nishanth Menon <nm@ti.com>
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+N: beagleboneai64
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# https://beagleboard.org/ai-64
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+obj-y += beagleboneai64.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include <cpu_func.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J721E
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J721E
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J721E
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - #1
+ host_id: 3
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #2
+ host_id: 5
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #3
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #4
+ host_id: 13
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #5
+ host_id: 21
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #6
+ host_id: 26
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #7
+ host_id: 28
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #8
+ host_id: 35
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #9
+ host_id: 37
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #10
+ host_id: 40
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #11
+ host_id: 42
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 3344
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 4
+ num_resource: 93
+ type: 7744
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 93
+ type: 7808
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 7872
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 8192
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 32
+ type: 8192
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 24
+ type: 8320
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 24
+ type: 8320
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 8384
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 8
+ type: 8384
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 8384
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 8384
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 8384
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 8384
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 4
+ type: 8384
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 4
+ type: 8384
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 40
+ num_resource: 12
+ type: 8384
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 52
+ num_resource: 12
+ type: 8384
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 128
+ type: 8576
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 128
+ num_resource: 128
+ type: 8576
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 128
+ type: 8640
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 128
+ num_resource: 128
+ type: 8640
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 48
+ type: 8704
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 8768
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 8
+ type: 8768
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 8768
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 6
+ type: 8768
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 8768
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 8768
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 13258
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 20480
+ num_resource: 1024
+ type: 13261
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 13322
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 22528
+ num_resource: 1024
+ type: 13325
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 86
+ type: 13386
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 124
+ num_resource: 32
+ type: 13386
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 12
+ type: 13386
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 12
+ type: 13386
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 180
+ num_resource: 12
+ type: 13386
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 192
+ num_resource: 12
+ type: 13386
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 204
+ num_resource: 12
+ type: 13386
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 216
+ num_resource: 28
+ type: 13386
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 244
+ num_resource: 8
+ type: 13386
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 252
+ num_resource: 4
+ type: 13386
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 1024
+ type: 13389
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 1062
+ num_resource: 512
+ type: 13389
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 1574
+ num_resource: 32
+ type: 13389
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 1606
+ num_resource: 32
+ type: 13389
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 1638
+ num_resource: 256
+ type: 13389
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 1894
+ num_resource: 256
+ type: 13389
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 2150
+ num_resource: 256
+ type: 13389
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 2406
+ num_resource: 256
+ type: 13389
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 2662
+ num_resource: 256
+ type: 13389
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 2918
+ num_resource: 512
+ type: 13389
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 3430
+ num_resource: 256
+ type: 13389
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 3686
+ num_resource: 922
+ type: 13389
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 13440
+ host_id: 12
+ reserved: 0
+
+ -
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--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for J721E
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ write_host_id: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+choice
+ prompt "BeagleBoard.org AM625 based BeaglePlay board"
+ optional
+
+config TARGET_AM625_A53_BEAGLEPLAY
+ bool "BeagleBoard.org AM625 BeaglePlay running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_AM625_R5_BEAGLEPLAY
+ bool "BeagleBoard.org AM625 BeaglePlay running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_AM625_A53_BEAGLEPLAY
+
+config SYS_BOARD
+ default "beagleplay"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM625_R5_BEAGLEPLAY
+
+config SYS_BOARD
+ default "beagleplay"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
--- /dev/null
+BEAGLEPLAY BOARD
+M: Nishanth Menon <nm@ti.com>
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+N: beagleplay
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# https://beagleboard.org/play
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+obj-y += beagleplay.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleplay.org/
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include <cpu_func.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
--- /dev/null
+#include <env/ti/ti_common.env>
+#include <env/ti/default_findfdt.env>
+#include <env/ti/mmc.env>
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+set_led_state_fail_load= led led-0 off; led led-1 on;
+ led led-2 off; led led-3 on; led led-4 off
+set_led_state_start_load=led led-0 on; led led-1 off;
+ led led-2 on; led led-3 off; led led-4 on
+boot=mmc
+mmcdev=1
+bootpart=1:1
+bootdir=/boot
+boot_targets=mmc1 mmc0 usb pxe
+bootmeths=script extlinux efi pxe
+rd_spec=-
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable : 0x5A
+ main_isolation_hostid : 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor : 0x1
+ scaling_profile : 0x1
+ disable_main_nav_secure_proxy : 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size : 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables : 0x00
+ trace_src_enables : 0x00
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size : 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #2
+ host_id: 30
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #3
+ host_id: 36
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #4
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #5
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #6
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #7
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #8
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #9
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #10
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #11
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #12
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #13
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #14
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #15
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #16
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #17
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #18
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #19
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #20
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #21
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #22
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #23
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #24
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #25
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #26
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #27
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #28
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #29
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #30
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #31
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #32
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size : 8
+ resasg_entries_size: 960
+ reserved : 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 64
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 22
+ type: 64
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 320
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
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+ type: 1667
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
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+ type: 1677
+ host_id: 12
+ reserved: 0
+
+ -
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+ type: 1677
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+ reserved: 0
+
+ -
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+ type: 1677
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+ reserved: 0
+
+ -
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+ reserved: 0
+
+ -
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+ reserved: 0
+
+ -
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+ type: 1678
+ host_id: 12
+ reserved: 0
+
+ -
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+ reserved: 0
+
+ -
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+ type: 1678
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+
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+
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+
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+
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+
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
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+
+ -
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+ num_resource: 6
+ type: 1696
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1697
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 1697
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5
+ num_resource: 35
+ type: 1802
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 8
+ type: 1802
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 512
+ type: 1805
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 525
+ num_resource: 256
+ type: 1805
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 525
+ num_resource: 256
+ type: 1805
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 781
+ num_resource: 128
+ type: 1805
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 909
+ num_resource: 627
+ type: 1805
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1024
+ type: 1807
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1808
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1809
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1810
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1812
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 6656
+ num_resource: 51
+ type: 1813
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1815
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1816
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9728
+ num_resource: 22
+ type: 1817
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10240
+ num_resource: 22
+ type: 1818
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10752
+ num_resource: 22
+ type: 1819
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11264
+ num_resource: 28
+ type: 1820
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11776
+ num_resource: 28
+ type: 1821
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 12288
+ num_resource: 28
+ type: 1822
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id : 0
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci : 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size : 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock : 0x5A
+ allow_wildcard_unlock : 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev : 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender : 0
+ handover_to_host_id : 0
+ rsvd: [0, 0, 0, 0]
ARM i.MX8MN BSH SMM S2 BOARDS
-M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
M: Michael Trimarchi <michael@amarulasolutions.com>
S: Maintained
F: arch/arm/dts/imx8mn-bsh-smm-s2*
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-
-obj-y := paz00.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/pinmux.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-void pin_mux_mmc(void)
-{
- /* SDMMC4: config 3, x8 on 2nd set of pins */
- pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PMUX_PINGRP_ATB);
- pinmux_tristate_disable(PMUX_PINGRP_GMA);
- pinmux_tristate_disable(PMUX_PINGRP_GME);
-
- /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
- pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
-
- pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
-
- /* For power GPIO PV1 */
- pinmux_tristate_disable(PMUX_PINGRP_UAC);
- /* For CD GPIO PV5 */
- pinmux_tristate_disable(PMUX_PINGRP_GPV);
-}
-#endif
-
-#ifdef CONFIG_VIDEO
-/* this is a weak define that we are overriding */
-void pin_mux_display(void)
-{
- debug("init display pinmux\n");
-
- /* EN_VDD_PANEL GPIO A4 */
- pinmux_tristate_disable(PMUX_PINGRP_DAP2);
-}
-#endif
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
obj-y += coreboot.o
+obj-$(CONFIG_$(SPL_TPL_)SMBIOS_PARSER) += sysinfo.o
return 0;
}
-#ifdef CONFIG_SMBIOS_PARSER
-int show_board_info(void)
-{
- const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size);
-
- if (!smbios)
- goto fallback;
-
- const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
- const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
- const struct smbios_type0 *t0 = (struct smbios_type0 *)bios;
- const struct smbios_type1 *t1 = (struct smbios_type1 *)system;
-
- if (!t0 || !t1)
- goto fallback;
-
- const char *bios_ver = smbios_string(bios, t0->bios_ver);
- const char *bios_date = smbios_string(bios, t0->bios_release_date);
- const char *model = smbios_string(system, t1->product_name);
- const char *manufacturer = smbios_string(system, t1->manufacturer);
-
- if (!model || !manufacturer || !bios_ver)
- goto fallback;
-
- printf("Vendor: %s\n", manufacturer);
- printf("Model: %s\n", model);
- printf("BIOS Version: %s\n", bios_ver);
- if (bios_date)
- printf("BIOS date: %s\n", bios_date);
-
- return 0;
-
-fallback:
- if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-
- if (model)
- printf("Model: %s\n", model);
- }
-
- return checkboard();
-}
-#endif
-
static struct splash_location coreboot_splash_locations[] = {
{
.name = "virtio_fs",
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * coreboot sysinfo driver
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <dm.h>
+#include <smbios.h>
+#include <sysinfo.h>
+#include <asm/cb_sysinfo.h>
+
+struct cb_sysinfo_priv {
+ const struct smbios_header *bios;
+ const struct smbios_header *system;
+ const struct smbios_type0 *t0;
+ const struct smbios_type1 *t1;
+};
+
+static int cb_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+ struct cb_sysinfo_priv *priv = dev_get_priv(dev);
+ const char *str = NULL;
+
+ switch (id) {
+ case SYSINFO_ID_BOARD_MODEL:
+ if (priv->t1)
+ str = smbios_string(priv->system,
+ priv->t1->product_name);
+ break;
+ case SYSINFO_ID_BOARD_MANUFACTURER:
+ if (priv->t1)
+ str = smbios_string(priv->system,
+ priv->t1->manufacturer);
+ break;
+ case SYSINFO_ID_PRIOR_STAGE_VERSION:
+ if (priv->t0)
+ str = smbios_string(priv->bios, priv->t0->bios_ver);
+ break;
+ case SYSINFO_ID_PRIOR_STAGE_DATE:
+ if (priv->t0)
+ str = smbios_string(priv->bios,
+ priv->t0->bios_release_date);
+ break;
+ }
+ if (!str)
+ return -ENOTSUPP;
+
+ strlcpy(val, str, size);
+
+ return 0;
+}
+
+static int cb_detect(struct udevice *dev)
+{
+ struct cb_sysinfo_priv *priv = dev_get_priv(dev);
+ const struct smbios_entry *smbios;
+
+ smbios = smbios_entry(lib_sysinfo.smbios_start,
+ lib_sysinfo.smbios_size);
+ if (!smbios)
+ return 0;
+
+ priv->bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
+ priv->system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
+ priv->t0 = (struct smbios_type0 *)priv->bios;
+ priv->t1 = (struct smbios_type1 *)priv->system;
+
+ return 0;
+}
+
+static const struct udevice_id sysinfo_coreboot_ids[] = {
+ { .compatible = "coreboot,sysinfo" },
+ { /* sentinel */ }
+};
+
+static const struct sysinfo_ops sysinfo_coreboot_ops = {
+ .detect = cb_detect,
+ .get_str = cb_get_str,
+};
+
+U_BOOT_DRIVER(sysinfo_coreboot) = {
+ .name = "sysinfo_coreboot",
+ .id = UCLASS_SYSINFO,
+ .of_match = sysinfo_coreboot_ids,
+ .ops = &sysinfo_coreboot_ops,
+ .priv_auto = sizeof(struct cb_sysinfo_priv),
+};
*/
#include <env.h>
-#include <common.h>
#include <mpc8xx.h>
#include <asm/cpm_8xx.h>
#include <asm/io.h>
*/
#include <config.h>
-#include <common.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/mtd/rawnand.h>
* Charles Frey <charles.frey@c-s.fr>
*/
-#include <common.h>
+#include <config.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include <init.h>
#include <asm/io.h>
#include <mpc8xx.h>
#include <watchdog.h>
+#include <asm/ppc.h>
+#include <asm/immap_8xx.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <command.h>
-#include <common.h>
#include <dm.h>
#include <env.h>
#include <env_internal.h>
* Board specific routines for the MCR3000 board
*/
-#include <common.h>
#include <env.h>
#include <hwconfig.h>
#include <init.h>
*/
#include <config.h>
-#include <common.h>
#include <nand.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <common.h>
#include <dm/uclass.h>
#include <hang.h>
#include <i2c_eeprom.h>
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
+ u8 ecc = 0;
- *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
+ *size = 4ULL >> ((memcfg >> 1) & 0x3);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */
+ ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
+ }
+
+ *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0);
return 0;
}
}
ddr_init(dram_timing_info[memcfg]);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
+ }
}
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
#include <common.h>
#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
+#include <linux/bitfield.h>
#include <malloc.h>
#include <spl.h>
return 0;
}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
+ FIELD_GET(MUX_CTRL_OFS_MASK, IMX8MM_PAD_ENET_MDC_GPIO1_IO16);
+ const char *phy_compat = "ethernet-phy-ieee802.3-c22";
+ bool is_bcmphy;
+ int phy_node;
+ int ret;
+
+ /* Do nothing if not i.MX8MM eDM SBC */
+ ret = fdt_node_check_compatible(fdt_blob, 0, "dmo,imx8mm-data-modul-edm-sbc");
+ if (ret)
+ return 0;
+
+ /*
+ * If GPIO1_16 RGMII_MDC is HIGH, then R530 is populated.
+ * R530 is populated only on boards with AR8031 PHY.
+ *
+ * If GPIO1_16 RGMII_MDC is LOW, then the in-SoM pull down
+ * is the dominant pull resistor. This is the case on boards
+ * with BCM54213PE PHY.
+ */
+ setbits_le32(mux, IOMUX_CONFIG_SION);
+ is_bcmphy = !(readl(GPIO1_BASE_ADDR) & BIT(16));
+ clrbits_le32(mux, IOMUX_CONFIG_SION);
+
+ phy_node = fdt_node_offset_by_compatible(fdt_blob, -1, phy_compat);
+ if (phy_node < 0)
+ return 0;
+
+ /*
+ * Update PHY MDC address in control DT based on the populated
+ * PHY type. AR8031 is at address 0, BCM54213PE is at address 1.
+ */
+ fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
+ "reg", is_bcmphy ? 1 : 0);
+
+ return 0;
+}
#include <common.h>
#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <env.h>
#include <env_internal.h>
+#include <linux/bitfield.h>
#include <malloc.h>
#include <net.h>
#include <spl.h>
return 0;
}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
+ FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_MDC__ENET_QOS_MDC);
+ const char *phy_compat = "ethernet-phy-ieee802.3-c22";
+ bool is_bcmphy;
+ int phy_node;
+ int ret;
+
+ /* Do nothing if not i.MX8MP eDM SBC */
+ ret = fdt_node_check_compatible(fdt_blob, 0, "dmo,imx8mp-data-modul-edm-sbc");
+ if (ret)
+ return 0;
+
+ /*
+ * If GPIO1_16 RGMII_MDC is HIGH, then R390 is populated.
+ * R390 is populated only on boards with AR8031 PHY.
+ *
+ * If GPIO1_16 RGMII_MDC is LOW, then the in-SoM pull down
+ * is the dominant pull resistor. This is the case on boards
+ * with BCM54213PE PHY.
+ */
+ setbits_le32(mux, IOMUX_CONFIG_SION);
+ is_bcmphy = !(readl(GPIO1_BASE_ADDR) & BIT(16));
+ clrbits_le32(mux, IOMUX_CONFIG_SION);
+
+ phy_node = fdt_node_offset_by_compatible(fdt_blob, -1, phy_compat);
+ if (phy_node < 0)
+ return 0;
+
+ /*
+ * Update PHY MDC address in control DT based on the populated
+ * PHY type. AR8031 is at address 0, BCM54213PE is at address 1.
+ */
+ fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
+ "reg", is_bcmphy ? 1 : 0);
+
+ /* Apply the same modification to EQoS PHY */
+ phy_node = fdt_node_offset_by_compatible(fdt_blob, phy_node, phy_compat);
+ if (phy_node < 0)
+ return 0;
+
+ fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
+ "reg", is_bcmphy ? 1 : 0);
+
+ return 0;
+}
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1303 },
- { 0x3d400024, 0x1c79100 },
+ { 0x3d400024, 0x1c7cf80 },
{ 0x3d400064, 0x710106 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
+ { 0x3d4000d0, 0xc0030721 },
{ 0x3d4000d4, 0xb80000 },
- { 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
+ { 0x3d400100, 0x1f262028 },
+ { 0x3d400104, 0x8083b },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x11040a11 },
- { 0x3d400114, 0x2050e0e },
- { 0x3d400118, 0x1010008 },
- { 0x3d40011c, 0x501 },
- { 0x3d400130, 0x20700 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
{ 0x3d400138, 0x10d },
{ 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400180, 0x3a6001d },
+ { 0x3d400184, 0x2f071f4 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x4a3820e },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x230e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x810191a },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9141c1c },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400200, 0x14 },
+#else
{ 0x3d400200, 0x17 },
+#endif
+ { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x14141400 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
{ 0x212149, 0xeba },
{ 0x213049, 0xeba },
{ 0x213149, 0xeba },
- { 0x43, 0xe7 },
- { 0x1043, 0xe7 },
- { 0x2043, 0xe7 },
- { 0x3043, 0xe7 },
- { 0x4043, 0xe7 },
- { 0x5043, 0xe7 },
- { 0x6043, 0xe7 },
- { 0x7043, 0xe7 },
- { 0x8043, 0xe7 },
- { 0x9043, 0xe7 },
+ { 0x43, 0x3ff },
+ { 0x1043, 0x3ff },
+ { 0x2043, 0x3ff },
+ { 0x3043, 0x3ff },
+ { 0x4043, 0x3ff },
+ { 0x5043, 0x3ff },
+ { 0x6043, 0x3ff },
+ { 0x7043, 0x3ff },
+ { 0x8043, 0x3ff },
+ { 0x9043, 0x3ff },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
- { 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
- { 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
+ { 0x2000b, 0x41a },
{ 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000d, 0x91d },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void board_dram_ecc_scrub(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+ /* DRAM Vdd1 always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
+ /* DRAM Vdd2/Vddq always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
+
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
#include <common.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <dm.h>
int board_phys_sdram_size(phys_size_t *size)
{
const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+ const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
u8 memcfg = dh_get_memcfg();
- *size = (u64)memsz[memcfg] << 20ULL;
+ /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
+ *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
return 0;
}
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+typedef void (*scrub_func_t)(void);
+extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
+extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
+
u8 dh_get_memcfg(void);
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
#endif /* __LPDDR4_TIMING_H__ */
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
{ 0x3d400134, 0xd100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0x799 },
- { 0x3d400108, 0x810191a },
+ { 0x3d400108, 0x8121b1a },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x13131300 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x3ffffff);
+ ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
+ ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
+ ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
+}
+#endif
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
- { 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400134, 0xd100002 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x810191a },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x8121b1a },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400200, 0x14 },
+#else
{ 0x3d400200, 0x17 },
+#endif
+ { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x14141400 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+ /* DRAM Vdd1 always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
+ /* DRAM Vdd2/Vddq always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
+
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
}
ddr_init(dram_timing_info[memcfg]);
+
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
+}
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+static const scrub_func_t dram_scrub_fn[8] = {
+ NULL, /* 512 MiB */
+ NULL, /* 1024 MiB */
+ NULL, /* 1536 MiB */
+ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */
+ NULL, /* 3072 MiB */
+ dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */
+ NULL, /* 6144 MiB */
+ NULL, /* 8192 MiB */
+};
+
+void board_dram_ecc_scrub(void)
+{
+ u8 memcfg = dh_get_memcfg();
+
+ if (!dram_scrub_fn[memcfg])
+ return;
+
+ dram_scrub_fn[memcfg]();
}
+#endif
void spl_board_init(void)
{
--- /dev/null
+CONFIG_CMD_QFW=y
+CONFIG_ACPI=y
+CONFIG_GENERATE_ACPI_TABLE=y
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select CMD_QFW
- select QFW_MMIO
+ select QFW if ACPI
+ select QFW_MMIO if CMD_QFW
imply VIRTIO_MMIO
imply VIRTIO_PCI
imply VIRTIO_NET
def_bool y
select GENERIC_RISCV
select SUPPORT_SPL
+ select QFW if ACPI
+ select QFW_MMIO if QFW
imply AHCI
imply SMP
imply BOARD_LATE_INIT
imply SCSI_AHCI
imply AHCI_PCI
imply E1000
- imply NVME
imply PCI
+ imply NVME_PCI
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply SCSI
- imply DM_SCSI
imply SYS_NS16550
imply SIFIVE_SERIAL
imply HTIF_CONSOLE if 64BIT
imply USB_XHCI_PCI
imply USB_KEYBOARD
imply CMD_USB
+ imply UFS
+ imply UFS_PCI
endif
def_bool y
select X86_RESET_VECTOR
select QEMU
- select QFW_PIO
+ select QFW_PIO if CMD_QFW
select BOARD_ROMSIZE_KB_1024
imply VIRTIO_PCI
imply VIRTIO_NET
* Copyright 2014 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
* Copyright 2014 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
+#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/immap_85xx.h>
#include "sleep.h"
vdd_read, 1, 0, do_vdd_read,
"read VDD",
" - Read the voltage specified in mV"
-)
+);
#ifndef __VSC_CROSSBAR_H_
#define __VSC_CROSSBAR_H_
-#include <common.h>
#include <i2c.h>
#include <errno.h>
i.MX8MP EVK BOARD
+M: Fabio Estevm <festevam@gmail.com>
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx8mp_evk/
* Copyright 2019 NXP
*/
-#include <common.h>
#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <linux/delay.h>
-#include <asm/global_data.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm-generic/gpio.h>
-#include <asm/arch/imx8mp_pins.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Enable RGMII TX clk output */
- setbits_le32(&gpr->gpr[1], BIT(22));
-}
-
-#if CONFIG_IS_ENABLED(NET)
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-#endif
int board_init(void)
{
- int ret = 0;
-
- if (IS_ENABLED(CONFIG_FEC_MXC)) {
- setup_fec();
- }
-
- return ret;
+ return 0;
}
int board_late_init(void)
},
};
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC 0
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
int power_init_board(void)
{
- struct pmic *p;
+ struct udevice *dev;
int ret;
- ret = power_pca9450_init(I2C_PMIC, 0x25);
- if (ret)
- printf("power init failed");
- p = pmic_get("PCA9450");
- pmic_probe(p);
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic@25\n");
+ return 0;
+ }
+ if (ret < 0)
+ return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
- pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/*
- * increase VDD_SOC to typical value 0.95V before first
- * DRAM access, set DVS1 to 0.85v for suspend.
+ * Increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85V for suspend.
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
-#ifdef CONFIG_IMX8M_VDD_SOC_850MV
- /* set DVS0 to 0.85v for special case*/
- pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
-#else
- pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
-#endif
- pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
- pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+ if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
- /* Kernel uses OD/OD freq for SOC */
- /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
- pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /*
+ * Kernel uses OD/OD freq for SOC.
+ * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+ * voltage 0.95V.
+ */
+
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
return 0;
}
enable_tzc380();
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
power_init_board();
/* DDR initialization */
return 0;
}
-static int setup_eqos(void)
-{
- struct blk_ctrl_wakeupmix_regs *bctrl =
- (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
-
- /* set INTF as RGMII, enable RGMII TXC clock */
- clrsetbits_le32(&bctrl->eqos_gpr,
- BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
- BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
-
- return set_clk_eqos(ENET_125MHZ);
-}
-
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
- if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
- setup_eqos();
-
return 0;
}
* Copyright 2019, 2021 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <fdt_support.h>
#include <i2c.h>
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2019, 2021 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <fdt_support.h>
#include <init.h>
* Copyright 2019, 2021-2022 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <fdt_support.h>
* Copyright 2021-2022 NXP
*/
-#include <common.h>
#include <i2c.h>
#include <init.h>
#include <asm/global_data.h>
* Copyright 2017 NXP
*/
+#include <config.h>
+#include <vsprintf.h>
+#include <linux/string.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
* Copyright 2015 Freescale Semiconductor, Inc.
*/
+#include <config.h>
+#include <vsprintf.h>
+#include <linux/string.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
struct udevice *dev;
int ret, dev_id, rev_id;
- ret = pmic_get("pfuze3000@8", &dev);
+ ret = pmic_get("pmic@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
#include <asm/arch/clk.h>
#include <asm/arch/pwm.h>
#include <i2c.h>
+#include <linux/time.h>
#include <irq_func.h>
#include <asm/arch/nexell.h>
#include <asm/arch/nx_gpio.h>
-#ifndef NSEC_PER_SEC
-#define NSEC_PER_SEC 1000000000L
-#endif
-
#define SAMPLE_BPS 9600
#define SAMPLE_IN_US 101 /* (1000000 / BPS) */
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x34b },
- { 0x2000c, 0xbb },
- { 0x2000d, 0x753 },
+ { 0x2000b, 0x465 },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x1203 },
- { 0x3d400024, 0x16e3600 },
- { 0x3d400064, 0x5b0087 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a00b4 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x402 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0x8d },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0xbc },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
+ { 0x3d400190, 0x49f820e },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
+ { 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0x699 },
- { 0x3d400108, 0x70e1617 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1001 },
+ { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0012 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0x599 },
- { 0x3d403020, 0x1001 },
+ { 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30005 },
struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
- { 0x100a2, 0x3 },
- { 0x100a3, 0x2 },
- { 0x100a4, 0x5 },
- { 0x100a5, 0x4 },
- { 0x100a6, 0x7 },
- { 0x100a7, 0x6 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
- { 0x110a2, 0x2 },
- { 0x110a3, 0x3 },
- { 0x110a4, 0x4 },
- { 0x110a5, 0x5 },
- { 0x110a6, 0x6 },
- { 0x110a7, 0x7 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
- { 0x120a2, 0x2 },
- { 0x120a3, 0x3 },
- { 0x120a4, 0x4 },
- { 0x120a5, 0x5 },
- { 0x120a6, 0x6 },
- { 0x120a7, 0x7 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
- { 0x130a2, 0x3 },
- { 0x130a3, 0x4 },
- { 0x130a4, 0x5 },
- { 0x130a5, 0x2 },
- { 0x130a6, 0x7 },
- { 0x130a7, 0x6 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
+ { 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1a3 },
+ { 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x120024, 0x1a3 },
+ { 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x220024, 0x1a3 },
+ { 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x2ee },
+ { 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
{
- /* P0 3000mts 1D */
- .drate = 3000,
+ /* P0 4000mts 1D */
+ .drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
},
{
- /* P0 3000mts 2D */
- .drate = 3000,
+ /* P0 4000mts 2D */
+ .drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 4000, 400, 100, },
};
/*
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
- { 0x3d400020, 0x1203 },
- { 0x3d400024, 0x16e3600 },
- { 0x3d400064, 0x5b00d2 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x401 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0xd8 },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
+ { 0x3d400190, 0x49f820e},
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
+ { 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x70e1617 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1001 },
+ { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x1001 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
- { 0x100a2, 0x3 },
- { 0x100a3, 0x2 },
- { 0x100a4, 0x5 },
- { 0x100a5, 0x4 },
- { 0x100a6, 0x7 },
- { 0x100a7, 0x6 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
- { 0x110a2, 0x2 },
- { 0x110a3, 0x3 },
- { 0x110a4, 0x4 },
- { 0x110a5, 0x5 },
- { 0x110a6, 0x6 },
- { 0x110a7, 0x7 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
- { 0x120a2, 0x2 },
- { 0x120a3, 0x3 },
- { 0x120a4, 0x4 },
- { 0x120a5, 0x5 },
- { 0x120a6, 0x6 },
- { 0x120a7, 0x7 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
- { 0x130a2, 0x3 },
- { 0x130a3, 0x4 },
- { 0x130a4, 0x5 },
- { 0x130a5, 0x2 },
- { 0x130a6, 0x7 },
- { 0x130a7, 0x6 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
+ { 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1a3 },
+ { 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x120024, 0x1a3 },
+ { 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
- { 0x220024, 0x1a3 },
+ { 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x2ee },
+ { 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = {
{
- /* P0 3000mts 1D */
- .drate = 3000,
+ /* P0 4000mts 1D */
+ .drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die),
},
{
- /* P0 3000mts 2D */
- .drate = 3000,
+ /* P0 4000mts 2D */
+ .drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die),
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 4000, 400, 100, },
};
if (!strncmp(base_model, "GW73", 4)) {
pcbrev = get_pcb_rev(base_model);
- if (pcbrev > 'B') {
+ if (pcbrev > 'B' && pcbrev < 'E') {
printf("adjusting dt for %s\n", base_model);
/*
- * revC replaced PCIe 5-port switch with 4-port
- * which changed ethernet1 PCIe GbE
+ * revC/D/E has PCIe 4-port switch which changes
+ * ethernet1 PCIe GbE:
* from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
* to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
*/
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
-#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
return 0;
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
- u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
-
- cphy_disable_overrides();
- if (reg & PWRDOM_STAT_SATA) {
- ahci_init((void __iomem *)HB_AHCI_BASE);
- scsi_scan(true);
- }
-}
-#endif
-
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG)
#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG)
+#define TEGRA_GPIO_PS0 144
+
void pmic_enable_cpu_vdd(void)
{
/* Set VDD_CORE to 1.200V. */
tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
udelay(10 * 1000);
}
+
+/*
+ * Unlike all other supported Tegra devices and most known Tegra devices, the
+ * HTC One X has no hardware way to enter APX/RCM mode, which may lead to a
+ * dangerous situation when, if BCT is set correctly and the bootloader is
+ * faulty, the device will hang in a permanent brick state. Exiting from this
+ * state can be done only by disassembling the device and shortening testpad
+ * to the ground.
+ *
+ * To prevent this or to minimize the probability of such an accident, it was
+ * proposed to add the RCM rebooting hook as early into SPL as possible since
+ * SPL is much more robust and has minimal changes that can break bootflow.
+ *
+ * gpio_early_init_uart() function was chosen as it is the earliest function
+ * exposed for setup by the device. Hook performs a check for volume up
+ * button state and triggers RCM if it is pressed.
+ */
+void gpio_early_init_uart(void)
+{
+ struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(TEGRA_GPIO_PS0)];
+ u32 value;
+
+ /* Configure pinmux */
+ pinmux_set_func(PMUX_PINGRP_KB_ROW8_PS0, PMUX_FUNC_KBC);
+ pinmux_set_pullupdown(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PULL_UP);
+ pinmux_tristate_disable(PMUX_PINGRP_KB_ROW8_PS0);
+ pinmux_set_io(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PIN_INPUT);
+
+ /* Configure GPIO direction as input. */
+ value = readl(&bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]);
+ value &= ~(1 << GPIO_BIT(TEGRA_GPIO_PS0));
+ writel(value, &bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]);
+
+ /* Enable the pin as a GPIO */
+ value = readl(&bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]);
+ value |= 1 << GPIO_BIT(TEGRA_GPIO_PS0);
+ writel(value, &bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]);
+
+ /* Get GPIO value */
+ value = readl(&bank->gpio_in[GPIO_PORT(TEGRA_GPIO_PS0)]);
+ value = (value >> GPIO_BIT(TEGRA_GPIO_PS0)) & 1;
+
+ /* Enter RCM if button is pressed */
+ if (!value) {
+ tegra_pmc_writel(2, PMC_SCRATCH0);
+ tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL);
+ }
+}
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
-#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-endeavoru.h"
-
-#define TPS80032_CTL1_I2C_ADDR 0x48
-#define TPS80032_PHOENIX_DEV_ON 0x25
-#define DEVOFF BIT(0)
-#define TPS80032_LDO1_CFG_STATE 0x9E
-#define TPS80032_LDO1_CFG_VOLTAGE 0x9F
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_config_pingrp_table(endeavoru_pinmux_common,
- ARRAY_SIZE(endeavoru_pinmux_common));
-}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void tps80032_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
- if (ret)
- log_debug("cannot find PMIC I2C chip\n");
-
- /* TPS80032: LDO1_REG = 1.2v to DSI */
- ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03);
- if (ret)
- log_debug("avdd_dsi_csi voltage set failed: %d\n", ret);
-
- /* TPS80032: LDO1_REG enable */
- ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01);
- if (ret)
- log_debug("avdd_dsi_csi enable failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up DSI power */
- tps80032_voltage_init();
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Copyright (c) 2022, Svyatoslav Ryhel.
- */
-
-#ifndef _PINMUX_CONFIG_ENDEAVORU_H_
-#define _PINMUX_CONFIG_ENDEAVORU_H_
-
-#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
- }
-
-#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static struct pmux_pingrp_config endeavoru_pinmux_common[] = {
- /* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3_PY4, UARTE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2_PY5, UARTE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD2, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
-
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6_PD3, INVALID, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7_PD4, INVALID, NORMAL, NORMAL, INPUT),
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* I2C pinmux */
- I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* HDMI pinmux */
- DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3_PO4, HSI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4_PO5, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, INPUT),
-
- /* DAP3 pinmux */
- DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
-
- /* PV-gpio group pinmux */
- DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PV2, RSVD2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PV3, RSVD2, NORMAL, NORMAL, OUTPUT),
-
- /* CLK2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD4, NORMAL, NORMAL, OUTPUT),
-
- /* LCD pinmux */
- DEFAULT_PINMUX(LCD_PWR1_PC1, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N_PN4, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2_PE2, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6_PE6, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8_PF0, RSVD4, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14_PF6, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15_PF7, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18_PM2, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19_PM3, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21_PM5, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D22_PM6, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_D23_PM7, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_DC1_PD2, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD4, NORMAL, NORMAL, OUTPUT),
-
- /* VI-group pinmux */
- LV_PINMUX(VI_D0_PT4, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4_PL2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6_PL4, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10_PT2, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11_PT3, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK_PT0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK_PT1, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC_PD6, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC_PD7, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* UART-2 pinmux */
- DEFAULT_PINMUX(UART2_RXD_PC3, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_RTS_N_PJ6, SPI4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_CTS_N_PJ5, SPI4, NORMAL, NORMAL, INPUT),
-
- /* UART-3 pinmux */
- DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
-
- /* PU-gpio group pinmux */
- DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU1, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU2, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU4, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU5, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PU6, PWM3, UP, TRISTATE, INPUT),
-
- /* DAP4 pinmux */
- DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT_PP6, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(DAP4_SCLK_PP7, RSVD4, NORMAL, NORMAL, OUTPUT),
-
- /* CLK3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD4, NORMAL, TRISTATE, INPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CLK_PK1, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS6_N_PI3, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD0_PG0, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD1_PG1, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD2_PG2, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD3_PG3, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD4_PG4, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD5_PG5, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD6_PG6, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD7_PG7, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11_PH3, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD14_PH6, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD15_PH7, NAND, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_DQS_PI2, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_RST_N_PI4, RSVD4, UP, TRISTATE, INPUT),
-
- DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB7, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PCC2, RSVD3, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT),
-
- /* KBC keys */
- DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
-
- /* CLK */
- DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(OWR, OWR, UP, NORMAL, INPUT),
-
- /* DAP1 pinmux */
- DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, OUTPUT),
-
- /* CLK1 pinmux */
- DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_OUT_PW4, RSVD4, NORMAL, NORMAL, INPUT),
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT),
-
- /* DAP2 pinmux */
- DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, DOWN, NORMAL, INPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT),
-
- DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
-
- /* PEX pinmux */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
-};
-
-#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */
erase CONFIG_SYS_MONITOR_BASE +${filesize} &&
cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} &&
protect on CONFIG_SYS_MONITOR_BASE +${filesize}
- update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} &&
+update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} &&
erase CONFIG_SYS_FLASH_BASE +${filesize} &&
cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} &&
protect on CONFIG_SYS_MONITOR_BASE +CONFIG_SYS_MONITOR_LEN
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
-#include <common.h>
+#include <config.h>
#include <event.h>
#include <i2c.h>
#include <asm/io.h>
config SYS_CONFIG_NAME
default "x3-t30"
-config DEVICE_P880
- bool "Enable support for LG Optimus 4X HD"
- help
- LG Optimus 4X HD derives from x3 board but has slight
- differences.
-
-config DEVICE_P895
- bool "Enable support for LG Optimus Vu"
- help
- LG Optimus Vu derives from x3 board but has slight
- differences.
-
endif
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
-CONFIG_DEVICE_P880=y
CONFIG_SYS_PROMPT="Tegra30 (P880) # "
CONFIG_VIDEO_LCD_RENESAS_R69328=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895"
-CONFIG_DEVICE_P895=y
CONFIG_SYS_PROMPT="Tegra30 (P895) # "
CONFIG_VIDEO_LCD_RENESAS_R61307=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Copyright (c) 2021, Svyatoslav Ryhel.
- */
-
-#ifndef _PINMUX_CONFIG_X3_H_
-#define _PINMUX_CONFIG_X3_H_
-
-#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_##_od, \
- .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
- }
-
-#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .lock = PMUX_PIN_LOCK_##_lock, \
- .od = PMUX_PIN_OD_DEFAULT, \
- .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
- }
-
-static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = {
- /* SDMMC1 pinmux */
- DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
-
- /* SDMMC3 pinmux */
-// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific
- LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* I2C4 pinmux */
- I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* Power I2C pinmux */
- I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
- I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
- /* HDMI-CEC pinmux */
- DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N
- DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
-// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured
-// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific
-// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured
- DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN
- DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT),
-
- /* DAP3 pinmux */
- DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT),
-
- /* CLK2 pinmux */
- DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT),
-
- /* LCD pinmux */
- DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured
- DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI
- DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO
- DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS
- DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL
- DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL
- DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK
- DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC
- DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC
- DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N
- DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID
- DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT),
-
- /* VI-group pinmux */
- LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
- LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* UART-B pinmux */
-// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific
-// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific
- DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
-
- /* UART-C pinmux */
- DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
-
- /* PU-gpio group pinmux */
-// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific
-// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific
-// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific
-// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific
- DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT),
-
- /* DAP4 pinmux */
- DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
-
- /* CLK3 pinmux */
- DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK
- DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
-
- DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT),
-
- DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific
- DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
-
- /* KBC keys */
- DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT),
-
- DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
-
- /* CLK */
- DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
-// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
-// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
-// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
-// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured
- DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
-
- /* DAP1 pinmux */
- DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
-
- /* CLK1 pinmux */
- DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT),
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific
-
- /* DAP2 pinmux */
- DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific
-// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific
- DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT),
-
- DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured
-// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured
- DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
-// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured
-
- /* PEX pinmux */
- DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE
- DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT),
-// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific
- DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT),
-// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific
- DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN
- DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT),
-};
-
-#ifdef CONFIG_DEVICE_P880
-static struct pmux_pingrp_config tegra3_p880_pinmux[] = {
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT),
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT),
-
- /* UART-B pinmux */
- DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT),
-
- /* GPIO group pinmux */
- DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT),
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT),
-};
-#endif /* CONFIG_DEVICE_P880 */
-
-#ifdef CONFIG_DEVICE_P895
-static struct pmux_pingrp_config tegra3_p895_pinmux[] = {
- /* SDMMC3 pinmux */
- DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT),
-
- /* SDMMC4 pinmux */
- LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-
- /* ULPI pinmux */
- DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT),
-
- /* UART-B pinmux */
- DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
-
- /* Gpio group pinmux */
- DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0
-
- /* SPDIF pinmux */
- DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT),
-
- /* SPI pinmux */
- DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
-
- /* GMI pinmux */
- DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT),
- DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
-};
-#endif /* CONFIG_DEVICE_P895 */
-#endif /* _PINMUX_CONFIG_X3_H_ */
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
-#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/tegra.h>
#include <asm/arch-tegra/fuse.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-x3.h"
-
-#define MAX77663_I2C_ADDR 0x1C
-
-#define MAX77663_REG_SD2 0x18
-#define MAX77663_REG_LDO2 0x27
-#define MAX77663_REG_LDO3 0x29
-#define MAX77663_REG_LDO5 0x2D
-#define MAX77663_REG_ONOFF_CFG1 0x41
-#define ONOFF_PWR_OFF BIT(1)
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= ONOFF_PWR_OFF;
-
- ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- /* wait some time and then print error */
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_config_pingrp_table(tegra3_x3_pinmux_common,
- ARRAY_SIZE(tegra3_x3_pinmux_common));
-
-#ifdef CONFIG_DEVICE_P880
- pinmux_config_pingrp_table(tegra3_p880_pinmux,
- ARRAY_SIZE(tegra3_p880_pinmux));
-#endif
-
-#ifdef CONFIG_DEVICE_P895
- pinmux_config_pingrp_table(tegra3_p895_pinmux,
- ARRAY_SIZE(tegra3_p895_pinmux));
-#endif
-}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void max77663_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* 0x60 for 1.8v, bit7:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
- if (ret)
- log_debug("vdd_1v8_vio set failed: %d\n", ret);
-
- /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2);
- if (ret)
- log_debug("avdd_usb set failed: %d\n", ret);
-
- /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up uSD and eMMC power */
- max77663_voltage_init();
-}
-#endif /* MMC */
int nvidia_board_init(void)
{
--- /dev/null
+MT8365 EVK
+M: Julien Masson <jmasson@baylibre.com>
+S: Maintained
+F: arch/arm/dts/mt8365-evk.dts
+F: board/mediatek/mt8365_evk/
+F: configs/mt8365_evk_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8365_evk.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 BayLibre SAS
+ * Author: Julien Masson <jmasson@baylibre.com>
+ */
+
+#include <asm/armv8/mmu.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+static struct mm_region mt8365_evk_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0xc0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8365_evk_mem_map;
help
Reserve memory for ECC/GFX/OPTEE/TIP/CP.
+source "board/nuvoton/common/Kconfig"
endif
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
+#include "../common/uart.h"
#define SR_MII_CTRL_SWR_BIT15 15
return 0;
}
+int last_stage_init(void)
+{
+ board_set_console();
+
+ return 0;
+}
--- /dev/null
+if ARCH_NPCM
+
+config SYS_SKIP_UART_INIT
+ bool "Skip UART initialization"
+ depends on NPCM_SERIAL
+ help
+ Select this if the UART you want to use is already
+ initialized by the time U-Boot starts its execution.
+endif
--- /dev/null
+obj-$(CONFIG_SYS_SKIP_UART_INIT) += uart.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Nuvoton Technology Corp.
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <env.h>
+#include <serial.h>
+#include <linux/delay.h>
+
+#define UART_DLL 0x0
+#define UART_DLM 0x4
+#define UART_LCR 0xc
+#define LCR_DLAB BIT(7)
+
+void board_set_console(void)
+{
+ const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
+ struct udevice *dev = gd->cur_serial_dev;
+ unsigned int baudrate, max_delta;
+ void __iomem *uart_reg;
+ struct clk clk;
+ char string[32];
+ u32 uart_clk;
+ u8 dll, dlm;
+ u16 divisor;
+ int ret, i;
+
+ if (!dev)
+ return;
+
+ uart_reg = dev_read_addr_ptr(dev);
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return;
+
+ uart_clk = clk_get_rate(&clk);
+ setbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ dll = readb(uart_reg + UART_DLL);
+ dlm = readb(uart_reg + UART_DLM);
+ clrbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ divisor = dll | (dlm << 8);
+ baudrate = uart_clk / ((16 * (divisor + 2)));
+ for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
+ max_delta = baudrate_table[i] / 20;
+ if (abs(baudrate - baudrate_table[i]) < max_delta) {
+ /* The baudrate is supported */
+ gd->baudrate = baudrate_table[i];
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(baudrate_table)) {
+ /* current baudrate is not suitable, set to default */
+ divisor = DIV_ROUND_CLOSEST(uart_clk, 16 * gd->baudrate) - 2;
+ setbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ writeb(divisor & 0xff, uart_reg + UART_DLL);
+ writeb(divisor >> 8, uart_reg + UART_DLM);
+ clrbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ udelay(100);
+ printf("\r\nUART(source %u): change baudrate from %u to %u\n",
+ uart_clk, baudrate, uart_clk / ((16 * (divisor + 2))));
+ }
+
+ debug("Set env baudrate=%u\n", gd->baudrate);
+ snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate);
+ env_set("console", string);
+
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Nuvoton Technology Corp.
+ */
+
+#ifndef _NUVOTON_UART_H
+#define _NUVOTON_UART_H
+
+void board_set_console(void);
+
+#endif /* _NUVOTON_COMMON_H */
endchoice
+source "board/nuvoton/common/Kconfig"
endif
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include <asm/mach-types.h>
+#include "../common/uart.h"
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+int last_stage_init(void)
+{
+ board_set_console();
+
+ return 0;
+}
extern struct phytec_eeprom_data eeprom_data;
+#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION)
+
/* Check if the SoM is actually one of the following products:
* - i.MX8MM
* - i.MX8MN
*
* Returns 0 in case it's a known SoM. Otherwise, returns -1.
*/
-u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
+int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
{
char *opt;
u8 som;
+ if (!data)
+ data = &eeprom_data;
+
/* We can not do the check for early API revisions */
if (data->api_rev < PHYTEC_API_REV2)
return -1;
- if (!data)
- data = &eeprom_data;
-
som = data->data.data_api2.som_no;
debug("%s: som id: %u\n", __func__, som);
debug("%s: rtc: %u\n", __func__, rtc);
return rtc;
}
+
+#else
+
+inline int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
+{
+ return -1;
+}
+
+inline u8 __maybe_unused
+phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */
#define PHYTEC_IMX8MM_SOM 69
#define PHYTEC_IMX8MP_SOM 70
-#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION)
-
-u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data);
+int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data);
-#else
-
-inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data)
-{
- return -1;
-}
-
-inline u8 __maybe_unused
-phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */
-
#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */
struct phytec_eeprom_data eeprom_data;
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
+
int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
int bus_num, int addr, int addr_fallback)
{
}
ptr = (int *)data;
- for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr))
- if (*ptr != 0x0)
+ for (i = 0; i < sizeof(struct phytec_eeprom_data); i++)
+ if (ptr[i] != 0x0)
break;
if (i == sizeof(struct phytec_eeprom_data)) {
sub_som_type2 = 2;
break;
default:
- break;
+ pr_err("%s: Invalid SoM type: %i", __func__, api2->som_type);
+ return;
};
printf("SoM: %s-%03u-%s-%03u ",
return api2->pcb_rev;
}
+
+#else
+
+inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
+ int bus_num, int addr,
+ int addr_fallback)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data)
+{
+}
+
+inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data)
+{
+ return NULL;
+}
+
+u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
} data;
} __packed;
-#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
-
int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
int bus_num, int addr,
int addr_fallback);
char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
-#else
-
-inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
- int bus_num, int addr)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data,
- int bus_num, int addr,
- int addr_fallback)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
- int bus_num, int addr)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-
-inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data)
-{
-}
-
-inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data)
-{
- return NULL;
-}
-
-u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data)
-{
- return PHYTEC_EEPROM_INVAL;
-}
-#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
-
#endif /* _PHYTEC_SOM_DETECTION_H */
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
S: Maintained
-F: arch/arm/dts/phycore-imx8mm.dts
-F: arch/arm/dts/phycore-imx8mm-u-boot.dtsi
+F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
+F: arch/arm/dts/imx8mm-phycore-som.dtsi
+F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
F: configs/phycore-imx8mm_defconfig
F: include/configs/phycore_imx8mm.h
ROCKPRO64
-M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/pine64/rockpro64_rk3399
--- /dev/null
+if TARGET_IMX8MP_DEBIX_MODEL_A
+
+config SYS_BOARD
+ default "imx8mp_debix_model_a"
+
+config SYS_VENDOR
+ default "polyhex"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_debix_model_a"
+
+config IMX_CONFIG
+ default "board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg"
+
+endif
--- /dev/null
+DEBIX MODEL A BOARD (i.MX8M Plus)
+M: Gilles Talis <gilles.talis@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx8mp-debix-model-a.dts
+F: arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
+F: board/polyhex/imx8mp_debix_model_a/
+F: include/configs/imx8mp_debix_model_a.h
+F: configs/imx8mp_debix_model_a_defconfig
--- /dev/null
+#
+# Copyright 2019 NXP
+# Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mp_debix_model_a.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+#if CONFIG_IS_ENABLED(NET)
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ int ret = 0;
+
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ return ret;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021, 2023 NXP
+ */
+
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
// SPDX-License-Identifier: GPL-2.0+
/*
- * Generated code from MX8M_DDR_tool v3.20 using RPAv20
- * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB
- * - imx8mm-gw7903
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
- * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ * Copyright 2019, 2023 NXP
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
-static struct dram_cfg_param ddr_ddrc_cfg[] = {
+struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
- { 0x3d400020, 0x203 },
- { 0x3d400024, 0x3a980 },
- { 0x3d400064, 0x5b0062 },
- { 0x3d4000d0, 0xc00305ba },
- { 0x3d4000d4, 0x940000 },
- { 0x3d4000dc, 0xd4002d },
- { 0x3d4000e0, 0x310000 },
- { 0x3d4000e8, 0x66004d },
- { 0x3d4000ec, 0x16004d },
- { 0x3d400100, 0x191e1920 },
- { 0x3d400104, 0x60630 },
- { 0x3d40010c, 0xb0b000 },
- { 0x3d400110, 0xe04080e },
- { 0x3d400114, 0x2040c0c },
- { 0x3d400118, 0x1010007 },
- { 0x3d40011c, 0x401 },
- { 0x3d400130, 0x20600 },
- { 0x3d400134, 0xc100002 },
- { 0x3d400138, 0x68 },
- { 0x3d400144, 0x96004b },
- { 0x3d400180, 0x2ee0017 },
- { 0x3d400184, 0x2605b8e },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1c61a00 },
+ { 0x3d400064, 0x710105 },
+ { 0x3d400070, 0x61027f10 },
+ { 0x3d400074, 0x7b0 },
+ { 0x3d4000d0, 0xc003071a },
+ { 0x3d4000d4, 0xb70000 },
+ { 0x3d4000dc, 0xe40036 },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x1e261f28 },
+ { 0x3d400104, 0x7073b },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x11040a11 },
+ { 0x3d400114, 0x2050e0e },
+ { 0x3d400118, 0x1010008 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20700 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x10c },
+ { 0x3d400144, 0xba005d },
+ { 0x3d400180, 0x3a2001c },
+ { 0x3d400184, 0x2f07187 },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x497820a },
+ { 0x3d400190, 0x49b820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x170a },
+ { 0x3d4001b4, 0x1b0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x70e1617 },
+ { 0x3d400108, 0x810191a },
{ 0x3d400200, 0x1f },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
- { 0x3d400218, 0xf0f0707 },
+ { 0x3d400218, 0x7070707 },
{ 0x3d40021c, 0xf0f },
- { 0x3d400250, 0x29001701 },
+ { 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 },
{ 0x3d40026c, 0x2005574 },
{ 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
{ 0x3d400408, 0x72ff },
{ 0x3d400494, 0x2100e07 },
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x1 },
- { 0x3d402024, 0x7d00 },
- { 0x3d402050, 0x20d040 },
- { 0x3d402064, 0xc000d },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x310000 },
- { 0x3d4020e8, 0x66004d },
- { 0x3d4020ec, 0x16004d },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d402104, 0x30407 },
{ 0x3d402108, 0x203060b },
{ 0x3d40211c, 0x301 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
- { 0x3d402138, 0xe },
+ { 0x3d402138, 0x1d },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x1 },
- { 0x3d403024, 0x1f40 },
- { 0x3d403050, 0x20d040 },
- { 0x3d403064, 0x30004 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x310000 },
- { 0x3d4030e8, 0x66004d },
- { 0x3d4030ec, 0x16004d },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x3d403104, 0x30404 },
{ 0x3d403108, 0x203060b },
{ 0x3d40311c, 0x301 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x4 },
+ { 0x3d403138, 0x8 },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
};
/* PHY Initialize Configuration */
-static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
{ 0x100a2, 0x2 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
{ 0x120a2, 0x3 },
- { 0x120a3, 0x4 },
+ { 0x120a3, 0x2 },
{ 0x120a4, 0x5 },
- { 0x120a5, 0x2 },
+ { 0x120a5, 0x4 },
{ 0x120a6, 0x7 },
{ 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
- { 0x20024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x120024, 0x1ab },
- { 0x2003a, 0x0 },
- { 0x220024, 0x1ab },
- { 0x2003a, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
{ 0x220056, 0x3 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x2ee },
+ { 0x20008, 0x3a2 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
- { 0x200b2, 0xdc },
+ { 0x200b2, 0x104 },
{ 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 },
{ 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 },
- { 0x1200b2, 0xdc },
+ { 0x1200b2, 0x104 },
{ 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 },
{ 0x111043, 0x5a1 },
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
- { 0x2200b2, 0xdc },
+ { 0x2200b2, 0x104 },
{ 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 },
{ 0x211043, 0x5a1 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
{ 0x22002d, 0x0 },
- { 0x200c7, 0x21 },
- { 0x1200c7, 0x21 },
- { 0x2200c7, 0x21 },
- { 0x200ca, 0x24 },
- { 0x1200ca, 0x24 },
- { 0x2200ca, 0x24 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
};
/* ddr phy trained csr */
-static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
{ 0x1200b2, 0x0 },
{ 0x2200b2, 0x0 },
};
/* P0 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp0_cfg[] = {
+struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xe88 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
- { 0x54006, 0x11 },
+ { 0x54006, 0x14 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3336 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3336 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp1_cfg[] = {
+struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
- { 0x54006, 0x11 },
+ { 0x54006, 0x14 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
+ { 0x54033, 0x3300 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
+ { 0x54039, 0x3300 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P2 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp2_cfg[] = {
+struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
- { 0x54006, 0x11 },
+ { 0x54006, 0x14 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
+ { 0x54033, 0x3300 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
+ { 0x54039, 0x3300 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xbb8 },
+ { 0x54003, 0xe88 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
- { 0x54006, 0x11 },
+ { 0x54006, 0x14 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
- { 0x5401f, 0x2dd4 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x54032, 0xd400 },
- { 0x54033, 0x312d },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3336 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
{ 0x54037, 0x1600 },
- { 0x54038, 0xd400 },
- { 0x54039, 0x312d },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3336 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
-static struct dram_cfg_param ddr_phy_pie[] = {
+struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
{ 0x90035, 0x2 },
{ 0x90036, 0x10 },
{ 0x90037, 0x139 },
- { 0x90038, 0xf },
+ { 0x90038, 0xb },
{ 0x90039, 0x7c0 },
{ 0x9003a, 0x139 },
{ 0x9003b, 0x44 },
- { 0x9003c, 0x630 },
+ { 0x9003c, 0x633 },
{ 0x9003d, 0x159 },
{ 0x9003e, 0x14f },
{ 0x9003f, 0x630 },
{ 0x90040, 0x159 },
{ 0x90041, 0x47 },
- { 0x90042, 0x630 },
+ { 0x90042, 0x633 },
{ 0x90043, 0x149 },
{ 0x90044, 0x4f },
- { 0x90045, 0x630 },
+ { 0x90045, 0x633 },
{ 0x90046, 0x179 },
{ 0x90047, 0x8 },
{ 0x90048, 0xe0 },
{ 0x90054, 0x448 },
{ 0x90055, 0x109 },
{ 0x90056, 0x40 },
- { 0x90057, 0x630 },
+ { 0x90057, 0x633 },
{ 0x90058, 0x179 },
{ 0x90059, 0x1 },
{ 0x9005a, 0x618 },
{ 0x9005b, 0x109 },
{ 0x9005c, 0x40c0 },
- { 0x9005d, 0x630 },
+ { 0x9005d, 0x633 },
{ 0x9005e, 0x149 },
{ 0x9005f, 0x8 },
{ 0x90060, 0x4 },
{ 0x90061, 0x48 },
{ 0x90062, 0x4040 },
- { 0x90063, 0x630 },
+ { 0x90063, 0x633 },
{ 0x90064, 0x149 },
{ 0x90065, 0x0 },
{ 0x90066, 0x4 },
{ 0x90067, 0x48 },
{ 0x90068, 0x40 },
- { 0x90069, 0x630 },
+ { 0x90069, 0x633 },
{ 0x9006a, 0x149 },
{ 0x9006b, 0x10 },
{ 0x9006c, 0x4 },
{ 0x9006f, 0x4 },
{ 0x90070, 0x78 },
{ 0x90071, 0x549 },
- { 0x90072, 0x630 },
+ { 0x90072, 0x633 },
{ 0x90073, 0x159 },
{ 0x90074, 0xd49 },
- { 0x90075, 0x630 },
+ { 0x90075, 0x633 },
{ 0x90076, 0x159 },
{ 0x90077, 0x94a },
- { 0x90078, 0x630 },
+ { 0x90078, 0x633 },
{ 0x90079, 0x159 },
{ 0x9007a, 0x441 },
- { 0x9007b, 0x630 },
+ { 0x9007b, 0x633 },
{ 0x9007c, 0x149 },
{ 0x9007d, 0x42 },
- { 0x9007e, 0x630 },
+ { 0x9007e, 0x633 },
{ 0x9007f, 0x149 },
{ 0x90080, 0x1 },
- { 0x90081, 0x630 },
+ { 0x90081, 0x633 },
{ 0x90082, 0x149 },
{ 0x90083, 0x0 },
{ 0x90084, 0xe0 },
{ 0x90098, 0x18 },
{ 0x90099, 0x4 },
{ 0x9009a, 0x58 },
- { 0x9009b, 0xa },
+ { 0x9009b, 0xb },
{ 0x9009c, 0x10 },
{ 0x9009d, 0x109 },
- { 0x9009e, 0x2 },
+ { 0x9009e, 0x1 },
{ 0x9009f, 0x10 },
{ 0x900a0, 0x109 },
{ 0x900a1, 0x5 },
{ 0x900a2, 0x7c0 },
{ 0x900a3, 0x109 },
- { 0x900a4, 0x10 },
- { 0x900a5, 0x10 },
- { 0x900a6, 0x109 },
{ 0x40000, 0x811 },
{ 0x40020, 0x880 },
{ 0x40040, 0x0 },
{ 0x4002a, 0xc15 },
{ 0x4004a, 0x0 },
{ 0x4006a, 0x0 },
- { 0x4000b, 0x623 },
+ { 0x4000b, 0x625 },
{ 0x4002b, 0x15 },
{ 0x4004b, 0x0 },
{ 0x4006b, 0x0 },
{ 0x4002d, 0xc1a },
{ 0x4004d, 0x0 },
{ 0x4006d, 0x0 },
- { 0x4000e, 0x623 },
+ { 0x4000e, 0x625 },
{ 0x4002e, 0x1a },
{ 0x4004e, 0x0 },
{ 0x4006e, 0x0 },
{ 0x4003a, 0x880 },
{ 0x4005a, 0x0 },
{ 0x4007a, 0x0 },
- { 0x900a7, 0x0 },
- { 0x900a8, 0x790 },
- { 0x900a9, 0x11a },
- { 0x900aa, 0x8 },
- { 0x900ab, 0x7aa },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
{ 0x900ac, 0x2a },
- { 0x900ad, 0x10 },
- { 0x900ae, 0x7b2 },
- { 0x900af, 0x2a },
- { 0x900b0, 0x0 },
- { 0x900b1, 0x7c8 },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
{ 0x900b2, 0x109 },
{ 0x900b3, 0x10 },
{ 0x900b4, 0x2a8 },
{ 0x90110, 0x0 },
{ 0x90111, 0x8b10 },
{ 0x90112, 0x168 },
- { 0x90113, 0x0 },
+ { 0x90113, 0x1 },
{ 0x90114, 0xab10 },
{ 0x90115, 0x168 },
{ 0x90116, 0x0 },
{ 0x90143, 0xf },
{ 0x90144, 0x408 },
{ 0x90145, 0x169 },
- { 0x90146, 0xc },
+ { 0x90146, 0xd },
{ 0x90147, 0x0 },
{ 0x90148, 0x68 },
{ 0x90149, 0x0 },
{ 0x90155, 0x20 },
{ 0x90156, 0x2aa },
{ 0x90157, 0x9 },
- { 0x90158, 0x0 },
- { 0x90159, 0x400 },
- { 0x9015a, 0x10e },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x10c },
- { 0x90164, 0x8 },
- { 0x90165, 0x7c8 },
- { 0x90166, 0x101 },
- { 0x90167, 0x8 },
- { 0x90168, 0x0 },
- { 0x90169, 0x8 },
- { 0x9016a, 0x8 },
- { 0x9016b, 0x448 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
{ 0x9016c, 0x109 },
- { 0x9016d, 0xf },
- { 0x9016e, 0x7c0 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
{ 0x9016f, 0x109 },
- { 0x90170, 0x0 },
- { 0x90171, 0xe8 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
{ 0x90172, 0x109 },
- { 0x90173, 0x47 },
- { 0x90174, 0x630 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
{ 0x90175, 0x109 },
{ 0x90176, 0x8 },
- { 0x90177, 0x618 },
- { 0x90178, 0x109 },
- { 0x90179, 0x8 },
- { 0x9017a, 0xe0 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
{ 0x9017b, 0x109 },
{ 0x9017c, 0x0 },
- { 0x9017d, 0x7c8 },
- { 0x9017e, 0x109 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
{ 0x9017f, 0x8 },
- { 0x90180, 0x8140 },
- { 0x90181, 0x10c },
- { 0x90182, 0x0 },
- { 0x90183, 0x1 },
- { 0x90184, 0x8 },
- { 0x90185, 0x8 },
- { 0x90186, 0x4 },
- { 0x90187, 0x8 },
- { 0x90188, 0x8 },
- { 0x90189, 0x7c8 },
- { 0x9018a, 0x101 },
- { 0x90006, 0x0 },
- { 0x90007, 0x0 },
- { 0x90008, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
{ 0x90009, 0x0 },
- { 0x9000a, 0x0 },
- { 0x9000b, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
- { 0x9001f, 0x2a },
- { 0x90026, 0x6a },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
{ 0x400d0, 0x0 },
{ 0x400d1, 0x101 },
{ 0x400d2, 0x105 },
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
- { 0x2000b, 0x5d },
- { 0x2000c, 0xbb },
- { 0x2000d, 0x753 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x74 },
+ { 0x2000c, 0xe8 },
+ { 0x2000d, 0x915 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0xc },
{ 0x12000c, 0x19 },
{ 0x9000f, 0x6110 },
{ 0x90010, 0x2152 },
{ 0x90011, 0xdfbd },
- { 0x90012, 0x60 },
+ { 0x90012, 0x2060 },
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
- { 0x120010, 0x5a },
- { 0x120011, 0x3 },
- { 0x220010, 0x5a },
- { 0x220011, 0x3 },
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
{ 0x136b4, 0x1 },
{ 0x137b4, 0x1 },
{ 0x138b4, 0x1 },
- { 0x2003a, 0x2 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
{ 0xc0080, 0x2 },
{ 0xd0000, 0x1 }
};
-static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3000mts 1D */
- .drate = 3000,
+ /* P0 3732mts 1D */
+ .drate = 3732,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3000mts 2D */
- .drate = 3000,
+ /* P0 3732mts 2D */
+ .drate = 3732,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
};
/* ddr timing config params */
-struct dram_timing_info dram_timing_512mb = {
+struct dram_timing_info dram_timing = {
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 3732, 400, 100, },
};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2018-2019, 2021 NXP
+ * Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
+#include <common.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("Failed to get PMIC\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output. */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
+ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+ /* Set DVS0 to 0.85V for special case. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+
+ /* Set DVS1 to 0.85v for suspend. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+ /*
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /*
+ * Kernel uses OD/OD frequency for SoC.
+ * To avoid timing risk from SoC to ARM,
+ * increase VDD_ARM to OD voltage 0.95V
+ */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (is_imx8mp() &&
+ !strcmp(name, "imx8mp-debix-model-a"))
+ return 0;
+
+ return -1;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
- u32 rev;
+ /*
+ * Use the r4 dtb by default as those are the most
+ * widespread devices.
+ */
+ u32 rev, dtb_rev = 4;
char rev_str[3];
+ char fdt_str[50];
env_set("board_name", "librem5");
if (fuse_read(9, 0, &rev)) {
env_set("board_rev", BOARD_REV_ERROR);
} else if (rev == 0) {
+ /*
+ * If the fuses aren't burnt we should use either the
+ * r2 or r3 DTB. The latter makes more sense as there
+ * are far more r3 devices out there.
+ */
+ dtb_rev = 3;
env_set("board_rev", BOARD_REV_UNKNOWN);
} else if (rev > 0) {
+ if (rev == 1)
+ dtb_rev = 2;
+ else if (rev < dtb_rev)
+ dtb_rev = rev;
+ /*
+ * FCC-approved devices report '5' as their board
+ * revision but use the r4 DTB as the PCB's are
+ * functionally identical.
+ */
+ else if (rev == 5)
+ dtb_rev = 4;
sprintf(rev_str, "%u", rev);
env_set("board_rev", rev_str);
}
printf("Board name: %s\n", env_get("board_name"));
printf("Board rev: %s\n", env_get("board_rev"));
+
+ sprintf(fdt_str, "freescale/imx8mq-librem5-r%u.dtb", dtb_rev);
+ env_set("fdtfile", fdt_str);
}
if (is_usb_boot()) {
F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
ROCK-PI-4
-M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-4-rk3399_defconfig
* Copyright (c) 2011 The Chromium OS Authors.
*/
-#include <common.h>
#include <addr_map.h>
+#include <config.h>
#include <cpu_func.h>
#include <cros_ec.h>
#include <dm.h>
-if TARGET_DRACO
-
-config SYS_BOARD
- default "draco"
-
-config SYS_VENDOR
- default "siemens"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "draco"
-
-endif
-
if TARGET_THUBAN
config SYS_BOARD
default "am33xx"
config SYS_CONFIG_NAME
- default "thuban"
+ default "draco-thuban"
endif
default "am33xx"
config SYS_CONFIG_NAME
- default "rastaban"
+ default "draco-rastaban"
endif
default "am33xx"
config SYS_CONFIG_NAME
- default "etamin"
+ default "draco-etamin"
config NAND_CS_INIT
def_bool y
DRACO BOARD
-M: Samuel Egli <samuel.egli@siemens.com>
+M: Enrico Leto <enrico.leto@siemens.com>
S: Maintained
F: board/siemens/draco/
-F: include/configs/draco.h
-F: configs/draco_defconfig
-F: configs/etamin_defconfig
-F: include/configs/thuban.h
-F: configs/thuban_defconfig
-F: include/configs/rastaban.h
-F: configs/rastaban_defconfig
+F: configs/draco-etamin_defconfig
+F: configs/draco-rastaban_defconfig
+F: configs/draco-thuban_defconfig
+F: include/configs/draco-etamin.h
+F: include/configs/draco-rastaban.h
+F: include/configs/draco-thuban.h
# Le Jin <le.jin@siemens.com>
# Jan Kiszka <jan.kiszka@siemens.com>
-config TARGET_IOT2050_A53
- bool "IOT2050 running on A53"
- select ARM64
- select SOC_K3_AM654
- select BOARD_LATE_INIT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
- help
- This builds U-Boot for the IOT2050 devices.
-
if TARGET_IOT2050_A53
config SYS_BOARD
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for HiFive Unmatched boards */
+
+kernel_addr_r=0x80200000
+kernel_comp_addr_r=0x88000000
+kernel_comp_size=0x4000000
+fdt_addr_r=0x8c000000
+scriptaddr=0x8c100000
+pxefile_addr_r=0x8c200000
+ramdisk_addr_r=0x8c300000
+type_guid_gpt_loader1=5B193300-FC78-40CD-8002-E86C45580B47
+type_guid_gpt_loader2=2E54B353-1271-4842-806F-E436D6AF6985
+type_guid_gpt_system=0FC63DAF-8483-4772-8E79-3D69D8477DE4
+partitions=
+ name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};
+ name=loader2,size=4MB,type=${type_guid_gpt_loader2};
+ name=system,size=-,bootable,type=${type_guid_gpt_system};
+fdtfile= CONFIG_DEFAULT_FDT_FILE
return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
}
+/* Override the default implementation, DT model is not accurate */
int checkboard(void)
{
request_detect_gpios();
}
#endif
-/* Override the default implementation, DT model is not accurate */
-int show_board_info(void)
-{
- return checkboard();
-}
-
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
static void board_get_alt_info_mtd(struct mtd_info *mtd, char *buf)
{
struct mtd_info *part;
- bool first = true;
const char *name;
int len, partnum = 0;
"mtd %s=", name);
len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
- "%s raw 0x0 0x%llx ",
+ "%s raw 0x0 0x%llx",
name, mtd->size);
list_for_each_entry(part, &mtd->partitions, node) {
partnum++;
- if (!first)
- len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";");
- first = false;
-
len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
- "%s_%s part %d",
+ ";%s_%s part %d",
name, part->name, partnum);
}
}
/* probe all MTD devices */
mtd_probe_devices();
- /* probe SPI flash device on a bus */
- if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) {
- mtd = get_mtd_device_nm("nor0");
- if (!IS_ERR_OR_NULL(mtd))
+ mtd_for_each_device(mtd)
+ if (!mtd_is_partition(mtd))
board_get_alt_info_mtd(mtd, buf);
-
- mtd = get_mtd_device_nm("nor1");
- if (!IS_ERR_OR_NULL(mtd))
- board_get_alt_info_mtd(mtd, buf);
- }
-
- mtd = get_mtd_device_nm("nand0");
- if (!IS_ERR_OR_NULL(mtd))
- board_get_alt_info_mtd(mtd, buf);
-
- mtd = get_mtd_device_nm("spi-nand0");
- if (!IS_ERR_OR_NULL(mtd))
- board_get_alt_info_mtd(mtd, buf);
}
if (IS_ENABLED(CONFIG_DFU_VIRT)) {
--- /dev/null
+if TARGET_ST_STM32MP25X
+
+config SYS_BOARD
+ default "stm32mp2"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp25_common"
+
+source "board/st/common/Kconfig"
+endif
--- /dev/null
+STM32MP2 BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrick Delaunay <patrick.delaunay@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/dts/stm32mp25*
+F: board/st/stm32mp2/
+F: configs/stm32mp25_defconfig
+F: include/configs/stm32mp25_common.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+#
+# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += stm32mp2.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_BOARD
+
+#include <config.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const void *fdt_compat;
+ int fdt_compat_len;
+ char dtb_name[256];
+ int buf_len;
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+ &fdt_compat_len);
+ if (fdt_compat && fdt_compat_len) {
+ if (strncmp(fdt_compat, "st,", 3) != 0) {
+ env_set("board_name", fdt_compat);
+ } else {
+ env_set("board_name", fdt_compat + 3);
+
+ buf_len = sizeof(dtb_name);
+ strlcpy(dtb_name, fdt_compat + 3, buf_len);
+ buf_len -= strlen(fdt_compat + 3);
+ strlcat(dtb_name, ".dtb", buf_len);
+ env_set("fdtfile", dtb_name);
+ }
+ }
+ }
+
+ return 0;
+}
S: Maintained
F: configs/orangepi_zero2_defconfig
+ORANGEPI ZERO 3 BOARD
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/orangepi_zero3_defconfig
+
ORANGEPI PC 2 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2017 NXP Semiconductors
-obj-y := pico-imx7d.o spl.o
+obj-y := pico-imx7d.o spl.o ../../freescale/common/mmc.o
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+#define PICO_MMC0 0
+#define PICO_MMC0_BLK 2
+#define PICO_MMC1 1
+#define PICO_MMC1_BLK 0
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return set_clk_enet(ENET_125MHZ);
}
-
-int board_phy_config(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe7;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
#endif
static void setup_iomux_uart(void)
set_wdog_reset(wdog);
+#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+ board_late_mmc_env_init();
+#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */
+#endif
+
/*
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
* since we use PMIC_PWRON to reset the board.
}
return 0;
}
+
+#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX)
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int board_mmc_get_env_dev(int devno)
+{
+ int dev_env = 0;
+
+ switch (get_boot_device()) {
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ env_set("bootdev", "MMC3");
+ dev_env = PICO_MMC0;
+ break;
+ case SD1_BOOT:
+ env_set("bootdev", "SD1");
+ dev_env = PICO_MMC1;
+ break;
+ default:
+ printf("Wrong boot device!");
+ }
+
+ return dev_env;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+ int blk_no = 0;
+
+ switch (dev_no) {
+ case PICO_MMC0:
+ blk_no = PICO_MMC0_BLK;
+ break;
+ case PICO_MMC1:
+ blk_no = PICO_MMC1_BLK;
+ break;
+ default:
+ printf("Invalid MMC device!");
+ }
+
+ return blk_no;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int mmc_get_env_dev(void)
+{
+ return board_mmc_get_env_dev(0);
+}
+#endif
+#endif /* CONFIG_FSL_ESDHC_IMX */
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-static iomux_v3_cfg_t const usdhc3_pads[] = {
+#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
+/* EMMC/SD */
+static const iomux_v3_cfg_t usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
+static const iomux_v3_cfg_t usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
- /* Assume uSDHC3 emmc is always present */
- return 1;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(struct bd_info *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ int ret;
+ u32 index;
+
+ /*
+ * Following map is done:
+ * (USDHC) (Physical Port)
+ * usdhc3 SOM MicroSD/MMC
+ * usdhc1 Carrier board MicroSD
+ * Always set boot USDHC as mmc0
+ */
+
+ imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
+ ARRAY_SIZE(usdhc3_emmc_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+ ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+
+ switch (get_boot_device()) {
+ case SD1_BOOT:
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case MMC3_BOOT:
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case SD3_BOOT:
+ default:
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ }
+
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
#endif
# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
#
-choice
- prompt "TI K3 AM62Ax based boards"
- optional
-
-config TARGET_AM62A7_A53_EVM
- bool "TI K3 based AM62A7 EVM running on A53"
- select ARM64
- select BINMAN
- imply BOARD
- imply SPL_BOARD
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM62A7_R5_EVM
- bool "TI K3 based AM62A7 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM62A7_R5_EVM || TARGET_AM62A7_A53_EVM
config SYS_BOARD
#include <env/ti/ti_common.env>
+#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
-default_device_tree=ti/k3-am62a7-sk.dtb
-findfdt=
- setenv name_fdt ${default_device_tree};
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
#include <asm/arch/hardware.h>
#include <asm/io.h>
-#include <common.h>
#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
-# Resource management configuration for AM62ax
+# Resource management configuration for AM62A
#
---
host_cfg_entries:
- #1
host_id: 12
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #2
- host_id: 30
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #3
- host_id: 36
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #4
- host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #5
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #6
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #7
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #8
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #9
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #10
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #11
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #12
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #13
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #14
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #15
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #16
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #17
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #18
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #19
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #20
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #21
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #22
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #23
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #24
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #25
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #26
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #27
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #28
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #29
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #30
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #31
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #32
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
resasg:
subhdr:
magic: 0x7B25
- size : 8
- resasg_entries_size: 1032
- reserved : 0
+ size: 8
+ resasg_entries_size: 1064
+ reserved: 0
resasg_entries:
-
start_resource: 0
type: 64
host_id: 12
reserved: 0
-
-
start_resource: 16
num_resource: 4
type: 64
host_id: 35
reserved: 0
-
-
start_resource: 16
num_resource: 4
type: 64
host_id: 36
reserved: 0
-
-
start_resource: 20
num_resource: 22
type: 64
host_id: 30
reserved: 0
-
-
start_resource: 0
num_resource: 16
type: 192
host_id: 12
reserved: 0
-
-
start_resource: 34
num_resource: 2
type: 192
host_id: 30
reserved: 0
-
-
start_resource: 0
- num_resource: 4
+ num_resource: 2
type: 320
host_id: 12
reserved: 0
-
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 36
+ reserved: 0
-
start_resource: 4
num_resource: 4
type: 320
host_id: 30
reserved: 0
-
-
start_resource: 0
num_resource: 26
type: 384
host_id: 128
reserved: 0
-
-
start_resource: 50176
num_resource: 164
type: 1666
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 1
type: 1667
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1677
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1677
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1677
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1677
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 6
type: 1677
host_id: 128
reserved: 0
-
-
start_resource: 54
num_resource: 18
type: 1678
host_id: 12
reserved: 0
-
-
start_resource: 72
num_resource: 6
type: 1678
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 72
num_resource: 6
type: 1678
host_id: 36
reserved: 0
-
-
start_resource: 78
num_resource: 2
type: 1678
host_id: 30
reserved: 0
-
-
start_resource: 80
num_resource: 2
type: 1678
host_id: 128
reserved: 0
-
-
start_resource: 32
num_resource: 12
type: 1679
host_id: 12
reserved: 0
-
-
start_resource: 44
num_resource: 6
type: 1679
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 44
num_resource: 6
type: 1679
host_id: 36
reserved: 0
-
-
start_resource: 50
num_resource: 2
type: 1679
host_id: 30
reserved: 0
-
-
start_resource: 52
num_resource: 2
type: 1679
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1696
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1696
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1696
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1696
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 6
type: 1696
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1697
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1697
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1697
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1697
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 2
type: 1697
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 12
type: 1698
host_id: 12
reserved: 0
-
-
start_resource: 12
num_resource: 6
type: 1698
- host_id: 35
+ host_id: 20
reserved: 0
-
-
start_resource: 12
num_resource: 6
type: 1698
host_id: 36
reserved: 0
-
-
start_resource: 18
num_resource: 2
type: 1698
host_id: 30
reserved: 0
-
-
start_resource: 20
num_resource: 2
type: 1698
host_id: 128
reserved: 0
-
-
start_resource: 6
- num_resource: 34
+ num_resource: 26
type: 1802
host_id: 12
reserved: 0
-
+ -
+ start_resource: 32
+ num_resource: 8
+ type: 1802
+ host_id: 20
+ reserved: 0
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 35
reserved: 0
-
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 36
reserved: 0
-
-
start_resource: 168
num_resource: 8
type: 1802
host_id: 30
reserved: 0
-
-
start_resource: 14
num_resource: 512
type: 1805
host_id: 12
reserved: 0
-
-
start_resource: 526
num_resource: 256
type: 1805
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reserved: 0
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start_resource: 910
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+ reserved: 0
+ -
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+ num_resource: 498
type: 1805
host_id: 128
reserved: 0
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# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
# Suman Anna <s-anna@ti.com>
-choice
- prompt "TI K3 AM62x based boards"
- optional
-
-config TARGET_AM625_A53_EVM
- bool "TI K3 based AM625 EVM running on A53"
- select ARM64
- select BINMAN
-
-config TARGET_AM625_R5_EVM
- bool "TI K3 based AM625 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
-
-endchoice
-
if TARGET_AM625_A53_EVM
config SYS_BOARD
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
-
-BEAGLEPLAY BOARD
-M: Nishanth Menon <nm@ti.com>
-M: Robert Nelson <robertcnelson@gmail.com>
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-N: beagleplay
+++ /dev/null
-# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
-
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
-CONFIG_OF_LIST="k3-am625-beagleplay"
-CONFIG_SPL_OF_LIST="k3-am625-beagleplay"
-CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
-CONFIG_EXT4_WRITE=y
-CONFIG_LZO=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# Use the Beagleplay env file
-CONFIG_ENV_SOURCE_FILE="beagleplay"
-# Do not use emmc boot - we will use FS only
-CONFIG_SUPPORT_EMMC_BOOT=n
-CONFIG_MMC_IO_VOLTAGE=y
-# CONFIG_SPL_MMC_IO_VOLTAGE is not set
-CONFIG_MMC_UHS_SUPPORT=y
-# CONFIG_SPL_MMC_UHS_SUPPORT is not set
-CONFIG_MMC_HS200_SUPPORT=y
-# CONFIG_SPL_MMC_HS200_SUPPORT is not set
-# Enable GPIO control
-CONFIG_DM_GPIO=y
-CONFIG_SPL_GPIO=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPIO_READ=y
-# Enable LEDs
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_SPL_LED=y
-CONFIG_SPL_LED_GPIO=y
-# Enable I2C bus
-CONFIG_SPL_I2C=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_CMD_I2C=y
-# Regulator
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_DM_REGULATOR_TPS65219=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_TPS65219=y
-CONFIG_CMD_PMIC=y
-# Uses Realtek phy rather than TI phy
-CONFIG_PHY_TI_DP83867=n
-CONFIG_PHY_REALTEK=y
-# No SPI flash on Beagleplay
-CONFIG_SPI=n
-CONFIG_SPI_FLASH=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_SPI_FLASH_SUPPORT=n
+++ /dev/null
-# Defconfig fragment to apply on top of:
-# am62x_evm_r5_defconfig
-#
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
-CONFIG_OF_LIST="k3-am625-r5-beagleplay"
-CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay"
-# Do spl board init
-CONFIG_SPL_BOARD_INIT=y
-# Do not use emmc boot - we will use FS only
-CONFIG_SUPPORT_EMMC_BOOT=n
-# No SPI flash on Beagleplay
-CONFIG_SPI=n
-CONFIG_SPI_FLASH=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_SPI_FLASH_SUPPORT=n
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
-# Resource management configuration for AM62
+# Resource management configuration for AM62X
#
---
host_cfg_entries:
- #1
host_id: 12
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #2
host_id: 30
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #3
host_id: 36
- allowed_atype : 0x2A
- allowed_qos : 0xAAAA
- allowed_orderid : 0xAAAAAAAA
- allowed_priority : 0xAAAA
- allowed_sched_priority : 0xAA
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
- #4
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #5
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #6
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #7
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #8
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #9
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #10
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #11
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #12
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #13
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #14
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #15
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #16
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #17
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #18
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #19
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #20
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #21
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #22
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #23
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #24
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #25
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #26
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #27
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #28
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #29
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #30
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #31
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
- #32
host_id: 0
- allowed_atype : 0
- allowed_qos : 0
- allowed_orderid : 0
- allowed_priority : 0
- allowed_sched_priority : 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
resasg:
subhdr:
magic: 0x7B25
- size : 8
- resasg_entries_size: 960
- reserved : 0
+ size: 8
+ resasg_entries_size: 976
+ reserved: 0
resasg_entries:
-
start_resource: 0
type: 64
host_id: 12
reserved: 0
-
-
start_resource: 16
num_resource: 4
type: 64
host_id: 35
reserved: 0
-
-
start_resource: 16
num_resource: 4
type: 64
host_id: 36
reserved: 0
-
-
start_resource: 20
num_resource: 22
type: 64
host_id: 30
reserved: 0
-
-
start_resource: 0
num_resource: 16
type: 192
host_id: 12
reserved: 0
-
-
start_resource: 34
num_resource: 2
type: 192
host_id: 30
reserved: 0
-
-
start_resource: 0
- num_resource: 4
+ num_resource: 2
type: 320
host_id: 12
reserved: 0
-
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 36
+ reserved: 0
-
start_resource: 4
num_resource: 4
type: 320
host_id: 30
reserved: 0
-
-
start_resource: 0
num_resource: 26
type: 384
host_id: 128
reserved: 0
-
-
start_resource: 50176
num_resource: 164
type: 1666
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 1
type: 1667
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1677
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1677
host_id: 35
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1677
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1677
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 6
type: 1677
host_id: 128
reserved: 0
-
-
start_resource: 54
num_resource: 18
type: 1678
host_id: 12
reserved: 0
-
-
start_resource: 72
num_resource: 6
type: 1678
host_id: 35
reserved: 0
-
-
start_resource: 72
num_resource: 6
type: 1678
host_id: 36
reserved: 0
-
-
start_resource: 78
num_resource: 2
type: 1678
host_id: 30
reserved: 0
-
-
start_resource: 80
num_resource: 2
type: 1678
host_id: 128
reserved: 0
-
-
start_resource: 32
num_resource: 12
type: 1679
host_id: 12
reserved: 0
-
-
start_resource: 44
num_resource: 6
type: 1679
host_id: 35
reserved: 0
-
-
start_resource: 44
num_resource: 6
type: 1679
host_id: 36
reserved: 0
-
-
start_resource: 50
num_resource: 2
type: 1679
host_id: 30
reserved: 0
-
-
start_resource: 52
num_resource: 2
type: 1679
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1696
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1696
host_id: 35
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1696
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1696
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 6
type: 1696
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 18
type: 1697
host_id: 12
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1697
host_id: 35
reserved: 0
-
-
start_resource: 18
num_resource: 6
type: 1697
host_id: 36
reserved: 0
-
-
start_resource: 24
num_resource: 2
type: 1697
host_id: 30
reserved: 0
-
-
start_resource: 26
num_resource: 2
type: 1697
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 12
type: 1698
host_id: 12
reserved: 0
-
-
start_resource: 12
num_resource: 6
type: 1698
host_id: 35
reserved: 0
-
-
start_resource: 12
num_resource: 6
type: 1698
host_id: 36
reserved: 0
-
-
start_resource: 18
num_resource: 2
type: 1698
host_id: 30
reserved: 0
-
-
start_resource: 20
num_resource: 2
type: 1698
host_id: 128
reserved: 0
-
-
start_resource: 5
num_resource: 35
type: 1802
host_id: 12
reserved: 0
-
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 35
reserved: 0
-
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 36
reserved: 0
-
-
start_resource: 168
num_resource: 8
type: 1802
host_id: 30
reserved: 0
-
-
start_resource: 13
num_resource: 512
type: 1805
host_id: 12
reserved: 0
-
-
start_resource: 525
num_resource: 256
type: 1805
host_id: 35
reserved: 0
-
-
start_resource: 525
num_resource: 256
type: 1805
host_id: 36
reserved: 0
-
-
start_resource: 781
num_resource: 128
type: 1805
host_id: 30
reserved: 0
-
-
start_resource: 909
num_resource: 627
type: 1805
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 1024
type: 1807
host_id: 128
reserved: 0
-
-
start_resource: 4096
num_resource: 29
type: 1808
host_id: 128
reserved: 0
-
-
start_resource: 4608
num_resource: 99
type: 1809
host_id: 128
reserved: 0
-
-
start_resource: 5120
num_resource: 24
type: 1810
host_id: 128
reserved: 0
-
-
start_resource: 5632
num_resource: 51
type: 1811
host_id: 128
reserved: 0
-
-
start_resource: 6144
num_resource: 51
type: 1812
host_id: 128
reserved: 0
-
-
start_resource: 6656
num_resource: 51
type: 1813
host_id: 128
reserved: 0
-
-
start_resource: 8192
num_resource: 32
type: 1814
host_id: 128
reserved: 0
-
-
start_resource: 8704
num_resource: 32
type: 1815
host_id: 128
reserved: 0
-
-
start_resource: 9216
num_resource: 32
type: 1816
host_id: 128
reserved: 0
-
-
start_resource: 9728
num_resource: 22
type: 1817
host_id: 128
reserved: 0
-
-
start_resource: 10240
num_resource: 22
type: 1818
host_id: 128
reserved: 0
-
-
start_resource: 10752
num_resource: 22
type: 1819
host_id: 128
reserved: 0
-
-
start_resource: 11264
num_resource: 28
type: 1820
host_id: 128
reserved: 0
-
-
start_resource: 11776
num_resource: 28
type: 1821
host_id: 128
reserved: 0
-
-
start_resource: 12288
num_resource: 28
type: 1822
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 1
type: 1923
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 10
type: 1936
host_id: 12
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1936
host_id: 35
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1936
host_id: 36
reserved: 0
-
-
start_resource: 13
num_resource: 3
type: 1936
host_id: 30
reserved: 0
-
-
start_resource: 16
num_resource: 3
type: 1936
host_id: 128
reserved: 0
-
-
start_resource: 19
num_resource: 64
type: 1937
host_id: 12
reserved: 0
-
-
start_resource: 19
num_resource: 64
type: 1937
host_id: 36
reserved: 0
-
-
start_resource: 83
num_resource: 8
type: 1938
host_id: 12
reserved: 0
-
-
start_resource: 91
num_resource: 8
type: 1939
host_id: 12
reserved: 0
-
-
start_resource: 99
num_resource: 10
type: 1942
host_id: 12
reserved: 0
-
-
start_resource: 109
num_resource: 3
type: 1942
host_id: 35
reserved: 0
-
-
start_resource: 109
num_resource: 3
type: 1942
host_id: 36
reserved: 0
-
-
start_resource: 112
num_resource: 3
type: 1942
host_id: 30
reserved: 0
-
-
start_resource: 115
num_resource: 3
type: 1942
host_id: 128
reserved: 0
-
-
start_resource: 118
num_resource: 16
type: 1943
host_id: 12
reserved: 0
-
-
start_resource: 118
num_resource: 16
type: 1943
host_id: 36
reserved: 0
-
-
start_resource: 134
num_resource: 8
type: 1944
host_id: 12
reserved: 0
-
-
start_resource: 134
num_resource: 8
type: 1945
host_id: 12
reserved: 0
-
-
start_resource: 142
num_resource: 8
type: 1946
host_id: 12
reserved: 0
-
-
start_resource: 142
num_resource: 8
type: 1947
host_id: 12
reserved: 0
-
-
start_resource: 0
num_resource: 10
type: 1955
host_id: 12
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1955
host_id: 35
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1955
host_id: 36
reserved: 0
-
-
start_resource: 13
num_resource: 3
type: 1955
host_id: 30
reserved: 0
-
-
start_resource: 16
num_resource: 3
type: 1955
host_id: 128
reserved: 0
-
-
start_resource: 19
num_resource: 8
type: 1956
host_id: 12
reserved: 0
-
-
start_resource: 19
num_resource: 8
type: 1956
host_id: 36
reserved: 0
-
-
start_resource: 27
num_resource: 1
type: 1957
host_id: 12
reserved: 0
-
-
start_resource: 28
num_resource: 1
type: 1958
host_id: 12
reserved: 0
-
-
start_resource: 0
num_resource: 10
type: 1961
host_id: 12
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1961
host_id: 35
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1961
host_id: 36
reserved: 0
-
-
start_resource: 13
num_resource: 3
type: 1961
host_id: 30
reserved: 0
-
-
start_resource: 16
num_resource: 3
type: 1961
host_id: 128
reserved: 0
-
-
start_resource: 0
num_resource: 10
type: 1962
host_id: 12
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1962
host_id: 35
reserved: 0
-
-
start_resource: 10
num_resource: 3
type: 1962
host_id: 36
reserved: 0
-
-
start_resource: 13
num_resource: 3
type: 1962
host_id: 30
reserved: 0
-
-
start_resource: 16
num_resource: 3
type: 1962
host_id: 128
reserved: 0
-
-
start_resource: 19
num_resource: 1
type: 1963
host_id: 12
reserved: 0
-
-
start_resource: 19
num_resource: 1
type: 1963
host_id: 36
reserved: 0
-
-
start_resource: 19
num_resource: 16
type: 1964
host_id: 12
reserved: 0
-
-
start_resource: 19
num_resource: 16
type: 1964
host_id: 36
reserved: 0
-
-
start_resource: 20
num_resource: 1
type: 1965
host_id: 12
reserved: 0
-
-
start_resource: 35
num_resource: 8
type: 1966
host_id: 12
reserved: 0
-
-
start_resource: 21
num_resource: 1
type: 1967
host_id: 12
reserved: 0
-
-
start_resource: 35
num_resource: 8
type: 1968
host_id: 12
reserved: 0
-
-
start_resource: 22
num_resource: 1
type: 1969
host_id: 12
reserved: 0
-
-
start_resource: 43
num_resource: 8
type: 1970
host_id: 12
reserved: 0
-
-
start_resource: 23
num_resource: 1
type: 1971
host_id: 12
reserved: 0
-
-
start_resource: 43
num_resource: 8
type: 1972
host_id: 12
reserved: 0
-
-
start_resource: 0
num_resource: 1
type: 2112
host_id: 128
reserved: 0
-
-
start_resource: 2
num_resource: 2
#
# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
-choice
- prompt "K3 AM64 based boards"
- optional
-
-config TARGET_AM642_A53_EVM
- bool "TI K3 based AM642 EVM running on A53"
- select ARM64
- select BINMAN
- imply BOARD
- imply SPL_BOARD
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM642_R5_EVM
- bool "TI K3 based AM642 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM642_A53_EVM
config SYS_BOARD
*
*/
-#include <common.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-choice
- prompt "K3 AM65 based boards"
- optional
-
-config TARGET_AM654_A53_EVM
- bool "TI K3 based AM654 EVM running on A53"
- select ARM64
- select SYS_DISABLE_DCACHE_OPS
- select BOARD_LATE_INIT
- select BINMAN
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM654_R5_EVM
- bool "TI K3 based AM654 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select K3_AM654_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM654_A53_EVM
config SYS_BOARD
*
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <image.h>
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-choice
- prompt "K3 J721E based boards"
- optional
-
-config TARGET_J721E_A72_EVM
- bool "TI K3 based J721E EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J721E_R5_EVM
- bool "TI K3 based J721E EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_J7200_A72_EVM
- bool "TI K3 based J7200 EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J7200_R5_EVM
- bool "TI K3 based J7200 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_J721E_A72_EVM
config SYS_BOARD
*
*/
-#include <common.h>
-#include <env.h>
-#include <fdt_support.h>
#include <generic-phy.h>
#include <image.h>
-#include <init.h>
-#include <log.h>
#include <net.h>
#include <asm/arch/hardware.h>
-#include <asm/global_data.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <spl.h>
#include <dm.h>
-#include <dm/uclass-internal.h>
-#include <linux/printk.h>
#include "../common/board_detect.h"
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
printf("Detected: %s rev %s\n", ep.name, ep.version);
daughter_card_detect_flags[i] = true;
-#ifndef CONFIG_SPL_BUILD
- int j;
- /*
- * Populate any MAC addresses from daughtercard into the U-Boot
- * environment, starting with a card-specific offset so we can
- * have multiple ext_cards contribute to the MAC pool in a well-
- * defined manner.
- */
- for (j = 0; j < mac_addr_cnt; j++) {
- if (!is_valid_ethaddr((u8 *)mac_addr[j]))
- continue;
-
- eth_env_set_enetaddr_by_index("eth",
- ext_cards[i].eth_offset + j,
- (uchar *)mac_addr[j]);
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ int j;
+ /*
+ * Populate any MAC addresses from daughtercard into the U-Boot
+ * environment, starting with a card-specific offset so we can
+ * have multiple ext_cards contribute to the MAC pool in a well-
+ * defined manner.
+ */
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
+
+ eth_env_set_enetaddr_by_index("eth",
+ ext_cards[i].eth_offset + j,
+ (uchar *)mac_addr[j]);
+ }
}
-#endif
}
-#ifndef CONFIG_SPL_BUILD
- char name_overlays[1024] = { 0 };
- for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
- if (!daughter_card_detect_flags[i])
- continue;
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ char name_overlays[1024] = { 0 };
- /* Skip if no overlays are to be added */
- if (!strlen(ext_cards[i].dtbo_name))
- continue;
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (!daughter_card_detect_flags[i])
+ continue;
- /*
- * Make sure we are not running out of buffer space by checking
- * if we can fit the new overlay, a trailing space to be used
- * as a separator, plus the terminating zero.
- */
- if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
- sizeof(name_overlays))
- return -ENOMEM;
-
- /* Append to our list of overlays */
- strcat(name_overlays, ext_cards[i].dtbo_name);
- strcat(name_overlays, " ");
- }
+ /* Skip if no overlays are to be added */
+ if (!strlen(ext_cards[i].dtbo_name))
+ continue;
- /* Apply device tree overlay(s) to the U-Boot environment, if any */
- if (strlen(name_overlays))
- return env_set("name_overlays", name_overlays);
-#endif
+ /*
+ * Make sure we are not running out of buffer space by checking
+ * if we can fit the new overlay, a trailing space to be used
+ * as a separator, plus the terminating zero.
+ */
+ if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+ sizeof(name_overlays))
+ return -ENOMEM;
+
+ /* Append to our list of overlays */
+ strcat(name_overlays, ext_cards[i].dtbo_name);
+ strcat(name_overlays, " ");
+ }
+
+ /* Apply device tree overlay(s) to the U-Boot environment, if any */
+ if (strlen(name_overlays))
+ return env_set("name_overlays", name_overlays);
+ }
return 0;
}
void spl_board_init(void)
{
-#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
struct udevice *dev;
int ret;
-#endif
if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
probe_daughtercards();
}
-#ifdef CONFIG_ESM_K3
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(k3_esm), &dev);
if (ret)
printf("ESM init failed: %d\n", ret);
}
-#endif
-#ifdef CONFIG_ESM_PMIC
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (IS_ENABLED(CONFIG_ESM_PMIC)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
&dev);
if (ret)
printf("ESM PMIC init failed: %d\n", ret);
}
-#endif
if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
IS_ENABLED(CONFIG_HBMC_AM654)) {
struct udevice *dev;
name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
#endif
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
# David Huang <d-huang@ti.com>
-choice
- prompt "K3 J721S2 board"
- optional
-
-config TARGET_J721S2_A72_EVM
- bool "TI K3 based J721S2 EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J721S2_R5_EVM
- bool "TI K3 based J721S2 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_J721S2_A72_EVM
config SYS_BOARD
*
*/
-#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <hang.h>
#include <asm/io.h>
#include <asm/arch/mux-k2g.h>
build_info();
print_bootinfo();
- return 0;
+ return tdx_checkboard();
}
static enum pcb_rev_t get_pcb_revision(void)
{
puts("Model: Toradex Apalis TK1 2GB\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
env_set("board_rev", env_str);
#endif /* CONFIG_BOARD_LATE_INIT */
-#ifdef CONFIG_CMD_USB_SDP
- if (is_boot_from_usb()) {
- printf("Serial Downloader recovery mode, using sdp command\n");
+ if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
env_set("bootdelay", "0");
- env_set("bootcmd", "sdp 0");
+ if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
+ printf("Serial Downloader recovery mode, using sdp command\n");
+ env_set("bootcmd", "sdp 0");
+ } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
+ printf("Fastboot recovery mode, using fastboot command\n");
+ env_set("bootcmd", "fastboot usb 0");
+ }
}
-#endif /* CONFIG_CMD_USB_SDP */
return 0;
}
is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
(gd->ram_size == 0x80000000) ? "2GB" :
(gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
- return 0;
+
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
printf("Model: Toradex Apalis T30 %dGB\n",
(gd->ram_size == 0x40000000) ? 1 : 2);
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
add_board_boot_modes(board_boot_modes);
#endif
-#ifdef CONFIG_CMD_USB_SDP
- if (is_boot_from_usb()) {
- printf("Serial Downloader recovery mode, using sdp command\n");
+ if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
env_set("bootdelay", "0");
- env_set("bootcmd", "sdp 0");
+ if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
+ printf("Serial Downloader recovery mode, using sdp command\n");
+ env_set("bootcmd", "sdp 0");
+ } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
+ printf("Fastboot recovery mode, using fastboot command\n");
+ env_set("bootcmd", "fastboot usb 0");
+ }
}
-#endif /* CONFIG_CMD_USB_SDP */
#if defined(CONFIG_VIDEO)
setup_lcd();
{
printf("Model: Toradex Colibri iMX6ULL\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
build_info();
print_bootinfo();
- return 0;
+ return tdx_checkboard();
}
static void select_dt_from_module_version(void)
env_set("board_rev", env_str);
#endif
-#ifdef CONFIG_CMD_USB_SDP
- if (is_boot_from_usb()) {
- printf("Serial Downloader recovery mode, using sdp command\n");
+ if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
env_set("bootdelay", "0");
- env_set("bootcmd", "sdp 0");
+ if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
+ printf("Serial Downloader recovery mode, using sdp command\n");
+ env_set("bootcmd", "sdp 0");
+ } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
+ printf("Fastboot recovery mode, using fastboot command\n");
+ env_set("bootcmd", "fastboot usb 0");
+ }
}
-#endif /* CONFIG_CMD_USB_SDP */
return 0;
}
printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
(gd->ram_size == 0x20000000) ? "512" : "256", it);
- return 0;
+
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
}
static iomux_v3_cfg_t const flash_detection_pads[] = {
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL),
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION,
};
static iomux_v3_cfg_t const uart1_pads[] = {
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/*
- * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
+ * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
* is pulled high with 4.7k for eMMC devices. This allows to reliably
- * detect eMMC/NAND flash
+ * detect eMMC vs NAND flash.
*/
imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads));
gpio_request(FLASH_DET_GPIO, "flash-detection-gpio");
printf("Model: Toradex Colibri iMX7%c\n",
is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
setup_lcd();
#endif
-#if defined(CONFIG_CMD_USB_SDP)
- if (is_boot_from_usb()) {
- printf("Serial Downloader recovery mode, using sdp command\n");
+ if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
env_set("bootdelay", "0");
- env_set("bootcmd", "sdp 0");
+ if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
+ printf("Serial Downloader recovery mode, using sdp command\n");
+ env_set("bootcmd", "sdp 0");
+ } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
+ printf("Fastboot recovery mode, using fastboot command\n");
+ env_set("bootcmd", "fastboot usb 0");
+ }
}
-#endif
+
if (is_emmc)
env_set("variant", "-emmc");
else
(get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
{
puts("Model: Toradex Colibri T30 1GB\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
else
puts("Model: Toradex Colibri VF50\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
return ver_name;
}
-int show_board_info(void)
+int tdx_checkboard(void)
{
unsigned char ethaddr[6];
int ft_common_board_setup(void *blob, struct bd_info *bd);
u32 get_board_revision(void);
+int tdx_checkboard(void);
#endif /* _TDX_COMMON_H */
# Copyright 2023 Toradex
#
-choice
- prompt "Toradex Verdin AM62 based boards"
- optional
-
-config TARGET_VERDIN_AM62_A53
- bool "Toradex Verdin AM62 running on A53"
- select ARM64
- select BINMAN
-
-config TARGET_VERDIN_AM62_R5
- bool "Toradex Verdin AM62 running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
-
-endchoice
-
if TARGET_VERDIN_AM62_A53
config SYS_BOARD
*
*/
+#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <dm/uclass.h>
#ifndef __TQMA6_BB__
#define __TQMA6_BB__
-#include <common.h>
-
int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
int tqma6_bb_board_mmc_init(struct bd_info *bis);
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00003030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
}
/* Override the default implementation, DT model is not accurate */
-int show_board_info(void)
+int checkboard(void)
{
int *board_type = (int *)OCRAM_START;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Variscite Ltd.
+ */
+#include <net.h>
+#include <miiphy.h>
+#include <env.h>
+#include "../common/imx9_eeprom.h"
+
+#define CHAR_BIT 8
+
+static u64 mac2int(const u8 hwaddr[])
+{
+ u8 i;
+ u64 ret = 0;
+ const u8 *p = hwaddr;
+
+ for (i = 6; i > 0; i--)
+ ret |= (u64)*p++ << (CHAR_BIT * (i - 1));
+
+ return ret;
+}
+
+static void int2mac(const u64 mac, u8 *hwaddr)
+{
+ u8 i;
+ u8 *p = hwaddr;
+
+ for (i = 6; i > 0; i--)
+ *p++ = mac >> (CHAR_BIT * (i - 1));
+}
+
+int var_setup_mac(struct var_eeprom *eeprom)
+{
+ int ret;
+ unsigned char enetaddr[6];
+ u64 addr;
+ unsigned char enet1addr[6];
+
+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = var_eeprom_get_mac(eeprom, enetaddr);
+ if (ret)
+ return ret;
+
+ if (!is_valid_ethaddr(enetaddr))
+ return -EINVAL;
+
+ eth_env_set_enetaddr("ethaddr", enetaddr);
+
+ addr = mac2int(enetaddr);
+ int2mac(addr + 1, enet1addr);
+ eth_env_set_enetaddr("eth1addr", enet1addr);
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Variscite Ltd.
+ *
+ */
+
+#ifndef _MX9_ETH_H_
+#define _MX9_ETH_H_
+
+int var_setup_mac(struct var_eeprom *eeprom);
+
+#endif /* _MX9_ETH_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Variscite Ltd.
+ *
+ */
+#include <command.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <u-boot/crc.h>
+#include <asm/arch-imx9/ddr.h>
+
+#include "imx9_eeprom.h"
+
+static int var_eeprom_get_dev(struct udevice **devp)
+{
+ int ret;
+ struct udevice *bus;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, VAR_SOM_EEPROM_I2C_NAME, &bus);
+ if (ret) {
+ printf("%s: No EEPROM I2C bus '%s'\n", __func__,
+ VAR_SOM_EEPROM_I2C_NAME);
+ return ret;
+ }
+
+ ret = dm_i2c_probe(bus, VAR_SOM_EEPROM_I2C_ADDR, 0, devp);
+ if (ret) {
+ printf("%s: I2C EEPROM probe failed\n", __func__);
+ return ret;
+ }
+
+ i2c_set_chip_offset_len(*devp, 1);
+ i2c_set_chip_addr_offset_mask(*devp, 1);
+
+ return 0;
+}
+
+int var_eeprom_read_header(struct var_eeprom *e)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = var_eeprom_get_dev(&dev);
+ if (ret) {
+ printf("%s: Failed to detect I2C EEPROM\n", __func__);
+ return ret;
+ }
+
+ /* Read EEPROM header to memory */
+ ret = dm_i2c_read(dev, 0, (void *)e, sizeof(*e));
+ if (ret) {
+ printf("%s: EEPROM read failed, ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int var_eeprom_get_mac(struct var_eeprom *ep, u8 *mac)
+{
+ flush_dcache_all();
+ if (!var_eeprom_is_valid(ep))
+ return -1;
+
+ memcpy(mac, ep->mac, sizeof(ep->mac));
+
+ return 0;
+}
+
+int var_eeprom_get_dram_size(struct var_eeprom *ep, phys_size_t *size)
+{
+ /* No data in EEPROM - return default DRAM size */
+ if (!var_eeprom_is_valid(ep)) {
+ *size = DEFAULT_SDRAM_SIZE;
+ return 0;
+ }
+
+ *size = (ep->dramsize * 128UL) << 20;
+ return 0;
+}
+
+void var_eeprom_print_prod_info(struct var_eeprom *ep)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return;
+
+ flush_dcache_all();
+
+ if (!var_eeprom_is_valid(ep))
+ return;
+
+ if (IS_ENABLED(CONFIG_TARGET_IMX93_VAR_SOM))
+ printf("\nPart number: VSM-MX93-%.*s\n",
+ (int)sizeof(ep->partnum), ep->partnum);
+
+ printf("Assembly: AS%.*s\n", (int)sizeof(ep->assembly), (char *)ep->assembly);
+
+ printf("Production date: %.*s %.*s %.*s\n",
+ 4, /* YYYY */
+ (char *)ep->date,
+ 3, /* MMM */
+ ((char *)ep->date) + 4,
+ 2, /* DD */
+ ((char *)ep->date) + 4 + 3);
+
+ printf("Serial Number: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ep->mac[0], ep->mac[1], ep->mac[2], ep->mac[3], ep->mac[4], ep->mac[5]);
+
+ debug("EEPROM version: 0x%x\n", ep->version);
+ debug("SOM features: 0x%x\n", ep->features);
+ printf("SOM revision: 0x%x\n", ep->somrev);
+ printf("DRAM PN: VIC-%04d\n", ep->ddr_vic);
+ debug("DRAM size: %d GiB\n\n", (ep->dramsize * 128) / 1024);
+}
+
+int var_carrier_eeprom_read(const char *bus_name, int addr, struct var_carrier_eeprom *ep)
+{
+ int ret;
+ struct udevice *bus;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, bus_name, &bus);
+ if (ret) {
+ printf("%s: No bus '%s'\n", __func__, bus_name);
+ return ret;
+ }
+
+ ret = dm_i2c_probe(bus, addr, 0, &dev);
+ if (ret) {
+ printf("%s: Carrier EEPROM I2C probe failed\n", __func__);
+ return ret;
+ }
+
+ /* Read EEPROM to memory */
+ ret = dm_i2c_read(dev, 0, (void *)ep, sizeof(*ep));
+ if (ret) {
+ printf("%s: Carrier EEPROM read failed, ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int var_carrier_eeprom_is_valid(struct var_carrier_eeprom *ep)
+{
+ u32 crc, crc_offset = offsetof(struct var_carrier_eeprom, crc);
+
+ if (htons(ep->magic) != VAR_CARRIER_EEPROM_MAGIC) {
+ printf("Invalid carrier EEPROM magic 0x%x, expected 0x%x\n",
+ htons(ep->magic), VAR_CARRIER_EEPROM_MAGIC);
+ return 0;
+ }
+
+ if (ep->struct_ver < 1) {
+ printf("Invalid carrier EEPROM version 0x%x\n", ep->struct_ver);
+ return 0;
+ }
+
+ if (ep->struct_ver == 1)
+ return 1;
+
+ /* Only EEPROM structure above version 1 has CRC field */
+ crc = crc32(0, (void *)ep, crc_offset);
+
+ if (crc != ep->crc) {
+ printf("Carrier EEPROM CRC mismatch (%08x != %08x)\n",
+ crc, be32_to_cpu(ep->crc));
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Returns carrier board revision string via 'rev' argument. For legacy
+ * carrier board revisions the "legacy" string is returned. For new carrier
+ * board revisions the actual carrier revision is returned. Symphony-Board
+ * 1.4 and below are legacy, 1.4a and above are new. DT8MCustomBoard 1.4 and
+ * below are legacy, 2.0 and above are new.
+ *
+ */
+void var_carrier_eeprom_get_revision(struct var_carrier_eeprom *ep, char *rev, size_t size)
+{
+ if (var_carrier_eeprom_is_valid(ep))
+ strlcpy(rev, (const char *)ep->carrier_rev, size);
+ else
+ strlcpy(rev, "legacy", size);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Variscite Ltd.
+ *
+ */
+
+#ifndef _MX9_VAR_EEPROM_H_
+#define _MX9_VAR_EEPROM_H_
+
+#ifdef CONFIG_ARCH_IMX9
+#include <asm/arch-imx9/ddr.h>
+#endif
+
+#define VAR_SOM_EEPROM_MAGIC 0x4D58 /* == HEX("MX") */
+
+#define VAR_SOM_EEPROM_I2C_ADDR 0x52
+
+/* Optional SOM features */
+#define VAR_EEPROM_F_WIFI BIT(0)
+#define VAR_EEPROM_F_ETH BIT(1)
+#define VAR_EEPROM_F_AUDIO BIT(2)
+
+/* SOM storage types */
+enum som_storage {
+ SOM_STORAGE_EMMC,
+ SOM_STORAGE_NAND,
+ SOM_STORAGE_UNDEFINED,
+};
+
+/* Number of DRAM adjustment tables */
+#define DRAM_TABLE_NUM 7
+
+struct __packed var_eeprom
+{
+ u16 magic; /* 00-0x00 - magic number */
+ u8 partnum[8]; /* 02-0x02 - part number */
+ u8 assembly[10]; /* 10-0x0a - assembly number */
+ u8 date[9]; /* 20-0x14 - build date */
+ u8 mac[6]; /* 29-0x1d - MAC address */
+ u8 somrev; /* 35-0x23 - SOM revision */
+ u8 version; /* 36-0x24 - EEPROM version */
+ u8 features; /* 37-0x25 - SOM features */
+ u8 dramsize; /* 38-0x26 - DRAM size */
+ u8 reserved[5]; /* 39 0x27 - reserved */
+ u32 ddr_crc32; /* 44-0x2c - CRC32 of DDR DATAi */
+ u16 ddr_vic; /* 48-0x30 - DDR VIC PN */
+ u16 off[DRAM_TABLE_NUM + 1]; /* 50-0x32 - DRAM table offsets */
+};
+
+#define VAR_EEPROM_DATA ((struct var_eeprom *)VAR_EEPROM_DRAM_START)
+
+#define VAR_CARRIER_EEPROM_MAGIC 0x5643 /* == HEX("VC") */
+
+#define CARRIER_REV_LEN 16
+struct __packed var_carrier_eeprom
+{
+ u16 magic; /* 00-0x00 - magic number */
+ u8 struct_ver; /* 01-0x01 - EEPROM structure version */
+ u8 carrier_rev[CARRIER_REV_LEN]; /* 02-0x02 - carrier board revision */
+ u32 crc; /* 10-0x0a - checksum */
+};
+
+static inline int var_eeprom_is_valid(struct var_eeprom *ep)
+{
+ if (htons(ep->magic) != VAR_SOM_EEPROM_MAGIC) {
+ debug("Invalid EEPROM magic 0x%x, expected 0x%x\n",
+ htons(ep->magic), VAR_SOM_EEPROM_MAGIC);
+ return 0;
+ }
+
+ return 1;
+}
+
+int var_eeprom_read_header(struct var_eeprom *e);
+int var_eeprom_get_dram_size(struct var_eeprom *e, phys_size_t *size);
+int var_eeprom_get_mac(struct var_eeprom *e, u8 *mac);
+void var_eeprom_print_prod_info(struct var_eeprom *e);
+
+int var_carrier_eeprom_read(const char *bus_name, int addr, struct var_carrier_eeprom *ep);
+int var_carrier_eeprom_is_valid(struct var_carrier_eeprom *ep);
+void var_carrier_eeprom_get_revision(struct var_carrier_eeprom *ep, char *rev, size_t size);
+
+#endif /* _MX9_VAR_EEPROM_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ */
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+#include <mmc.h>
+#include <vsprintf.h>
+#include <env.h>
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = env_get("mmcautodetect");
+
+ if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
+ return 1;
+
+ return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+ char cmd[32];
+ u32 dev_no = mmc_get_env_dev();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ env_set_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ env_set_ulong("mmcblk", mmc_map_to_kernel_blk(dev_no));
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE
-M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
+M: Hugo Villeneuve <hvilleneuve@dimonoff.com>
S: Maintained
F: arch/arm/dts/imx8mn-var-som*
F: board/variscite/imx8mn_var_som/
#include <fdt_support.h>
#include <i2c_eeprom.h>
#include <malloc.h>
-#include <asm/io.h>
#include <asm/global_data.h>
#include <dt-bindings/gpio/gpio.h>
#include <linux/libfdt.h>
u8 partnumber2[5]; /* Part number 2 */
} __packed;
-static void setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
-}
-
int board_init(void)
{
- if (IS_ENABLED(CONFIG_FEC_MXC))
- setup_fec();
-
return 0;
}
--- /dev/null
+if TARGET_IMX93_VAR_SOM
+
+config SYS_BOARD
+ default "imx93_var_som"
+
+config SYS_VENDOR
+ default "variscite"
+
+config SYS_CONFIG_NAME
+ default "imx93_var_som"
+
+endif
--- /dev/null
+ARM i.MX93 VARISCITE VAR-SOM-MX93 MODULE
+M: Mathieu Othacehe <m.othacehe@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx93-var-som*
+F: board/variscite/imx93_var_som/
+F: configs/imx93_var_som_defconfig
+F: include/configs/imx93_var_som.h
--- /dev/null
+#
+# Copyright 2022 NXP
+# Copyright 2023 Variscite Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx93_var_som.o
+obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += ../common/imx9_eeprom.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += lpddr4x_timing.o
+else
+obj-y += ../common/eth.o
+obj-y += ../common/mmc.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/arch-imx9/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-imx9/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <power/pmic.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+#include "../common/imx9_eeprom.h"
+#include "../common/eth.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CARRIER_EEPROM_ADDR 0x54
+
+#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+ MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(LPUART1_CLK_ROOT);
+
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ struct var_eeprom *ep = VAR_EEPROM_DATA;
+
+ var_eeprom_get_dram_size(ep, size);
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static int setup_eqos(void)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
+int board_init(void)
+{
+ set_clk_enet(ENET_125MHZ);
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
+ return 0;
+}
+
+#define SDRAM_SIZE_STR_LEN 5
+
+int board_late_init(void)
+{
+ int ret;
+ struct var_eeprom *ep = VAR_EEPROM_DATA;
+ char sdram_size_str[SDRAM_SIZE_STR_LEN];
+ struct var_carrier_eeprom carrier_eeprom;
+ char carrier_rev[CARRIER_REV_LEN] = {0};
+ char som_rev[CARRIER_REV_LEN] = {0};
+
+ var_setup_mac(ep);
+ var_eeprom_print_prod_info(ep);
+
+ /* SDRAM ENV */
+ snprintf(sdram_size_str, SDRAM_SIZE_STR_LEN, "%d",
+ (int)(gd->ram_size / 1024 / 1024));
+ env_set("sdram_size", sdram_size_str);
+
+ /* Carrier Board ENV */
+ ret = var_carrier_eeprom_read(VAR_CARRIER_EEPROM_I2C_NAME,
+ CARRIER_EEPROM_ADDR, &carrier_eeprom);
+ if (!ret) {
+ var_carrier_eeprom_get_revision(&carrier_eeprom, carrier_rev,
+ sizeof(carrier_rev));
+ env_set("carrier_rev", carrier_rev);
+ }
+
+ /* SoM Rev ENV */
+ snprintf(som_rev, CARRIER_REV_LEN, "som_rev1%d", ep->somrev);
+ env_set("som_rev", som_rev);
+
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ board_late_mmc_env_init();
+
+ env_set("sec_boot", "no");
+ if (IS_ENABLED(CONFIG_AHAB_BOOT))
+ env_set("sec_boot", "yes");
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ env_set("board_name", "VAR-SOM-MX93");
+
+ return 0;
+}
--- /dev/null
+initrd_addr=0x83800000
+image=Image.gz
+img_addr=0x82000000
+console=ttyLP0,115200
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+boot_fit=no
+bootdir=/boot
+fdt_file=undefined
+bootm_size=0x10000000
+mmcdev=0
+mmcpart=1
+mmcautodetect=yes
+optargs=setenv bootargs ${bootargs} ${kernelargs};
+mmcroot=root=/dev/mmcblk0p1
+mmcargs=setenv bootargs ${jh_clk} console=${console} ${mmcroot} rootwait rw
+loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=load mmc ${mmcdev}:${mmcpart} ${img_addr} ${bootdir}/${image};
+ unzip ${img_addr} ${loadaddr}
+findfdt=if test $fdt_file = undefined; then
+ setenv fdt_file CONFIG_DEFAULT_FDT_FILE ;
+ fi;
+ echo fdt_file=${fdt_file};
+loadfdt=run findfdt;load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${bootdir}/${fdt_file}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r};
+mmcboot=echo Booting from mmc ...;
+ run mmcargs;
+ run optargs;
+ if test ${sec_boot} = yes; then
+ if run auth_os; then
+ "run boot_os;
+ else
+ "echo ERR: failed to authenticate;
+ fi;
+ else
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ if run loadfdt; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+netargs=setenv bootargs ${jh_clk} console=${console}
+ root=/dev/nfs
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+ etboot=echo Booting from net ...;
+ run netargs;
+ run optargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ if test ${sec_boot} = yes; then
+ ${get_cmd} ${cntr_addr} ${cntr_file};
+ if run auth_os; then
+ "run boot_os;
+ else
+ "echo ERR: failed to authenticate;
+ fi;
+ else
+ ${get_cmd} ${img_addr} ${image}; unzip ${img_addr} ${loadaddr};
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ run findfdt;
+ if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+bsp_bootcmd=echo Running BSP bootcmd ...;
+ mmc dev ${mmcdev}; if mmc rescan; then
+ if run loadbootscript; then
+ run bootscript;
+ else
+ if test ${sec_boot} = yes; then
+ if run loadcntr; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ else
+ if run loadimage; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ fi;
+ fi;
+ fi;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 NXP
+ *
+ * Code generated with DDR Tool.
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x4e300110, 0x44100001 },
+ { 0x4e300000, 0x8000ff },
+ { 0x4e300008, 0x0 },
+ { 0x4e300080, 0x80000512 },
+ { 0x4e300084, 0x0 },
+ { 0x4e300100, 0x24ab321b },
+ { 0x4e300104, 0xa8ee001b },
+ { 0x4e300108, 0x2f2ee233 },
+ { 0x4e30010c, 0x5e18b },
+ { 0x4e300114, 0x1002 },
+ { 0x4e300124, 0x1c770000 },
+ { 0x4e300160, 0x5402 },
+ { 0x4e30016c, 0x35f00000 },
+ { 0x4e300170, 0x8b0b0608 },
+ { 0x4e300250, 0x28 },
+ { 0x4e300254, 0x0 },
+ { 0x4e30025c, 0x400 },
+ { 0x4e300260, 0x800 },
+ { 0x4e300300, 0x14281114 },
+ { 0x4e300304, 0x163110a },
+ { 0x4e300308, 0xa200e3c },
+ { 0x4e300f04, 0x80 },
+ { 0x4e300800, 0x43b30002 },
+ { 0x4e300804, 0x1f1f1f1f },
+ { 0x4e301000, 0x0 },
+
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x4 },
+ { 0x100a1, 0x5 },
+ { 0x100a2, 0x6 },
+ { 0x100a3, 0x7 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x1 },
+ { 0x100a6, 0x2 },
+ { 0x100a7, 0x3 },
+ { 0x110a0, 0x3 },
+ { 0x110a1, 0x2 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x1 },
+ { 0x110a4, 0x7 },
+ { 0x110a5, 0x6 },
+ { 0x110a6, 0x4 },
+ { 0x110a7, 0x5 },
+ { 0x1005f, 0x5ff },
+ { 0x1015f, 0x5ff },
+ { 0x1105f, 0x5ff },
+ { 0x1115f, 0x5ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x2002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x2007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x20056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x10049, 0xe00 },
+ { 0x10149, 0xe00 },
+ { 0x11049, 0xe00 },
+ { 0x11149, 0xe00 },
+ { 0x43, 0x60 },
+ { 0x1043, 0x60 },
+ { 0x2043, 0x60 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x2009b, 0x2 },
+ { 0x20008, 0x3a5 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x10c },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x200fa, 0x2 },
+ { 0x20019, 0x1 },
+ { 0x200f0, 0x0 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x2002c, 0x0 },
+
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x4 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x15 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xff },
+ { 0x5400b, 0x4 },
+ { 0x5400c, 0x1 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x32 },
+ { 0x5401b, 0x1146 },
+ { 0x5401c, 0x1108 },
+ { 0x5401e, 0x6 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x32 },
+ { 0x54021, 0x1146 },
+ { 0x54022, 0x1108 },
+ { 0x54024, 0x6 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3236 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x811 },
+ { 0x54036, 0x11 },
+ { 0x54037, 0x600 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3236 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x811 },
+ { 0x5403c, 0x11 },
+ { 0x5403d, 0x600 },
+ { 0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x4 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x15 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xff },
+ { 0x5400b, 0x4 },
+ { 0x5400c, 0x1 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x2080 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x32 },
+ { 0x5401b, 0x1146 },
+ { 0x5401c, 0x1108 },
+ { 0x5401e, 0x6 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x32 },
+ { 0x54021, 0x1146 },
+ { 0x54022, 0x1108 },
+ { 0x54024, 0x6 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3236 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x811 },
+ { 0x54036, 0x11 },
+ { 0x54037, 0x600 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3236 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x811 },
+ { 0x5403c, 0x11 },
+ { 0x5403d, 0x600 },
+ { 0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x30 },
+ { 0x90051, 0x65a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x45a },
+ { 0x90055, 0x9 },
+ { 0x90056, 0x0 },
+ { 0x90057, 0x448 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x179 },
+ { 0x9005c, 0x1 },
+ { 0x9005d, 0x618 },
+ { 0x9005e, 0x109 },
+ { 0x9005f, 0x40c0 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x8 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x4040 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x0 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x48 },
+ { 0x9006b, 0x40 },
+ { 0x9006c, 0x633 },
+ { 0x9006d, 0x149 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x658 },
+ { 0x90070, 0x109 },
+ { 0x90071, 0x10 },
+ { 0x90072, 0x4 },
+ { 0x90073, 0x18 },
+ { 0x90074, 0x0 },
+ { 0x90075, 0x4 },
+ { 0x90076, 0x78 },
+ { 0x90077, 0x549 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0xd49 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x159 },
+ { 0x9007d, 0x94a },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x159 },
+ { 0x90080, 0x441 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x42 },
+ { 0x90084, 0x633 },
+ { 0x90085, 0x149 },
+ { 0x90086, 0x1 },
+ { 0x90087, 0x633 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x0 },
+ { 0x9008a, 0xe0 },
+ { 0x9008b, 0x109 },
+ { 0x9008c, 0xa },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x9 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x149 },
+ { 0x90092, 0x9 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x159 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x10 },
+ { 0x90097, 0x109 },
+ { 0x90098, 0x0 },
+ { 0x90099, 0x3c0 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x18 },
+ { 0x9009c, 0x4 },
+ { 0x9009d, 0x48 },
+ { 0x9009e, 0x18 },
+ { 0x9009f, 0x4 },
+ { 0x900a0, 0x58 },
+ { 0x900a1, 0xb },
+ { 0x900a2, 0x10 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x1 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x900a7, 0x5 },
+ { 0x900a8, 0x7c0 },
+ { 0x900a9, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900aa, 0x0 },
+ { 0x900ab, 0x790 },
+ { 0x900ac, 0x11a },
+ { 0x900ad, 0x8 },
+ { 0x900ae, 0x7aa },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x7b2 },
+ { 0x900b2, 0x2a },
+ { 0x900b3, 0x0 },
+ { 0x900b4, 0x7c8 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x10 },
+ { 0x900b7, 0x10 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x10 },
+ { 0x900ba, 0x2a8 },
+ { 0x900bb, 0x129 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x370 },
+ { 0x900be, 0x129 },
+ { 0x900bf, 0xa },
+ { 0x900c0, 0x3c8 },
+ { 0x900c1, 0x1a9 },
+ { 0x900c2, 0xc },
+ { 0x900c3, 0x408 },
+ { 0x900c4, 0x199 },
+ { 0x900c5, 0x14 },
+ { 0x900c6, 0x790 },
+ { 0x900c7, 0x11a },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x4 },
+ { 0x900ca, 0x18 },
+ { 0x900cb, 0xe },
+ { 0x900cc, 0x408 },
+ { 0x900cd, 0x199 },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x8568 },
+ { 0x900d0, 0x108 },
+ { 0x900d1, 0x18 },
+ { 0x900d2, 0x790 },
+ { 0x900d3, 0x16a },
+ { 0x900d4, 0x8 },
+ { 0x900d5, 0x1d8 },
+ { 0x900d6, 0x169 },
+ { 0x900d7, 0x10 },
+ { 0x900d8, 0x8558 },
+ { 0x900d9, 0x168 },
+ { 0x900da, 0x1ff8 },
+ { 0x900db, 0x85a8 },
+ { 0x900dc, 0x1e8 },
+ { 0x900dd, 0x50 },
+ { 0x900de, 0x798 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x60 },
+ { 0x900e1, 0x7a0 },
+ { 0x900e2, 0x16a },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0x8310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0x8 },
+ { 0x900e7, 0xa310 },
+ { 0x900e8, 0x168 },
+ { 0x900e9, 0xa },
+ { 0x900ea, 0x408 },
+ { 0x900eb, 0x169 },
+ { 0x900ec, 0x6e },
+ { 0x900ed, 0x0 },
+ { 0x900ee, 0x68 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x408 },
+ { 0x900f1, 0x169 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0x8310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x0 },
+ { 0x900f6, 0xa310 },
+ { 0x900f7, 0x168 },
+ { 0x900f8, 0x1ff8 },
+ { 0x900f9, 0x85a8 },
+ { 0x900fa, 0x1e8 },
+ { 0x900fb, 0x68 },
+ { 0x900fc, 0x798 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x78 },
+ { 0x900ff, 0x7a0 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x68 },
+ { 0x90102, 0x790 },
+ { 0x90103, 0x16a },
+ { 0x90104, 0x8 },
+ { 0x90105, 0x8b10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0x8 },
+ { 0x90108, 0xab10 },
+ { 0x90109, 0x168 },
+ { 0x9010a, 0xa },
+ { 0x9010b, 0x408 },
+ { 0x9010c, 0x169 },
+ { 0x9010d, 0x58 },
+ { 0x9010e, 0x0 },
+ { 0x9010f, 0x68 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x408 },
+ { 0x90112, 0x169 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0x8b10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x1 },
+ { 0x90117, 0xab10 },
+ { 0x90118, 0x168 },
+ { 0x90119, 0x0 },
+ { 0x9011a, 0x1d8 },
+ { 0x9011b, 0x169 },
+ { 0x9011c, 0x80 },
+ { 0x9011d, 0x790 },
+ { 0x9011e, 0x16a },
+ { 0x9011f, 0x18 },
+ { 0x90120, 0x7aa },
+ { 0x90121, 0x6a },
+ { 0x90122, 0xa },
+ { 0x90123, 0x0 },
+ { 0x90124, 0x1e9 },
+ { 0x90125, 0x8 },
+ { 0x90126, 0x8080 },
+ { 0x90127, 0x108 },
+ { 0x90128, 0xf },
+ { 0x90129, 0x408 },
+ { 0x9012a, 0x169 },
+ { 0x9012b, 0xc },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x68 },
+ { 0x9012e, 0x9 },
+ { 0x9012f, 0x0 },
+ { 0x90130, 0x1a9 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x408 },
+ { 0x90133, 0x169 },
+ { 0x90134, 0x0 },
+ { 0x90135, 0x8080 },
+ { 0x90136, 0x108 },
+ { 0x90137, 0x8 },
+ { 0x90138, 0x7aa },
+ { 0x90139, 0x6a },
+ { 0x9013a, 0x0 },
+ { 0x9013b, 0x8568 },
+ { 0x9013c, 0x108 },
+ { 0x9013d, 0xb7 },
+ { 0x9013e, 0x790 },
+ { 0x9013f, 0x16a },
+ { 0x90140, 0x1f },
+ { 0x90141, 0x0 },
+ { 0x90142, 0x68 },
+ { 0x90143, 0x8 },
+ { 0x90144, 0x8558 },
+ { 0x90145, 0x168 },
+ { 0x90146, 0xf },
+ { 0x90147, 0x408 },
+ { 0x90148, 0x169 },
+ { 0x90149, 0xd },
+ { 0x9014a, 0x0 },
+ { 0x9014b, 0x68 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x408 },
+ { 0x9014e, 0x169 },
+ { 0x9014f, 0x0 },
+ { 0x90150, 0x8558 },
+ { 0x90151, 0x168 },
+ { 0x90152, 0x8 },
+ { 0x90153, 0x3c8 },
+ { 0x90154, 0x1a9 },
+ { 0x90155, 0x3 },
+ { 0x90156, 0x370 },
+ { 0x90157, 0x129 },
+ { 0x90158, 0x20 },
+ { 0x90159, 0x2aa },
+ { 0x9015a, 0x9 },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x104 },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x448 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0xf },
+ { 0x90168, 0x7c0 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x0 },
+ { 0x9016b, 0xe8 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x47 },
+ { 0x9016e, 0x630 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0x618 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0xe0 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x0 },
+ { 0x90177, 0x7c8 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0x8140 },
+ { 0x9017b, 0x10c },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x478 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x1 },
+ { 0x90181, 0x8 },
+ { 0x90182, 0x8 },
+ { 0x90183, 0x4 },
+ { 0x90184, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2b },
+ { 0x90026, 0x69 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x75 },
+ { 0x2000c, 0xe9 },
+ { 0x2000d, 0x91c },
+ { 0x2000e, 0x2c },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x400f1, 0xe },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3733mts 1D */
+ .drate = 3733,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P0 3733mts 2D */
+ .drate = 3733,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3733, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+#include <command.h>
+#include <cpu_func.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/sections.h>
+#include <asm/mach-imx/syscounter.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+#include "../common/imx9_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct var_eeprom eeprom = {0};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+ struct var_eeprom *ep = VAR_EEPROM_DATA;
+
+ puts("Normal Boot\n");
+
+ /* Copy EEPROM contents to DRAM */
+ memcpy(ep, &eeprom, sizeof(*ep));
+}
+
+void spl_dram_init(void)
+{
+ /* EEPROM initialization */
+ var_eeprom_read_header(&eeprom);
+
+ ddr_init(&dram_timing);
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pca9450@25\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* enable DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+
+ /* set standby voltage to 0.65V */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+ /* I2C_LT_EN*/
+ pmic_reg_write(dev, 0xa, 0x3);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ timer_init();
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ spl_early_init();
+
+ preloader_console_init();
+
+ ret = arch_cpu_init();
+ if (ret) {
+ printf("Fail to init Sentinel API\n");
+ } else {
+ printf("SOC: 0x%x\n", gd->arch.soc_rev);
+ printf("LC: 0x%x\n", gd->arch.lifecycle);
+ }
+ power_init_board();
+
+ set_arm_core_max_clk();
+
+ /* Init power of mix */
+ soc_power_init();
+
+ /* Setup TRDC for DDR access */
+ trdc_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Put M33 into CPUWAIT for following kick */
+ ret = m33_prepare();
+ if (!ret)
+ printf("M33 prepare ok\n");
+
+ board_init_r(NULL, 0);
+}
#include <env.h>
#include <linux/delay.h>
#include <linux/sizes.h>
-#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <phy.h>
config BOOT_SCRIPT_OFFSET
hex "Boot script offset"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV
default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
default 0x3E80000 if ARCH_ZYNQMP
default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0 if TARGET_XILINX_MBV
help
Specifies distro boot script offset in NAND/QSPI/NOR flash.
#endif
#if defined(CONFIG_LMB)
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE (1 * 1024 * 1024)
+#endif
+
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
fru, 8, 1, do_fru,
"FRU table info",
fru_help_text
-)
+);
--- /dev/null
+if TARGET_XILINX_MBV
+
+config SYS_BOARD
+ default "mbv"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "xilinx_mbv"
+
+config TEXT_BASE
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+ imply BOARD_LATE_INIT
+ imply CMD_SBI
+ imply CMD_PING
+
+source "board/xilinx/Kconfig"
+
+endif
--- /dev/null
+XILINX MicroBlaze V BOARD
+M: Michal Simek <michal.simek@amd.com>
+S: Maintained
+F: arch/riscv/dts/xilinx-mbv*
+F: board/xilinx/mbv/
+F: configs/xilinx_mbv*
+F: include/configs/xilinx_mbv.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+obj-y += board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+int board_init(void)
+{
+ return 0;
+}
U_BOOT_CMD(versal, 4, 1, do_versal,
"versal sub-system",
versal_help_text
-)
+);
"mmc 0=boot.bin fat 0 1;"
"%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
break;
+#if defined(CONFIG_SPL_SPI_LOAD)
case ZYNQ_BM_QSPI:
snprintf(buf, DFU_ALT_BUF_LEN,
"sf 0:0=boot.bin raw 0 0x1500000;"
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
CONFIG_SYS_SPI_U_BOOT_OFFS);
break;
+#endif
default:
return;
}
zynqmp, 9, 1, do_zynqmp,
"ZynqMP sub-system",
zynqmp_help_text
-)
+);
/* FIXME remove this when vivado is fixed */
#include <asm/io.h>
-#include <common.h>
#include <linux/delay.h>
#define xil_printf(...)
puts("DFU alt info setting: done\n");
}
#endif
+
+#if defined(CONFIG_SPL_SPI_LOAD)
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
+{
+ u32 offset;
+ int multiboot = multi_boot();
+
+ offset = multiboot * SZ_32K;
+ offset += CONFIG_SYS_SPI_U_BOOT_OFFS;
+
+ log_info("SPI offset:\t0x%x\n", offset);
+
+ return offset;
+}
+#endif
--- /dev/null
+autoload=no
+baudrate=115200
+boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
+boot_efi_binary=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr ${fdtcontroladdr};fi;load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootaa64.efi; if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi
+boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf}
+boot_net_usb_start=usb start
+boot_prefixes=/ /boot/
+boot_script_dhcp=boot.scr.uimg
+boot_scripts=boot.scr.uimg boot.scr
+boot_syslinux_conf=extlinux/extlinux.conf
+bootcmd_dhcp=run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00011:UNDI:003000;setenv bootp_arch 0xb;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci;
+bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;
+bootcmd_mmc0=devnum=0; run mmc_boot
+bootcmd_mmc1=devnum=1; run mmc_boot
+bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
+bootcmd_usb0=devnum=0; run usb_boot
+bootcmd_usb1=devnum=1; run usb_boot
+bootcmd_usb2=devnum=2; run usb_boot
+bootcmd_usb3=devnum=3; run usb_boot
+bootdelay=2
+bootfstype=fat
+bootm_low=0
+bootm_size=0x80000000
+distro_bootcmd=scsi_need_init=; for target in ${boot_targets}; do run bootcmd_${target}; done
+efi_dtb_prefixes=/ /dtb/ /dtb/current/
+fdt_addr_r=0x40000000
+fdt_high=0x10000000
+fileaddr=0x18000000
+initrd_high=0x79000000
+kernel_addr_r=0x18000000
+load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
+mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
+pxefile_addr_r=0x10000000
+ramdisk_addr_r=0x02100000
+scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi;
+scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done; setenv devplist
+scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootaa64.efi; then echo Found EFI removable media binary efi/boot/bootaa64.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile
+scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo SCRIPT FAILED: continuing...; fi
+scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done
+script_offset_f=0x3e80000
+script_size_f=0x80000
+scriptaddr=0x20000000
+usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
+preboot=setenv boot_targets; setenv modeboot; run board_setup
+
+# SOM specific boot methods
+som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; fi;"
+som_mmc_boot=setenv boot_targets mmc0 && run distro_bootcmd
+
+k26_starter=SMK-K26-XCL2G
+k24_starter=SMK-K24-XCL2G
+bootcmd=setenv model $board_name && if setexpr model gsub .*$k24_starter* $k24_starter || setexpr model gsub .*$k26_starter* $k26_starter; then run som_cc_boot; else run som_mmc_boot; run som_cc_boot; fi
+
+usb_hub_init=mw 1000 0056 && sleep 1 && i2c write 1000 2d aa 2 -s
+
+# usb hub init
+kv260_setup=i2c dev 1 && run usb_hub_init
+# usb hub init
+kr260_setup=i2c dev 1 && run usb_hub_init; i2c dev 2 && run usb_hub_init;
+# usb hub init with enabling PM nodes for ...
+kd240_setup=i2c dev 0 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw node 47
+
+board_setup=\
+if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\
+if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\
+if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi;
help
Utilities for parsing PXE file formats.
-config BOOT_DEFAULTS
- bool # Common defaults for standard boot and distroboot
+config BOOT_DEFAULTS_FEATURES
+ bool
+ select SUPPORT_RAW_INITRD
+ select ENV_VARS_UBOOT_CONFIG
+ imply USB_STORAGE
+ imply EFI_PARTITION
+ imply ISO_PARTITION
+
+config BOOT_DEFAULTS_CMDS
+ bool
imply USE_BOOTCOMMAND
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_DHCP if CMD_NET
select CMD_PING if CMD_NET
select CMD_PXE if CMD_NET
- select SUPPORT_RAW_INITRD
- select ENV_VARS_UBOOT_CONFIG
select CMD_BOOTI if ARM64
select CMD_BOOTZ if ARM && !ARM64
imply CMD_MII if NET
- imply USB_STORAGE
- imply EFI_PARTITION
- imply ISO_PARTITION
+
+config BOOT_DEFAULTS
+ bool # Common defaults for standard boot and distroboot
+ select BOOT_DEFAULTS_FEATURES
+ select BOOT_DEFAULTS_CMDS if CMDLINE
help
These are not required but are commonly needed to support a good
selection of booting methods. Enable this to improve the capability
config BOOTSTD_DEFAULTS
bool "Select some common defaults for standard boot"
depends on BOOTSTD
- imply USE_BOOTCOMMAND
select BOOT_DEFAULTS
select BOOTMETH_DISTRO
help
standard boot does not support all of the features of distro boot
yet.
+config BOOTSTD_PROG
+ bool "Use programmatic boot"
+ depends on !CMDLINE
+ default y
+ help
+ Enable this to provide a board_run_command() function which can boot
+ a systen without using commands. If the boot fails, then U-Boot will
+ panic.
+
+ Note: This currently has many limitations and is not a useful booting
+ solution. Future work will eventually make this a viable option.
+
config BOOTMETH_GLOBAL
bool
help
config BOOTMETH_EFILOADER
bool "Bootdev support for EFI boot"
- depends on EFI_LOADER
+ depends on BOOTEFI_BOOTMGR
default y
help
Enables support for EFI boot using bootdevs. This makes the
config BOOTMETH_DISTRO
bool # Options needed to boot any distro
- select BOOTMETH_SCRIPT # E.g. Armbian uses scripts
+ select BOOTMETH_SCRIPT if CMDLINE # E.g. Armbian uses scripts
select BOOTMETH_EXTLINUX # E.g. Debian uses these
select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH
- select BOOTMETH_EFILOADER if EFI_LOADER # E.g. Ubuntu uses this
+ select BOOTMETH_EFILOADER if BOOTEFI_BOOTMGR # E.g. Ubuntu uses this
config SPL_BOOTMETH_VBE
bool "Bootdev support for Verified Boot for Embedded (SPL)"
config BOOTMETH_SCRIPT
bool "Bootdev support for U-Boot scripts"
default y if BOOTSTD_FULL
+ depends on CMDLINE
select HUSH_PARSER
help
Enables support for booting a distro via a U-Boot script. This makes
event log memory region.
endif # MEASURED_BOOT
+config SYS_BOOTM_LEN
+ hex "Maximum size of a decompresed OS image"
+ depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
+ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
+ default 0x4000000 if PPC || ARM64
+ default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
+ default 0x800000
+ help
+ This is the maximum size of the buffer that is used to decompress the OS
+ image in to if attempting to boot a compressed image.
+
config SUPPORT_RAW_INITRD
bool "Enable raw initrd images"
help
config DISTRO_DEFAULTS
bool "(deprecated) Script-based booting of Linux distributions"
+ select CMDLINE
select BOOT_DEFAULTS
select AUTO_COMPLETE
select CMDLINE_EDITING
config AUTOBOOT
bool "Autoboot"
+ depends on CMDLINE
default y
help
This enables the autoboot. See doc/README.autoboot for detail.
+if AUTOBOOT
+
config BOOTDELAY
int "delay in seconds before automatically booting"
default 2
- depends on AUTOBOOT
help
Delay before automatically running bootcmd;
set to 0 to autoboot with no delay, but you can stop it by key input.
U-Boot automatic booting process and bring the device
to the U-Boot prompt for user input.
+if AUTOBOOT_KEYED
+
config AUTOBOOT_FLUSH_STDIN
bool "Enable flushing stdin before starting to read the password"
- depends on AUTOBOOT_KEYED && !SANDBOX
+ depends on !SANDBOX
help
When this option is enabled stdin buffer will be flushed before
starting to read the password.
config AUTOBOOT_PROMPT
string "Autoboot stop prompt"
- depends on AUTOBOOT_KEYED
default "Autoboot in %d seconds\\n"
help
This string is displayed before the boot delay selected by
config AUTOBOOT_ENCRYPTION
bool "Enable encryption in autoboot stopping"
- depends on AUTOBOOT_KEYED
help
This option allows a string to be entered into U-Boot to stop the
autoboot.
config AUTOBOOT_DELAY_STR
string "Delay autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option delays the automatic boot feature by issuing
a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR
config AUTOBOOT_STOP_STR
string "Stop autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option enables stopping (aborting) of the automatic
boot feature only by issuing a specific input key or
config AUTOBOOT_KEYED_CTRLC
bool "Enable Ctrl-C autoboot interruption"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option allows for the boot sequence to be interrupted
by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
config AUTOBOOT_NEVER_TIMEOUT
bool "Make the password entry never time-out"
- depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION && CRYPT_PW
+ depends on AUTOBOOT_ENCRYPTION && CRYPT_PW
help
This option removes the timeout from the password entry
when the user first presses the <Enter> key before entering
config AUTOBOOT_STOP_STR_ENABLE
bool "Enable fixed string to stop autobooting"
- depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
+ depends on AUTOBOOT_ENCRYPTION
help
This option enables the feature to add a fixed stop
string that is defined at compile time.
includes a ":", the portion prior to the ":" will be treated
as a salt value.
+endif # AUTOBOOT_KEYED
+
+if !AUTOBOOT_KEYED
+
config AUTOBOOT_USE_MENUKEY
bool "Allow a specify key to run a menu from the environment"
- depends on !AUTOBOOT_KEYED
help
If a specific key is pressed to stop autoboot, then the commands in
the environment variable 'menucmd' are executed before boot starts.
For example, 33 means "!" in ASCII, so pressing ! at boot would take
this action.
+endif
+
+endif # AUTOBOOT
+
config AUTOBOOT_MENU_SHOW
bool "Show a menu on boot"
depends on CMD_BOOTMENU
menu "Devicetree fixup"
+config OF_ENV_SETUP
+ bool "Run a command from environment to set up device tree before boot"
+ depends on CMD_FDT
+ help
+ This causes U-Boot to run a command from the environment variable
+ fdt_fixup before booting into the operating system, which can use the
+ fdt command to modify the device tree. The device tree is then passed
+ to the OS.
+
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
help
config USE_BOOTCOMMAND
bool "Enable a default value for bootcmd"
+ depends on CMDLINE
help
Provide a default value for the bootcmd entry in the environment. If
autoboot is enabled this is what will be run automatically. Enable
config USE_PREBOOT
bool "Enable preboot"
+ depends on CMDLINE
help
When this option is enabled, the existence of the environment
variable "preboot" will be checked immediately before starting the
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootmeth-uclass.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootstd-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTSTD_PROG) += prog_boot.o
+
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o
-obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootmeth_cros.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o
ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL
-obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o
+obj-$(CONFIG_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o
obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o
obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
#ifndef USE_HOSTCC
#include <common.h>
+#include <bootm.h>
#include <bootstage.h>
#include <cli.h>
#include <command.h>
struct bootm_headers images; /* pointers to os/initrd/fdt images */
-static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], struct bootm_headers *images,
- ulong *os_data, ulong *os_len);
-
__weak void board_quiesce_devices(void)
{
}
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
+/**
+ * image_get_kernel - verify legacy format kernel image
+ * @img_addr: in RAM address of the legacy format image to be verified
+ * @verify: data CRC verification flag
+ *
+ * image_get_kernel() verifies legacy image integrity and returns pointer to
+ * legacy image header if image verification was completed successfully.
+ *
+ * returns:
+ * pointer to a legacy image header if valid image was found
+ * otherwise return NULL
+ */
+static struct legacy_img_hdr *image_get_kernel(ulong img_addr, int verify)
+{
+ struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)img_addr;
+
+ if (!image_check_magic(hdr)) {
+ puts("Bad Magic Number\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC);
+ return NULL;
+ }
+ bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER);
+
+ if (!image_check_hcrc(hdr)) {
+ puts("Bad Header Checksum\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_HEADER);
+ return NULL;
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM);
+ image_print_contents(hdr);
+
+ if (verify) {
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(hdr)) {
+ printf("Bad Data CRC\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM);
+ return NULL;
+ }
+ puts("OK\n");
+ }
+ bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH);
+
+ if (!image_check_target_arch(hdr)) {
+ printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr));
+ bootstage_error(BOOTSTAGE_ID_CHECK_ARCH);
+ return NULL;
+ }
+ return hdr;
+}
+#endif
+
+/**
+ * boot_get_kernel() - find kernel image
+ *
+ * @addr_fit: first argument to bootm: address, fit configuration, etc.
+ * @os_data: pointer to a ulong variable, will hold os data start address
+ * @os_len: pointer to a ulong variable, will hold os data length
+ * address and length, otherwise NULL
+ * pointer to image header if valid image was found, plus kernel start
+ * @kernp: image header if valid image was found, otherwise NULL
+ *
+ * boot_get_kernel() tries to find a kernel image, verifies its integrity
+ * and locates kernel data.
+ *
+ * Return: 0 on success, -ve on error. -EPROTOTYPE means that the image is in
+ * a wrong or unsupported format
+ */
+static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images,
+ ulong *os_data, ulong *os_len, const void **kernp)
+{
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
+ struct legacy_img_hdr *hdr;
+#endif
+ ulong img_addr;
+ const void *buf;
+ const char *fit_uname_config = NULL, *fit_uname_kernel = NULL;
+#if CONFIG_IS_ENABLED(FIT)
+ int os_noffset;
+#endif
+
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ const void *boot_img;
+ const void *vendor_boot_img;
+#endif
+ img_addr = genimg_get_kernel_addr_fit(addr_fit, &fit_uname_config,
+ &fit_uname_kernel);
+
+ if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD))
+ img_addr += image_load_offset;
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC);
+
+ /* check image type, for FIT images get FIT kernel node */
+ *os_data = *os_len = 0;
+ buf = map_sysmem(img_addr, 0);
+ switch (genimg_get_format(buf)) {
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
+ case IMAGE_FORMAT_LEGACY:
+ printf("## Booting kernel from Legacy Image at %08lx ...\n",
+ img_addr);
+ hdr = image_get_kernel(img_addr, images->verify);
+ if (!hdr)
+ return -EINVAL;
+ bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE);
+
+ /* get os_data and os_len */
+ switch (image_get_type(hdr)) {
+ case IH_TYPE_KERNEL:
+ case IH_TYPE_KERNEL_NOLOAD:
+ *os_data = image_get_data(hdr);
+ *os_len = image_get_data_size(hdr);
+ break;
+ case IH_TYPE_MULTI:
+ image_multi_getimg(hdr, 0, os_data, os_len);
+ break;
+ case IH_TYPE_STANDALONE:
+ *os_data = image_get_data(hdr);
+ *os_len = image_get_data_size(hdr);
+ break;
+ default:
+ bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
+ return -EPROTOTYPE;
+ }
+
+ /*
+ * copy image header to allow for image overwrites during
+ * kernel decompression.
+ */
+ memmove(&images->legacy_hdr_os_copy, hdr,
+ sizeof(struct legacy_img_hdr));
+
+ /* save pointer to image header */
+ images->legacy_hdr_os = hdr;
+
+ images->legacy_hdr_valid = 1;
+ bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
+ break;
+#endif
+#if CONFIG_IS_ENABLED(FIT)
+ case IMAGE_FORMAT_FIT:
+ os_noffset = fit_image_load(images, img_addr,
+ &fit_uname_kernel, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_KERNEL,
+ BOOTSTAGE_ID_FIT_KERNEL_START,
+ FIT_LOAD_IGNORED, os_data, os_len);
+ if (os_noffset < 0)
+ return -ENOENT;
+
+ images->fit_hdr_os = map_sysmem(img_addr, 0);
+ images->fit_uname_os = fit_uname_kernel;
+ images->fit_uname_cfg = fit_uname_config;
+ images->fit_noffset_os = os_noffset;
+ break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID: {
+ int ret;
+
+ boot_img = buf;
+ vendor_boot_img = NULL;
+ if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+ boot_img = map_sysmem(get_abootimg_addr(), 0);
+ vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
+ }
+ printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
+ ret = android_image_get_kernel(boot_img, vendor_boot_img,
+ images->verify, os_data, os_len);
+ if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+ unmap_sysmem(vendor_boot_img);
+ unmap_sysmem(boot_img);
+ }
+ if (ret)
+ return ret;
+ break;
+ }
+#endif
+ default:
+ bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
+ return -EPROTOTYPE;
+ }
+
+ debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n",
+ *os_data, *os_len, *os_len);
+ *kernp = buf;
+
+ return 0;
+}
+
#ifdef CONFIG_LMB
static void boot_start_lmb(struct bootm_headers *images)
{
static inline void boot_start_lmb(struct bootm_headers *images) { }
#endif
-static int bootm_start(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int bootm_start(void)
{
memset((void *)&images, 0, sizeof(images));
images.verify = env_get_yesno("verify");
return 0;
}
-static ulong bootm_data_addr(int argc, char *const argv[])
+static ulong bootm_data_addr(const char *addr_str)
{
ulong addr;
- if (argc > 0)
- addr = simple_strtoul(argv[0], NULL, 16);
+ if (addr_str)
+ addr = hextoul(addr_str, NULL);
else
addr = image_load_addr;
return addr;
}
-static int bootm_pre_load(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+/**
+ * bootm_pre_load() - Handle the pre-load processing
+ *
+ * This can be used to do a full signature check of the image, for example.
+ * It calls image_pre_load() with the data address of the image to check.
+ *
+ * @addr_str: String containing load address in hex, or NULL to use
+ * image_load_addr
+ * Return: 0 if OK, CMD_RET_FAILURE on failure
+ */
+static int bootm_pre_load(const char *addr_str)
{
- ulong data_addr = bootm_data_addr(argc, argv);
+ ulong data_addr = bootm_data_addr(addr_str);
int ret = 0;
if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD))
return ret;
}
-static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+/**
+ * bootm_find_os(): Find the OS to boot
+ *
+ * @cmd_name: Command name that started this boot, e.g. "bootm"
+ * @addr_fit: Address and/or FIT specifier (first arg of bootm command)
+ * Return: 0 on success, -ve on error
+ */
+static int bootm_find_os(const char *cmd_name, const char *addr_fit)
{
const void *os_hdr;
#ifdef CONFIG_ANDROID_BOOT_IMAGE
int ret;
/* get kernel image header, start address and length */
- os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
- &images, &images.os.image_start, &images.os.image_len);
- if (images.os.image_len == 0) {
- puts("ERROR: can't get kernel image!\n");
+ ret = boot_get_kernel(addr_fit, &images, &images.os.image_start,
+ &images.os.image_len, &os_hdr);
+ if (ret) {
+ if (ret == -EPROTOTYPE)
+ printf("Wrong Image Type for %s command\n", cmd_name);
+
+ printf("ERROR %dE: can't get kernel image!\n", ret);
return 1;
}
}
if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
- if (IS_ENABLED(CONFIG_CMD_BOOTI) &&
- images.os.arch == IH_ARCH_ARM64 &&
- images.os.os == IH_OS_LINUX) {
- ulong image_addr;
- ulong image_size;
-
- ret = booti_setup(images.os.image_start, &image_addr,
- &image_size, true);
- if (ret != 0)
- return 1;
-
- images.os.type = IH_TYPE_KERNEL;
- images.os.load = image_addr;
- images.ep = image_addr;
- } else {
- images.os.load = images.os.image_start;
- images.ep += images.os.image_start;
- }
+ images.os.load = images.os.image_start;
+ images.ep += images.os.image_start;
}
images.os.start = map_to_sysmem(os_hdr);
}
/**
- * bootm_find_images - wrapper to find and locate various images
- * @flag: Ignored Argument
- * @argc: command argument count
- * @argv: command argument list
- * @start: OS image start address
- * @size: OS image size
- *
- * boot_find_images() will attempt to load an available ramdisk,
- * flattened device tree, as well as specifically marked
- * "loadable" images (loadables are FIT only)
+ * check_overlap() - Check if an image overlaps the OS
*
- * Note: bootm_find_images will skip an image if it is not found
- *
- * @return:
- * 0, if all existing images were loaded correctly
- * 1, if an image is found but corrupted, or invalid
+ * @name: Name of image to check (used to print error)
+ * @base: Base address of image
+ * @end: End address of image (+1)
+ * @os_start: Start of OS
+ * @os_size: Size of OS in bytes
+ * Return: 0 if OK, -EXDEV if the image overlaps the OS
*/
-int bootm_find_images(int flag, int argc, char *const argv[], ulong start,
- ulong size)
+static int check_overlap(const char *name, ulong base, ulong end,
+ ulong os_start, ulong os_size)
{
+ ulong os_end;
+
+ if (!base)
+ return 0;
+ os_end = os_start + os_size;
+
+ if ((base >= os_start && base < os_end) ||
+ (end > os_start && end <= os_end) ||
+ (base < os_start && end >= os_end)) {
+ printf("ERROR: %s image overlaps OS image (OS=%lx..%lx)\n",
+ name, os_start, os_end);
+
+ return -EXDEV;
+ }
+
+ return 0;
+}
+
+int bootm_find_images(ulong img_addr, const char *conf_ramdisk,
+ const char *conf_fdt, ulong start, ulong size)
+{
+ const char *select = conf_ramdisk;
+ char addr_str[17];
+ void *buf;
int ret;
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ /* Look for an Android boot image */
+ buf = map_sysmem(images.os.start, 0);
+ if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) {
+ strcpy(addr_str, simple_xtoa(img_addr));
+ select = addr_str;
+ }
+ }
+
+ if (conf_ramdisk)
+ select = conf_ramdisk;
+
/* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH,
+ ret = boot_get_ramdisk(select, &images, IH_INITRD_ARCH,
&images.rd_start, &images.rd_end);
if (ret) {
puts("Ramdisk image is corrupt or invalid\n");
}
/* check if ramdisk overlaps OS image */
- if (images.rd_start && (((ulong)images.rd_start >= start &&
- (ulong)images.rd_start < start + size) ||
- ((ulong)images.rd_end > start &&
- (ulong)images.rd_end <= start + size) ||
- ((ulong)images.rd_start < start &&
- (ulong)images.rd_end >= start + size))) {
- printf("ERROR: RD image overlaps OS image (OS=0x%lx..0x%lx)\n",
- start, start + size);
+ if (check_overlap("RD", images.rd_start, images.rd_end, start, size))
return 1;
- }
-#if CONFIG_IS_ENABLED(OF_LIBFDT)
- /* find flattened device tree */
- ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
- &images.ft_addr, &images.ft_len);
- if (ret) {
- puts("Could not find a valid device tree\n");
- return 1;
- }
+ if (CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ buf = map_sysmem(img_addr, 0);
- /* check if FDT overlaps OS image */
- if (images.ft_addr &&
- (((ulong)images.ft_addr >= start &&
- (ulong)images.ft_addr < start + size) ||
- ((ulong)images.ft_addr + images.ft_len >= start &&
- (ulong)images.ft_addr + images.ft_len < start + size))) {
- printf("ERROR: FDT image overlaps OS image (OS=0x%lx..0x%lx)\n",
- start, start + size);
- return 1;
- }
+ /* find flattened device tree */
+ ret = boot_get_fdt(buf, conf_fdt, IH_ARCH_DEFAULT, &images,
+ &images.ft_addr, &images.ft_len);
+ if (ret) {
+ puts("Could not find a valid device tree\n");
+ return 1;
+ }
- if (IS_ENABLED(CONFIG_CMD_FDT))
- set_working_fdt_addr(map_to_sysmem(images.ft_addr));
-#endif
+ /* check if FDT overlaps OS image */
+ if (check_overlap("FDT", map_to_sysmem(images.ft_addr),
+ images.ft_len, start, size))
+ return 1;
+
+ if (IS_ENABLED(CONFIG_CMD_FDT))
+ set_working_fdt_addr(map_to_sysmem(images.ft_addr));
+ }
#if CONFIG_IS_ENABLED(FIT)
if (IS_ENABLED(CONFIG_FPGA)) {
/* find bitstreams */
- ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
- NULL, NULL);
+ ret = boot_get_fpga(&images);
if (ret) {
printf("FPGA image is corrupted or invalid\n");
return 1;
}
/* find all of the loadables */
- ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
- NULL, NULL);
+ ret = boot_get_loadable(&images);
if (ret) {
printf("Loadable(s) is corrupt or invalid\n");
return 1;
return 0;
}
-static int bootm_find_other(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int bootm_find_other(ulong img_addr, const char *conf_ramdisk,
+ const char *conf_fdt)
{
- if (((images.os.type == IH_TYPE_KERNEL) ||
- (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
- (images.os.type == IH_TYPE_MULTI)) &&
- (images.os.os == IH_OS_LINUX ||
- images.os.os == IH_OS_VXWORKS))
- return bootm_find_images(flag, argc, argv, 0, 0);
+ if ((images.os.type == IH_TYPE_KERNEL ||
+ images.os.type == IH_TYPE_KERNEL_NOLOAD ||
+ images.os.type == IH_TYPE_MULTI) &&
+ (images.os.os == IH_OS_LINUX || images.os.os == IH_OS_VXWORKS ||
+ images.os.os == IH_OS_EFI || images.os.os == IH_OS_TEE)) {
+ return bootm_find_images(img_addr, conf_ramdisk, conf_fdt, 0,
+ 0);
+ }
return 0;
}
void *load_buf, *image_buf;
int err;
+ /*
+ * For a "noload" compressed kernel we need to allocate a buffer large
+ * enough to decompress in to and use that as the load address now.
+ * Assume that the kernel compression is at most a factor of 4 since
+ * zstd almost achieves that.
+ * Use an alignment of 2MB since this might help arm64
+ */
+ if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) {
+ ulong req_size = ALIGN(image_len * 4, SZ_1M);
+
+ load = lmb_alloc(&images->lmb, req_size, SZ_2M);
+ if (!load)
+ return 1;
+ os.load = load;
+ debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n",
+ req_size, load, image_len);
+ }
+
load_buf = map_sysmem(load, 0);
image_buf = map_sysmem(os.image_start, image_len);
err = image_decomp(os.comp, load, os.image_start, os.type,
}
}
+ if (IS_ENABLED(CONFIG_CMD_BOOTI) && images->os.arch == IH_ARCH_ARM64 &&
+ images->os.os == IH_OS_LINUX) {
+ ulong relocated_addr;
+ ulong image_size;
+ int ret;
+
+ ret = booti_setup(load, &relocated_addr, &image_size, false);
+ if (ret) {
+ printf("Failed to prep arm64 kernel (err=%d)\n", ret);
+ return BOOTM_ERR_RESET;
+ }
+
+ /* Handle BOOTM_STATE_LOADOS */
+ if (relocated_addr != load) {
+ printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n",
+ load, relocated_addr,
+ relocated_addr + image_size);
+ memmove((void *)relocated_addr, load_buf, image_size);
+ }
+
+ images->ep = relocated_addr;
+ images->os.start = relocated_addr;
+ images->os.end = relocated_addr + image_size;
+ }
+
lmb_reserve(&images->lmb, images->os.load, (load_end -
images->os.load));
return 0;
return ret;
}
-/**
- * Execute selected states of the bootm command.
- *
- * Note the arguments to this state must be the first argument, Any 'bootm'
- * or sub-command arguments must have already been taken.
- *
- * Note that if states contains more than one flag it MUST contain
- * BOOTM_STATE_START, since this handles and consumes the command line args.
- *
- * Also note that aside from boot_os_fn functions and bootm_load_os no other
- * functions we store the return value of in 'ret' may use a negative return
- * value, without special handling.
- *
- * @param cmdtp Pointer to bootm command table entry
- * @param flag Command flags (CMD_FLAG_...)
- * @param argc Number of subcommand arguments (0 = no arguments)
- * @param argv Arguments
- * @param states Mask containing states to run (BOOTM_STATE_...)
- * @param images Image header information
- * @param boot_progress 1 to show boot progress, 0 to not do this
- * Return: 0 if ok, something else on error. Some errors will cause this
- * function to perform a reboot! If states contains BOOTM_STATE_OS_GO
- * then the intent is to boot an OS, so this function will not return
- * unless the image type is standalone.
- */
-int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], int states, struct bootm_headers *images,
- int boot_progress)
+int bootm_run_states(struct bootm_info *bmi, int states)
{
+ struct bootm_headers *images = bmi->images;
boot_os_fn *boot_fn;
ulong iflag = 0;
int ret = 0, need_boot_fn;
* any error.
*/
if (states & BOOTM_STATE_START)
- ret = bootm_start(cmdtp, flag, argc, argv);
+ ret = bootm_start();
if (!ret && (states & BOOTM_STATE_PRE_LOAD))
- ret = bootm_pre_load(cmdtp, flag, argc, argv);
+ ret = bootm_pre_load(bmi->addr_img);
if (!ret && (states & BOOTM_STATE_FINDOS))
- ret = bootm_find_os(cmdtp, flag, argc, argv);
+ ret = bootm_find_os(bmi->cmd_name, bmi->addr_img);
+
+ if (!ret && (states & BOOTM_STATE_FINDOTHER)) {
+ ulong img_addr;
- if (!ret && (states & BOOTM_STATE_FINDOTHER))
- ret = bootm_find_other(cmdtp, flag, argc, argv);
+ img_addr = bmi->addr_img ? hextoul(bmi->addr_img, NULL)
+ : image_load_addr;
+ ret = bootm_find_other(img_addr, bmi->conf_ramdisk,
+ bmi->conf_fdt);
+ }
if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !ret &&
(states & BOOTM_STATE_MEASURE))
return 1;
}
-
/* Call various other states that are not generally used */
if (!ret && (states & BOOTM_STATE_OS_CMDLINE))
- ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images);
+ ret = boot_fn(BOOTM_STATE_OS_CMDLINE, bmi);
if (!ret && (states & BOOTM_STATE_OS_BD_T))
- ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images);
+ ret = boot_fn(BOOTM_STATE_OS_BD_T, bmi);
if (!ret && (states & BOOTM_STATE_OS_PREP)) {
- ret = bootm_process_cmdline_env(images->os.os == IH_OS_LINUX);
+ int flags = 0;
+ /* For Linux OS do all substitutions at console processing */
+ if (images->os.os == IH_OS_LINUX)
+ flags = BOOTM_CL_ALL;
+ ret = bootm_process_cmdline_env(flags);
if (ret) {
printf("Cmdline setup failed (err=%d)\n", ret);
ret = CMD_RET_FAILURE;
goto err;
}
- ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images);
+ ret = boot_fn(BOOTM_STATE_OS_PREP, bmi);
}
#ifdef CONFIG_TRACE
if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) {
char *cmd_list = env_get("fakegocmd");
- ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO,
- images, boot_fn);
+ ret = boot_selected_os(BOOTM_STATE_OS_FAKE_GO, bmi, boot_fn);
if (!ret && cmd_list)
- ret = run_command_list(cmd_list, -1, flag);
+ ret = run_command_list(cmd_list, -1, 0);
}
#endif
/* Now run the OS! We hope this doesn't return */
if (!ret && (states & BOOTM_STATE_OS_GO))
- ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO,
- images, boot_fn);
+ ret = boot_selected_os(BOOTM_STATE_OS_GO, bmi, boot_fn);
/* Deal with any fallout */
err:
if (iflag)
enable_interrupts();
- if (ret == BOOTM_ERR_UNIMPLEMENTED)
+ if (ret == BOOTM_ERR_UNIMPLEMENTED) {
bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL);
- else if (ret == BOOTM_ERR_RESET)
- do_reset(cmdtp, flag, argc, argv);
+ } else if (ret == BOOTM_ERR_RESET) {
+ printf("Resetting the board...\n");
+ reset_cpu();
+ }
return ret;
}
+int boot_run(struct bootm_info *bmi, const char *cmd, int extra_states)
+{
+ int states;
+
+ bmi->cmd_name = cmd;
+ states = BOOTM_STATE_MEASURE | BOOTM_STATE_OS_PREP |
+ BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO;
+ if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
+ states |= BOOTM_STATE_RAMDISK;
+ states |= extra_states;
+
+ return bootm_run_states(bmi, states);
+}
+
+int bootm_run(struct bootm_info *bmi)
+{
+ return boot_run(bmi, "bootm", BOOTM_STATE_START | BOOTM_STATE_FINDOS |
+ BOOTM_STATE_PRE_LOAD | BOOTM_STATE_FINDOTHER |
+ BOOTM_STATE_LOADOS);
+}
+
+int bootz_run(struct bootm_info *bmi)
+{
+ return boot_run(bmi, "bootz", 0);
+}
+
+int booti_run(struct bootm_info *bmi)
+{
+ return boot_run(bmi, "booti", 0);
+}
+
int bootm_boot_start(ulong addr, const char *cmdline)
{
- static struct cmd_tbl cmd = {"bootm"};
char addr_str[30];
- char *argv[] = {addr_str, NULL};
+ struct bootm_info bmi;
int states;
int ret;
- /*
- * TODO(sjg@chromium.org): This uses the command-line interface, but
- * should not. To clean this up, the various bootm states need to be
- * passed an info structure instead of cmdline flags. Then this can
- * set up the required info and move through the states without needing
- * the command line.
- */
states = BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD |
BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS |
BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
printf("Failed to set cmdline\n");
return ret;
}
- ret = do_bootm_states(&cmd, 0, 1, argv, states, &images, 1);
+ bootm_init(&bmi);
+ bmi.addr_img = addr_str;
+ bmi.cmd_name = "bootm";
+ ret = bootm_run_states(&bmi, states);
return ret;
}
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-/**
- * image_get_kernel - verify legacy format kernel image
- * @img_addr: in RAM address of the legacy format image to be verified
- * @verify: data CRC verification flag
- *
- * image_get_kernel() verifies legacy image integrity and returns pointer to
- * legacy image header if image verification was completed successfully.
- *
- * returns:
- * pointer to a legacy image header if valid image was found
- * otherwise return NULL
- */
-static struct legacy_img_hdr *image_get_kernel(ulong img_addr, int verify)
-{
- struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)img_addr;
-
- if (!image_check_magic(hdr)) {
- puts("Bad Magic Number\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC);
- return NULL;
- }
- bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER);
-
- if (!image_check_hcrc(hdr)) {
- puts("Bad Header Checksum\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_HEADER);
- return NULL;
- }
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM);
- image_print_contents(hdr);
-
- if (verify) {
- puts(" Verifying Checksum ... ");
- if (!image_check_dcrc(hdr)) {
- printf("Bad Data CRC\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM);
- return NULL;
- }
- puts("OK\n");
- }
- bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH);
-
- if (!image_check_target_arch(hdr)) {
- printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr));
- bootstage_error(BOOTSTAGE_ID_CHECK_ARCH);
- return NULL;
- }
- return hdr;
-}
-#endif
-
-/**
- * boot_get_kernel - find kernel image
- * @os_data: pointer to a ulong variable, will hold os data start address
- * @os_len: pointer to a ulong variable, will hold os data length
- *
- * boot_get_kernel() tries to find a kernel image, verifies its integrity
- * and locates kernel data.
- *
- * returns:
- * pointer to image header if valid image was found, plus kernel start
- * address and length, otherwise NULL
- */
-static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], struct bootm_headers *images,
- ulong *os_data, ulong *os_len)
+void bootm_init(struct bootm_info *bmi)
{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- struct legacy_img_hdr *hdr;
-#endif
- ulong img_addr;
- const void *buf;
- const char *fit_uname_config = NULL;
- const char *fit_uname_kernel = NULL;
-#if CONFIG_IS_ENABLED(FIT)
- int os_noffset;
-#endif
-
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- const void *boot_img;
- const void *vendor_boot_img;
-#endif
- img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0],
- &fit_uname_config,
- &fit_uname_kernel);
-
- if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD))
- img_addr += image_load_offset;
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC);
-
- /* check image type, for FIT images get FIT kernel node */
- *os_data = *os_len = 0;
- buf = map_sysmem(img_addr, 0);
- switch (genimg_get_format(buf)) {
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
- printf("## Booting kernel from Legacy Image at %08lx ...\n",
- img_addr);
- hdr = image_get_kernel(img_addr, images->verify);
- if (!hdr)
- return NULL;
- bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE);
-
- /* get os_data and os_len */
- switch (image_get_type(hdr)) {
- case IH_TYPE_KERNEL:
- case IH_TYPE_KERNEL_NOLOAD:
- *os_data = image_get_data(hdr);
- *os_len = image_get_data_size(hdr);
- break;
- case IH_TYPE_MULTI:
- image_multi_getimg(hdr, 0, os_data, os_len);
- break;
- case IH_TYPE_STANDALONE:
- *os_data = image_get_data(hdr);
- *os_len = image_get_data_size(hdr);
- break;
- default:
- printf("Wrong Image Type for %s command\n",
- cmdtp->name);
- bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
- return NULL;
- }
-
- /*
- * copy image header to allow for image overwrites during
- * kernel decompression.
- */
- memmove(&images->legacy_hdr_os_copy, hdr,
- sizeof(struct legacy_img_hdr));
-
- /* save pointer to image header */
- images->legacy_hdr_os = hdr;
-
- images->legacy_hdr_valid = 1;
- bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
- break;
-#endif
-#if CONFIG_IS_ENABLED(FIT)
- case IMAGE_FORMAT_FIT:
- os_noffset = fit_image_load(images, img_addr,
- &fit_uname_kernel, &fit_uname_config,
- IH_ARCH_DEFAULT, IH_TYPE_KERNEL,
- BOOTSTAGE_ID_FIT_KERNEL_START,
- FIT_LOAD_IGNORED, os_data, os_len);
- if (os_noffset < 0)
- return NULL;
-
- images->fit_hdr_os = map_sysmem(img_addr, 0);
- images->fit_uname_os = fit_uname_kernel;
- images->fit_uname_cfg = fit_uname_config;
- images->fit_noffset_os = os_noffset;
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- boot_img = buf;
- vendor_boot_img = NULL;
- if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
- boot_img = map_sysmem(get_abootimg_addr(), 0);
- vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
- }
- printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
- if (android_image_get_kernel(boot_img, vendor_boot_img, images->verify,
- os_data, os_len))
- return NULL;
- if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
- unmap_sysmem(vendor_boot_img);
- unmap_sysmem(boot_img);
- }
- break;
-#endif
- default:
- printf("Wrong Image Format for %s command\n", cmdtp->name);
- bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO);
- return NULL;
- }
-
- debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n",
- *os_data, *os_len, *os_len);
-
- return buf;
+ memset(bmi, '\0', sizeof(struct bootm_info));
+ bmi->boot_progress = true;
+ if (IS_ENABLED(CONFIG_CMD_BOOTM))
+ bmi->images = &images;
}
/**
DECLARE_GLOBAL_DATA_PTR;
-static int do_bootm_standalone(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_standalone(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int (*appl)(int, char *const[]);
if (!env_get_autostart()) {
return 0;
}
appl = (int (*)(int, char * const []))images->ep;
- appl(argc, argv);
+ appl(bmi->argc, bmi->argv);
return 0;
}
}
#ifdef CONFIG_BOOTM_NETBSD
-static int do_bootm_netbsd(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_netbsd(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*loader)(struct bd_info *bd, struct legacy_img_hdr *hdr,
char *console, char *cmdline);
struct legacy_img_hdr *os_hdr, *hdr;
os_hdr = hdr;
}
- if (argc > 0) {
+ if (bmi->argc > 0) {
ulong len;
int i;
- for (i = 0, len = 0; i < argc; i += 1)
- len += strlen(argv[i]) + 1;
+ for (i = 0, len = 0; i < bmi->argc; i += 1)
+ len += strlen(bmi->argv[i]) + 1;
cmdline = malloc(len);
- copy_args(cmdline, argc, argv, ' ');
+ copy_args(cmdline, bmi->argc, bmi->argv, ' ');
} else {
cmdline = env_get("bootargs");
if (cmdline == NULL)
#endif /* CONFIG_BOOTM_NETBSD*/
#ifdef CONFIG_BOOTM_RTEMS
-static int do_bootm_rtems(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_rtems(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*entry_point)(struct bd_info *);
if (flag != BOOTM_STATE_OS_GO)
#endif /* CONFIG_BOOTM_RTEMS */
#if defined(CONFIG_BOOTM_OSE)
-static int do_bootm_ose(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_ose(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*entry_point)(void);
if (flag != BOOTM_STATE_OS_GO)
#endif /* CONFIG_BOOTM_OSE */
#if defined(CONFIG_BOOTM_PLAN9)
-static int do_bootm_plan9(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_plan9(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*entry_point)(void);
char *s;
if (s != NULL) {
char *confaddr = (char *)hextoul(s, NULL);
- if (argc > 0) {
- copy_args(confaddr, argc, argv, '\n');
+ if (bmi->argc) {
+ copy_args(confaddr, bmi->argc, bmi->argv, '\n');
} else {
s = env_get("bootargs");
if (s != NULL)
puts("## vxWorks terminated\n");
}
-static int do_bootm_vxworks_legacy(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_vxworks_legacy(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
+
if (flag != BOOTM_STATE_OS_GO)
return 0;
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("VxWorks");
- return 1;
- }
-#endif
-
do_bootvx_fdt(images);
return 1;
}
-int do_bootm_vxworks(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+int do_bootm_vxworks(int flag, struct bootm_info *bmi)
{
char *bootargs;
int pos;
if (std_dtb) {
if (flag & BOOTM_STATE_OS_PREP)
printf(" Using standard DTB\n");
- return do_bootm_linux(flag, argc, argv, images);
+ return do_bootm_linux(flag, bmi);
} else {
if (flag & BOOTM_STATE_OS_PREP)
printf(" !!! WARNING !!! Using legacy DTB\n");
- return do_bootm_vxworks_legacy(flag, argc, argv, images);
+ return do_bootm_vxworks_legacy(flag, bmi);
}
}
#endif
#if defined(CONFIG_CMD_ELF)
-static int do_bootm_qnxelf(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_qnxelf(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
char *local_args[2];
char str[16];
int dcache;
#endif
sprintf(str, "%lx", images->ep); /* write entry-point into string */
- local_args[0] = argv[0];
+ local_args[0] = bmi->argv[0];
local_args[1] = str; /* and provide it via the arguments */
/*
#endif
#ifdef CONFIG_INTEGRITY
-static int do_bootm_integrity(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_integrity(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*entry_point)(void);
if (flag != BOOTM_STATE_OS_GO)
#endif
#ifdef CONFIG_BOOTM_OPENRTOS
-static int do_bootm_openrtos(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_openrtos(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
void (*entry_point)(void);
if (flag != BOOTM_STATE_OS_GO)
#endif
#ifdef CONFIG_BOOTM_OPTEE
-static int do_bootm_tee(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_tee(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int ret;
- /* Verify OS type */
- if (images->os.os != IH_OS_TEE) {
- return 1;
- };
-
/* Validate OPTEE header */
ret = optee_verify_bootm_image(images->os.image_start,
images->os.load,
if (ret)
return ret;
- /* Locate FDT etc */
- ret = bootm_find_images(flag, argc, argv, 0, 0);
- if (ret)
- return ret;
-
/* From here we can run the regular linux boot path */
- return do_bootm_linux(flag, argc, argv, images);
+ return do_bootm_linux(flag, bmi);
}
#endif
#ifdef CONFIG_BOOTM_EFI
-static int do_bootm_efi(int flag, int argc, char *const argv[],
- struct bootm_headers *images)
+static int do_bootm_efi(int flag, struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int ret;
- efi_status_t efi_ret;
void *image_buf;
if (flag != BOOTM_STATE_OS_GO)
return 0;
- /* Locate FDT, if provided */
- ret = bootm_find_images(flag, argc, argv, 0, 0);
- if (ret)
- return ret;
-
- /* Initialize EFI drivers */
- efi_ret = efi_init_obj_list();
- if (efi_ret != EFI_SUCCESS) {
- printf("## Failed to initialize UEFI sub-system: r = %lu\n",
- efi_ret & ~EFI_ERROR_MASK);
- return 1;
- }
+ /* We expect to return */
+ images->os.type = IH_TYPE_STANDALONE;
- /* Install device tree */
- efi_ret = efi_install_fdt(images->ft_len
- ? images->ft_addr : EFI_FDT_USE_INTERNAL);
- if (efi_ret != EFI_SUCCESS) {
- printf("## Failed to install device tree: r = %lu\n",
- efi_ret & ~EFI_ERROR_MASK);
- return 1;
- }
+ image_buf = map_sysmem(images->ep, images->os.image_len);
/* Run EFI image */
printf("## Transferring control to EFI (at address %08lx) ...\n",
images->ep);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
- /* We expect to return */
- images->os.type = IH_TYPE_STANDALONE;
-
- image_buf = map_sysmem(images->ep, images->os.image_len);
+ ret = efi_binary_run(image_buf, images->os.image_len,
+ images->ft_len
+ ? images->ft_addr : EFI_FDT_USE_INTERNAL);
- efi_ret = efi_run_image(image_buf, images->os.image_len);
- if (efi_ret != EFI_SUCCESS)
- return 1;
- return 0;
+ return ret;
}
#endif
/* please define board specific board_preboot_os() */
}
-int boot_selected_os(int argc, char *const argv[], int state,
- struct bootm_headers *images, boot_os_fn *boot_fn)
+int boot_selected_os(int state, struct bootm_info *bmi, boot_os_fn *boot_fn)
{
arch_preboot_os();
board_preboot_os();
- boot_fn(state, argc, argv, images);
+
+ boot_fn(state, bmi);
/* Stand-alone may return when 'autostart' is 'no' */
- if (images->os.type == IH_TYPE_STANDALONE ||
+ if (bmi->images->os.type == IH_TYPE_STANDALONE ||
IS_ENABLED(CONFIG_SANDBOX) ||
state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
return 0;
if (ret)
return log_msg_ret("read", ret);
bflow->buf = map_sysmem(addr, bflow->size);
- bflow->flags |= BOOTFLOWF_STATIC_BUF;
set_efi_bootdev(desc, bflow);
*/
} else {
log_debug("No device tree available\n");
+ bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
return 0;
char file_addr[17], fname[256];
char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
struct cmd_tbl cmdtp = {}; /* dummy */
- const char *addr_str, *fdt_addr_str;
+ const char *addr_str, *fdt_addr_str, *bootfile_name;
int ret, arch, size;
ulong addr, fdt_addr;
char str[36];
ret = env_set("bootp_vci", str);
if (ret)
return log_msg_ret("vcs", ret);
- ret = env_set_ulong("bootp_arch", arch);
+ ret = env_set_hex("bootp_arch", arch);
if (ret)
return log_msg_ret("ars", ret);
return log_msg_ret("sz", -EINVAL);
bflow->size = size;
+ /* bootfile should be setup by dhcp*/
+ bootfile_name = env_get("bootfile");
+ if (!bootfile_name)
+ return log_msg_ret("bootfile_name", ret);
+ bflow->fname = strdup(bootfile_name);
+
/* do the hideous EFI hack */
efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0),
bflow->size);
bflow->fdt_addr = fdt_addr;
} else {
log_debug("No device tree available\n");
+ bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
bflow->state = BOOTFLOWST_READY;
{
int ret;
+ /*
+ * bootmeth_efi doesn't allocate any buffer neither for blk nor net device
+ * set flag to avoid freeing static buffer.
+ */
+ bflow->flags |= BOOTFLOWF_STATIC_BUF;
+
if (bootmeth_uses_network(bflow)) {
/* we only support reading from one device, so ignore 'dev' */
ret = distro_efi_read_bootflow_net(bflow);
static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
{
ulong kernel, fdt;
- char cmd[50];
int ret;
kernel = env_get_hex("kernel_addr_r", 0);
return log_msg_ret("read", ret);
/*
- * use the provided device tree if available, else fall back to
- * the control FDT
+ * use the provided device tree if not using the built-in fdt
*/
- if (bflow->fdt_fname)
+ if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT)
fdt = bflow->fdt_addr;
- else
- fdt = (ulong)map_to_sysmem(gd->fdt_blob);
+
} else {
/*
* This doesn't actually work for network devices:
fdt = env_get_hex("fdt_addr_r", 0);
}
- /*
- * At some point we can add a real interface to bootefi so we can call
- * this directly. For now, go through the CLI, like distro boot.
- */
- snprintf(cmd, sizeof(cmd), "bootefi %lx %lx", kernel, fdt);
- if (run_command(cmd, 0))
- return log_msg_ret("run", -EINVAL);
+ if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) {
+ log_debug("Booting with built-in fdt\n");
+ if (efi_binary_run(map_sysmem(kernel, 0), bflow->size,
+ EFI_FDT_USE_INTERNAL))
+ return log_msg_ret("run", -EINVAL);
+ } else {
+ log_debug("Booting with external fdt\n");
+ if (efi_binary_run(map_sysmem(kernel, 0), bflow->size,
+ map_sysmem(fdt, 0)))
+ return log_msg_ret("run", -EINVAL);
+ }
return 0;
}
#include <dm.h>
#include <efi_loader.h>
#include <efi_variable.h>
+#include <malloc.h>
/**
* struct efi_mgr_priv - private info for the efi-mgr driver
bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid,
&size);
if (bootorder) {
+ free(bootorder);
bflow->state = BOOTFLOWST_READY;
return 0;
}
int ret;
/* Booting is handled by the 'bootefi bootmgr' command */
- ret = run_command("bootefi bootmgr", 0);
+ ret = efi_bootmgr_run(EFI_FDT_USE_INTERNAL);
return 0;
}
return node;
}
-/* Resize the fdt to its actual size + a bit of padding */
int fdt_shrink_to_minimum(void *blob, uint extrasize)
{
int i;
}
}
-/**
- * genimg_get_kernel_addr_fit - get the real kernel address and return 2
- * FIT strings
- * @img_addr: a string might contain real image address
- * @fit_uname_config: double pointer to a char, will hold pointer to a
- * configuration unit name
- * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
- * name
- *
- * genimg_get_kernel_addr_fit get the real kernel start address from a string
- * which is normally the first argv of bootm/bootz
- *
- * returns:
- * kernel start address
- */
-ulong genimg_get_kernel_addr_fit(char * const img_addr,
+ulong genimg_get_kernel_addr_fit(const char *const img_addr,
const char **fit_uname_config,
const char **fit_uname_kernel)
{
return 0;
}
-/**
- * boot_get_ramdisk - main ramdisk handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @images: pointer to the bootm images structure
- * @arch: expected ramdisk architecture
- * @rd_start: pointer to a ulong variable, will hold ramdisk start address
- * @rd_end: pointer to a ulong variable, will hold ramdisk end
- *
- * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
- * Currently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if ramdisk image was found and valid, or skiped
- * rd_start and rd_end are set to ramdisk start/end addresses if
- * ramdisk image is found and valid
- *
- * 1, if ramdisk image is found but corrupted, or invalid
- * rd_start and rd_end are set to 0 if no ramdisk exists
- */
-int boot_get_ramdisk(int argc, char *const argv[], struct bootm_headers *images,
- u8 arch, ulong *rd_start, ulong *rd_end)
+int boot_get_ramdisk(char const *select, struct bootm_headers *images,
+ uint arch, ulong *rd_start, ulong *rd_end)
{
ulong rd_data, rd_len;
- const char *select = NULL;
*rd_start = 0;
*rd_end = 0;
- if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
- char *buf;
-
- /* Look for an Android boot image */
- buf = map_sysmem(images->os.start, 0);
- if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
- select = (argc == 0) ? env_get("loadaddr") : argv[0];
- }
-
- if (argc >= 2)
- select = argv[1];
-
/*
* Look for a '-' which indicates to ignore the
* ramdisk argument
return boot_get_setup_fit(images, arch, setup_start, setup_len);
}
-int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images,
- u8 arch, const ulong *ld_start, ulong * const ld_len)
+int boot_get_fpga(struct bootm_headers *images)
{
ulong tmp_img_addr, img_data, img_len;
void *buf;
tmp_img_addr,
(const char **)&uname,
&images->fit_uname_cfg,
- arch,
+ IH_ARCH_DEFAULT,
IH_TYPE_FPGA,
BOOTSTAGE_ID_FPGA_INIT,
FIT_LOAD_OPTIONAL_NON_ZERO,
fit_loadable_handler->handler(img_data, img_len);
}
-int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images,
- u8 arch, const ulong *ld_start, ulong * const ld_len)
+int boot_get_loadable(struct bootm_headers *images)
{
/*
* These variables are used to hold the current image location
fit_img_result = fit_image_load(images, tmp_img_addr,
&uname,
&images->fit_uname_cfg,
- arch, IH_TYPE_LOADABLE,
+ IH_ARCH_DEFAULT,
+ IH_TYPE_LOADABLE,
BOOTSTAGE_ID_FIT_LOADABLE_START,
FIT_LOAD_OPTIONAL_NON_ZERO,
&img_data, &img_len);
}
if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) {
- ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
+ ret = image_setup_libfdt(images, *of_flat_tree, lmb);
if (ret)
return ret;
}
*/
#include <common.h>
+#include <command.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <env.h>
#include <dm/ofnode.h>
#include <tee/optee.h>
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD 0x80
-
DECLARE_GLOBAL_DATA_PTR;
static void fdt_error(const char *msg)
return 0;
}
-/**
- * boot_get_fdt - main fdt handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @arch: architecture (IH_ARCH_...)
- * @images: pointer to the bootm images structure
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
- *
- * boot_get_fdt() is responsible for finding a valid flat device tree image.
- * Currently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if fdt image was found and valid, or skipped
- * of_flat_tree and of_size are set to fdt start address and length if
- * fdt image is found and valid
- *
- * 1, if fdt image is found but corrupted
- * of_flat_tree and of_size are set to 0 if no fdt exists
- */
-int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
- struct bootm_headers *images, char **of_flat_tree, ulong *of_size)
+int boot_get_fdt(void *buf, const char *select, uint arch,
+ struct bootm_headers *images, char **of_flat_tree,
+ ulong *of_size)
{
- ulong img_addr;
- ulong fdt_addr;
- char *fdt_blob = NULL;
- void *buf;
- const char *select = NULL;
+ char *fdt_blob = NULL;
+ ulong fdt_addr;
*of_flat_tree = NULL;
*of_size = 0;
- img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL);
- buf = map_sysmem(img_addr, 0);
-
- if (argc > 2)
- select = argv[2];
if (select || genimg_has_config(images)) {
int ret;
}
int image_setup_libfdt(struct bootm_headers *images, void *blob,
- int of_size, struct lmb *lmb)
+ struct lmb *lmb)
{
ulong *initrd_start = &images->initrd_start;
ulong *initrd_end = &images->initrd_end;
- int ret = -EPERM;
- int fdt_ret;
+ int ret, fdt_ret, of_size;
+
+ if (IS_ENABLED(CONFIG_OF_ENV_SETUP)) {
+ const char *fdt_fixup;
+
+ fdt_fixup = env_get("fdt_fixup");
+ if (fdt_fixup) {
+ set_working_fdt_addr(map_to_sysmem(blob));
+ ret = run_command_list(fdt_fixup, -1, 0);
+ if (ret)
+ printf("WARNING: fdt_fixup command returned %d\n",
+ ret);
+ }
+ }
+
+ ret = -EPERM;
if (fdt_root(blob) < 0) {
printf("ERROR: root node setup failed\n");
goto err;
}
}
+
+ if (fdt_initrd(blob, *initrd_start, *initrd_end))
+ goto err;
+
+ if (!ft_verify_fdt(blob))
+ goto err;
+
+ /* after here we are using a livetree */
if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) {
struct event_ft_fixup fixup;
/* Delete the old LMB reservation */
if (lmb)
- lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
- (phys_size_t)fdt_totalsize(blob));
+ lmb_free(lmb, map_to_sysmem(blob), fdt_totalsize(blob));
ret = fdt_shrink_to_minimum(blob, 0);
if (ret < 0)
goto err;
of_size = ret;
- if (*initrd_start && *initrd_end) {
- of_size += FDT_RAMDISK_OVERHEAD;
- fdt_set_totalsize(blob, of_size);
- }
/* Create a new LMB reservation */
if (lmb)
- lmb_reserve(lmb, (ulong)blob, of_size);
-
- fdt_initrd(blob, *initrd_start, *initrd_end);
- if (!ft_verify_fdt(blob))
- goto err;
+ lmb_reserve(lmb, map_to_sysmem(blob), of_size);
#if defined(CONFIG_ARCH_KEYSTONE)
if (IS_ENABLED(CONFIG_OF_BOARD_SETUP))
#include <time.h>
#include <linux/libfdt.h>
#include <u-boot/crc.h>
+#include <linux/kconfig.h>
#else
#include <linux/compiler.h>
#include <linux/sizes.h>
#include <bootm.h>
#include <image.h>
#include <bootstage.h>
-#include <linux/kconfig.h>
#include <u-boot/crc.h>
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
#else /* USE_HOSTCC */
#include "mkimage.h"
+#include <linux/kconfig.h>
#include <u-boot/md5.h>
#include <time.h>
#include <relocate.h>
#include <linux/lzo.h>
#include <linux/zstd.h>
-#include <linux/kconfig.h>
#include <lzma/LzmaTypes.h>
#include <lzma/LzmaDec.h>
#include <lzma/LzmaTools.h>
* @type: OS type (IH_OS_...)
* @comp_type: Compression type being used (IH_COMP_...)
* @is_xip: true if the load address matches the image start
+ * @load: Load address for printing
*/
-static void print_decomp_msg(int comp_type, int type, bool is_xip)
+static void print_decomp_msg(int comp_type, int type, bool is_xip,
+ ulong load)
{
const char *name = genimg_get_type_name(type);
+ /* Shows "Loading Kernel Image" for example */
if (comp_type == IH_COMP_NONE)
- printf(" %s %s\n", is_xip ? "XIP" : "Loading", name);
+ printf(" %s %s", is_xip ? "XIP" : "Loading", name);
else
- printf(" Uncompressing %s\n", name);
+ printf(" Uncompressing %s", name);
+
+ printf(" to %lx\n", load);
}
int image_decomp_type(const unsigned char *buf, ulong len)
int ret = -ENOSYS;
*load_end = load;
- print_decomp_msg(comp, type, load == image_start);
+ print_decomp_msg(comp, type, load == image_start, load);
/*
* Load the image to the right place, decompressing if needed. After
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <bootflow.h>
+#include <bootstd.h>
+#include <command.h>
+#include <dm.h>
+
+/*
+ * show_bootmeths() - List available bootmeths
+ *
+ * We could refactor this to use do_bootmeth_list() if more detail (or ordering)
+ * are needed
+ */
+static void show_bootmeths(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ printf("Bootmeths: ");
+ uclass_id_foreach_dev(UCLASS_BOOTMETH, dev, uc)
+ printf(" %s", dev->name);
+ printf("\n");
+}
+
+int bootstd_prog_boot(void)
+{
+ struct bootflow_iter iter;
+ struct bootflow bflow;
+ int ret, flags, i;
+
+ printf("Programmatic boot starting\n");
+ show_bootmeths();
+ flags = BOOTFLOWIF_HUNT | BOOTFLOWIF_SHOW | BOOTFLOWIF_SKIP_GLOBAL;
+
+ bootstd_clear_glob();
+ for (i = 0, ret = bootflow_scan_first(NULL, NULL, &iter, flags, &bflow);
+ i < 1000 && ret != -ENODEV;
+ i++, ret = bootflow_scan_next(&iter, &bflow)) {
+ if (!bflow.err)
+ bootflow_run_boot(&iter, &bflow);
+ bootflow_free(&bflow);
+ }
+
+ return -EFAULT;
+}
label->name);
goto cleanup;
}
+
+ if (label->fdtdir) {
+ printf("Skipping fdtdir %s for failure retrieving dts\n",
+ label->fdtdir);
+ }
}
if (label->kaslrseed)
-menu "Command line interface"
-
-config CMDLINE
- bool "Support U-Boot commands"
+menuconfig CMDLINE
+ bool "Command line interface"
default y
help
Enable U-Boot's command-line functions. This provides a means
Depending on the number of commands enabled, this can add
substantially to the size of U-Boot.
+if CMDLINE
+
config HUSH_PARSER
bool "Use hush shell"
- depends on CMDLINE
help
This option enables the "hush" shell (from Busybox) as command line
interpreter, thus enabling powerful command line syntax like
If disabled, you get the old, much simpler behaviour with a somewhat
smaller memory footprint.
+menu "Hush flavor to use"
+depends on HUSH_PARSER
+
+config HUSH_OLD_PARSER
+ bool "Use hush old parser"
+ help
+ This option enables the old flavor of hush based on hush Busybox from
+ 2005.
+
+config HUSH_MODERN_PARSER
+ bool "Use hush modern parser"
+ default y
+ help
+ This option enables the new flavor of hush based on hush upstream
+ Busybox.
+
+config HUSH_SELECTABLE
+ bool
+ default y if HUSH_OLD_PARSER && HUSH_MODERN_PARSER
+endmenu
+
config CMDLINE_EDITING
bool "Enable command line editing"
- depends on CMDLINE
default y
help
Enable editing and History functions for interactive command line
config AUTO_COMPLETE
bool "Enable auto complete using TAB"
- depends on CMDLINE
default y
help
Enable auto completion of commands using TAB.
config SYS_LONGHELP
bool "Enable long help messages"
- depends on CMDLINE
- default y if CMDLINE
+ default y
help
Defined when you want long help messages included
Do not set this option when short of memory.
int "Maximum number arguments accepted by commands"
default 16
-config SYS_CBSIZE
- int "Console input buffer size"
- default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
- RCAR_GEN3 || TARGET_SOCFPGA_SOC64
- default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
- FSL_LSCH3 || X86
- default 256 if M68K || PPC
- default 1024
-
-config SYS_PBSIZE
- int "Buffer size for console output"
- default 1024 if ARCH_SUNXI
- default 1044
-
config SYS_XTRACE
bool "Command execution tracer"
- depends on CMDLINE
- default y if CMDLINE
+ default y
help
This option enables the possiblity to print all commands before
executing them and after all variables are evaluated (similar
config BOOTM_EFI
bool "Support booting UEFI FIT images"
- depends on CMD_BOOTEFI && CMD_BOOTM && FIT
+ depends on BOOTEFI_BOOTMGR && CMD_BOOTM && FIT
default y
help
Support booting UEFI FIT images via the bootm command.
config CMD_BOOTI
bool "booti"
- depends on ARM64 || RISCV
+ depends on ARM64 || RISCV || SANDBOX
default y
help
Boot an AArch64 Linux Kernel image from memory.
help
Support booting VxWorks images via the bootm command.
-config SYS_BOOTM_LEN
- hex "Maximum size of a decompresed OS image"
- depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
- LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
- default 0x4000000 if PPC || ARM64
- default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
- default 0x800000
- help
- This is the maximum size of the buffer that is used to decompress the OS
- image in to, if passing a compressed image to bootm/booti/bootz.
-
config CMD_BOOTEFI
bool "bootefi"
depends on EFI_LOADER
help
Boot an EFI image from memory.
+if CMD_BOOTEFI
+config CMD_BOOTEFI_BINARY
+ bool "Allow booting an EFI binary directly"
+ depends on BOOTEFI_BOOTMGR
+ default y
+ help
+ Select this option to enable direct execution of binary at 'bootefi'.
+ This subcommand will allow you to load the UEFI binary using
+ other U-Boot commands or external methods and then run it.
+
+config CMD_BOOTEFI_BOOTMGR
+ bool "UEFI Boot Manager command"
+ depends on BOOTEFI_BOOTMGR
+ default y
+ help
+ Select this option to enable the 'bootmgr' subcommand of 'bootefi'.
+ This subcommand will allow you to select the UEFI binary to be booted
+ via UEFI variables Boot####, BootOrder, and BootNext.
+
config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
- depends on CMD_BOOTEFI && !CPU_V7M
default y
help
This compiles a standard EFI hello world application with U-Boot so
up EFI support on a new architecture.
source lib/efi_selftest/Kconfig
+endif
config CMD_BOOTMENU
bool "bootmenu"
help
Extract a part of a multi-image.
+config SYS_XIMG_LEN
+ hex "imxtract max gunzip size"
+ default 0x800000
+ depends on CMD_XIMG && GZIP
+ help
+ This provides the size of the commad-line argument area
+ used by imxtract for extracting pieces of FIT image.
+ It should be large enough to fit uncompressed size of
+ FIT piece we are extracting.
+
config CMD_SPL
bool "spl export - Export boot information for Falcon boot"
depends on SPL
config CMD_BCB
bool "bcb"
- depends on MMC
depends on PARTITIONS
help
Read/modify/write the fields of Bootloader Control Block, usually
config CMD_BIND
bool "bind/unbind - Bind or unbind a device to/from a driver"
depends on DM
- default y if USB_ETHER
+ imply CMD_DM
help
Bind or unbind a device to/from a driver from the command line.
This is useful in situations where a device may be handled by several
Enable the 'gpt' command to ready and write GPT style partition
tables.
-config RANDOM_UUID
- bool "GPT Random UUID generation"
- select LIB_UUID
- help
- Enable the generation of partitions with random UUIDs if none
- are provided.
-
config CMD_GPT_RENAME
bool "GPT partition renaming commands"
depends on CMD_GPT
Turndra tsi148 device. See the command help for full details.
config CMD_UFS
- bool "Enable UFS - Universal Flash Subsystem commands"
+ bool "ufs - Universal Flash Storage commands"
depends on UFS
help
"This provides commands to initialise and configure universal flash
menuconfig CMD_NET
bool "Network commands"
default y
- imply NETDEVICES
if CMD_NET
config CMD_EFICONFIG
bool "eficonfig - provide menu-driven uefi variables maintenance interface"
default y if !HAS_BOARD_SIZE_LIMIT
- depends on CMD_BOOTEFI_BOOTMGR
+ depends on BOOTEFI_BOOTMGR
select MENU
help
Enable the 'eficonfig' command which provides the menu-driven UEFI
config CMD_QFW
bool "qfw"
select QFW
+ default y if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT || \
+ TARGET_QEMU_X86 || TARGET_QEMU_X86_64
help
This provides access to the QEMU firmware interface. The main
feature is to allow easy loading of files passed to qemu-system
config CMD_SELECT_FONT
bool "select font size"
depends on VIDEO
+ default y if CONSOLE_TRUETYPE
help
Enabling this will provide 'font' command.
Allows font selection at runtime.
a number of sub-commands for performing EC tasks such as
updating its flash, accessing a small saved context area
and talking to the I2C bus behind the EC (if there is one).
+
+config CMD_SCMI
+ bool "Enable scmi command"
+ depends on SCMI_FIRMWARE
+ default n
+ help
+ This command provides user interfaces to several SCMI (System
+ Control and Management Interface) protocols available on Arm
+ platforms to manage system resources.
endmenu
menu "Filesystem commands"
default y
help
Enable useful commands for the Meson Soc family developed by Amlogic Inc.
-endmenu
+
+endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
obj-$(CONFIG_CMD_OSD) += osd.o
obj-$(CONFIG_CMD_NVME) += nvme.o
obj-$(CONFIG_SANDBOX) += sb.o
obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_CMD_SCMI) += scmi.o
obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o
obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
obj-$(CONFIG_CMD_SEAMA) += seama.o
# Foundries.IO SCP03
obj-$(CONFIG_CMD_SCP03) += scp03.o
+obj-$(CONFIG_HUSH_SELECTABLE) += cli.o
+
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/
obj-$(CONFIG_SANDBOX) += sandbox/
obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
-# core command
-obj-y += nvedit.o
-
obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
#include <common.h>
#include <command.h>
#include <display_options.h>
+#include <log.h>
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/acpi_table.h>
/**
* dump_hdr() - Dump an ACPI header
*
- * If the header is for FACS then it shows the revision information as well
+ * Except for the Firmware ACPI Control Structure (FACS)
+ * additionally show the revision information.
*
* @hdr: ACPI header to dump
*/
{
bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN);
- printf("%.*s %08lx %5x", ACPI_NAME_LEN, hdr->signature,
+ printf("%.*s %16lx %5x", ACPI_NAME_LEN, hdr->signature,
(ulong)map_to_sysmem(hdr), hdr->length);
if (has_hdr) {
printf(" v%02d %.6s %.8s %x %.4s %x\n", hdr->revision,
hdr = acpi_find_table(sig);
if (!hdr)
return -ENOENT;
- printf("%.*s @ %08lx\n", ACPI_NAME_LEN, hdr->signature,
- (ulong)map_to_sysmem(hdr));
+ printf("%.*s @ %16lx\n", ACPI_NAME_LEN, hdr->signature,
+ (ulong)nomap_to_sysmem(hdr));
print_buffer(0, hdr, 1, hdr->length, 0);
return 0;
static void list_fadt(struct acpi_fadt *fadt)
{
- if (fadt->dsdt)
- dump_hdr(map_sysmem(fadt->dsdt, 0));
- if (fadt->firmware_ctrl)
- dump_hdr(map_sysmem(fadt->firmware_ctrl, 0));
+ if (fadt->header.revision >= 3 && fadt->x_dsdt)
+ dump_hdr(nomap_sysmem(fadt->x_dsdt, 0));
+ else if (fadt->dsdt)
+ dump_hdr(nomap_sysmem(fadt->dsdt, 0));
+ if (!IS_ENABLED(CONFIG_X86) &&
+ !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI))
+ log_err("FADT not ACPI-hardware-reduced-compliant\n");
+ if (fadt->header.revision >= 3 && fadt->x_firmware_ctrl)
+ dump_hdr(nomap_sysmem(fadt->x_firmware_ctrl, 0));
+ else if (fadt->firmware_ctrl)
+ dump_hdr(nomap_sysmem(fadt->firmware_ctrl, 0));
}
-static int list_rsdt(struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt)
+static void list_rsdt(struct acpi_rsdp *rsdp)
{
int len, i, count;
+ struct acpi_rsdt *rsdt;
+ struct acpi_xsdt *xsdt;
- dump_hdr(&rsdt->header);
- if (xsdt)
+ if (rsdp->rsdt_address) {
+ rsdt = nomap_sysmem(rsdp->rsdt_address, 0);
+ dump_hdr(&rsdt->header);
+ }
+ if (rsdp->xsdt_address) {
+ xsdt = nomap_sysmem(rsdp->xsdt_address, 0);
dump_hdr(&xsdt->header);
- len = rsdt->header.length - sizeof(rsdt->header);
- count = len / sizeof(u32);
+ len = xsdt->header.length - sizeof(xsdt->header);
+ count = len / sizeof(u64);
+ } else if (rsdp->rsdt_address) {
+ len = rsdt->header.length - sizeof(rsdt->header);
+ count = len / sizeof(u32);
+ } else {
+ return;
+ }
+
for (i = 0; i < count; i++) {
struct acpi_table_header *hdr;
+ u64 entry;
- if (!rsdt->entry[i])
+ if (rsdp->xsdt_address)
+ entry = xsdt->entry[i];
+ else
+ entry = rsdt->entry[i];
+ if (!entry)
break;
- hdr = map_sysmem(rsdt->entry[i], 0);
+ hdr = nomap_sysmem(entry, 0);
dump_hdr(hdr);
if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN))
list_fadt((struct acpi_fadt *)hdr);
- if (xsdt) {
- if (xsdt->entry[i] != rsdt->entry[i]) {
- printf(" (xsdt mismatch %llx)\n",
- xsdt->entry[i]);
- }
- }
}
-
- return 0;
}
-static int list_rsdp(struct acpi_rsdp *rsdp)
+static void list_rsdp(struct acpi_rsdp *rsdp)
{
- struct acpi_rsdt *rsdt;
- struct acpi_xsdt *xsdt;
-
- printf("RSDP %08lx %5x v%02d %.6s\n", (ulong)map_to_sysmem(rsdp),
+ printf("RSDP %16lx %5x v%02d %.6s\n", (ulong)map_to_sysmem(rsdp),
rsdp->length, rsdp->revision, rsdp->oem_id);
- rsdt = map_sysmem(rsdp->rsdt_address, 0);
- xsdt = map_sysmem(rsdp->xsdt_address, 0);
- list_rsdt(rsdt, xsdt);
-
- return 0;
+ list_rsdt(rsdp);
}
static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
printf("No ACPI tables present\n");
return 0;
}
- printf("Name Base Size Detail\n");
- printf("---- -------- ----- ------\n");
+ printf("Name Base Size Detail\n"
+ "---- ---------------- ----- ----------------------------\n");
list_rsdp(rsdp);
return 0;
char sig[ACPI_NAME_LEN];
int ret;
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
name = argv[1];
if (strlen(name) != ACPI_NAME_LEN) {
printf("Table name '%s' must be four characters\n", name);
{
struct afs_image *afi = NULL;
int i;
+ loff_t len_read = 0;
parse_flash();
for (i = 0; i < num_afs_images; i++) {
for (i = 0; i < afi->region_count; i++) {
ulong from, to;
+ u32 size;
from = afi->flash_mem_start + afi->regions[i].offset;
if (address) {
return CMD_RET_FAILURE;
}
- memcpy((void *)to, (void *)from, afi->regions[i].size);
+ size = afi->regions[i].size;
+ memcpy((void *)to, (void *)from, size);
printf("loaded region %d from %08lX to %08lX, %08X bytes\n",
i,
from,
to,
- afi->regions[i].size);
+ size);
+
+ len_read += size;
}
+
+ env_set_hex("filesize", len_read);
+
return CMD_RET_SUCCESS;
}
BCB_CMD_STORE,
};
-static int bcb_dev = -1;
-static int bcb_part = -1;
+static const char * const fields[] = {
+ "command",
+ "status",
+ "recovery",
+ "stage"
+};
+
static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } };
+static struct disk_partition partition_data;
+
+static struct blk_desc *block;
+static struct disk_partition *partition = &partition_data;
static int bcb_cmd_get(char *cmd)
{
switch (cmd) {
case BCB_CMD_LOAD:
+ if (argc != 3 && argc != 4)
+ goto err;
+ break;
case BCB_CMD_FIELD_SET:
if (argc != 3)
goto err;
return -1;
}
- if (cmd != BCB_CMD_LOAD && (bcb_dev < 0 || bcb_part < 0)) {
+ if (cmd != BCB_CMD_LOAD && !block) {
printf("Error: Please, load BCB first!\n");
return -1;
}
return -1;
}
-static int bcb_field_get(char *name, char **fieldp, int *sizep)
+static int bcb_field_get(const char *name, char **fieldp, int *sizep)
{
if (!strcmp(name, "command")) {
*fieldp = bcb.command;
return 0;
}
-static int __bcb_load(int devnum, const char *partp)
+static void __bcb_reset(void)
+{
+ block = NULL;
+ partition = &partition_data;
+ memset(&partition_data, 0, sizeof(struct disk_partition));
+ memset(&bcb, 0, sizeof(struct bootloader_message));
+}
+
+static int __bcb_initialize(const char *iface, int devnum, const char *partp)
{
- struct blk_desc *desc;
- struct disk_partition info;
- u64 cnt;
char *endp;
int part, ret;
- desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, devnum);
- if (!desc) {
+ block = blk_get_dev(iface, devnum);
+ if (!block) {
ret = -ENODEV;
goto err_read_fail;
}
/*
- * always select the USER mmc hwpart in case another
+ * always select the first hwpart in case another
* blk operation selected a different hwpart
*/
- ret = blk_dselect_hwpart(desc, 0);
+ ret = blk_dselect_hwpart(block, 0);
if (IS_ERR_VALUE(ret)) {
ret = -ENODEV;
goto err_read_fail;
part = simple_strtoul(partp, &endp, 0);
if (*endp == '\0') {
- ret = part_get_info(desc, part, &info);
+ ret = part_get_info(block, part, partition);
if (ret)
goto err_read_fail;
} else {
- part = part_get_info_by_name(desc, partp, &info);
+ part = part_get_info_by_name(block, partp, partition);
if (part < 0) {
ret = part;
goto err_read_fail;
}
}
- cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz);
- if (cnt > info.size)
+ return CMD_RET_SUCCESS;
+
+err_read_fail:
+ printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
+ __bcb_reset();
+ return CMD_RET_FAILURE;
+}
+
+static int __bcb_load(void)
+{
+ u64 cnt;
+ int ret;
+
+ cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz);
+ if (cnt > partition->size)
goto err_too_small;
- if (blk_dread(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dread(block, partition->start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err_read_fail;
}
- bcb_dev = desc->devnum;
- bcb_part = part;
- debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part);
+ debug("%s: Loaded from %d %d:%s\n", __func__, block->uclass_id,
+ block->devnum, partition->name);
return CMD_RET_SUCCESS;
err_read_fail:
- printf("Error: mmc %d:%s read failed (%d)\n", devnum, partp, ret);
+ printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
goto err;
err_too_small:
- printf("Error: mmc %d:%s too small!", devnum, partp);
- goto err;
+ printf("Error: %d %d:%s too small!", block->uclass_id,
+ block->devnum, partition->name);
err:
- bcb_dev = -1;
- bcb_part = -1;
-
+ __bcb_reset();
return CMD_RET_FAILURE;
}
static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
+ int ret;
+ int devnum;
char *endp;
- int devnum = simple_strtoul(argv[1], &endp, 0);
+ char *iface = "mmc";
+
+ if (argc == 4) {
+ iface = argv[1];
+ argc--;
+ argv++;
+ }
+ devnum = simple_strtoul(argv[1], &endp, 0);
if (*endp != '\0') {
printf("Error: Device id '%s' not a number\n", argv[1]);
return CMD_RET_FAILURE;
}
- return __bcb_load(devnum, argv[2]);
+ ret = __bcb_initialize(iface, devnum, argv[2]);
+ if (ret != CMD_RET_SUCCESS)
+ return ret;
+
+ return __bcb_load();
}
-static int __bcb_set(char *fieldp, const char *valp)
+static int __bcb_set(const char *fieldp, const char *valp)
{
int size, len;
char *field, *str, *found, *tmp;
static int __bcb_store(void)
{
- struct blk_desc *desc;
- struct disk_partition info;
u64 cnt;
int ret;
- desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, bcb_dev);
- if (!desc) {
- ret = -ENODEV;
- goto err;
- }
-
- ret = part_get_info(desc, bcb_part, &info);
- if (ret)
- goto err;
+ cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz);
- cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz);
-
- if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dwrite(block, partition->start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err;
}
return CMD_RET_SUCCESS;
err:
- printf("Error: mmc %d:%d write failed (%d)\n", bcb_dev, bcb_part, ret);
+ printf("Error: %d %d:%s write failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
return CMD_RET_FAILURE;
}
return __bcb_store();
}
-int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp)
+int bcb_find_partition_and_load(const char *iface, int devnum, char *partp)
{
int ret;
- ret = __bcb_load(devnum, partp);
- if (ret != CMD_RET_SUCCESS)
- return ret;
+ __bcb_reset();
- ret = __bcb_set("command", reasonp);
+ ret = __bcb_initialize(iface, devnum, partp);
if (ret != CMD_RET_SUCCESS)
return ret;
- ret = __bcb_store();
- if (ret != CMD_RET_SUCCESS)
- return ret;
+ return __bcb_load();
+}
- return 0;
+int bcb_load(struct blk_desc *block_description, struct disk_partition *disk_partition)
+{
+ __bcb_reset();
+
+ block = block_description;
+ partition = disk_partition;
+
+ return __bcb_load();
+}
+
+int bcb_set(enum bcb_field field, const char *value)
+{
+ if (field > BCB_FIELD_STAGE)
+ return CMD_RET_FAILURE;
+ return __bcb_set(fields[field], value);
+}
+
+int bcb_get(enum bcb_field field, char *value_out, size_t value_size)
+{
+ int size;
+ char *field_value;
+
+ if (field > BCB_FIELD_STAGE)
+ return CMD_RET_FAILURE;
+ if (bcb_field_get(fields[field], &field_value, &size))
+ return CMD_RET_FAILURE;
+
+ strlcpy(value_out, field_value, value_size);
+
+ return CMD_RET_SUCCESS;
+}
+
+int bcb_store(void)
+{
+ return __bcb_store();
+}
+
+void bcb_reset(void)
+{
+ __bcb_reset();
}
static struct cmd_tbl cmd_bcb_sub[] = {
U_BOOT_CMD(
bcb, CONFIG_SYS_MAXARGS, 1, do_bcb,
"Load/set/clear/test/dump/store Android BCB fields",
- "load <dev> <part> - load BCB from mmc <dev>:<part>\n"
- "bcb set <field> <val> - set BCB <field> to <val>\n"
- "bcb clear [<field>] - clear BCB <field> or all fields\n"
- "bcb test <field> <op> <val> - test BCB <field> against <val>\n"
- "bcb dump <field> - dump BCB <field>\n"
- "bcb store - store BCB back to mmc\n"
+ "load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>\n"
+ "load <dev> <part> - load BCB from mmc <dev>:<part>\n"
+ "bcb set <field> <val> - set BCB <field> to <val>\n"
+ "bcb clear [<field>] - clear BCB <field> or all fields\n"
+ "bcb test <field> <op> <val> - test BCB <field> against <val>\n"
+ "bcb dump <field> - dump BCB <field>\n"
+ "bcb store - store BCB back to <interface>\n"
"\n"
"Legend:\n"
- "<dev> - MMC device index containing the BCB partition\n"
- "<part> - MMC partition index or name containing the BCB\n"
- "<field> - one of {command,status,recovery,stage,reserved}\n"
- "<op> - the binary operator used in 'bcb test':\n"
- " '=' returns true if <val> matches the string stored in <field>\n"
- " '~' returns true if <val> matches a subset of <field>'s string\n"
- "<val> - string/text provided as input to bcb {set,test}\n"
- " NOTE: any ':' character in <val> will be replaced by line feed\n"
- " during 'bcb set' and used as separator by upper layers\n"
+ "<interface> - storage device interface (virtio, mmc, etc)\n"
+ "<dev> - storage device index containing the BCB partition\n"
+ "<part> - partition index or name containing the BCB\n"
+ "<field> - one of {command,status,recovery,stage,reserved}\n"
+ "<op> - the binary operator used in 'bcb test':\n"
+ " '=' returns true if <val> matches the string stored in <field>\n"
+ " '~' returns true if <val> matches a subset of <field>'s string\n"
+ "<val> - string/text provided as input to bcb {set,test}\n"
+ " NOTE: any ':' character in <val> will be replaced by line feed\n"
+ " during 'bcb set' and used as separator by upper layers\n"
);
#include <command.h>
#include <dm.h>
#include <env.h>
+#include <getopt.h>
#include <lmb.h>
#include <mapmem.h>
#include <net.h>
bdinfo_print_num_l(" clock", info.clock);
}
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int bdinfo_print_all(struct bd_info *bd)
{
- struct bd_info *bd = gd->bd;
-
#ifdef DEBUG
bdinfo_print_num_l("bd address", (ulong)bd);
#endif
return 0;
}
+int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct bd_info *bd = gd->bd;
+ struct getopt_state gs;
+ int opt;
+
+ if (!CONFIG_IS_ENABLED(GETOPT) || argc == 1)
+ return bdinfo_print_all(bd);
+
+ getopt_init_state(&gs);
+ while ((opt = getopt(&gs, argc, argv, "aem")) > 0) {
+ switch (opt) {
+ case 'a':
+ return bdinfo_print_all(bd);
+ case 'e':
+ if (!IS_ENABLED(CONFIG_CMD_NET))
+ return CMD_RET_USAGE;
+ print_eth();
+ return CMD_RET_SUCCESS;
+ case 'm':
+ print_bi_dram(bd);
+ return CMD_RET_SUCCESS;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+
+ return CMD_RET_USAGE;
+}
+
U_BOOT_CMD(
- bdinfo, 1, 1, do_bdinfo,
+ bdinfo, 2, 1, do_bdinfo,
"print Board Info structure",
""
);
"Bind a device to a driver",
"<node path> <driver>\n"
"bind <class> <index> <driver>\n"
+ "Use 'dm tree' to list all devices registered in the driver model,\n"
+ "their path, class, index and current driver.\n"
);
U_BOOT_CMD(
"<node path>\n"
"unbind <class> <index>\n"
"unbind <class> <index> <driver>\n"
+ "Use 'dm tree' to list all devices registered in the driver model,\n"
+ "their path, class, index and current driver.\n"
);
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
-#include <bootm.h>
-#include <charset.h>
#include <command.h>
-#include <dm.h>
+#include <efi.h>
#include <efi_loader.h>
-#include <efi_selftest.h>
-#include <env.h>
-#include <errno.h>
-#include <image.h>
+#include <exports.h>
#include <log.h>
#include <malloc.h>
-#include <asm/global_data.h>
-#include <linux/libfdt.h>
-#include <linux/libfdt_env.h>
#include <mapmem.h>
-#include <memalign.h>
+#include <vsprintf.h>
#include <asm-generic/sections.h>
-#include <linux/linkage.h>
+#include <asm/global_data.h>
+#include <linux/string.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct efi_device_path *bootefi_image_path;
-static struct efi_device_path *bootefi_device_path;
-static void *image_addr;
-static size_t image_size;
-
-/**
- * efi_get_image_parameters() - return image parameters
- *
- * @img_addr: address of loaded image in memory
- * @img_size: size of loaded image
- */
-void efi_get_image_parameters(void **img_addr, size_t *img_size)
-{
- *img_addr = image_addr;
- *img_size = image_size;
-}
-
-/**
- * efi_clear_bootdev() - clear boot device
- */
-static void efi_clear_bootdev(void)
-{
- efi_free_pool(bootefi_device_path);
- efi_free_pool(bootefi_image_path);
- bootefi_device_path = NULL;
- bootefi_image_path = NULL;
- image_addr = NULL;
- image_size = 0;
-}
-
-/**
- * efi_set_bootdev() - set boot device
- *
- * This function is called when a file is loaded, e.g. via the 'load' command.
- * We use the path to this file to inform the UEFI binary about the boot device.
- *
- * @dev: device, e.g. "MMC"
- * @devnr: number of the device, e.g. "1:2"
- * @path: path to file loaded
- * @buffer: buffer with file loaded
- * @buffer_size: size of file loaded
- */
-void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
- void *buffer, size_t buffer_size)
-{
- struct efi_device_path *device, *image;
- efi_status_t ret;
-
- log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev,
- devnr, path, buffer, buffer_size);
-
- /* Forget overwritten image */
- if (buffer + buffer_size >= image_addr &&
- image_addr + image_size >= buffer)
- efi_clear_bootdev();
-
- /* Remember only PE-COFF and FIT images */
- if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
- if (IS_ENABLED(CONFIG_FIT) &&
- !fit_check_format(buffer, IMAGE_SIZE_INVAL)) {
- /*
- * FIT images of type EFI_OS are started via command
- * bootm. We should not use their boot device with the
- * bootefi command.
- */
- buffer = 0;
- buffer_size = 0;
- } else {
- log_debug("- not remembering image\n");
- return;
- }
- }
-
- /* efi_set_bootdev() is typically called repeatedly, recover memory */
- efi_clear_bootdev();
-
- image_addr = buffer;
- image_size = buffer_size;
-
- ret = efi_dp_from_name(dev, devnr, path, &device, &image);
- if (ret == EFI_SUCCESS) {
- bootefi_device_path = device;
- if (image) {
- /* FIXME: image should not contain device */
- struct efi_device_path *image_tmp = image;
-
- efi_dp_split_file_path(image, &device, &image);
- efi_free_pool(image_tmp);
- }
- bootefi_image_path = image;
- log_debug("- boot device %pD\n", device);
- if (image)
- log_debug("- image %pD\n", image);
- } else {
- log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
- efi_clear_bootdev();
- }
-}
-
-/**
- * efi_env_set_load_options() - set load options from environment variable
- *
- * @handle: the image handle
- * @env_var: name of the environment variable
- * @load_options: pointer to load options (output)
- * Return: status code
- */
-static efi_status_t efi_env_set_load_options(efi_handle_t handle,
- const char *env_var,
- u16 **load_options)
-{
- const char *env = env_get(env_var);
- size_t size;
- u16 *pos;
- efi_status_t ret;
-
- *load_options = NULL;
- if (!env)
- return EFI_SUCCESS;
- size = sizeof(u16) * (utf8_utf16_strlen(env) + 1);
- pos = calloc(size, 1);
- if (!pos)
- return EFI_OUT_OF_RESOURCES;
- *load_options = pos;
- utf8_utf16_strcpy(&pos, env);
- ret = efi_set_load_options(handle, size, *load_options);
- if (ret != EFI_SUCCESS) {
- free(*load_options);
- *load_options = NULL;
- }
- return ret;
-}
-
-#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
-
-/**
- * copy_fdt() - Copy the device tree to a new location available to EFI
- *
- * The FDT is copied to a suitable location within the EFI memory map.
- * Additional 12 KiB are added to the space in case the device tree needs to be
- * expanded later with fdt_open_into().
- *
- * @fdtp: On entry a pointer to the flattened device tree.
- * On exit a pointer to the copy of the flattened device tree.
- * FDT start
- * Return: status code
- */
-static efi_status_t copy_fdt(void **fdtp)
-{
- unsigned long fdt_ram_start = -1L, fdt_pages;
- efi_status_t ret = 0;
- void *fdt, *new_fdt;
- u64 new_fdt_addr;
- uint fdt_size;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- u64 ram_start = gd->bd->bi_dram[i].start;
- u64 ram_size = gd->bd->bi_dram[i].size;
-
- if (!ram_size)
- continue;
-
- if (ram_start < fdt_ram_start)
- fdt_ram_start = ram_start;
- }
-
- /*
- * Give us at least 12 KiB of breathing room in case the device tree
- * needs to be expanded later.
- */
- fdt = *fdtp;
- fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000);
- fdt_size = fdt_pages << EFI_PAGE_SHIFT;
-
- ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
- EFI_ACPI_RECLAIM_MEMORY, fdt_pages,
- &new_fdt_addr);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to reserve space for FDT\n");
- goto done;
- }
- new_fdt = (void *)(uintptr_t)new_fdt_addr;
- memcpy(new_fdt, fdt, fdt_totalsize(fdt));
- fdt_set_totalsize(new_fdt, fdt_size);
-
- *fdtp = (void *)(uintptr_t)new_fdt_addr;
-done:
- return ret;
-}
-
-/**
- * get_config_table() - get configuration table
- *
- * @guid: GUID of the configuration table
- * Return: pointer to configuration table or NULL
- */
-static void *get_config_table(const efi_guid_t *guid)
-{
- size_t i;
-
- for (i = 0; i < systab.nr_tables; i++) {
- if (!guidcmp(guid, &systab.tables[i].guid))
- return systab.tables[i].table;
- }
- return NULL;
-}
-
-#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */
-
-/**
- * efi_install_fdt() - install device tree
- *
- * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory
- * address will will be installed as configuration table, otherwise the device
- * tree located at the address indicated by environment variable fdt_addr or as
- * fallback fdtcontroladdr will be used.
- *
- * On architectures using ACPI tables device trees shall not be installed as
- * configuration table.
- *
- * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use the
- * the hardware device tree as indicated by environment variable
- * fdt_addr or as fallback the internal device tree as indicated by
- * the environment variable fdtcontroladdr
- * Return: status code
- */
-efi_status_t efi_install_fdt(void *fdt)
-{
- /*
- * The EBBR spec requires that we have either an FDT or an ACPI table
- * but not both.
- */
-#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
- if (fdt) {
- log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
- return EFI_SUCCESS;
- }
-#else
- struct bootm_headers img = { 0 };
- efi_status_t ret;
-
- if (fdt == EFI_FDT_USE_INTERNAL) {
- const char *fdt_opt;
- uintptr_t fdt_addr;
-
- /* Look for device tree that is already installed */
- if (get_config_table(&efi_guid_fdt))
- return EFI_SUCCESS;
- /* Check if there is a hardware device tree */
- fdt_opt = env_get("fdt_addr");
- /* Use our own device tree as fallback */
- if (!fdt_opt) {
- fdt_opt = env_get("fdtcontroladdr");
- if (!fdt_opt) {
- log_err("ERROR: need device tree\n");
- return EFI_NOT_FOUND;
- }
- }
- fdt_addr = hextoul(fdt_opt, NULL);
- if (!fdt_addr) {
- log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n");
- return EFI_LOAD_ERROR;
- }
- fdt = map_sysmem(fdt_addr, 0);
- }
-
- /* Install device tree */
- if (fdt_check_header(fdt)) {
- log_err("ERROR: invalid device tree\n");
- return EFI_LOAD_ERROR;
- }
-
- /* Prepare device tree for payload */
- ret = copy_fdt(&fdt);
- if (ret) {
- log_err("ERROR: out of memory\n");
- return EFI_OUT_OF_RESOURCES;
- }
-
- if (image_setup_libfdt(&img, fdt, 0, NULL)) {
- log_err("ERROR: failed to process device tree\n");
- return EFI_LOAD_ERROR;
- }
-
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
-
- efi_try_purge_kaslr_seed(fdt);
-
- if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
- ret = efi_tcg2_measure_dtb(fdt);
- if (ret == EFI_SECURITY_VIOLATION) {
- log_err("ERROR: failed to measure DTB\n");
- return ret;
- }
- }
-
- /* Install device tree as UEFI table */
- ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: failed to install device tree\n");
- return ret;
- }
-#endif /* GENERATE_ACPI_TABLE */
-
- return EFI_SUCCESS;
-}
-
-/**
- * do_bootefi_exec() - execute EFI binary
- *
- * The image indicated by @handle is started. When it returns the allocated
- * memory for the @load_options is freed.
- *
- * @handle: handle of loaded image
- * @load_options: load options
- * Return: status code
- *
- * Load the EFI binary into a newly assigned memory unwinding the relocation
- * information, install the loaded image protocol, and call the binary.
- */
-static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options)
-{
- efi_status_t ret;
- efi_uintn_t exit_data_size = 0;
- u16 *exit_data = NULL;
-
- /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
- switch_to_non_secure_mode();
-
- /*
- * The UEFI standard requires that the watchdog timer is set to five
- * minutes when invoking an EFI boot option.
- *
- * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
- * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
- */
- ret = efi_set_watchdog(300);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to set watchdog timer\n");
- goto out;
- }
-
- /* Call our payload! */
- ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
- if (ret != EFI_SUCCESS) {
- log_err("## Application failed, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- if (exit_data) {
- log_err("## %ls\n", exit_data);
- efi_free_pool(exit_data);
- }
- }
-
- efi_restore_gd();
-
-out:
- free(load_options);
-
- if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
- if (efi_initrd_deregister() != EFI_SUCCESS)
- log_err("Failed to remove loadfile2 for initrd\n");
- }
-
- /* Control is returned to U-Boot, disable EFI watchdog */
- efi_set_watchdog(0);
+static struct efi_device_path *test_image_path;
+static struct efi_device_path *test_device_path;
- return ret;
-}
-
-/**
- * do_efibootmgr() - execute EFI boot manager
- *
- * Return: status code
- */
-static int do_efibootmgr(void)
-{
- efi_handle_t handle;
- efi_status_t ret;
- void *load_options;
-
- ret = efi_bootmgr_load(&handle, &load_options);
- if (ret != EFI_SUCCESS) {
- log_notice("EFI boot manager: Cannot load any image\n");
- return CMD_RET_FAILURE;
- }
-
- ret = do_bootefi_exec(handle, load_options);
-
- if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-/**
- * do_bootefi_image() - execute EFI binary
- *
- * Set up memory image for the binary to be loaded, prepare device path, and
- * then call do_bootefi_exec() to execute it.
- *
- * @image_opt: string with image start address
- * @size_opt: string with image size or NULL
- * Return: status code
- */
-static int do_bootefi_image(const char *image_opt, const char *size_opt)
-{
- void *image_buf;
- unsigned long addr, size;
- efi_status_t ret;
-
-#ifdef CONFIG_CMD_BOOTEFI_HELLO
- if (!strcmp(image_opt, "hello")) {
- image_buf = __efi_helloworld_begin;
- size = __efi_helloworld_end - __efi_helloworld_begin;
- efi_clear_bootdev();
- } else
-#endif
- {
- addr = strtoul(image_opt, NULL, 16);
- /* Check that a numeric value was passed */
- if (!addr)
- return CMD_RET_USAGE;
- image_buf = map_sysmem(addr, 0);
-
- if (size_opt) {
- size = strtoul(size_opt, NULL, 16);
- if (!size)
- return CMD_RET_USAGE;
- efi_clear_bootdev();
- } else {
- if (image_buf != image_addr) {
- log_err("No UEFI binary known at %s\n",
- image_opt);
- return CMD_RET_FAILURE;
- }
- size = image_size;
- }
- }
- ret = efi_run_image(image_buf, size);
-
- if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-/**
- * efi_run_image() - run loaded UEFI image
- *
- * @source_buffer: memory address of the UEFI image
- * @source_size: size of the UEFI image
- * Return: status code
- */
-efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size)
-{
- efi_handle_t mem_handle = NULL, handle;
- struct efi_device_path *file_path = NULL;
- struct efi_device_path *msg_path;
- efi_status_t ret, ret2;
- u16 *load_options;
-
- if (!bootefi_device_path || !bootefi_image_path) {
- log_debug("Not loaded from disk\n");
- /*
- * Special case for efi payload not loaded from disk,
- * such as 'bootefi hello' or for example payload
- * loaded directly into memory via JTAG, etc:
- */
- file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)source_buffer,
- source_size);
- /*
- * Make sure that device for device_path exist
- * in load_image(). Otherwise, shell and grub will fail.
- */
- ret = efi_install_multiple_protocol_interfaces(&mem_handle,
- &efi_guid_device_path,
- file_path, NULL);
- if (ret != EFI_SUCCESS)
- goto out;
- msg_path = file_path;
- } else {
- file_path = efi_dp_append(bootefi_device_path,
- bootefi_image_path);
- msg_path = bootefi_image_path;
- log_debug("Loaded from disk\n");
- }
-
- log_info("Booting %pD\n", msg_path);
-
- ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer,
- source_size, &handle));
- if (ret != EFI_SUCCESS) {
- log_err("Loading image failed\n");
- goto out;
- }
-
- /* Transfer environment variable as load options */
- ret = efi_env_set_load_options(handle, "bootargs", &load_options);
- if (ret != EFI_SUCCESS)
- goto out;
-
- ret = do_bootefi_exec(handle, load_options);
-
-out:
- ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle,
- &efi_guid_device_path,
- file_path, NULL);
- efi_free_pool(file_path);
- return (ret != EFI_SUCCESS) ? ret : ret2;
-}
-
-#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
static efi_status_t bootefi_run_prepare(const char *load_options_path,
struct efi_device_path *device_path,
struct efi_device_path *image_path,
efi_status_t ret;
/* Construct a dummy device path */
- bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0);
- if (!bootefi_device_path)
+ test_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0);
+ if (!test_device_path)
return EFI_OUT_OF_RESOURCES;
- bootefi_image_path = efi_dp_from_file(NULL, path);
- if (!bootefi_image_path) {
+ test_image_path = efi_dp_from_file(NULL, path);
+ if (!test_image_path) {
ret = EFI_OUT_OF_RESOURCES;
goto failure;
}
- ret = bootefi_run_prepare(load_options_path, bootefi_device_path,
- bootefi_image_path, image_objp,
+ ret = bootefi_run_prepare(load_options_path, test_device_path,
+ test_image_path, image_objp,
loaded_image_infop);
if (ret == EFI_SUCCESS)
return ret;
failure:
+ efi_free_pool(test_device_path);
+ efi_free_pool(test_image_path);
+ /* TODO: not sure calling clear function is necessary */
efi_clear_bootdev();
return ret;
}
ret = EFI_CALL(efi_selftest(&image_obj->header, &systab));
efi_restore_gd();
free(loaded_image_info->load_options);
+ efi_free_pool(test_device_path);
+ efi_free_pool(test_image_path);
if (ret != EFI_SUCCESS)
efi_delete_handle(&image_obj->header);
else
return ret != EFI_SUCCESS;
}
-#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */
/**
* do_bootefi() - execute `bootefi` command
char *const argv[])
{
efi_status_t ret;
- char *img_addr, *img_size, *str_copy, *pos;
- void *fdt;
+ char *p;
+ void *fdt, *image_buf;
+ unsigned long addr, size;
+ void *image_addr;
+ size_t image_size;
if (argc < 2)
return CMD_RET_USAGE;
- /* Initialize EFI drivers */
- ret = efi_init_obj_list();
- if (ret != EFI_SUCCESS) {
- log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- return CMD_RET_FAILURE;
- }
-
if (argc > 2) {
uintptr_t fdt_addr;
} else {
fdt = EFI_FDT_USE_INTERNAL;
}
- ret = efi_install_fdt(fdt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
- if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
- if (!strcmp(argv[1], "bootmgr"))
- return do_efibootmgr();
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) &&
+ !strcmp(argv[1], "bootmgr")) {
+ ret = efi_bootmgr_run(fdt);
+
+ if (ret == EFI_INVALID_PARAMETER)
+ return CMD_RET_USAGE;
+ else if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
}
-#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
- if (!strcmp(argv[1], "selftest"))
+
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_SELFTEST) &&
+ !strcmp(argv[1], "selftest")) {
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = efi_install_fdt(fdt);
+ if (ret == EFI_INVALID_PARAMETER)
+ return CMD_RET_USAGE;
+ else if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
return do_efi_selftest();
-#endif
- str_copy = strdup(argv[1]);
- if (!str_copy) {
- log_err("Out of memory\n");
- return CMD_RET_FAILURE;
}
- pos = str_copy;
- img_addr = strsep(&pos, ":");
- img_size = strsep(&pos, ":");
- ret = do_bootefi_image(img_addr, img_size);
- free(str_copy);
- return ret;
+ if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BINARY))
+ return CMD_RET_SUCCESS;
+
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_HELLO) &&
+ !strcmp(argv[1], "hello")) {
+ image_buf = __efi_helloworld_begin;
+ size = __efi_helloworld_end - __efi_helloworld_begin;
+ /* TODO: not sure calling clear function is necessary */
+ efi_clear_bootdev();
+ } else {
+ addr = strtoul(argv[1], NULL, 16);
+ /* Check that a numeric value was passed */
+ if (!addr)
+ return CMD_RET_USAGE;
+ image_buf = map_sysmem(addr, 0);
+
+ p = strchr(argv[1], ':');
+ if (p) {
+ size = strtoul(++p, NULL, 16);
+ if (!size)
+ return CMD_RET_USAGE;
+ efi_clear_bootdev();
+ } else {
+ /* Image should be already loaded */
+ efi_get_image_parameters(&image_addr, &image_size);
+
+ if (image_buf != image_addr) {
+ log_err("No UEFI binary known at %s\n",
+ argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ size = image_size;
+ }
+ }
+
+ ret = efi_binary_run(image_buf, size, fdt);
+
+ if (ret == EFI_INVALID_PARAMETER)
+ return CMD_RET_USAGE;
+ else if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
}
U_BOOT_LONGHELP(bootefi,
struct udevice *dev = NULL;
struct bootflow bflow;
bool all = false, boot = false, errors = false, no_global = false;
- bool list = false, no_hunter = false;
+ bool list = false, no_hunter = false, menu = false, text_mode = false;
int num_valid = 0;
const char *label = NULL;
bool has_args;
no_global = strchr(argv[1], 'G');
list = strchr(argv[1], 'l');
no_hunter = strchr(argv[1], 'H');
+ menu = strchr(argv[1], 'm');
+ text_mode = strchr(argv[1], 't');
argc--;
argv++;
}
}
if (list)
show_bootflow(i, &bflow, errors);
- if (boot && !bflow.err)
+ if (!menu && boot && !bflow.err)
bootflow_run_boot(&iter, &bflow);
}
bootflow_iter_uninit(&iter);
if (list)
show_footer(i, num_valid);
- if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && !num_valid && !list)
- printf("No bootflows found; try again with -l\n");
+ if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && IS_ENABLED(CONFIG_EXPO)) {
+ if (!num_valid && !list) {
+ printf("No bootflows found; try again with -l\n");
+ } else if (menu) {
+ struct bootflow *sel_bflow;
+
+ ret = bootflow_handle_menu(std, text_mode, &sel_bflow);
+ if (!ret && boot) {
+ ret = console_clear();
+ if (ret) {
+ log_err("Failed to clear console: %dE\n",
+ ret);
+ return ret;
+ }
+
+ bootflow_run_boot(NULL, sel_bflow);
+ }
+ }
+ }
return 0;
}
op = argv[1];
arg = argv[2];
if (*op == 's') {
- if (argc < 4)
+ if (argc < 3)
return CMD_RET_USAGE;
- val = argv[3];
+ val = argv[3] ?: (const char *)BOOTFLOWCL_EMPTY;
}
switch (*op) {
/*
* Image booting support
*/
-static int booti_start(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], struct bootm_headers *images)
+static int booti_start(struct bootm_info *bmi)
{
+ struct bootm_headers *images = bmi->images;
int ret;
ulong ld;
ulong relocated_addr;
unsigned long decomp_len;
int ctype;
- ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START,
- images, 1);
+ ret = bootm_run_states(bmi, BOOTM_STATE_START);
/* Setup Linux kernel Image entry point */
- if (!argc) {
+ if (!bmi->addr_img) {
ld = image_load_addr;
debug("* kernel: default image load address = 0x%08lx\n",
image_load_addr);
} else {
- ld = hextoul(argv[0], NULL);
+ ld = hextoul(bmi->addr_img, NULL);
debug("* kernel: cmdline image address = 0x%08lx\n", ld);
}
unmap_sysmem((void *)ld);
ret = booti_setup(ld, &relocated_addr, &image_size, false);
- if (ret != 0)
+ if (ret || IS_ENABLED(CONFIG_SANDBOX))
return 1;
/* Handle BOOTM_STATE_LOADOS */
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
* have a header that provide this informaiton.
*/
- if (bootm_find_images(flag, argc, argv, relocated_addr, image_size))
+ if (bootm_find_images(image_load_addr, bmi->conf_ramdisk, bmi->conf_fdt,
+ relocated_addr, image_size))
return 1;
return 0;
int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ struct bootm_info bmi;
+ int states;
int ret;
/* Consume 'booti' */
argc--; argv++;
- if (booti_start(cmdtp, flag, argc, argv, &images))
+ bootm_init(&bmi);
+ if (argc)
+ bmi.addr_img = argv[0];
+ if (argc > 1)
+ bmi.conf_ramdisk = argv[1];
+ if (argc > 2)
+ bmi.conf_fdt = argv[2];
+ bmi.boot_progress = true;
+ bmi.cmd_name = "booti";
+ /* do not set up argc and argv[] since nothing uses them */
+
+ if (booti_start(&bmi))
return 1;
/*
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
-#ifdef CONFIG_RISCV_SMODE
- images.os.arch = IH_ARCH_RISCV;
-#elif CONFIG_ARM64
- images.os.arch = IH_ARCH_ARM64;
-#endif
- ret = do_bootm_states(cmdtp, flag, argc, argv,
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
- BOOTM_STATE_RAMDISK |
-#endif
- BOOTM_STATE_MEASURE |
- BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
- BOOTM_STATE_OS_GO,
- &images, 1);
+ if (IS_ENABLED(CONFIG_RISCV_SMODE))
+ images.os.arch = IH_ARCH_RISCV;
+ else if (IS_ENABLED(CONFIG_ARM64))
+ images.os.arch = IH_ARCH_ARM64;
+
+ states = BOOTM_STATE_MEASURE | BOOTM_STATE_OS_PREP |
+ BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO;
+ if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
+ states |= BOOTM_STATE_RAMDISK;
+
+ ret = bootm_run_states(&bmi, states);
return ret;
}
static int do_bootm_subcommand(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ struct bootm_info bmi;
int ret = 0;
long state;
struct cmd_tbl *c;
return CMD_RET_USAGE;
}
- ret = do_bootm_states(cmdtp, flag, argc, argv, state, &images, 0);
+ bootm_init(&bmi);
+ if (argc)
+ bmi.addr_img = argv[0];
+ if (argc > 1)
+ bmi.conf_ramdisk = argv[1];
+ if (argc > 2)
+ bmi.conf_fdt = argv[2];
+ bmi.cmd_name = "bootm";
+ bmi.boot_progress = false;
+
+ /* set up argc and argv[] since some OSes use them */
+ bmi.argc = argc;
+ bmi.argv = argv;
+
+ ret = bootm_run_states(&bmi, state);
#if defined(CONFIG_CMD_BOOTM_PRE_LOAD)
if (!ret && (state & BOOTM_STATE_PRE_LOAD))
int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- int states;
+ struct bootm_info bmi;
int ret;
/* determine if we have a sub command */
return do_bootm_subcommand(cmdtp, flag, argc, argv);
}
- states = BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_PRE_LOAD |
- BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS |
- BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
- BOOTM_STATE_OS_GO;
- if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH))
- states |= BOOTM_STATE_RAMDISK;
- if (IS_ENABLED(CONFIG_MEASURED_BOOT))
- states |= BOOTM_STATE_MEASURE;
- if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS))
- states |= BOOTM_STATE_OS_CMDLINE;
- ret = do_bootm_states(cmdtp, flag, argc, argv, states, &images, 1);
+ bootm_init(&bmi);
+ if (argc)
+ bmi.addr_img = argv[0];
+ if (argc > 1)
+ bmi.conf_ramdisk = argv[1];
+ if (argc > 2)
+ bmi.conf_fdt = argv[2];
+
+ /* set up argc and argv[] since some OSes use them */
+ bmi.argc = argc;
+ bmi.argv = argv;
+
+ ret = bootm_run(&bmi);
return ret ? CMD_RET_FAILURE : 0;
}
static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[], struct bootm_headers *images)
{
- int ret;
ulong zi_start, zi_end;
+ struct bootm_info bmi;
+ int ret;
+
+ bootm_init(&bmi);
+ if (argc)
+ bmi.addr_img = argv[0];
+ if (argc > 1)
+ bmi.conf_ramdisk = argv[1];
+ if (argc > 2)
+ bmi.conf_fdt = argv[2];
+ /* do not set up argc and argv[] since nothing uses them */
- ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START,
- images, 1);
+ ret = bootm_run_states(&bmi, BOOTM_STATE_START);
/* Setup Linux kernel zImage entry point */
if (!argc) {
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
* have a header that provide this informaiton.
*/
- if (bootm_find_images(flag, argc, argv, images->ep, zi_end - zi_start))
+ if (bootm_find_images(image_load_addr, cmd_arg1(argc, argv),
+ cmd_arg2(argc, argv), images->ep,
+ zi_end - zi_start))
return 1;
return 0;
int do_bootz(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ struct bootm_info bmi;
int ret;
/* Consume 'bootz' */
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
- ret = do_bootm_states(cmdtp, flag, argc, argv,
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
- BOOTM_STATE_RAMDISK |
-#endif
- BOOTM_STATE_MEASURE |
- BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
- BOOTM_STATE_OS_GO,
- &images, 1);
+
+ bootm_init(&bmi);
+ if (argc)
+ bmi.addr_img = argv[0];
+ if (argc > 1)
+ bmi.conf_ramdisk = argv[1];
+ if (argc > 2)
+ bmi.conf_fdt = argv[2];
+ bmi.cmd_name = "bootz";
+
+ ret = bootz_run(&bmi);
return ret;
}
"list subvolumes of a BTRFS filesystem",
"<interface> <dev[:part]>\n"
" - List subvolumes of a BTRFS filesystem."
-)
+);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <cli.h>
+#include <command.h>
+#include <string.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *gd_flags_to_parser_name(void)
+{
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER)
+ return "old";
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER)
+ return "modern";
+ return NULL;
+}
+
+static int do_cli_get(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *current = gd_flags_to_parser_name();
+
+ if (!current) {
+ printf("current cli value is not valid, this should not happen!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%s\n", current);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int parser_string_to_gd_flags(const char *parser)
+{
+ if (!strcmp(parser, "old"))
+ return GD_FLG_HUSH_OLD_PARSER;
+ if (!strcmp(parser, "modern"))
+ return GD_FLG_HUSH_MODERN_PARSER;
+ return -1;
+}
+
+static int gd_flags_to_parser_config(int flag)
+{
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER)
+ return CONFIG_VAL(HUSH_OLD_PARSER);
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER)
+ return CONFIG_VAL(HUSH_MODERN_PARSER);
+ return -1;
+}
+
+static void reset_parser_gd_flags(void)
+{
+ gd->flags &= ~GD_FLG_HUSH_OLD_PARSER;
+ gd->flags &= ~GD_FLG_HUSH_MODERN_PARSER;
+}
+
+static int do_cli_set(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ char *parser_name;
+ int parser_config;
+ int parser_flag;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ parser_name = argv[1];
+
+ parser_flag = parser_string_to_gd_flags(parser_name);
+ if (parser_flag == -1) {
+ printf("Bad value for parser name: %s\n", parser_name);
+ return CMD_RET_USAGE;
+ }
+
+ parser_config = gd_flags_to_parser_config(parser_flag);
+ switch (parser_config) {
+ case -1:
+ printf("Bad value for parser flags: %d\n", parser_flag);
+ return CMD_RET_FAILURE;
+ case 0:
+ printf("Want to set current parser to %s, but its code was not compiled!\n",
+ parser_name);
+ return CMD_RET_FAILURE;
+ }
+
+ reset_parser_gd_flags();
+ gd->flags |= parser_flag;
+
+ cli_init();
+ cli_loop();
+
+ /* cli_loop() should never return. */
+ return CMD_RET_FAILURE;
+}
+
+static struct cmd_tbl parser_sub[] = {
+ U_BOOT_CMD_MKENT(get, 1, 1, do_cli_get, "", ""),
+ U_BOOT_CMD_MKENT(set, 2, 1, do_cli_set, "", ""),
+};
+
+static int do_cli(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* drop initial "parser" arg */
+ argc--;
+ argv++;
+
+ cp = find_cmd_tbl(argv[0], parser_sub, ARRAY_SIZE(parser_sub));
+ if (cp)
+ return cp->cmd(cmdtp, flag, argc, argv);
+
+ return CMD_RET_USAGE;
+}
+
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+static char cli_help_text[] =
+ "get - print current cli\n"
+ "set - set the current cli, possible value are: old, modern"
+ ;
+#endif
+
+U_BOOT_CMD(cli, 3, 1, do_cli,
+ "cli",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+ cli_help_text
+#endif
+);
}
}
-int __weak soc_clk_dump(void)
+static int soc_clk_dump(void)
{
struct udevice *dev;
+ const struct clk_ops *ops;
printf(" Rate Usecnt Name\n");
printf("------------------------------------------\n");
uclass_foreach_dev_probe(UCLASS_CLK, dev)
show_clks(dev, -1, 0);
+ uclass_foreach_dev_probe(UCLASS_CLK, dev) {
+ ops = dev_get_driver_ops(dev);
+ if (ops && ops->dump) {
+ printf("\n%s %s:\n", dev->driver->name, dev->name);
+ ops->dump(dev);
+ }
+ }
+
return 0;
}
#else
-int __weak soc_clk_dump(void)
+static int soc_clk_dump(void)
{
puts("Not implemented\n");
return 1;
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <dm.h>
-#include <video_console.h>
-
-#define CSI "\x1b["
static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- __maybe_unused struct udevice *dev;
-
- /*
- * Send clear screen and home
- *
- * FIXME(Heinrich Schuchardt <xypron.glpk@gmx.de>): This should go
- * through an API and only be written to serial terminals, not video
- * displays
- */
- printf(CSI "2J" CSI "1;1H");
- if (IS_ENABLED(CONFIG_VIDEO_ANSI))
- return 0;
-
- if (IS_ENABLED(CONFIG_VIDEO)) {
- if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev))
- return CMD_RET_FAILURE;
- if (vidconsole_clear_and_reset(dev))
- return CMD_RET_FAILURE;
- }
+ if (console_clear())
+ return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
bootstage_mark(BOOTSTAGE_ID_IDE_BOOT_DEVICE);
- part = blk_get_device_part_str(intf, (argc == 3) ? argv[2] : NULL,
- &dev_desc, &info, 1);
+ part = blk_get_device_part_str(intf, cmd_arg2(argc, argv),
+ &dev_desc, &info, 1);
if (part < 0) {
bootstage_error(BOOTSTAGE_ID_IDE_TYPE);
return 1;
"The values which can be provided with the -l option are:\n"
CONFIG_EEPROM_LAYOUT_HELP_STRING"\n"
#endif
-)
+);
for (i = 0; i < systab->nr_tables; i++) {
struct efi_configuration_table *tab = &systab->tables[i];
- char guid_str[37];
- uuid_bin_to_str(tab->guid.b, guid_str, 1);
- printf("%p %pUl %s\n", tab->table, guid_str,
+ printf("%p %pUl %s\n", tab->table, tab->guid.b,
uuid_guid_get_str(tab->guid.b) ?: "(unknown)");
}
}
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
+#include <net.h>
#include <part.h>
#include <search.h>
#include <linux/ctype.h>
return initrd_dp;
}
+/**
+ * efi_boot_add_uri() - set URI load option
+ *
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * @var_name16: variable name buffer
+ * @var_name16_size: variable name buffer size
+ * @lo: pointer to the load option
+ * @file_path: buffer to set the generated device path pointer
+ * @fp_size: file_path size
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ */
+static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16,
+ size_t var_name16_size, struct efi_load_option *lo,
+ struct efi_device_path **file_path,
+ efi_uintn_t *fp_size)
+{
+ int id;
+ char *pos;
+ char *endp;
+ u16 *label;
+ efi_uintn_t uridp_len;
+ struct efi_device_path_uri *uridp;
+
+ if (argc < 3 || lo->label)
+ return CMD_RET_USAGE;
+
+ id = (int)hextoul(argv[1], &endp);
+ if (*endp != '\0' || id > 0xffff)
+ return CMD_RET_USAGE;
+
+ label = efi_convert_string(argv[2]);
+ if (!label)
+ return CMD_RET_FAILURE;
+
+ if (!wget_validate_uri(argv[3])) {
+ printf("ERROR: invalid URI\n");
+ return CMD_RET_FAILURE;
+ }
+
+ efi_create_indexed_name(var_name16, var_name16_size, "Boot", id);
+ lo->label = label;
+
+ uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1;
+ uridp = efi_alloc(uridp_len + sizeof(END));
+ uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI;
+ uridp->dp.length = uridp_len;
+ strcpy(uridp->uri, argv[3]);
+ pos = (char *)uridp + uridp_len;
+ memcpy(pos, &END, sizeof(END));
+
+ *file_path = &uridp->dp;
+ *fp_size += uridp_len + sizeof(END);
+
+ return CMD_RET_SUCCESS;
+}
+
/**
* do_efi_boot_add() - set UEFI load option
*
argc -= 1;
argv += 1;
break;
+ case 'u':
+ if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) {
+ r = efi_boot_add_uri(argc, argv, var_name16,
+ sizeof(var_name16), &lo,
+ &file_path, &fp_size);
+ if (r != CMD_RET_SUCCESS)
+ goto out;
+ fp_free = file_path;
+ argc -= 3;
+ argv += 3;
+ } else{
+ r = CMD_RET_USAGE;
+ goto out;
+ }
+ break;
default:
r = CMD_RET_USAGE;
goto out;
}
static struct cmd_tbl cmd_efidebug_test_sub[] = {
-#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR
+#ifdef CONFIG_BOOTEFI_BOOTMGR
U_BOOT_CMD_MKENT(bootmgr, CONFIG_SYS_MAXARGS, 1, do_efi_test_bootmgr,
"", ""),
#endif
" -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n"
" -i|-I <interface> <devnum>[:<part>] <initrd file path>\n"
" (-b, -i for short form device path)\n"
+#if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
+ " -u <bootid> <label> <uri>\n"
+#endif
" -s '<optional data>'\n"
"efidebug boot rm <bootid#1> [<bootid#2> [<bootid#3> [...]]]\n"
" - delete UEFI BootXXXX variables\n"
" - show UEFI memory map\n"
"efidebug tables\n"
" - show UEFI configuration tables\n"
-#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR
+#ifdef CONFIG_BOOTEFI_BOOTMGR
"efidebug test bootmgr\n"
" - run simple bootmgr for test\n"
#endif
"list files in a directory (default /)",
"<interface> <dev[:part]> [directory]\n"
" - list files from 'dev' on 'interface' in a 'directory'"
-)
+);
U_BOOT_CMD(
ext2load, 6, 0, do_ext2load,
"<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n"
" - load binary file 'filename' from 'dev' on 'interface'\n"
" to address 'addr' from ext2 filesystem."
-)
+);
" If 'bytes' is 0 or omitted, the file is read until the end.\n"
" 'pos' gives the file byte position to start reading from.\n"
" If 'pos' is 0 or omitted, the file is read from the start."
-)
+);
static int do_save_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
" 'bytes' gives the size to save in bytes and is mandatory.\n"
" 'pos' gives the file byte position to start writing to.\n"
" If 'pos' is 0 or omitted, the file is written from the start."
-)
+);
static int do_ls_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
"<interface> [<dev[:part]> [directory]]\n"
" - List files in directory 'directory' of partition 'part' on\n"
" device type 'interface' instance 'dev'."
-)
+);
static int do_ln_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
"<interface> <dev[:part]> target linkname\n"
" - create a symbolic link to 'target' with the name 'linkname' on\n"
" device type 'interface' instance 'dev'."
-)
+);
static int do_fstype_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- const char *op = argc >= 2 ? argv[1] : NULL;
+ const char *op = cmd_arg1(argc, argv);
int confirmed = argc >= 3 && !strcmp(argv[2], "-y");
u32 bank, word, cnt, val, cmp;
ulong addr;
}
if (argc == 2 || argc == 3)
- return mmc_partconf_print(mmc, argc == 3 ? argv[2] : NULL);
+ return mmc_partconf_print(mmc, cmd_arg2(argc, argv));
ack = dectoul(argv[2], NULL);
part_num = dectoul(argv[3], NULL);
#include <env.h>
#include <watchdog.h>
#include <malloc.h>
+#include <mapmem.h>
#include <asm/byteorder.h>
#include <jffs2/jffs2.h>
#include <nand.h>
env_set_hex("nand_erasesize", mtd->erasesize);
}
-static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
+static int raw_access(struct mtd_info *mtd, void *buf, loff_t off,
ulong count, int read, int no_verify)
{
int ret = 0;
while (count--) {
/* Raw access */
mtd_oob_ops_t ops = {
- .datbuf = (u8 *)addr,
- .oobbuf = ((u8 *)addr) + mtd->writesize,
+ .datbuf = buf,
+ .oobbuf = buf + mtd->writesize,
.len = mtd->writesize,
.ooblen = mtd->oobsize,
.mode = MTD_OPS_RAW
break;
}
- addr += mtd->writesize + mtd->oobsize;
+ buf += mtd->writesize + mtd->oobsize;
off += mtd->writesize;
}
int read;
int raw = 0;
int no_verify = 0;
+ void *buf;
if (argc < 4)
goto usage;
}
mtd = get_nand_dev_by_index(dev);
+ buf = map_sysmem(addr, maxsize);
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
ret = nand_read_skip_bad(mtd, off, &rwsize,
- NULL, maxsize,
- (u_char *)addr);
+ NULL, maxsize, buf);
else
ret = nand_write_skip_bad(mtd, off, &rwsize,
- NULL, maxsize,
- (u_char *)addr,
+ NULL, maxsize, buf,
WITH_WR_VERIFY);
#ifdef CONFIG_CMD_NAND_TRIMFFS
} else if (!strcmp(s, ".trimffs")) {
if (read) {
printf("Unknown nand command suffix '%s'\n", s);
+ unmap_sysmem(buf);
return 1;
}
ret = nand_write_skip_bad(mtd, off, &rwsize, NULL,
- maxsize, (u_char *)addr,
+ maxsize, buf,
WITH_DROP_FFS | WITH_WR_VERIFY);
#endif
} else if (!strcmp(s, ".oob")) {
/* out-of-band data */
mtd_oob_ops_t ops = {
- .oobbuf = (u8 *)addr,
+ .oobbuf = buf,
.ooblen = rwsize,
.mode = MTD_OPS_RAW
};
else
ret = mtd_write_oob(mtd, off, &ops);
} else if (raw) {
- ret = raw_access(mtd, addr, off, pagecount, read,
+ ret = raw_access(mtd, buf, off, pagecount, read,
no_verify);
} else {
printf("Unknown nand command suffix '%s'.\n", s);
+ unmap_sysmem(buf);
return 1;
}
+ unmap_sysmem(buf);
printf(" %zu bytes %s: %s\n", rwsize,
read ? "read" : "written", ret ? "ERROR" : "OK");
*/
#define MAX_ENV_SIZE (1 << 20) /* 1 MiB */
-/*
- * This variable is incremented on each do_env_set(), so it can
- * be used via env_get_id() as an indication, if the environment
- * has changed or not. So it is possible to reread an environment
- * variable only if the environment was changed ... done so for
- * example in NetInitLoop()
- */
-static int env_id = 1;
-
-int env_get_id(void)
-{
- return env_id;
-}
-
#ifndef CONFIG_SPL_BUILD
/*
* Command interface: print one or all environment variables
#endif
#endif /* CONFIG_SPL_BUILD */
-/*
- * Set a new environment variable,
- * or replace or delete an existing one.
- */
-static int _do_env_set(int flag, int argc, char *const argv[], int env_flag)
-{
- int i, len;
- char *name, *value, *s;
- struct env_entry e, *ep;
-
- debug("Initial value for argc=%d\n", argc);
-
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI)
- if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
- return do_env_set_efi(NULL, flag, --argc, ++argv);
-#endif
-
- while (argc > 1 && **(argv + 1) == '-') {
- char *arg = *++argv;
-
- --argc;
- while (*++arg) {
- switch (*arg) {
- case 'f': /* force */
- env_flag |= H_FORCE;
- break;
- default:
- return CMD_RET_USAGE;
- }
- }
- }
- debug("Final value for argc=%d\n", argc);
- name = argv[1];
-
- if (strchr(name, '=')) {
- printf("## Error: illegal character '='"
- "in variable name \"%s\"\n", name);
- return 1;
- }
-
- env_id++;
-
- /* Delete only ? */
- if (argc < 3 || argv[2] == NULL) {
- int rc = hdelete_r(name, &env_htab, env_flag);
-
- /* If the variable didn't exist, don't report an error */
- return rc && rc != -ENOENT ? 1 : 0;
- }
-
- /*
- * Insert / replace new value
- */
- for (i = 2, len = 0; i < argc; ++i)
- len += strlen(argv[i]) + 1;
-
- value = malloc(len);
- if (value == NULL) {
- printf("## Can't malloc %d bytes\n", len);
- return 1;
- }
- for (i = 2, s = value; i < argc; ++i) {
- char *v = argv[i];
-
- while ((*s++ = *v++) != '\0')
- ;
- *(s - 1) = ' ';
- }
- if (s != value)
- *--s = '\0';
-
- e.key = name;
- e.data = value;
- hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag);
- free(value);
- if (!ep) {
- printf("## Error inserting \"%s\" variable, errno=%d\n",
- name, errno);
- return 1;
- }
-
- return 0;
-}
-
-int env_set(const char *varname, const char *varvalue)
-{
- const char * const argv[4] = { "setenv", varname, varvalue, NULL };
-
- /* before import into hashtable */
- if (!(gd->flags & GD_FLG_ENV_READY))
- return 1;
-
- if (varvalue == NULL || varvalue[0] == '\0')
- return _do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC);
- else
- return _do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
if (argc < 2)
return CMD_RET_USAGE;
- return _do_env_set(flag, argc, argv, H_INTERACTIVE);
+ return env_do_env_set(flag, argc, argv, H_INTERACTIVE);
}
/*
}
/* Continue calling setenv code */
- return _do_env_set(flag, len, local_args, H_INTERACTIVE);
+ return env_do_env_set(flag, len, local_args, H_INTERACTIVE);
}
#endif
if (buffer[0] == '\0') {
const char * const _argv[3] = { "setenv", argv[1], NULL };
- return _do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE);
+ return env_do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE);
} else {
const char * const _argv[4] = { "setenv", argv[1], buffer,
NULL };
- return _do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE);
+ return env_do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE);
}
}
#endif /* CONFIG_CMD_EDITENV */
}
debug("Final value for argc=%d\n", argc);
- env_id++;
+ env_inc_id();
while (--argc > 0) {
char *name = *++argv;
#ifdef CONFIG_PARTITION_TYPE_GUID
"part type <interface> <dev>:<part>\n"
" - print partition type\n"
-#endif
"part type <interface> <dev>:<part> <varname>\n"
" - set environment variable to partition type\n"
+#endif
"part set <interface> <dev> type\n"
" - set partition type for a device\n"
"part types\n"
"list - list UCLASS_PINCTRL devices\n"
"pinmux dev [pincontroller-name] - select pin-controller device\n"
"pinmux status [-a | pin-name] - print pin-controller muxing [for all | for pin-name]\n"
-)
+);
" - list : print firmware(s) currently loaded\n"
" - cpus : print online cpu number\n"
" - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
+);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SCMI (System Control and Management Interface) utility command
+ *
+ * Copyright (c) 2023 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include <command.h>
+#include <exports.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <stdlib.h>
+#include <asm/types.h>
+#include <dm/device.h>
+#include <dm/uclass.h> /* uclass_get_device */
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+struct {
+ enum scmi_std_protocol id;
+ const char *name;
+} protocol_name[] = {
+ {SCMI_PROTOCOL_ID_BASE, "Base"},
+ {SCMI_PROTOCOL_ID_POWER_DOMAIN, "Power domain management"},
+ {SCMI_PROTOCOL_ID_SYSTEM, "System power management"},
+ {SCMI_PROTOCOL_ID_PERF, "Performance domain management"},
+ {SCMI_PROTOCOL_ID_CLOCK, "Clock management"},
+ {SCMI_PROTOCOL_ID_SENSOR, "Sensor management"},
+ {SCMI_PROTOCOL_ID_RESET_DOMAIN, "Reset domain management"},
+ {SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"},
+};
+
+/**
+ * get_agent() - get SCMI agent device
+ *
+ * Return: Pointer to SCMI agent device on success, NULL on failure
+ */
+static struct udevice *get_agent(void)
+{
+ struct udevice *agent;
+
+ if (uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent)) {
+ printf("Cannot find any SCMI agent\n");
+ return NULL;
+ }
+
+ return agent;
+}
+
+/**
+ * get_base_proto() - get SCMI base protocol device
+ * @agent: SCMI agent device
+ *
+ * Return: Pointer to SCMI base protocol device on success,
+ * NULL on failure
+ */
+static struct udevice *get_base_proto(struct udevice *agent)
+{
+ struct udevice *base_proto;
+
+ if (!agent) {
+ agent = get_agent();
+ if (!agent)
+ return NULL;
+ }
+
+ base_proto = scmi_get_protocol(agent, SCMI_PROTOCOL_ID_BASE);
+ if (!base_proto) {
+ printf("SCMI base protocol not found\n");
+ return NULL;
+ }
+
+ return base_proto;
+}
+
+/**
+ * get_proto_name() - get the name of SCMI protocol
+ *
+ * @id: SCMI Protocol ID
+ *
+ * Get the printable name of the protocol, @id
+ *
+ * Return: Name string on success, NULL on failure
+ */
+static const char *get_proto_name(enum scmi_std_protocol id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(protocol_name); i++)
+ if (id == protocol_name[i].id)
+ return protocol_name[i].name;
+
+ return NULL;
+}
+
+/**
+ * do_scmi_info() - get the information of SCMI services
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Get the information of SCMI services using various interfaces
+ * provided by the Base protocol.
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *agent, *base_proto;
+ u32 agent_id, num_protocols;
+ u8 *agent_name, *protocols;
+ int i, ret;
+
+ if (argc != 1)
+ return CMD_RET_USAGE;
+
+ agent = get_agent();
+ if (!agent)
+ return CMD_RET_FAILURE;
+ base_proto = get_base_proto(agent);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ printf("SCMI device: %s\n", agent->name);
+ printf(" protocol version: 0x%x\n", scmi_version(agent));
+ printf(" # of agents: %d\n", scmi_num_agents(agent));
+ for (i = 0; i < scmi_num_agents(agent); i++) {
+ ret = scmi_base_discover_agent(base_proto, i, &agent_id,
+ &agent_name);
+ if (ret) {
+ if (ret != -EOPNOTSUPP)
+ printf("base_discover_agent() failed for id: %d (%d)\n",
+ i, ret);
+ break;
+ }
+ printf(" %c%2d: %s\n", i == scmi_agent_id(agent) ? '>' : ' ',
+ i, agent_name);
+ free(agent_name);
+ }
+ printf(" # of protocols: %d\n", scmi_num_protocols(agent));
+ num_protocols = scmi_num_protocols(agent);
+ protocols = scmi_protocols(agent);
+ if (protocols)
+ for (i = 0; i < num_protocols; i++)
+ printf(" %s\n", get_proto_name(protocols[i]));
+ printf(" vendor: %s\n", scmi_vendor(agent));
+ printf(" sub vendor: %s\n", scmi_sub_vendor(agent));
+ printf(" impl version: 0x%x\n", scmi_impl_version(agent));
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_set_dev() - set access permission to device
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Set access permission to device with SCMI_BASE_SET_DEVICE_PERMISSIONS
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_set_dev(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, device_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ device_id = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[3], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_SET_DEVICE_PERMISSIONS,
+ &attributes);
+ if (ret) {
+ printf("This operation is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_set_device_permissions(base_proto, agent_id,
+ device_id, flags);
+ if (ret) {
+ printf("%s access to device:%u failed (%d)\n",
+ flags ? "Allowing" : "Denying", device_id, ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_set_proto() - set protocol permission to device
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Set protocol permission to device with SCMI_BASE_SET_PROTOCOL_PERMISSIONS
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_set_proto(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, device_id, protocol_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ device_id = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ protocol_id = simple_strtoul(argv[3], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[4], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_SET_PROTOCOL_PERMISSIONS,
+ &attributes);
+ if (ret) {
+ printf("This operation is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_set_protocol_permissions(base_proto, agent_id,
+ device_id, protocol_id,
+ flags);
+ if (ret) {
+ printf("%s access to protocol:0x%x on device:%u failed (%d)\n",
+ flags ? "Allowing" : "Denying", protocol_id, device_id,
+ ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_reset() - reset platform resource settings
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Reset platform resource settings with BASE_RESET_AGENT_CONFIGURATION
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_reset(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_RESET_AGENT_CONFIGURATION,
+ &attributes);
+ if (ret) {
+ printf("Reset is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_reset_agent_configuration(base_proto, agent_id, flags);
+ if (ret) {
+ printf("Reset failed (%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_scmi_sub[] = {
+ U_BOOT_CMD_MKENT(info, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_info, "", ""),
+ U_BOOT_CMD_MKENT(perm_dev, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_set_dev, "", ""),
+ U_BOOT_CMD_MKENT(perm_proto, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_set_proto, "", ""),
+ U_BOOT_CMD_MKENT(reset, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_reset, "", ""),
+};
+
+/**
+ * do_scmi() - SCMI utility
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Provide user interfaces to SCMI protocols.
+ *
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ argc--; argv++;
+
+ cp = find_cmd_tbl(argv[0], cmd_scmi_sub, ARRAY_SIZE(cmd_scmi_sub));
+ if (!cp)
+ return CMD_RET_USAGE;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+static char scmi_help_text[] =
+ " - SCMI utility\n"
+ " info - get the info of SCMI services\n"
+ " perm_dev <agent-id in hex> <device-id in hex> <flags in hex>\n"
+ " - set access permission to device\n"
+ " perm_proto <agent-id in hex> <device-id in hex> <protocol-id in hex> <flags in hex>\n"
+ " - set protocol permission to device\n"
+ " reset <agent-id in hex> <flags in hex>\n"
+ " - reset platform resource settings\n"
+ "";
+
+U_BOOT_CMD(scmi, CONFIG_SYS_MAXARGS, 0, do_scmi, "SCMI utility",
+ scmi_help_text);
if (argc == 2) {
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
-#ifndef CONFIG_DM_SCSI
- scsi_bus_reset(NULL);
-#endif
ret = scsi_scan(true);
if (ret)
return CMD_RET_FAILURE;
}
U_BOOT_CMD(ufs, 3, 1, do_ufs,
- "UFS sub system",
+ "UFS sub-system",
"init [dev] - init UFS subsystem\n"
);
#include <common.h>
#include <command.h>
#include <display_options.h>
-#include <timestamp.h>
-#include <version.h>
#include <version_string.h>
#include <linux/compiler.h>
#ifdef CONFIG_SYS_COREBOOT
#include <asm/cb_sysinfo.h>
#endif
-#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
-
-const char version_string[] = U_BOOT_VERSION_STRING;
-const unsigned short version_num = U_BOOT_VERSION_NUM;
-const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
-
static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
#include <asm/cache.h>
#include <asm/io.h>
-#ifndef CFG_SYS_XIMG_LEN
-/* use 8MByte as default max gunzip size */
-#define CFG_SYS_XIMG_LEN 0x800000
-#endif
-
static int
do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
size_t fit_len;
#endif
#ifdef CONFIG_GZIP
- uint unc_len = CFG_SYS_XIMG_LEN;
+ uint unc_len = CONFIG_SYS_XIMG_LEN;
#endif
uint8_t comp;
The buffer is allocated immediately after the malloc() region is
ready.
+config SYS_CBSIZE
+ int "Console input buffer size"
+ default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
+ RCAR_GEN3 || TARGET_SOCFPGA_SOC64
+ default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
+ FSL_LSCH3 || X86
+ default 256 if M68K || PPC
+ default 1024
+ help
+ Set the size of the console input buffer. This is used both in the
+ case of reading input literally from the user in some manner as well
+ as when we need to construct or modify that type of input, for
+ example when constructing "bootargs" for the OS.
+
+config SYS_PBSIZE
+ int "Console output buffer size"
+ default 1024 if ARCH_SUNXI
+ default 1044
+ help
+ Set the size of the console output buffer. This is used when we need
+ to work with some form of a buffer while providing output in some
+ form to the user.
+
config DISABLE_CONSOLE
bool "Add functionality to disable console completely"
help
obj-y += init/
obj-y += main.o
obj-y += exports.o
-obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
+obj-y += cli_getch.o cli_simple.o cli_readline.o
+obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o
+obj-$(CONFIG_HUSH_MODERN_PARSER) += cli_hush_modern.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
+obj-y += version.o
# # boards
obj-y += board_f.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_UPDATE_COMMON) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
-obj-$(CONFIG_CMDLINE) += cli_getch.o cli_readline.o cli_simple.o
endif # !CONFIG_SPL_BUILD
#include <malloc.h>
#include <mapmem.h>
#include <spl.h>
+#include <tables_csum.h>
#include <asm/global_data.h>
#include <u-boot/crc.h>
* start address of the data in each blob is aligned as required. Note that
* each blob's *data* is aligned to BLOBLIST_ALIGN regardless of the alignment
* of the bloblist itself or the blob header.
- *
- * So far, only BLOBLIST_ALIGN alignment is supported.
*/
DECLARE_GLOBAL_DATA_PTR;
enum bloblist_tag_t tag;
const char *name;
} tag_name[] = {
- { BLOBLISTT_NONE, "(none)" },
+ { BLOBLISTT_VOID, "(void)" },
/* BLOBLISTT_AREA_FIRMWARE_TOP */
+ { BLOBLISTT_CONTROL_FDT, "Control FDT" },
+ { BLOBLISTT_HOB_BLOCK, "HOB block" },
+ { BLOBLISTT_HOB_LIST, "HOB list" },
+ { BLOBLISTT_ACPI_TABLES, "ACPI tables for x86" },
+ { BLOBLISTT_TPM_EVLOG, "TPM event log defined by TCG EFI" },
+ { BLOBLISTT_TPM_CRB_BASE, "TPM Command Response Buffer address" },
/* BLOBLISTT_AREA_FIRMWARE */
- { BLOBLISTT_ACPI_GNVS, "ACPI GNVS" },
- { BLOBLISTT_INTEL_VBT, "Intel Video-BIOS table" },
{ BLOBLISTT_TPM2_TCG_LOG, "TPM v2 log space" },
{ BLOBLISTT_TCPA_LOG, "TPM log space" },
- { BLOBLISTT_ACPI_TABLES, "ACPI tables for x86" },
+ { BLOBLISTT_ACPI_GNVS, "ACPI GNVS" },
+
+ /* BLOBLISTT_AREA_TF */
+ { BLOBLISTT_OPTEE_PAGABLE_PART, "OP-TEE pagable part" },
+
+ /* BLOBLISTT_AREA_OTHER */
+ { BLOBLISTT_INTEL_VBT, "Intel Video-BIOS table" },
{ BLOBLISTT_SMBIOS_TABLES, "SMBIOS tables for x86" },
{ BLOBLISTT_VBOOT_CTX, "Chrome OS vboot context" },
static struct bloblist_rec *bloblist_first_blob(struct bloblist_hdr *hdr)
{
- if (hdr->alloced <= hdr->hdr_size)
+ if (hdr->used_size <= hdr->hdr_size)
return NULL;
return (struct bloblist_rec *)((void *)hdr + hdr->hdr_size);
}
+static inline uint rec_hdr_size(struct bloblist_rec *rec)
+{
+ return (rec->tag_and_hdr_size & BLOBLISTR_HDR_SIZE_MASK) >>
+ BLOBLISTR_HDR_SIZE_SHIFT;
+}
+
+static inline uint rec_tag(struct bloblist_rec *rec)
+{
+ return (rec->tag_and_hdr_size & BLOBLISTR_TAG_MASK) >>
+ BLOBLISTR_TAG_SHIFT;
+}
+
static ulong bloblist_blob_end_ofs(struct bloblist_hdr *hdr,
struct bloblist_rec *rec)
{
ulong offset;
offset = (void *)rec - (void *)hdr;
- offset += rec->hdr_size + ALIGN(rec->size, BLOBLIST_ALIGN);
+ /*
+ * The data section of next TE should start from an address aligned
+ * to 1 << hdr->align_log2.
+ */
+ offset += rec_hdr_size(rec) + rec->size;
+ offset = round_up(offset + rec_hdr_size(rec), 1 << hdr->align_log2);
+ offset -= rec_hdr_size(rec);
return offset;
}
{
ulong offset = bloblist_blob_end_ofs(hdr, rec);
- if (offset >= hdr->alloced)
+ if (offset >= hdr->used_size)
return NULL;
return (struct bloblist_rec *)((void *)hdr + offset);
}
return NULL;
foreach_rec(rec, hdr) {
- if (rec->tag == tag)
+ if (rec_tag(rec) == tag)
return rec;
}
return NULL;
}
-static int bloblist_addrec(uint tag, int size, int align,
+static int bloblist_addrec(uint tag, int size, int align_log2,
struct bloblist_rec **recp)
{
struct bloblist_hdr *hdr = gd->bloblist;
struct bloblist_rec *rec;
- int data_start, new_alloced;
+ int data_start, aligned_start, new_alloced;
- if (!align)
- align = BLOBLIST_ALIGN;
+ if (!align_log2)
+ align_log2 = BLOBLIST_BLOB_ALIGN_LOG2;
/* Figure out where the new data will start */
- data_start = map_to_sysmem(hdr) + hdr->alloced + sizeof(*rec);
+ data_start = map_to_sysmem(hdr) + hdr->used_size + sizeof(*rec);
- /* Align the address and then calculate the offset from ->alloced */
- data_start = ALIGN(data_start, align) - map_to_sysmem(hdr);
+ /* Align the address and then calculate the offset from used size */
+ aligned_start = ALIGN(data_start, 1U << align_log2) - data_start;
+
+ /* If we need to create a dummy record, create it */
+ if (aligned_start) {
+ int void_size = aligned_start - sizeof(*rec);
+ struct bloblist_rec *vrec;
+ int ret;
+
+ ret = bloblist_addrec(BLOBLISTT_VOID, void_size, 0, &vrec);
+ if (ret)
+ return log_msg_ret("void", ret);
+
+ /* start the record after that */
+ data_start = map_to_sysmem(hdr) + hdr->used_size + sizeof(*vrec);
+ }
/* Calculate the new allocated total */
- new_alloced = data_start + ALIGN(size, align);
+ new_alloced = data_start - map_to_sysmem(hdr) +
+ ALIGN(size, 1U << align_log2);
- if (new_alloced > hdr->size) {
- log_err("Failed to allocate %x bytes size=%x, need size=%x\n",
- size, hdr->size, new_alloced);
+ if (new_alloced > hdr->total_size) {
+ log_err("Failed to allocate %x bytes\n", size);
+ log_err("Used size=%x, total size=%x\n",
+ hdr->used_size, hdr->total_size);
return log_msg_ret("bloblist add", -ENOSPC);
}
- rec = (void *)hdr + hdr->alloced;
+ rec = (void *)hdr + hdr->used_size;
- rec->tag = tag;
- rec->hdr_size = data_start - hdr->alloced;
+ rec->tag_and_hdr_size = tag | sizeof(*rec) << BLOBLISTR_HDR_SIZE_SHIFT;
rec->size = size;
- rec->spare = 0;
/* Zero the record data */
- memset((void *)rec + rec->hdr_size, '\0', rec->size);
+ memset((void *)rec + rec_hdr_size(rec), '\0', rec->size);
- hdr->alloced = new_alloced;
+ hdr->used_size = new_alloced;
*recp = rec;
return 0;
}
static int bloblist_ensurerec(uint tag, struct bloblist_rec **recp, int size,
- int align)
+ int align_log2)
{
struct bloblist_rec *rec;
} else {
int ret;
- ret = bloblist_addrec(tag, size, align, &rec);
+ ret = bloblist_addrec(tag, size, align_log2, &rec);
if (ret)
return ret;
}
if (size && size != rec->size)
return NULL;
- return (void *)rec + rec->hdr_size;
+ return (void *)rec + rec_hdr_size(rec);
}
-void *bloblist_add(uint tag, int size, int align)
+void *bloblist_add(uint tag, int size, int align_log2)
{
struct bloblist_rec *rec;
- if (bloblist_addrec(tag, size, align, &rec))
+ if (bloblist_addrec(tag, size, align_log2, &rec))
return NULL;
- return (void *)rec + rec->hdr_size;
+ return (void *)rec + rec_hdr_size(rec);
}
-int bloblist_ensure_size(uint tag, int size, int align, void **blobp)
+int bloblist_ensure_size(uint tag, int size, int align_log2, void **blobp)
{
struct bloblist_rec *rec;
int ret;
- ret = bloblist_ensurerec(tag, &rec, size, align);
+ ret = bloblist_ensurerec(tag, &rec, size, align_log2);
if (ret)
return ret;
- *blobp = (void *)rec + rec->hdr_size;
+ *blobp = (void *)rec + rec_hdr_size(rec);
return 0;
}
if (bloblist_ensurerec(tag, &rec, size, 0))
return NULL;
- return (void *)rec + rec->hdr_size;
+ return (void *)rec + rec_hdr_size(rec);
}
int bloblist_ensure_size_ret(uint tag, int *sizep, void **blobp)
*sizep = rec->size;
else if (ret)
return ret;
- *blobp = (void *)rec + rec->hdr_size;
+ *blobp = (void *)rec + rec_hdr_size(rec);
return 0;
}
int new_size)
{
int expand_by; /* Number of bytes to expand by (-ve to contract) */
- int new_alloced; /* New value for @hdr->alloced */
+ int new_alloced;
ulong next_ofs; /* Offset of the record after @rec */
- expand_by = ALIGN(new_size - rec->size, BLOBLIST_ALIGN);
- new_alloced = ALIGN(hdr->alloced + expand_by, BLOBLIST_ALIGN);
+ expand_by = ALIGN(new_size - rec->size, BLOBLIST_BLOB_ALIGN);
+ new_alloced = ALIGN(hdr->used_size + expand_by, BLOBLIST_BLOB_ALIGN);
if (new_size < 0) {
log_debug("Attempt to shrink blob size below 0 (%x)\n",
new_size);
return log_msg_ret("size", -EINVAL);
}
- if (new_alloced > hdr->size) {
- log_err("Failed to allocate %x bytes size=%x, need size=%x\n",
- new_size, hdr->size, new_alloced);
+ if (new_alloced > hdr->total_size) {
+ log_err("Failed to allocate %x bytes\n", new_size);
+ log_err("Used size=%x, total size=%x\n",
+ hdr->used_size, hdr->total_size);
return log_msg_ret("alloc", -ENOSPC);
}
/* Move the following blobs up or down, if this is not the last */
next_ofs = bloblist_blob_end_ofs(hdr, rec);
- if (next_ofs != hdr->alloced) {
+ if (next_ofs != hdr->used_size) {
memmove((void *)hdr + next_ofs + expand_by,
(void *)hdr + next_ofs, new_alloced - next_ofs);
}
- hdr->alloced = new_alloced;
+ hdr->used_size = new_alloced;
/* Zero the new part of the blob */
if (expand_by > 0) {
- memset((void *)rec + rec->hdr_size + rec->size, '\0',
+ memset((void *)rec + rec_hdr_size(rec) + rec->size, '\0',
new_size - rec->size);
}
static u32 bloblist_calc_chksum(struct bloblist_hdr *hdr)
{
- struct bloblist_rec *rec;
- u32 chksum;
+ u8 chksum;
- chksum = crc32(0, (unsigned char *)hdr,
- offsetof(struct bloblist_hdr, chksum));
- foreach_rec(rec, hdr) {
- chksum = crc32(chksum, (void *)rec, rec->hdr_size);
- chksum = crc32(chksum, (void *)rec + rec->hdr_size, rec->size);
- }
+ chksum = table_compute_checksum(hdr, hdr->used_size);
+ chksum += hdr->chksum;
return chksum;
}
-int bloblist_new(ulong addr, uint size, uint flags)
+int bloblist_new(ulong addr, uint size, uint flags, uint align_log2)
{
struct bloblist_hdr *hdr;
hdr->hdr_size = sizeof(*hdr);
hdr->flags = flags;
hdr->magic = BLOBLIST_MAGIC;
- hdr->size = size;
- hdr->alloced = hdr->hdr_size;
+ hdr->used_size = hdr->hdr_size;
+ hdr->total_size = size;
+ hdr->align_log2 = align_log2 ? align_log2 : BLOBLIST_BLOB_ALIGN_LOG2;
hdr->chksum = 0;
gd->bloblist = hdr;
return log_msg_ret("Bad magic", -ENOENT);
if (hdr->version != BLOBLIST_VERSION)
return log_msg_ret("Bad version", -EPROTONOSUPPORT);
- if (size && hdr->size != size)
- return log_msg_ret("Bad size", -EFBIG);
+ if (!hdr->total_size || (size && hdr->total_size != size))
+ return log_msg_ret("Bad total size", -EFBIG);
+ if (hdr->used_size > hdr->total_size)
+ return log_msg_ret("Bad used size", -ENOENT);
+ if (hdr->hdr_size != sizeof(struct bloblist_hdr))
+ return log_msg_ret("Bad header size", -ENOENT);
+
chksum = bloblist_calc_chksum(hdr);
if (hdr->chksum != chksum) {
log_err("Checksum %x != %x\n", hdr->chksum, chksum);
struct bloblist_hdr *hdr = gd->bloblist;
hdr->chksum = bloblist_calc_chksum(hdr);
- log_debug("Finished bloblist size %lx at %lx\n", (ulong)hdr->size,
+ log_debug("Finished bloblist size %lx at %lx\n", (ulong)hdr->used_size,
(ulong)map_to_sysmem(hdr));
return 0;
{
struct bloblist_hdr *hdr = gd->bloblist;
- return hdr->size;
+ return hdr->used_size;
+}
+
+ulong bloblist_get_total_size(void)
+{
+ struct bloblist_hdr *hdr = gd->bloblist;
+
+ return hdr->total_size;
}
-void bloblist_get_stats(ulong *basep, ulong *sizep, ulong *allocedp)
+void bloblist_get_stats(ulong *basep, ulong *tsizep, ulong *usizep)
{
struct bloblist_hdr *hdr = gd->bloblist;
*basep = map_to_sysmem(gd->bloblist);
- *sizep = hdr->size;
- *allocedp = hdr->alloced;
+ *tsizep = hdr->total_size;
+ *usizep = hdr->used_size;
}
static void show_value(const char *prompt, ulong value)
{
- printf("%s:%*s %-5lx ", prompt, 8 - (int)strlen(prompt), "", value);
+ printf("%s:%*s %-5lx ", prompt, 10 - (int)strlen(prompt), "", value);
print_size(value, "\n");
}
void bloblist_show_stats(void)
{
- ulong base, size, alloced;
+ ulong base, tsize, usize;
- bloblist_get_stats(&base, &size, &alloced);
- printf("base: %lx\n", base);
- show_value("size", size);
- show_value("alloced", alloced);
- show_value("free", size - alloced);
+ bloblist_get_stats(&base, &tsize, &usize);
+ printf("base: %lx\n", base);
+ show_value("total size", tsize);
+ show_value("used size", usize);
+ show_value("free", tsize - usize);
}
void bloblist_show_list(void)
for (rec = bloblist_first_blob(hdr); rec;
rec = bloblist_next_blob(hdr, rec)) {
printf("%08lx %8x %4x %s\n",
- (ulong)map_to_sysmem((void *)rec + rec->hdr_size),
- rec->size, rec->tag, bloblist_tag_name(rec->tag));
+ (ulong)map_to_sysmem((void *)rec + rec_hdr_size(rec)),
+ rec->size, rec_tag(rec),
+ bloblist_tag_name(rec_tag(rec)));
}
}
memcpy(to, from, from_size);
hdr = to;
- hdr->size = to_size;
+ hdr->total_size = to_size;
}
int bloblist_init(void)
addr, ret);
} else {
/* Get the real size, if it is not what we expected */
- size = gd->bloblist->size;
+ size = gd->bloblist->total_size;
}
}
if (ret) {
}
log_debug("Creating new bloblist size %lx at %lx\n", size,
addr);
- ret = bloblist_new(addr, size, 0);
+ ret = bloblist_new(addr, size, 0, 0);
} else {
log_debug("Found existing bloblist size %lx at %lx\n", size,
addr);
return 0;
}
-/*
- * Check sysinfo for board information. Failing that if the root node of the DTB
- * has a "model" property, show it.
- *
- * Then call checkboard().
- */
-int __weak show_board_info(void)
+static const struct to_show {
+ const char *name;
+ enum sysinfo_id id;
+} to_show[] = {
+ { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER},
+ { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION },
+ { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE },
+ { /* sentinel */ }
+};
+
+static int try_sysinfo(void)
+{
+ struct udevice *dev;
+ char str[80];
+ int ret;
+
+ /* This might provide more detail */
+ ret = sysinfo_get(&dev);
+ if (ret)
+ return ret;
+
+ ret = sysinfo_detect(dev);
+ if (ret)
+ return ret;
+
+ ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str);
+ if (ret)
+ return ret;
+ printf("Model: %s\n", str);
+
+ if (IS_ENABLED(CONFIG_SYSINFO_EXTRA)) {
+ const struct to_show *item;
+
+ for (item = to_show; item->id; item++) {
+ ret = sysinfo_get_str(dev, item->id, sizeof(str), str);
+ if (!ret)
+ printf("%s: %s\n", item->name, str);
+ }
+ }
+
+ return 0;
+}
+
+int show_board_info(void)
{
if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- struct udevice *dev;
- const char *model;
- char str[80];
int ret = -ENOSYS;
- if (IS_ENABLED(CONFIG_SYSINFO)) {
- /* This might provide more detail */
- ret = sysinfo_get(&dev);
- if (!ret) {
- ret = sysinfo_detect(dev);
- if (!ret) {
- ret = sysinfo_get_str(dev,
- SYSINFO_ID_BOARD_MODEL,
- sizeof(str), str);
- }
- }
- }
+ if (IS_ENABLED(CONFIG_SYSINFO))
+ ret = try_sysinfo();
/* Fail back to the main 'model' if available */
- if (ret)
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- else
- model = str;
+ if (ret) {
+ const char *model;
- if (model)
- printf("Model: %s\n", model);
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ if (model)
+ printf("Model: %s\n", model);
+ }
}
return checkboard();
}
#endif
-#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
-static int initr_scsi(void)
-{
- puts("SCSI: ");
- scsi_init();
- puts("\n");
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_CMD_NET
static int initr_net(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
-#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
- INIT_FUNC_WATCHDOG_RESET
- initr_scsi,
-#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init,
#endif
#include <linux/errno.h>
#ifdef CONFIG_CMDLINE
+
+static inline bool use_hush_old(void)
+{
+ return IS_ENABLED(CONFIG_HUSH_SELECTABLE) ?
+ gd->flags & GD_FLG_HUSH_OLD_PARSER :
+ IS_ENABLED(CONFIG_HUSH_OLD_PARSER);
+}
+
/*
* Run a command using the selected parser.
*
return 0;
#else
- int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP;
+ if (use_hush_old()) {
+ int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP;
- if (flag & CMD_FLAG_ENV)
- hush_flags |= FLAG_CONT_ON_NEWLINE;
- return parse_string_outer(cmd, hush_flags);
+ if (flag & CMD_FLAG_ENV)
+ hush_flags |= FLAG_CONT_ON_NEWLINE;
+ return parse_string_outer(cmd, hush_flags);
+ }
+ /*
+ * Possible values for flags are the following:
+ * FLAG_EXIT_FROM_LOOP: This flags ensures we exit from loop in
+ * parse_and_run_stream() after first iteration while normal
+ * behavior, * i.e. when called from cli_loop(), is to loop
+ * infinitely.
+ * FLAG_PARSE_SEMICOLON: modern Hush parses ';' and does not stop
+ * first time it sees one. So, I think we do not need this flag.
+ * FLAG_REPARSING: For the moment, I do not understand the goal
+ * of this flag.
+ * FLAG_CONT_ON_NEWLINE: This flag seems to be used to continue
+ * parsing even when reading '\n' when coming from
+ * run_command(). In this case, modern Hush reads until it finds
+ * '\0'. So, I think we do not need this flag.
+ */
+ return parse_string_outer_modern(cmd, FLAG_EXIT_FROM_LOOP);
#endif
}
#ifndef CONFIG_HUSH_PARSER
return cli_simple_run_command(cmd, flag);
#else
+ int ret;
+
+ if (use_hush_old()) {
+ ret = parse_string_outer(cmd,
+ FLAG_PARSE_SEMICOLON
+ | FLAG_EXIT_FROM_LOOP);
+ } else {
+ ret = parse_string_outer_modern(cmd,
+ FLAG_PARSE_SEMICOLON
+ | FLAG_EXIT_FROM_LOOP);
+ }
+
/*
* parse_string_outer() returns 1 for failure, so clean up
* its result.
*/
- if (parse_string_outer(cmd,
- FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP))
+ if (ret)
return -1;
return 0;
buff[len] = '\0';
}
#ifdef CONFIG_HUSH_PARSER
- rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
+ if (use_hush_old()) {
+ rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
+ } else {
+ rcode = parse_string_outer_modern(buff, FLAG_PARSE_SEMICOLON);
+ }
#else
/*
* This function will overwrite any \n it sees with a \0, which
void cli_loop(void)
{
bootstage_mark(BOOTSTAGE_ID_ENTER_CLI_LOOP);
-#ifdef CONFIG_HUSH_PARSER
- parse_file_outer();
+#if CONFIG_IS_ENABLED(HUSH_PARSER)
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER)
+ parse_and_run_file();
+ else if (gd->flags & GD_FLG_HUSH_OLD_PARSER)
+ parse_file_outer();
+
+ printf("Problem\n");
/* This point is never reached */
for (;;);
#elif defined(CONFIG_CMDLINE)
void cli_init(void)
{
#ifdef CONFIG_HUSH_PARSER
- u_boot_hush_start();
+ /* This if block is used to initialize hush parser gd flag. */
+ if (!(gd->flags & GD_FLG_HUSH_OLD_PARSER)
+ && !(gd->flags & GD_FLG_HUSH_MODERN_PARSER)) {
+ if (CONFIG_IS_ENABLED(HUSH_OLD_PARSER))
+ gd->flags |= GD_FLG_HUSH_OLD_PARSER;
+ else if (CONFIG_IS_ENABLED(HUSH_MODERN_PARSER))
+ gd->flags |= GD_FLG_HUSH_MODERN_PARSER;
+ }
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ u_boot_hush_start();
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ u_boot_hush_start_modern();
+ } else {
+ printf("No valid hush parser to use, cli will not initialized!\n");
+ return;
+ }
#endif
#if defined(CONFIG_HUSH_INIT_VAR)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file defines the compilation unit for the new hush shell version. The
+ * actual implementation from upstream BusyBox can be found in
+ * `cli_hush_upstream.c` which is included at the end of this file.
+ *
+ * This "wrapper" technique is used to keep the changes to the upstream version
+ * as minmal as possible. Instead, all defines and redefines necessary are done
+ * here, outside the upstream sources. This will hopefully make upgrades to
+ * newer revisions much easier.
+ *
+ * Copyright (c) 2021, Harald Seiler, DENX Software Engineering, hws@denx.de
+ */
+
+#include <env.h>
+#include <malloc.h> /* malloc, free, realloc*/
+#include <linux/ctype.h> /* isalpha, isdigit */
+#include <console.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <cli_hush.h>
+#include <command.h> /* find_cmd */
+#include <asm/global_data.h>
+
+/*
+ * BusyBox Version: UPDATE THIS WHEN PULLING NEW UPSTREAM REVISION!
+ */
+#define BB_VER "1.35.0.git7d1c7d833785"
+
+/*
+ * Define hush features by the names used upstream.
+ */
+#define ENABLE_HUSH_INTERACTIVE 1
+#define ENABLE_FEATURE_EDITING 1
+#define ENABLE_HUSH_IF 1
+#define ENABLE_HUSH_LOOPS 1
+/* No MMU in U-Boot */
+#define BB_MMU 0
+#define USE_FOR_NOMMU(...) __VA_ARGS__
+#define USE_FOR_MMU(...)
+
+/*
+ * Size-saving "small" ints (arch-dependent)
+ */
+#if CONFIG_IS_ENABLED(X86) || CONFIG_IS_ENABLED(X86_64) || CONFIG_IS_ENABLED(MIPS)
+/* add other arches which benefit from this... */
+typedef signed char smallint;
+typedef unsigned char smalluint;
+#else
+/* for arches where byte accesses generate larger code: */
+typedef int smallint;
+typedef unsigned smalluint;
+#endif
+
+/*
+ * Alignment defines used by BusyBox.
+ */
+#define ALIGN1 __attribute__((aligned(1)))
+#define ALIGN2 __attribute__((aligned(2)))
+#define ALIGN4 __attribute__((aligned(4)))
+#define ALIGN8 __attribute__((aligned(8)))
+#define ALIGN_PTR __attribute__((aligned(sizeof(void*))))
+
+/*
+ * Miscellaneous compiler/platform defines.
+ */
+#define FAST_FUNC /* not used in U-Boot */
+#define UNUSED_PARAM __always_unused
+#define ALWAYS_INLINE __always_inline
+#define NOINLINE noinline
+
+/*
+ * Defines to provide equivalents to what libc/BusyBox defines.
+ */
+#define EOF (-1)
+#define EXIT_SUCCESS 0
+#define EXIT_FAILURE 1
+
+/*
+ * Stubs to provide libc/BusyBox functions based on U-Boot equivalents where it
+ * makes sense.
+ */
+#define utoa simple_itoa
+
+static void __noreturn xfunc_die(void)
+{
+ panic("HUSH died!");
+}
+
+#define bb_error_msg_and_die(format, ...) do { \
+panic("HUSH: " format, __VA_ARGS__); \
+} while (0);
+
+#define bb_simple_error_msg_and_die(msg) do { \
+panic_str("HUSH: " msg); \
+} while (0);
+
+/* fdprintf() is used for debug output. */
+static int __maybe_unused fdprintf(int fd, const char *format, ...)
+{
+ va_list args;
+ uint i;
+
+ assert(fd == 2);
+
+ va_start(args, format);
+ i = vprintf(format, args);
+ va_end(args);
+
+ return i;
+}
+
+static void bb_verror_msg(const char *s, va_list p, const char* strerr)
+{
+ /* TODO: what to do with strerr arg? */
+ vprintf(s, p);
+}
+
+static void bb_error_msg(const char *s, ...)
+{
+ va_list p;
+
+ va_start(p, s);
+ bb_verror_msg(s, p, NULL);
+ va_end(p);
+}
+
+static void bb_simple_error_msg(const char *s)
+{
+ bb_error_msg("%s", s);
+}
+
+static void *xmalloc(size_t size)
+{
+ void *p = NULL;
+ if (!(p = malloc(size)))
+ panic("out of memory");
+ return p;
+}
+
+static void *xzalloc(size_t size)
+{
+ void *p = xmalloc(size);
+ memset(p, 0, size);
+ return p;
+}
+
+static void *xrealloc(void *ptr, size_t size)
+{
+ void *p = NULL;
+ if (!(p = realloc(ptr, size)))
+ panic("out of memory");
+ return p;
+}
+
+static void *xmemdup(const void *s, int n)
+{
+ return memcpy(xmalloc(n), s, n);
+}
+
+#define xstrdup strdup
+#define xstrndup strndup
+
+static void *mempcpy(void *dest, const void *src, size_t len)
+{
+ return memcpy(dest, src, len) + len;
+}
+
+/* Like strcpy but can copy overlapping strings. */
+static void overlapping_strcpy(char *dst, const char *src)
+{
+ /*
+ * Cheap optimization for dst == src case -
+ * better to have it here than in many callers.
+ */
+ if (dst != src) {
+ while ((*dst = *src) != '\0') {
+ dst++;
+ src++;
+ }
+ }
+}
+
+static char* skip_whitespace(const char *s)
+{
+ /*
+ * In POSIX/C locale (the only locale we care about: do we REALLY want
+ * to allow Unicode whitespace in, say, .conf files? nuts!)
+ * isspace is only these chars: "\t\n\v\f\r" and space.
+ * "\t\n\v\f\r" happen to have ASCII codes 9,10,11,12,13.
+ * Use that.
+ */
+ while (*s == ' ' || (unsigned char)(*s - 9) <= (13 - 9))
+ s++;
+
+ return (char *) s;
+}
+
+static char* skip_non_whitespace(const char *s)
+{
+ while (*s != '\0' && *s != ' ' && (unsigned char)(*s - 9) > (13 - 9))
+ s++;
+
+ return (char *) s;
+}
+
+#define is_name(c) ((c) == '_' || isalpha((unsigned char)(c)))
+#define is_in_name(c) ((c) == '_' || isalnum((unsigned char)(c)))
+
+static const char* endofname(const char *name)
+{
+ if (!is_name(*name))
+ return name;
+ while (*++name) {
+ if (!is_in_name(*name))
+ break;
+ }
+ return name;
+}
+
+/**
+ * list_size() - returns the number of elements in char ** before NULL.
+ *
+ * Argument must contain NULL to signalize its end.
+ *
+ * @list The list to count the number of element.
+ * @return The number of element in list.
+ */
+static size_t list_size(char **list)
+{
+ size_t size;
+
+ for (size = 0; list[size] != NULL; size++);
+
+ return size;
+}
+
+static int varcmp(const char *p, const char *q)
+{
+ int c, d;
+
+ while ((c = *p) == (d = *q)) {
+ if (c == '\0' || c == '=')
+ goto out;
+ p++;
+ q++;
+ }
+ if (c == '=')
+ c = '\0';
+ if (d == '=')
+ d = '\0';
+out:
+ return c - d;
+}
+
+struct in_str;
+static int u_boot_cli_readline(struct in_str *i);
+
+struct in_str;
+static int u_boot_cli_readline(struct in_str *i);
+
+/*
+ * BusyBox globals which are needed for hush.
+ */
+static uint8_t xfunc_error_retval;
+
+static const char defifsvar[] __aligned(1) = "IFS= \t\n";
+#define defifs (defifsvar + 4)
+
+/* This define is used to check if exit command was called. */
+#define EXIT_RET_CODE -2
+
+/*
+ * This define is used for changes that need be done directly in the upstream
+ * sources still. Ideally, its use should be minimized as much as possible.
+ */
+#define __U_BOOT__
+
+/*
+ *
+ * +-- Include of the upstream sources --+ *
+ * V V
+ */
+#include "cli_hush_upstream.c"
+/*
+ * A A
+ * +-- Include of the upstream sources --+ *
+ *
+ */
+
+int u_boot_hush_start_modern(void)
+{
+ INIT_G();
+ return 0;
+}
+
+static int u_boot_cli_readline(struct in_str *i)
+{
+ char *prompt;
+ char __maybe_unused *ps_prompt = NULL;
+
+ if (!G.promptmode)
+ prompt = CONFIG_SYS_PROMPT;
+#ifdef CONFIG_SYS_PROMPT_HUSH_PS2
+ else
+ prompt = CONFIG_SYS_PROMPT_HUSH_PS2;
+#else
+ /* TODO: default value? */
+ #error "SYS_PROMPT_HUSH_PS2 is not defined!"
+#endif
+
+ if (CONFIG_IS_ENABLED(CMDLINE_PS_SUPPORT)) {
+ if (!G.promptmode)
+ ps_prompt = env_get("PS1");
+ else
+ ps_prompt = env_get("PS2");
+
+ if (ps_prompt)
+ prompt = ps_prompt;
+ }
+
+ return cli_readline(prompt);
+}
--- /dev/null
+/* vi: set sw=4 ts=4: */
+/*
+ * A prototype Bourne shell grammar parser.
+ * Intended to follow the original Thompson and Ritchie
+ * "small and simple is beautiful" philosophy, which
+ * incidentally is a good match to today's BusyBox.
+ *
+ * Copyright (C) 2000,2001 Larry Doolittle <larry@doolittle.boa.org>
+ * Copyright (C) 2008,2009 Denys Vlasenko <vda.linux@googlemail.com>
+ *
+ * Licensed under GPLv2 or later, see file LICENSE in this source tree.
+ *
+ * Credits:
+ * The parser routines proper are all original material, first
+ * written Dec 2000 and Jan 2001 by Larry Doolittle. The
+ * execution engine, the builtins, and much of the underlying
+ * support has been adapted from busybox-0.49pre's lash, which is
+ * Copyright (C) 1999-2004 by Erik Andersen <andersen@codepoet.org>
+ * written by Erik Andersen <andersen@codepoet.org>. That, in turn,
+ * is based in part on ladsh.c, by Michael K. Johnson and Erik W.
+ * Troan, which they placed in the public domain. I don't know
+ * how much of the Johnson/Troan code has survived the repeated
+ * rewrites.
+ *
+ * Other credits:
+ * o_addchr derived from similar w_addchar function in glibc-2.2.
+ * parse_redirect, redirect_opt_num, and big chunks of main
+ * and many builtins derived from contributions by Erik Andersen.
+ * Miscellaneous bugfixes from Matt Kraai.
+ *
+ * There are two big (and related) architecture differences between
+ * this parser and the lash parser. One is that this version is
+ * actually designed from the ground up to understand nearly all
+ * of the Bourne grammar. The second, consequential change is that
+ * the parser and input reader have been turned inside out. Now,
+ * the parser is in control, and asks for input as needed. The old
+ * way had the input reader in control, and it asked for parsing to
+ * take place as needed. The new way makes it much easier to properly
+ * handle the recursion implicit in the various substitutions, especially
+ * across continuation lines.
+ *
+ * TODOs:
+ * grep for "TODO" and fix (some of them are easy)
+ * make complex ${var%...} constructs support optional
+ * make here documents optional
+ * special variables (done: PWD, PPID, RANDOM)
+ * follow IFS rules more precisely, including update semantics
+ * tilde expansion
+ * aliases
+ * "command" missing features:
+ * command -p CMD: run CMD using default $PATH
+ * (can use this to override standalone shell as well?)
+ * command BLTIN: disables special-ness (e.g. errors do not abort)
+ * command -V CMD1 CMD2 CMD3 (multiple args) (not in standard)
+ * builtins mandated by standards we don't support:
+ * [un]alias, fc:
+ * fc -l[nr] [BEG] [END]: list range of commands in history
+ * fc [-e EDITOR] [BEG] [END]: edit/rerun range of commands
+ * fc -s [PAT=REP] [CMD]: rerun CMD, replacing PAT with REP
+ *
+ * Bash compat TODO:
+ * redirection of stdout+stderr: &> and >&
+ * reserved words: function select
+ * advanced test: [[ ]]
+ * process substitution: <(list) and >(list)
+ * let EXPR [EXPR...]
+ * Each EXPR is an arithmetic expression (ARITHMETIC EVALUATION)
+ * If the last arg evaluates to 0, let returns 1; 0 otherwise.
+ * NB: let `echo 'a=a + 1'` - error (IOW: multi-word expansion is used)
+ * ((EXPR))
+ * The EXPR is evaluated according to ARITHMETIC EVALUATION.
+ * This is exactly equivalent to let "EXPR".
+ * $[EXPR]: synonym for $((EXPR))
+ * indirect expansion: ${!VAR}
+ * substring op on @: ${@:n:m}
+ *
+ * Won't do:
+ * Some builtins mandated by standards:
+ * newgrp [GRP]: not a builtin in bash but a suid binary
+ * which spawns a new shell with new group ID
+ *
+ * Status of [[ support:
+ * [[ args ]] are CMD_SINGLEWORD_NOGLOB:
+ * v='a b'; [[ $v = 'a b' ]]; echo 0:$?
+ * [[ /bin/n* ]]; echo 0:$?
+ * = is glob match operator, not equality operator: STR = GLOB
+ * == same as =
+ * =~ is regex match operator: STR =~ REGEX
+ * TODO:
+ * quoting needs to be considered (-f is an operator, "-f" and ""-f are not; etc)
+ * in word = GLOB, quoting should be significant on char-by-char basis: a*cd"*"
+ */
+//config:config HUSH
+//config: bool "hush (70 kb)"
+//config: default y
+//config: select SHELL_HUSH
+//config: help
+//config: hush is a small shell. It handles the normal flow control
+//config: constructs such as if/then/elif/else/fi, for/in/do/done, while loops,
+//config: case/esac. Redirections, here documents, $((arithmetic))
+//config: and functions are supported.
+//config:
+//config: It will compile and work on no-mmu systems.
+//config:
+//config: It does not handle select, aliases, tilde expansion,
+//config: &>file and >&file redirection of stdout+stderr.
+//config:
+// This option is visible (has a description) to make it possible to select
+// a "scripted" applet (such as NOLOGIN) but avoid selecting any shells:
+//config:config SHELL_HUSH
+//config: bool "Internal shell for embedded script support"
+//config: default n
+//config:
+//config:# hush options
+//config:# It's only needed to get "nice" menuconfig indenting.
+//config:if SHELL_HUSH || HUSH || SH_IS_HUSH || BASH_IS_HUSH
+//config:
+//config:config HUSH_BASH_COMPAT
+//config: bool "bash-compatible extensions"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_BRACE_EXPANSION
+//config: bool "Brace expansion"
+//config: default y
+//config: depends on HUSH_BASH_COMPAT
+//config: help
+//config: Enable {abc,def} extension.
+//config:
+//config:config HUSH_BASH_SOURCE_CURDIR
+//config: bool "'source' and '.' builtins search current directory after $PATH"
+//config: default n # do not encourage non-standard behavior
+//config: depends on HUSH_BASH_COMPAT
+//config: help
+//config: This is not compliant with standards. Avoid if possible.
+//config:
+//config:config HUSH_LINENO_VAR
+//config: bool "$LINENO variable (bashism)"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_INTERACTIVE
+//config: bool "Interactive mode"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable interactive mode (prompt and command editing).
+//config: Without this, hush simply reads and executes commands
+//config: from stdin just like a shell script from a file.
+//config: No prompt, no PS1/PS2 magic shell variables.
+//config:
+//config:config HUSH_SAVEHISTORY
+//config: bool "Save command history to .hush_history"
+//config: default y
+//config: depends on HUSH_INTERACTIVE && FEATURE_EDITING_SAVEHISTORY
+//config:
+//config:config HUSH_JOB
+//config: bool "Job control"
+//config: default y
+//config: depends on HUSH_INTERACTIVE
+//config: help
+//config: Enable job control: Ctrl-Z backgrounds, Ctrl-C interrupts current
+//config: command (not entire shell), fg/bg builtins work. Without this option,
+//config: "cmd &" still works by simply spawning a process and immediately
+//config: prompting for next command (or executing next command in a script),
+//config: but no separate process group is formed.
+//config:
+//config:config HUSH_TICK
+//config: bool "Support command substitution"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable `command` and $(command).
+//config:
+//config:config HUSH_IF
+//config: bool "Support if/then/elif/else/fi"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_LOOPS
+//config: bool "Support for, while and until loops"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_CASE
+//config: bool "Support case ... esac statement"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable case ... esac statement. +400 bytes.
+//config:
+//config:config HUSH_FUNCTIONS
+//config: bool "Support funcname() { commands; } syntax"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable support for shell functions. +800 bytes.
+//config:
+//config:config HUSH_LOCAL
+//config: bool "local builtin"
+//config: default y
+//config: depends on HUSH_FUNCTIONS
+//config: help
+//config: Enable support for local variables in functions.
+//config:
+//config:config HUSH_RANDOM_SUPPORT
+//config: bool "Pseudorandom generator and $RANDOM variable"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable pseudorandom generator and dynamic variable "$RANDOM".
+//config: Each read of "$RANDOM" will generate a new pseudorandom value.
+//config:
+//config:config HUSH_MODE_X
+//config: bool "Support 'hush -x' option and 'set -x' command"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: This instructs hush to print commands before execution.
+//config: Adds ~300 bytes.
+//config:
+//config:config HUSH_ECHO
+//config: bool "echo builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_PRINTF
+//config: bool "printf builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_TEST
+//config: bool "test builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_HELP
+//config: bool "help builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_EXPORT
+//config: bool "export builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_EXPORT_N
+//config: bool "Support 'export -n' option"
+//config: default y
+//config: depends on HUSH_EXPORT
+//config: help
+//config: export -n unexports variables. It is a bash extension.
+//config:
+//config:config HUSH_READONLY
+//config: bool "readonly builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config: help
+//config: Enable support for read-only variables.
+//config:
+//config:config HUSH_KILL
+//config: bool "kill builtin (supports kill %jobspec)"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_WAIT
+//config: bool "wait builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_COMMAND
+//config: bool "command builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_TRAP
+//config: bool "trap builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_TYPE
+//config: bool "type builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_TIMES
+//config: bool "times builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_READ
+//config: bool "read builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_SET
+//config: bool "set builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_UNSET
+//config: bool "unset builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_ULIMIT
+//config: bool "ulimit builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_UMASK
+//config: bool "umask builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_GETOPTS
+//config: bool "getopts builtin"
+//config: default y
+//config: depends on SHELL_HUSH
+//config:
+//config:config HUSH_MEMLEAK
+//config: bool "memleak builtin (debugging)"
+//config: default n
+//config: depends on SHELL_HUSH
+//config:
+//config:endif # hush options
+
+//applet:IF_HUSH(APPLET(hush, BB_DIR_BIN, BB_SUID_DROP))
+// APPLET_ODDNAME:name main location suid_type help
+//applet:IF_SH_IS_HUSH( APPLET_ODDNAME(sh, hush, BB_DIR_BIN, BB_SUID_DROP, hush))
+//applet:IF_BASH_IS_HUSH(APPLET_ODDNAME(bash, hush, BB_DIR_BIN, BB_SUID_DROP, hush))
+
+//kbuild:lib-$(CONFIG_SHELL_HUSH) += hush.o match.o shell_common.o
+//kbuild:lib-$(CONFIG_HUSH_RANDOM_SUPPORT) += random.o
+
+/* -i (interactive) is also accepted,
+ * but does nothing, therefore not shown in help.
+ * NOMMU-specific options are not meant to be used by users,
+ * therefore we don't show them either.
+ */
+//usage:#define hush_trivial_usage
+//usage: "[-enxl] [-c 'SCRIPT' [ARG0 ARGS] | FILE ARGS | -s ARGS]"
+//usage:#define hush_full_usage "\n\n"
+//usage: "Unix shell interpreter"
+
+#ifndef __U_BOOT__
+#if !(defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) \
+ || defined(__APPLE__) \
+ )
+# include <malloc.h> /* for malloc_trim */
+#endif
+#include <glob.h>
+/* #include <dmalloc.h> */
+#if ENABLE_HUSH_CASE
+# include <fnmatch.h>
+#endif
+#include <sys/times.h>
+#include <sys/utsname.h> /* for setting $HOSTNAME */
+
+#include "busybox.h" /* for APPLET_IS_NOFORK/NOEXEC */
+#include "unicode.h"
+#include "shell_common.h"
+#include "math.h"
+#include "match.h"
+#if ENABLE_HUSH_RANDOM_SUPPORT
+# include "random.h"
+#else
+# define CLEAR_RANDOM_T(rnd) ((void)0)
+#endif
+#ifndef O_CLOEXEC
+# define O_CLOEXEC 0
+#endif
+#ifndef F_DUPFD_CLOEXEC
+# define F_DUPFD_CLOEXEC F_DUPFD
+#endif
+
+#if ENABLE_FEATURE_SH_EMBEDDED_SCRIPTS && !ENABLE_SHELL_ASH
+# include "embedded_scripts.h"
+#else
+# define NUM_SCRIPTS 0
+#endif
+#endif /* !__U_BOOT__ */
+
+/* So far, all bash compat is controlled by one config option */
+/* Separate defines document which part of code implements what */
+#define BASH_PATTERN_SUBST ENABLE_HUSH_BASH_COMPAT
+#define BASH_SUBSTR ENABLE_HUSH_BASH_COMPAT
+#define BASH_SOURCE ENABLE_HUSH_BASH_COMPAT
+#define BASH_DOLLAR_SQUOTE ENABLE_HUSH_BASH_COMPAT
+#define BASH_HOSTNAME_VAR ENABLE_HUSH_BASH_COMPAT
+#define BASH_EPOCH_VARS ENABLE_HUSH_BASH_COMPAT
+#define BASH_TEST2 (ENABLE_HUSH_BASH_COMPAT && ENABLE_HUSH_TEST)
+#define BASH_READ_D ENABLE_HUSH_BASH_COMPAT
+
+
+/* Build knobs */
+#define LEAK_HUNTING 0
+#define BUILD_AS_NOMMU 0
+/* Enable/disable sanity checks. Ok to enable in production,
+ * only adds a bit of bloat. Set to >1 to get non-production level verbosity.
+ * Keeping 1 for now even in released versions.
+ */
+#define HUSH_DEBUG 1
+/* Slightly bigger (+200 bytes), but faster hush.
+ * So far it only enables a trick with counting SIGCHLDs and forks,
+ * which allows us to do fewer waitpid's.
+ * (we can detect a case where neither forks were done nor SIGCHLDs happened
+ * and therefore waitpid will return the same result as last time)
+ */
+#define ENABLE_HUSH_FAST 0
+/* TODO: implement simplified code for users which do not need ${var%...} ops
+ * So far ${var%...} ops are always enabled:
+ */
+#define ENABLE_HUSH_DOLLAR_OPS 1
+
+
+#if BUILD_AS_NOMMU
+# undef BB_MMU
+# undef USE_FOR_NOMMU
+# undef USE_FOR_MMU
+# define BB_MMU 0
+# define USE_FOR_NOMMU(...) __VA_ARGS__
+# define USE_FOR_MMU(...)
+#endif
+
+#ifndef __U_BOOT__
+#include "NUM_APPLETS.h"
+#if NUM_APPLETS == 1
+/* STANDALONE does not make sense, and won't compile */
+# undef ENABLE_FEATURE_SH_STANDALONE
+# undef IF_FEATURE_SH_STANDALONE
+# undef IF_NOT_FEATURE_SH_STANDALONE
+# define ENABLE_FEATURE_SH_STANDALONE 0
+# define IF_FEATURE_SH_STANDALONE(...)
+# define IF_NOT_FEATURE_SH_STANDALONE(...) __VA_ARGS__
+#endif
+#endif /* __U_BOOT__ */
+
+#if !ENABLE_HUSH_INTERACTIVE
+# undef ENABLE_FEATURE_EDITING
+# define ENABLE_FEATURE_EDITING 0
+# undef ENABLE_FEATURE_EDITING_FANCY_PROMPT
+# define ENABLE_FEATURE_EDITING_FANCY_PROMPT 0
+# undef ENABLE_FEATURE_EDITING_SAVE_ON_EXIT
+# define ENABLE_FEATURE_EDITING_SAVE_ON_EXIT 0
+#endif
+
+/* Do we support ANY keywords? */
+#if ENABLE_HUSH_IF || ENABLE_HUSH_LOOPS || ENABLE_HUSH_CASE
+# define HAS_KEYWORDS 1
+# define IF_HAS_KEYWORDS(...) __VA_ARGS__
+# define IF_HAS_NO_KEYWORDS(...)
+#else
+# define HAS_KEYWORDS 0
+# define IF_HAS_KEYWORDS(...)
+# define IF_HAS_NO_KEYWORDS(...) __VA_ARGS__
+#endif
+
+/* If you comment out one of these below, it will be #defined later
+ * to perform debug printfs to stderr: */
+#define debug_printf(...) do {} while (0)
+/* Finer-grained debug switches */
+#define debug_printf_parse(...) do {} while (0)
+#define debug_printf_heredoc(...) do {} while (0)
+#define debug_print_tree(a, b) do {} while (0)
+#define debug_printf_exec(...) do {} while (0)
+#define debug_printf_env(...) do {} while (0)
+#define debug_printf_jobs(...) do {} while (0)
+#define debug_printf_expand(...) do {} while (0)
+#define debug_printf_varexp(...) do {} while (0)
+#define debug_printf_glob(...) do {} while (0)
+#define debug_printf_redir(...) do {} while (0)
+#define debug_printf_list(...) do {} while (0)
+#define debug_printf_subst(...) do {} while (0)
+#define debug_printf_prompt(...) do {} while (0)
+#define debug_printf_clean(...) do {} while (0)
+
+#define ERR_PTR ((void*)(long)1)
+
+#define JOB_STATUS_FORMAT "[%u] %-22s %.40s\n"
+
+#define _SPECIAL_VARS_STR "_*@$!?#-"
+#ifndef __U_BOOT__
+#define SPECIAL_VARS_STR ("_*@$!?#-" + 1)
+#define NUMERIC_SPECVARS_STR ("_*@$!?#-" + 3)
+#else /* __U_BOOT__ */
+#define SPECIAL_VARS_STR "*@$!?#-"
+#define NUMERIC_SPECVARS_STR "$!?#-"
+#endif /* __U_BOOT__ */
+#if BASH_PATTERN_SUBST
+/* Support / and // replace ops */
+/* Note that // is stored as \ in "encoded" string representation */
+# define VAR_ENCODED_SUBST_OPS "\\/%#:-=+?"
+# define VAR_SUBST_OPS ("\\/%#:-=+?" + 1)
+# define MINUS_PLUS_EQUAL_QUESTION ("\\/%#:-=+?" + 5)
+#else
+# define VAR_ENCODED_SUBST_OPS "%#:-=+?"
+# define VAR_SUBST_OPS "%#:-=+?"
+# define MINUS_PLUS_EQUAL_QUESTION ("%#:-=+?" + 3)
+#endif
+
+#define SPECIAL_VAR_SYMBOL_STR "\3"
+#define SPECIAL_VAR_SYMBOL 3
+/* The "variable" with name "\1" emits string "\3". Testcase: "echo ^C" */
+#define SPECIAL_VAR_QUOTED_SVS 1
+
+struct variable;
+
+static const char hush_version_str[] ALIGN1 = "HUSH_VERSION="BB_VER;
+
+/* This supports saving pointers malloced in vfork child,
+ * to be freed in the parent.
+ */
+#if !BB_MMU
+typedef struct nommu_save_t {
+ struct variable *old_vars;
+ char **argv;
+ char **argv_from_re_execing;
+} nommu_save_t;
+#endif
+
+
+enum {
+ RES_NONE = 0,
+#if ENABLE_HUSH_IF
+ RES_IF ,
+ RES_THEN ,
+ RES_ELIF ,
+ RES_ELSE ,
+ RES_FI ,
+#endif
+#if ENABLE_HUSH_LOOPS
+ RES_FOR ,
+ RES_WHILE ,
+ RES_UNTIL ,
+ RES_DO ,
+ RES_DONE ,
+#endif
+#if ENABLE_HUSH_LOOPS || ENABLE_HUSH_CASE
+ RES_IN ,
+#endif
+#if ENABLE_HUSH_CASE
+ RES_CASE ,
+ /* three pseudo-keywords support contrived "case" syntax: */
+ RES_CASE_IN, /* "case ... IN", turns into RES_MATCH when IN is observed */
+ RES_MATCH , /* "word)" */
+ RES_CASE_BODY, /* "this command is inside CASE" */
+ RES_ESAC ,
+#endif
+ RES_XXXX ,
+ RES_SNTX
+};
+
+typedef struct o_string {
+ char *data;
+ int length; /* position where data is appended */
+ int maxlen;
+ int o_expflags;
+ /* At least some part of the string was inside '' or "",
+ * possibly empty one: word"", wo''rd etc. */
+ smallint has_quoted_part;
+ smallint has_empty_slot;
+ smallint ended_in_ifs;
+} o_string;
+enum {
+ EXP_FLAG_SINGLEWORD = 0x80, /* must be 0x80 */
+ EXP_FLAG_GLOB = 0x2,
+ /* Protect newly added chars against globbing
+ * by prepending \ to *, ?, [, \ */
+ EXP_FLAG_ESC_GLOB_CHARS = 0x1,
+};
+/* Used for initialization: o_string foo = NULL_O_STRING; */
+#define NULL_O_STRING { NULL }
+
+#ifndef debug_printf_parse
+static const char *const assignment_flag[] ALIGN_PTR = {
+ "MAYBE_ASSIGNMENT",
+ "DEFINITELY_ASSIGNMENT",
+ "NOT_ASSIGNMENT",
+ "WORD_IS_KEYWORD",
+};
+#endif
+
+/* We almost can use standard FILE api, but we need an ability to move
+ * its fd when redirects coincide with it. No api exists for that
+ * (RFE for it at https://sourceware.org/bugzilla/show_bug.cgi?id=21902).
+ * HFILE is our internal alternative. Only supports reading.
+ * Since we now can, we incorporate linked list of all opened HFILEs
+ * into the struct (used to be a separate mini-list).
+ */
+typedef struct HFILE {
+ char *cur;
+ char *end;
+ struct HFILE *next_hfile;
+ int fd;
+ char buf[1024];
+} HFILE;
+
+typedef struct in_str {
+ const char *p;
+ int peek_buf[2];
+ int last_char;
+ HFILE *file;
+} in_str;
+
+#ifndef __U_BOOT__
+/* The descrip member of this structure is only used to make
+ * debugging output pretty */
+static const struct {
+ int32_t mode;
+ signed char default_fd;
+ char descrip[3];
+} redir_table[] ALIGN4 = {
+ { O_RDONLY, 0, "<" },
+ { O_CREAT|O_TRUNC|O_WRONLY, 1, ">" },
+ { O_CREAT|O_APPEND|O_WRONLY, 1, ">>" },
+ { O_CREAT|O_RDWR, 1, "<>" },
+ { O_RDONLY, 0, "<<" },
+/* Should not be needed. Bogus default_fd helps in debugging */
+/* { O_RDONLY, 77, "<<" }, */
+};
+
+struct redir_struct {
+ struct redir_struct *next;
+ char *rd_filename; /* filename */
+ int rd_fd; /* fd to redirect */
+ /* fd to redirect to, or -3 if rd_fd is to be closed (n>&-) */
+ int rd_dup;
+ smallint rd_type; /* (enum redir_type) */
+ /* note: for heredocs, rd_filename contains heredoc delimiter,
+ * and subsequently heredoc itself; and rd_dup is a bitmask:
+ * bit 0: do we need to trim leading tabs?
+ * bit 1: is heredoc quoted (<<'delim' syntax) ?
+ */
+};
+typedef enum redir_type {
+ REDIRECT_INPUT = 0,
+ REDIRECT_OVERWRITE = 1,
+ REDIRECT_APPEND = 2,
+ REDIRECT_IO = 3,
+ REDIRECT_HEREDOC = 4,
+ REDIRECT_HEREDOC2 = 5, /* REDIRECT_HEREDOC after heredoc is loaded */
+
+ REDIRFD_CLOSE = -3,
+ REDIRFD_SYNTAX_ERR = -2,
+ REDIRFD_TO_FILE = -1,
+ /* otherwise, rd_fd is redirected to rd_dup */
+
+ HEREDOC_SKIPTABS = 1,
+ HEREDOC_QUOTED = 2,
+} redir_type;
+
+#endif /* !__U_BOOT__ */
+
+struct command {
+#ifndef __U_BOOT__
+ pid_t pid; /* 0 if exited */
+#endif /* !__U_BOOT__ */
+ unsigned assignment_cnt; /* how many argv[i] are assignments? */
+#if ENABLE_HUSH_LINENO_VAR
+ unsigned lineno;
+#endif
+ smallint cmd_type; /* CMD_xxx */
+#define CMD_NORMAL 0
+#define CMD_SUBSHELL 1
+#if BASH_TEST2
+/* used for "[[ EXPR ]]" */
+# define CMD_TEST2_SINGLEWORD_NOGLOB 2
+#endif
+#if BASH_TEST2 || ENABLE_HUSH_LOCAL || ENABLE_HUSH_EXPORT || ENABLE_HUSH_READONLY
+/* used to prevent word splitting and globbing in "export v=t*" */
+# define CMD_SINGLEWORD_NOGLOB 3
+#endif
+#if ENABLE_HUSH_FUNCTIONS
+# define CMD_FUNCDEF 4
+#endif
+
+ smalluint cmd_exitcode;
+ /* if non-NULL, this "command" is { list }, ( list ), or a compound statement */
+ struct pipe *group;
+#if !BB_MMU
+ char *group_as_string;
+#endif
+#if ENABLE_HUSH_FUNCTIONS
+ struct function *child_func;
+/* This field is used to prevent a bug here:
+ * while...do f1() {a;}; f1; f1() {b;}; f1; done
+ * When we execute "f1() {a;}" cmd, we create new function and clear
+ * cmd->group, cmd->group_as_string, cmd->argv[0].
+ * When we execute "f1() {b;}", we notice that f1 exists,
+ * and that its "parent cmd" struct is still "alive",
+ * we put those fields back into cmd->xxx
+ * (struct function has ->parent_cmd ptr to facilitate that).
+ * When we loop back, we can execute "f1() {a;}" again and set f1 correctly.
+ * Without this trick, loop would execute a;b;b;b;...
+ * instead of correct sequence a;b;a;b;...
+ * When command is freed, it severs the link
+ * (sets ->child_func->parent_cmd to NULL).
+ */
+#endif
+#ifdef __U_BOOT__
+ int argc; /* number of program arguments */
+#endif
+ char **argv; /* command name and arguments */
+/* argv vector may contain variable references (^Cvar^C, ^C0^C etc)
+ * and on execution these are substituted with their values.
+ * Substitution can make _several_ words out of one argv[n]!
+ * Example: argv[0]=='.^C*^C.' here: echo .$*.
+ * References of the form ^C`cmd arg^C are `cmd arg` substitutions.
+ */
+#ifndef __U_BOOT__
+ struct redir_struct *redirects; /* I/O redirections */
+#endif /* !__U_BOOT__ */
+};
+/* Is there anything in this command at all? */
+#ifndef __U_BOOT__
+#define IS_NULL_CMD(cmd) \
+ (!(cmd)->group && !(cmd)->argv && !(cmd)->redirects)
+
+#else /* __U_BOOT__ */
+#define IS_NULL_CMD(cmd) \
+ (!(cmd)->group && !(cmd)->argv)
+#endif /* __U_BOOT__ */
+struct pipe {
+ struct pipe *next;
+ int num_cmds; /* total number of commands in pipe */
+#ifndef __U_BOOT__
+ int alive_cmds; /* number of commands running (not exited) */
+ int stopped_cmds; /* number of commands alive, but stopped */
+#if ENABLE_HUSH_JOB
+ unsigned jobid; /* job number */
+ pid_t pgrp; /* process group ID for the job */
+ char *cmdtext; /* name of job */
+#endif
+#endif /* !__U_BOOT__ */
+ struct command *cmds; /* array of commands in pipe */
+ smallint followup; /* PIPE_BG, PIPE_SEQ, PIPE_OR, PIPE_AND */
+ IF_HAS_KEYWORDS(smallint pi_inverted;) /* "! cmd | cmd" */
+ IF_HAS_KEYWORDS(smallint res_word;) /* needed for if, for, while, until... */
+};
+typedef enum pipe_style {
+ PIPE_SEQ = 0,
+ PIPE_AND = 1,
+ PIPE_OR = 2,
+ PIPE_BG = 3,
+} pipe_style;
+/* Is there anything in this pipe at all? */
+#define IS_NULL_PIPE(pi) \
+ ((pi)->num_cmds == 0 IF_HAS_KEYWORDS( && (pi)->res_word == RES_NONE))
+
+/* This holds pointers to the various results of parsing */
+struct parse_context {
+ /* linked list of pipes */
+ struct pipe *list_head;
+ /* last pipe (being constructed right now) */
+ struct pipe *pipe;
+ /* last command in pipe (being constructed right now) */
+ struct command *command;
+#ifndef __U_BOOT__
+ /* last redirect in command->redirects list */
+ struct redir_struct *pending_redirect;
+#endif /* !__U_BOOT__ */
+ o_string word;
+#if !BB_MMU
+ o_string as_string;
+#endif
+ smallint is_assignment; /* 0:maybe, 1:yes, 2:no, 3:keyword */
+#if HAS_KEYWORDS
+ smallint ctx_res_w;
+ smallint ctx_inverted; /* "! cmd | cmd" */
+#if ENABLE_HUSH_CASE
+ smallint ctx_dsemicolon; /* ";;" seen */
+#endif
+ /* bitmask of FLAG_xxx, for figuring out valid reserved words */
+ int old_flag;
+ /* group we are enclosed in:
+ * example: "if pipe1; pipe2; then pipe3; fi"
+ * when we see "if" or "then", we malloc and copy current context,
+ * and make ->stack point to it. then we parse pipeN.
+ * when closing "then" / fi" / whatever is found,
+ * we move list_head into ->stack->command->group,
+ * copy ->stack into current context, and delete ->stack.
+ * (parsing of { list } and ( list ) doesn't use this method)
+ */
+ struct parse_context *stack;
+#endif
+};
+enum {
+ MAYBE_ASSIGNMENT = 0,
+ DEFINITELY_ASSIGNMENT = 1,
+ NOT_ASSIGNMENT = 2,
+ /* Not an assignment, but next word may be: "if v=xyz cmd;" */
+ WORD_IS_KEYWORD = 3,
+};
+
+#ifndef __U_BOOT__
+/* On program start, environ points to initial environment.
+ * putenv adds new pointers into it, unsetenv removes them.
+ * Neither of these (de)allocates the strings.
+ * setenv allocates new strings in malloc space and does putenv,
+ * and thus setenv is unusable (leaky) for shell's purposes */
+#define setenv(...) setenv_is_leaky_dont_use()
+#endif /* !__U_BOOT__ */
+struct variable {
+ struct variable *next;
+ char *varstr; /* points to "name=" portion */
+ int max_len; /* if > 0, name is part of initial env; else name is malloced */
+#ifndef __U_BOOT__
+ uint16_t var_nest_level;
+ smallint flg_export; /* putenv should be done on this var */
+ smallint flg_read_only;
+#endif /* !__U_BOOT__ */
+};
+
+enum {
+ BC_BREAK = 1,
+ BC_CONTINUE = 2,
+};
+
+#if ENABLE_HUSH_FUNCTIONS
+struct function {
+ struct function *next;
+ char *name;
+ struct command *parent_cmd;
+ struct pipe *body;
+# if !BB_MMU
+ char *body_as_string;
+# endif
+};
+#endif
+
+
+/* set -/+o OPT support. (TODO: make it optional)
+ * bash supports the following opts:
+ * allexport off
+ * braceexpand on
+ * emacs on
+ * errexit off
+ * errtrace off
+ * functrace off
+ * hashall on
+ * histexpand off
+ * history on
+ * ignoreeof off
+ * interactive-comments on
+ * keyword off
+ * monitor on
+ * noclobber off
+ * noexec off
+ * noglob off
+ * nolog off
+ * notify off
+ * nounset off
+ * onecmd off
+ * physical off
+ * pipefail off
+ * posix off
+ * privileged off
+ * verbose off
+ * vi off
+ * xtrace off
+ */
+static const char o_opt_strings[] ALIGN1 =
+ "pipefail\0"
+ "noexec\0"
+ "errexit\0"
+#if ENABLE_HUSH_MODE_X
+ "xtrace\0"
+#endif
+ ;
+enum {
+ OPT_O_PIPEFAIL,
+ OPT_O_NOEXEC,
+ OPT_O_ERREXIT,
+#if ENABLE_HUSH_MODE_X
+ OPT_O_XTRACE,
+#endif
+ NUM_OPT_O
+};
+
+/* "Globals" within this file */
+/* Sorted roughly by size (smaller offsets == smaller code) */
+struct globals {
+#ifndef __U_BOOT__
+ /* interactive_fd != 0 means we are an interactive shell.
+ * If we are, then saved_tty_pgrp can also be != 0, meaning
+ * that controlling tty is available. With saved_tty_pgrp == 0,
+ * job control still works, but terminal signals
+ * (^C, ^Z, ^Y, ^\) won't work at all, and background
+ * process groups can only be created with "cmd &".
+ * With saved_tty_pgrp != 0, hush will use tcsetpgrp()
+ * to give tty to the foreground process group,
+ * and will take it back when the group is stopped (^Z)
+ * or killed (^C).
+ */
+#if ENABLE_HUSH_INTERACTIVE
+ /* 'interactive_fd' is a fd# open to ctty, if we have one
+ * _AND_ if we decided to act interactively */
+ int interactive_fd;
+ IF_NOT_FEATURE_EDITING_FANCY_PROMPT(char *PS1;)
+# define G_interactive_fd (G.interactive_fd)
+#else
+# define G_interactive_fd 0
+#endif
+#else /* __U_BOOT__ */
+# define G_interactive_fd 0
+#endif /* __U_BOOT__ */
+#ifndef __U_BOOT__
+#if ENABLE_FEATURE_EDITING
+ line_input_t *line_input_state;
+#endif
+ pid_t root_pid;
+ pid_t root_ppid;
+ pid_t last_bg_pid;
+#if ENABLE_HUSH_RANDOM_SUPPORT
+ random_t random_gen;
+#endif
+#if ENABLE_HUSH_JOB
+ int run_list_level;
+ unsigned last_jobid;
+ pid_t saved_tty_pgrp;
+ struct pipe *job_list;
+# define G_saved_tty_pgrp (G.saved_tty_pgrp)
+#else
+# define G_saved_tty_pgrp 0
+#endif
+#endif /* !__U_BOOT__ */
+ /* How deeply are we in context where "set -e" is ignored */
+ int errexit_depth;
+#ifndef __U_BOOT__
+ /* "set -e" rules (do we follow them correctly?):
+ * Exit if pipe, list, or compound command exits with a non-zero status.
+ * Shell does not exit if failed command is part of condition in
+ * if/while, part of && or || list except the last command, any command
+ * in a pipe but the last, or if the command's return value is being
+ * inverted with !. If a compound command other than a subshell returns a
+ * non-zero status because a command failed while -e was being ignored, the
+ * shell does not exit. A trap on ERR, if set, is executed before the shell
+ * exits [ERR is a bashism].
+ *
+ * If a compound command or function executes in a context where -e is
+ * ignored, none of the commands executed within are affected by the -e
+ * setting. If a compound command or function sets -e while executing in a
+ * context where -e is ignored, that setting does not have any effect until
+ * the compound command or the command containing the function call completes.
+ */
+
+ char o_opt[NUM_OPT_O];
+#if ENABLE_HUSH_MODE_X
+# define G_x_mode (G.o_opt[OPT_O_XTRACE])
+#else
+# define G_x_mode 0
+#endif
+ char opt_s;
+ char opt_c;
+#endif /* !__U_BOOT__ */
+#if ENABLE_HUSH_INTERACTIVE
+ smallint promptmode; /* 0: PS1, 1: PS2 */
+#endif
+ /* set by signal handler if SIGINT is received _and_ its trap is not set */
+ smallint flag_SIGINT;
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_LOOPS
+ smallint flag_break_continue;
+#endif
+#endif /* !__U_BOOT__ */
+#if ENABLE_HUSH_FUNCTIONS
+ /* 0: outside of a function (or sourced file)
+ * -1: inside of a function, ok to use return builtin
+ * 1: return is invoked, skip all till end of func
+ */
+ smallint flag_return_in_progress;
+# define G_flag_return_in_progress (G.flag_return_in_progress)
+#else
+# define G_flag_return_in_progress 0
+#endif
+ smallint exiting; /* used to prevent EXIT trap recursion */
+ /* These support $? */
+ smalluint last_exitcode;
+ smalluint expand_exitcode;
+ smalluint last_bg_pid_exitcode;
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_SET
+ /* are global_argv and global_argv[1..n] malloced? (note: not [0]) */
+ smalluint global_args_malloced;
+# define G_global_args_malloced (G.global_args_malloced)
+#else
+# define G_global_args_malloced 0
+#endif
+#if ENABLE_HUSH_BASH_COMPAT
+ int dead_job_exitcode; /* for "wait -n" */
+#endif
+#endif /* !__U_BOOT__ */
+ /* how many non-NULL argv's we have. NB: $# + 1 */
+ int global_argc;
+ char **global_argv;
+#if !BB_MMU
+ char *argv0_for_re_execing;
+#endif
+#if ENABLE_HUSH_LOOPS
+#ifndef __U_BOOT__
+ unsigned depth_break_continue;
+#endif /* !__U_BOOT__ */
+ unsigned depth_of_loop;
+#endif
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_GETOPTS
+ unsigned getopt_count;
+#endif
+#endif /* !__U_BOOT__ */
+ const char *ifs;
+#ifdef __U_BOOT__
+ int flag_repeat;
+ int do_repeat;
+ int run_command_flags;
+#endif /* __U_BOOT__ */
+ char *ifs_whitespace; /* = G.ifs or malloced */
+#ifndef __U_BOOT__
+ const char *cwd;
+#endif /* !__U_BOOT__ */
+ struct variable *top_var;
+ char **expanded_assignments;
+ struct variable **shadowed_vars_pp;
+ unsigned var_nest_level;
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_FUNCTIONS
+# if ENABLE_HUSH_LOCAL
+ unsigned func_nest_level; /* solely to prevent "local v" in non-functions */
+# endif
+ struct function *top_func;
+#endif
+ /* Signal and trap handling */
+#if ENABLE_HUSH_FAST
+ unsigned count_SIGCHLD;
+ unsigned handled_SIGCHLD;
+ smallint we_have_children;
+#endif
+#if ENABLE_HUSH_LINENO_VAR
+ unsigned parse_lineno;
+ unsigned execute_lineno;
+#endif
+ HFILE *HFILE_list;
+ HFILE *HFILE_stdin;
+ /* Which signals have non-DFL handler (even with no traps set)?
+ * Set at the start to:
+ * (SIGQUIT + maybe SPECIAL_INTERACTIVE_SIGS + maybe SPECIAL_JOBSTOP_SIGS)
+ * SPECIAL_INTERACTIVE_SIGS are cleared after fork.
+ * The rest is cleared right before execv syscalls.
+ * Other than these two times, never modified.
+ */
+ unsigned special_sig_mask;
+#if ENABLE_HUSH_JOB
+ unsigned fatal_sig_mask;
+# define G_fatal_sig_mask (G.fatal_sig_mask)
+#else
+# define G_fatal_sig_mask 0
+#endif
+#if ENABLE_HUSH_TRAP
+ int pre_trap_exitcode;
+# if ENABLE_HUSH_FUNCTIONS
+ int return_exitcode;
+# endif
+ char **traps; /* char *traps[NSIG] */
+# define G_traps G.traps
+#else
+# define G_traps ((char**)NULL)
+#endif
+ sigset_t pending_set;
+#if ENABLE_HUSH_MEMLEAK
+ unsigned long memleak_value;
+#endif
+#if ENABLE_HUSH_MODE_X
+ unsigned x_mode_depth;
+ /* "set -x" output should not be redirectable with subsequent 2>FILE.
+ * We dup fd#2 to x_mode_fd when "set -x" is executed, and use it
+ * for all subsequent output.
+ */
+ int x_mode_fd;
+ o_string x_mode_buf;
+#endif
+#endif /* !__U_BOOT__ */
+#if HUSH_DEBUG >= 2
+ int debug_indent;
+#endif
+#ifndef __U_BOOT__
+ struct sigaction sa;
+ char optstring_buf[sizeof("eixcs")];
+#if BASH_EPOCH_VARS
+ char epoch_buf[sizeof("%llu.nnnnnn") + sizeof(long long)*3];
+#endif
+#if ENABLE_FEATURE_EDITING
+ char user_input_buf[CONFIG_FEATURE_EDITING_MAX_LEN];
+#endif
+#endif /* !__U_BOOT__ */
+};
+#ifdef __U_BOOT__
+struct globals *ptr_to_globals;
+#endif /* __U_BOOT__ */
+#define G (*ptr_to_globals)
+/* Not #defining name to G.name - this quickly gets unwieldy
+ * (too many defines). Also, I actually prefer to see when a variable
+ * is global, thus "G." prefix is a useful hint */
+#ifdef __U_BOOT__
+#define SET_PTR_TO_GLOBALS(x) do { \
+ (*(struct globals**)&ptr_to_globals) = (void*)(x); \
+ barrier(); \
+} while (0)
+#define INIT_G() do { \
+ SET_PTR_TO_GLOBALS(xzalloc(sizeof(G))); \
+ G.promptmode = 1; \
+} while (0)
+#else /* !__U_BOOT__ */
+#define INIT_G() do { \
+ SET_PTR_TO_GLOBALS(xzalloc(sizeof(G))); \
+ /* memset(&G.sa, 0, sizeof(G.sa)); */ \
+ sigfillset(&G.sa.sa_mask); \
+ G.sa.sa_flags = SA_RESTART; \
+} while (0)
+#endif /* !__U_BOOT__ */
+
+
+#ifndef __U_BOOT__
+/* Function prototypes for builtins */
+static int builtin_cd(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_ECHO
+static int builtin_echo(char **argv) FAST_FUNC;
+#endif
+static int builtin_eval(char **argv) FAST_FUNC;
+static int builtin_exec(char **argv) FAST_FUNC;
+static int builtin_exit(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_EXPORT
+static int builtin_export(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_READONLY
+static int builtin_readonly(char **argv) FAST_FUNC;
+#endif
+static int builtin_false(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_JOB
+static int builtin_fg_bg(char **argv) FAST_FUNC;
+static int builtin_jobs(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_GETOPTS
+static int builtin_getopts(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_HELP
+static int builtin_help(char **argv) FAST_FUNC;
+#endif
+#if MAX_HISTORY && ENABLE_FEATURE_EDITING
+static int builtin_history(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_LOCAL
+static int builtin_local(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_MEMLEAK
+static int builtin_memleak(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_PRINTF
+static int builtin_printf(char **argv) FAST_FUNC;
+#endif
+static int builtin_pwd(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_READ
+static int builtin_read(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_SET
+static int builtin_set(char **argv) FAST_FUNC;
+#endif
+static int builtin_shift(char **argv) FAST_FUNC;
+static int builtin_source(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_TEST || BASH_TEST2
+static int builtin_test(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_TRAP
+static int builtin_trap(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_TYPE
+static int builtin_type(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_TIMES
+static int builtin_times(char **argv) FAST_FUNC;
+#endif
+static int builtin_true(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_UMASK
+static int builtin_umask(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_UNSET
+static int builtin_unset(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_KILL
+static int builtin_kill(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_WAIT
+static int builtin_wait(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_LOOPS
+static int builtin_break(char **argv) FAST_FUNC;
+static int builtin_continue(char **argv) FAST_FUNC;
+#endif
+#if ENABLE_HUSH_FUNCTIONS
+static int builtin_return(char **argv) FAST_FUNC;
+#endif
+
+/* Table of built-in functions. They can be forked or not, depending on
+ * context: within pipes, they fork. As simple commands, they do not.
+ * When used in non-forking context, they can change global variables
+ * in the parent shell process. If forked, of course they cannot.
+ * For example, 'unset foo | whatever' will parse and run, but foo will
+ * still be set at the end. */
+struct built_in_command {
+ const char *b_cmd;
+ int (*b_function)(char **argv) FAST_FUNC;
+#if ENABLE_HUSH_HELP
+ const char *b_descr;
+# define BLTIN(cmd, func, help) { cmd, func, help }
+#else
+# define BLTIN(cmd, func, help) { cmd, func }
+#endif
+};
+
+static const struct built_in_command bltins1[] ALIGN_PTR = {
+ BLTIN("." , builtin_source , "Run commands in file"),
+ BLTIN(":" , builtin_true , NULL),
+#if ENABLE_HUSH_JOB
+ BLTIN("bg" , builtin_fg_bg , "Resume job in background"),
+#endif
+#if ENABLE_HUSH_LOOPS
+ BLTIN("break" , builtin_break , "Exit loop"),
+#endif
+ BLTIN("cd" , builtin_cd , "Change directory"),
+#if ENABLE_HUSH_LOOPS
+ BLTIN("continue" , builtin_continue, "Start new loop iteration"),
+#endif
+ BLTIN("eval" , builtin_eval , "Construct and run shell command"),
+ BLTIN("exec" , builtin_exec , "Execute command, don't return to shell"),
+ BLTIN("exit" , builtin_exit , NULL),
+#if ENABLE_HUSH_EXPORT
+ BLTIN("export" , builtin_export , "Set environment variables"),
+#endif
+ BLTIN("false" , builtin_false , NULL),
+#if ENABLE_HUSH_JOB
+ BLTIN("fg" , builtin_fg_bg , "Bring job to foreground"),
+#endif
+#if ENABLE_HUSH_GETOPTS
+ BLTIN("getopts" , builtin_getopts , NULL),
+#endif
+#if ENABLE_HUSH_HELP
+ BLTIN("help" , builtin_help , NULL),
+#endif
+#if MAX_HISTORY && ENABLE_FEATURE_EDITING
+ BLTIN("history" , builtin_history , "Show history"),
+#endif
+#if ENABLE_HUSH_JOB
+ BLTIN("jobs" , builtin_jobs , "List jobs"),
+#endif
+#if ENABLE_HUSH_KILL
+ BLTIN("kill" , builtin_kill , "Send signals to processes"),
+#endif
+#if ENABLE_HUSH_LOCAL
+ BLTIN("local" , builtin_local , "Set local variables"),
+#endif
+#if ENABLE_HUSH_MEMLEAK
+ BLTIN("memleak" , builtin_memleak , NULL),
+#endif
+#if ENABLE_HUSH_READ
+ BLTIN("read" , builtin_read , "Input into variable"),
+#endif
+#if ENABLE_HUSH_READONLY
+ BLTIN("readonly" , builtin_readonly, "Make variables read-only"),
+#endif
+#if ENABLE_HUSH_FUNCTIONS
+ BLTIN("return" , builtin_return , "Return from function"),
+#endif
+#if ENABLE_HUSH_SET
+ BLTIN("set" , builtin_set , "Set positional parameters"),
+#endif
+ BLTIN("shift" , builtin_shift , "Shift positional parameters"),
+#if BASH_SOURCE
+ BLTIN("source" , builtin_source , NULL),
+#endif
+#if ENABLE_HUSH_TIMES
+ BLTIN("times" , builtin_times , NULL),
+#endif
+#if ENABLE_HUSH_TRAP
+ BLTIN("trap" , builtin_trap , "Trap signals"),
+#endif
+ BLTIN("true" , builtin_true , NULL),
+#if ENABLE_HUSH_TYPE
+ BLTIN("type" , builtin_type , "Show command type"),
+#endif
+#if ENABLE_HUSH_ULIMIT
+ BLTIN("ulimit" , shell_builtin_ulimit, "Control resource limits"),
+#endif
+#if ENABLE_HUSH_UMASK
+ BLTIN("umask" , builtin_umask , "Set file creation mask"),
+#endif
+#if ENABLE_HUSH_UNSET
+ BLTIN("unset" , builtin_unset , "Unset variables"),
+#endif
+#if ENABLE_HUSH_WAIT
+ BLTIN("wait" , builtin_wait , "Wait for process to finish"),
+#endif
+};
+/* These builtins won't be used if we are on NOMMU and need to re-exec
+ * (it's cheaper to run an external program in this case):
+ */
+static const struct built_in_command bltins2[] ALIGN_PTR = {
+#if ENABLE_HUSH_TEST
+ BLTIN("[" , builtin_test , NULL),
+#endif
+#if BASH_TEST2
+ BLTIN("[[" , builtin_test , NULL),
+#endif
+#if ENABLE_HUSH_ECHO
+ BLTIN("echo" , builtin_echo , NULL),
+#endif
+#if ENABLE_HUSH_PRINTF
+ BLTIN("printf" , builtin_printf , NULL),
+#endif
+ BLTIN("pwd" , builtin_pwd , NULL),
+#if ENABLE_HUSH_TEST
+ BLTIN("test" , builtin_test , NULL),
+#endif
+};
+
+#endif /* !__U_BOOT__ */
+
+/* Debug printouts.
+ */
+#if HUSH_DEBUG >= 2
+/* prevent disasters with G.debug_indent < 0 */
+# define indent() fdprintf(2, "%*s", (G.debug_indent * 2) & 0xff, "")
+# define debug_enter() (G.debug_indent++)
+# define debug_leave() (G.debug_indent--)
+#else
+# define indent() ((void)0)
+# define debug_enter() ((void)0)
+# define debug_leave() ((void)0)
+#endif
+
+#ifndef debug_printf
+# define debug_printf(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_parse
+# define debug_printf_parse(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_heredoc
+# define debug_printf_heredoc(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_exec
+#define debug_printf_exec(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_env
+# define debug_printf_env(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_jobs
+# define debug_printf_jobs(...) (indent(), fdprintf(2, __VA_ARGS__))
+# define DEBUG_JOBS 1
+#else
+# define DEBUG_JOBS 0
+#endif
+
+#ifndef debug_printf_expand
+# define debug_printf_expand(...) (indent(), fdprintf(2, __VA_ARGS__))
+# define DEBUG_EXPAND 1
+#else
+# define DEBUG_EXPAND 0
+#endif
+
+#ifndef debug_printf_varexp
+# define debug_printf_varexp(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_glob
+# define debug_printf_glob(...) (indent(), fdprintf(2, __VA_ARGS__))
+# define DEBUG_GLOB 1
+#else
+# define DEBUG_GLOB 0
+#endif
+
+#ifndef debug_printf_redir
+# define debug_printf_redir(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_list
+# define debug_printf_list(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_subst
+# define debug_printf_subst(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_prompt
+# define debug_printf_prompt(...) (indent(), fdprintf(2, __VA_ARGS__))
+#endif
+
+#ifndef debug_printf_clean
+# define debug_printf_clean(...) (indent(), fdprintf(2, __VA_ARGS__))
+# define DEBUG_CLEAN 1
+#else
+# define DEBUG_CLEAN 0
+#endif
+
+#if DEBUG_EXPAND
+static void debug_print_strings(const char *prefix, char **vv)
+{
+ indent();
+ fdprintf(2, "%s:\n", prefix);
+ while (*vv)
+ fdprintf(2, " '%s'\n", *vv++);
+}
+#else
+# define debug_print_strings(prefix, vv) ((void)0)
+#endif
+
+
+/* Leak hunting. Use hush_leaktool.sh for post-processing.
+ */
+#if LEAK_HUNTING
+static void *xxmalloc(int lineno, size_t size)
+{
+ void *ptr = xmalloc((size + 0xff) & ~0xff);
+ fdprintf(2, "line %d: malloc %p\n", lineno, ptr);
+ return ptr;
+}
+static void *xxrealloc(int lineno, void *ptr, size_t size)
+{
+ ptr = xrealloc(ptr, (size + 0xff) & ~0xff);
+ fdprintf(2, "line %d: realloc %p\n", lineno, ptr);
+ return ptr;
+}
+static char *xxstrdup(int lineno, const char *str)
+{
+ char *ptr = xstrdup(str);
+ fdprintf(2, "line %d: strdup %p\n", lineno, ptr);
+ return ptr;
+}
+static void xxfree(void *ptr)
+{
+ fdprintf(2, "free %p\n", ptr);
+ free(ptr);
+}
+# define xmalloc(s) xxmalloc(__LINE__, s)
+# define xrealloc(p, s) xxrealloc(__LINE__, p, s)
+# define xstrdup(s) xxstrdup(__LINE__, s)
+# define free(p) xxfree(p)
+#endif
+
+
+/* Syntax and runtime errors. They always abort scripts.
+ * In interactive use they usually discard unparsed and/or unexecuted commands
+ * and return to the prompt.
+ * HUSH_DEBUG >= 2 prints line number in this file where it was detected.
+ */
+#if HUSH_DEBUG < 2
+# define msg_and_die_if_script(lineno, ...) msg_and_die_if_script(__VA_ARGS__)
+# define syntax_error(lineno, msg) syntax_error(msg)
+# define syntax_error_at(lineno, msg) syntax_error_at(msg)
+# define syntax_error_unterm_ch(lineno, ch) syntax_error_unterm_ch(ch)
+# define syntax_error_unterm_str(lineno, s) syntax_error_unterm_str(s)
+# define syntax_error_unexpected_ch(lineno, ch) syntax_error_unexpected_ch(ch)
+#endif
+
+static void die_if_script(void)
+{
+ if (!G_interactive_fd) {
+ if (G.last_exitcode) /* sometines it's 2, not 1 (bash compat) */
+ xfunc_error_retval = G.last_exitcode;
+ xfunc_die();
+ }
+}
+
+#ifdef __U_BOOT__
+static void __maybe_unused msg_and_die_if_script(unsigned lineno, const char *fmt, ...)
+#else /* !__U_BOOT__ */
+static void msg_and_die_if_script(unsigned lineno, const char *fmt, ...)
+#endif /* !__U_BOOT__ */
+{
+ va_list p;
+
+#if HUSH_DEBUG >= 2
+ bb_error_msg("hush.c:%u", lineno);
+#endif
+ va_start(p, fmt);
+ bb_verror_msg(fmt, p, NULL);
+ va_end(p);
+ die_if_script();
+}
+
+static void syntax_error(unsigned lineno UNUSED_PARAM, const char *msg)
+{
+ if (msg)
+ bb_error_msg("syntax error: %s", msg);
+ else
+ bb_simple_error_msg("syntax error");
+ die_if_script();
+}
+
+static void syntax_error_at(unsigned lineno UNUSED_PARAM, const char *msg)
+{
+ bb_error_msg("syntax error at '%s'", msg);
+ die_if_script();
+}
+
+static void syntax_error_unterm_str(unsigned lineno UNUSED_PARAM, const char *s)
+{
+ bb_error_msg("syntax error: unterminated %s", s);
+//? source4.tests fails: in bash, echo ${^} in script does not terminate the script
+// (but bash --posix, or if bash is run as "sh", does terminate in script, so maybe uncomment this?)
+// die_if_script();
+}
+
+static void syntax_error_unterm_ch(unsigned lineno, char ch)
+{
+ char msg[2] = { ch, '\0' };
+ syntax_error_unterm_str(lineno, msg);
+}
+
+static void syntax_error_unexpected_ch(unsigned lineno UNUSED_PARAM, int ch)
+{
+ char msg[2];
+ msg[0] = ch;
+ msg[1] = '\0';
+#if HUSH_DEBUG >= 2
+ bb_error_msg("hush.c:%u", lineno);
+#endif
+ bb_error_msg("syntax error: unexpected %s", ch == EOF ? "EOF" : msg);
+ die_if_script();
+}
+
+#if HUSH_DEBUG < 2
+# undef msg_and_die_if_script
+# undef syntax_error
+# undef syntax_error_at
+# undef syntax_error_unterm_ch
+# undef syntax_error_unterm_str
+# undef syntax_error_unexpected_ch
+#else
+# define msg_and_die_if_script(...) msg_and_die_if_script(__LINE__, __VA_ARGS__)
+# define syntax_error(msg) syntax_error(__LINE__, msg)
+# define syntax_error_at(msg) syntax_error_at(__LINE__, msg)
+# define syntax_error_unterm_ch(ch) syntax_error_unterm_ch(__LINE__, ch)
+# define syntax_error_unterm_str(s) syntax_error_unterm_str(__LINE__, s)
+# define syntax_error_unexpected_ch(ch) syntax_error_unexpected_ch(__LINE__, ch)
+#endif
+
+/* Utility functions
+ */
+/* Replace each \x with x in place, return ptr past NUL. */
+static char *unbackslash(char *src)
+{
+#ifdef __U_BOOT__
+ char *dst = src = (char *)strchrnul(src, '\\');
+#else /* !__U_BOOT__ */
+ char *dst = src = strchrnul(src, '\\');
+#endif /* !__U_BOOT__ */
+ while (1) {
+ if (*src == '\\') {
+ src++;
+ if (*src != '\0') {
+ /* \x -> x */
+ *dst++ = *src++;
+ continue;
+ }
+ /* else: "\<nul>". Do not delete this backslash.
+ * Testcase: eval 'echo ok\'
+ */
+ *dst++ = '\\';
+ /* fallthrough */
+ }
+ if ((*dst++ = *src++) == '\0')
+ break;
+ }
+ return dst;
+}
+
+static char **add_strings_to_strings(char **strings, char **add, int need_to_dup)
+{
+ int i;
+ unsigned count1;
+ unsigned count2;
+ char **v;
+
+ v = strings;
+ count1 = 0;
+ if (v) {
+ while (*v) {
+ count1++;
+ v++;
+ }
+ }
+ count2 = 0;
+ v = add;
+ while (*v) {
+ count2++;
+ v++;
+ }
+ v = xrealloc(strings, (count1 + count2 + 1) * sizeof(char*));
+ v[count1 + count2] = NULL;
+ i = count2;
+ while (--i >= 0)
+ v[count1 + i] = (need_to_dup ? xstrdup(add[i]) : add[i]);
+ return v;
+}
+#if LEAK_HUNTING
+static char **xx_add_strings_to_strings(int lineno, char **strings, char **add, int need_to_dup)
+{
+ char **ptr = add_strings_to_strings(strings, add, need_to_dup);
+ fdprintf(2, "line %d: add_strings_to_strings %p\n", lineno, ptr);
+ return ptr;
+}
+#define add_strings_to_strings(strings, add, need_to_dup) \
+ xx_add_strings_to_strings(__LINE__, strings, add, need_to_dup)
+#endif
+
+/* Note: takes ownership of "add" ptr (it is not strdup'ed) */
+static char **add_string_to_strings(char **strings, char *add)
+{
+ char *v[2];
+ v[0] = add;
+ v[1] = NULL;
+ return add_strings_to_strings(strings, v, /*dup:*/ 0);
+}
+
+#if LEAK_HUNTING
+static char **xx_add_string_to_strings(int lineno, char **strings, char *add)
+{
+ char **ptr = add_string_to_strings(strings, add);
+ fdprintf(2, "line %d: add_string_to_strings %p\n", lineno, ptr);
+ return ptr;
+}
+#define add_string_to_strings(strings, add) \
+ xx_add_string_to_strings(__LINE__, strings, add)
+#endif
+
+static void free_strings(char **strings)
+{
+ char **v;
+
+ if (!strings)
+ return;
+ v = strings;
+ while (*v) {
+ free(*v);
+ v++;
+ }
+ free(strings);
+}
+
+#ifndef __U_BOOT__
+static int dup_CLOEXEC(int fd, int avoid_fd)
+{
+ int newfd;
+ repeat:
+ newfd = fcntl(fd, F_DUPFD_CLOEXEC, avoid_fd + 1);
+ if (newfd >= 0) {
+ if (F_DUPFD_CLOEXEC == F_DUPFD) /* if old libc (w/o F_DUPFD_CLOEXEC) */
+ fcntl(newfd, F_SETFD, FD_CLOEXEC);
+ } else { /* newfd < 0 */
+ if (errno == EBUSY)
+ goto repeat;
+ if (errno == EINTR)
+ goto repeat;
+ }
+ return newfd;
+}
+
+static int xdup_CLOEXEC_and_close(int fd, int avoid_fd)
+{
+ int newfd;
+ repeat:
+ newfd = fcntl(fd, F_DUPFD_CLOEXEC, avoid_fd + 1);
+ if (newfd < 0) {
+ if (errno == EBUSY)
+ goto repeat;
+ if (errno == EINTR)
+ goto repeat;
+ /* fd was not open? */
+ if (errno == EBADF)
+ return fd;
+ xfunc_die();
+ }
+ if (F_DUPFD_CLOEXEC == F_DUPFD) /* if old libc (w/o F_DUPFD_CLOEXEC) */
+ fcntl(newfd, F_SETFD, FD_CLOEXEC);
+ close(fd);
+ return newfd;
+}
+
+
+/* Manipulating HFILEs */
+static HFILE *hfopen(const char *name)
+{
+ HFILE *fp;
+ int fd;
+
+ fd = STDIN_FILENO;
+ if (name) {
+ fd = open(name, O_RDONLY | O_CLOEXEC);
+ if (fd < 0)
+ return NULL;
+ if (O_CLOEXEC == 0) /* ancient libc */
+ close_on_exec_on(fd);
+ }
+
+ fp = xmalloc(sizeof(*fp));
+ if (name == NULL)
+ G.HFILE_stdin = fp;
+ fp->fd = fd;
+ fp->cur = fp->end = fp->buf;
+ fp->next_hfile = G.HFILE_list;
+ G.HFILE_list = fp;
+ return fp;
+}
+static void hfclose(HFILE *fp)
+{
+ HFILE **pp = &G.HFILE_list;
+ while (*pp) {
+ HFILE *cur = *pp;
+ if (cur == fp) {
+ *pp = cur->next_hfile;
+ break;
+ }
+ pp = &cur->next_hfile;
+ }
+ if (fp->fd >= 0)
+ close(fp->fd);
+ free(fp);
+}
+static int refill_HFILE_and_getc(HFILE *fp)
+{
+ int n;
+
+ if (fp->fd < 0) {
+ /* Already saw EOF */
+ return EOF;
+ }
+#if ENABLE_HUSH_INTERACTIVE && !ENABLE_FEATURE_EDITING
+ /* If user presses ^C, read() restarts after SIGINT (we use SA_RESTART).
+ * IOW: ^C will not immediately stop line input.
+ * But poll() is different: it does NOT restart after signals.
+ */
+ if (fp == G.HFILE_stdin) {
+ struct pollfd pfd[1];
+ pfd[0].fd = fp->fd;
+ pfd[0].events = POLLIN;
+ n = poll(pfd, 1, -1);
+ if (n < 0
+ /*&& errno == EINTR - assumed true */
+ && sigismember(&G.pending_set, SIGINT)
+ ) {
+ return '\0';
+ }
+ }
+#else
+/* if FEATURE_EDITING=y, we do not use this routine for interactive input */
+#endif
+ /* Try to buffer more input */
+ n = safe_read(fp->fd, fp->buf, sizeof(fp->buf));
+ if (n < 0) {
+ bb_simple_perror_msg("read error");
+ n = 0;
+ }
+ fp->cur = fp->buf;
+ fp->end = fp->buf + n;
+ if (n == 0) {
+ /* EOF/error */
+ close(fp->fd);
+ fp->fd = -1;
+ return EOF;
+ }
+ return (unsigned char)(*fp->cur++);
+}
+/* Inlined for common case of non-empty buffer.
+ */
+static ALWAYS_INLINE int hfgetc(HFILE *fp)
+{
+ if (fp->cur < fp->end)
+ return (unsigned char)(*fp->cur++);
+ /* Buffer empty */
+ return refill_HFILE_and_getc(fp);
+}
+static int move_HFILEs_on_redirect(int fd, int avoid_fd)
+{
+ HFILE *fl = G.HFILE_list;
+ while (fl) {
+ if (fd == fl->fd) {
+ /* We use it only on script files, they are all CLOEXEC */
+ fl->fd = xdup_CLOEXEC_and_close(fd, avoid_fd);
+ debug_printf_redir("redirect_fd %d: matches a script fd, moving it to %d\n", fd, fl->fd);
+ return 1; /* "found and moved" */
+ }
+ fl = fl->next_hfile;
+ }
+#if ENABLE_HUSH_MODE_X
+ if (G.x_mode_fd > 0 && fd == G.x_mode_fd) {
+ G.x_mode_fd = xdup_CLOEXEC_and_close(fd, avoid_fd);
+ return 1; /* "found and moved" */
+ }
+#endif
+ return 0; /* "not in the list" */
+}
+#if ENABLE_FEATURE_SH_STANDALONE && BB_MMU
+static void close_all_HFILE_list(void)
+{
+ HFILE *fl = G.HFILE_list;
+ while (fl) {
+ /* hfclose would also free HFILE object.
+ * It is disastrous if we share memory with a vforked parent.
+ * I'm not sure we never come here after vfork.
+ * Therefore just close fd, nothing more.
+ *
+ * ">" instead of ">=": we don't close fd#0,
+ * interactive shell uses hfopen(NULL) as stdin input
+ * which has fl->fd == 0, but fd#0 gets redirected in pipes.
+ * If we'd close it here, then e.g. interactive "set | sort"
+ * with NOFORKed sort, would have sort's input fd closed.
+ */
+ if (fl->fd > 0)
+ /*hfclose(fl); - unsafe */
+ close(fl->fd);
+ fl = fl->next_hfile;
+ }
+}
+#endif
+static int fd_in_HFILEs(int fd)
+{
+ HFILE *fl = G.HFILE_list;
+ while (fl) {
+ if (fl->fd == fd)
+ return 1;
+ fl = fl->next_hfile;
+ }
+ return 0;
+}
+
+#endif /* !__U_BOOT__ */
+
+/* Helpers for setting new $n and restoring them back
+ */
+typedef struct save_arg_t {
+ char *sv_argv0;
+ char **sv_g_argv;
+ int sv_g_argc;
+#ifndef __U_BOOT__
+ IF_HUSH_SET(smallint sv_g_malloced;)
+#endif /* !__U_BOOT__ */
+} save_arg_t;
+
+#ifndef __U_BOOT__
+static void save_and_replace_G_args(save_arg_t *sv, char **argv)
+{
+ sv->sv_argv0 = argv[0];
+ sv->sv_g_argv = G.global_argv;
+ sv->sv_g_argc = G.global_argc;
+ IF_HUSH_SET(sv->sv_g_malloced = G.global_args_malloced;)
+
+ argv[0] = G.global_argv[0]; /* retain $0 */
+ G.global_argv = argv;
+ IF_HUSH_SET(G.global_args_malloced = 0;)
+
+ G.global_argc = 1 + string_array_len(argv + 1);
+}
+
+static void restore_G_args(save_arg_t *sv, char **argv)
+{
+#if ENABLE_HUSH_SET
+ if (G.global_args_malloced) {
+ /* someone ran "set -- arg1 arg2 ...", undo */
+ char **pp = G.global_argv;
+ while (*++pp) /* note: does not free $0 */
+ free(*pp);
+ free(G.global_argv);
+ }
+#endif
+ argv[0] = sv->sv_argv0;
+ G.global_argv = sv->sv_g_argv;
+ G.global_argc = sv->sv_g_argc;
+ IF_HUSH_SET(G.global_args_malloced = sv->sv_g_malloced;)
+}
+#endif /* !__U_BOOT__ */
+
+
+#ifndef __U_BOOT__
+/* Basic theory of signal handling in shell
+ * ========================================
+ * This does not describe what hush does, rather, it is current understanding
+ * what it _should_ do. If it doesn't, it's a bug.
+ * http://www.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#trap
+ *
+ * Signals are handled only after each pipe ("cmd | cmd | cmd" thing)
+ * is finished or backgrounded. It is the same in interactive and
+ * non-interactive shells, and is the same regardless of whether
+ * a user trap handler is installed or a shell special one is in effect.
+ * ^C or ^Z from keyboard seems to execute "at once" because it usually
+ * backgrounds (i.e. stops) or kills all members of currently running
+ * pipe.
+ *
+ * Wait builtin is interruptible by signals for which user trap is set
+ * or by SIGINT in interactive shell.
+ *
+ * Trap handlers will execute even within trap handlers. (right?)
+ *
+ * User trap handlers are forgotten when subshell ("(cmd)") is entered,
+ * except for handlers set to '' (empty string).
+ *
+ * If job control is off, backgrounded commands ("cmd &")
+ * have SIGINT, SIGQUIT set to SIG_IGN.
+ *
+ * Commands which are run in command substitution ("`cmd`")
+ * have SIGTTIN, SIGTTOU, SIGTSTP set to SIG_IGN.
+ *
+ * Ordinary commands have signals set to SIG_IGN/DFL as inherited
+ * by the shell from its parent.
+ *
+ * Signals which differ from SIG_DFL action
+ * (note: child (i.e., [v]forked) shell is not an interactive shell):
+ *
+ * SIGQUIT: ignore
+ * SIGTERM (interactive): ignore
+ * SIGHUP (interactive):
+ * Send SIGCONT to stopped jobs, send SIGHUP to all jobs and exit.
+ * Kernel would do this for us ("orphaned process group" handling
+ * according to POSIX) if we are a session leader and thus our death
+ * frees the controlling tty, but to be bash-compatible, we also do it
+ * for every interactive shell's death by SIGHUP.
+ * (Also, we need to restore tty pgrp, otherwise e.g. Midnight Commander
+ * backgrounds when hush started from it gets killed by SIGHUP).
+ * SIGTTIN, SIGTTOU, SIGTSTP (if job control is on): ignore
+ * Note that ^Z is handled not by trapping SIGTSTP, but by seeing
+ * that all pipe members are stopped. Try this in bash:
+ * while :; do :; done - ^Z does not background it
+ * (while :; do :; done) - ^Z backgrounds it
+ * SIGINT (interactive): wait for last pipe, ignore the rest
+ * of the command line, show prompt. NB: ^C does not send SIGINT
+ * to interactive shell while shell is waiting for a pipe,
+ * since shell is bg'ed (is not in foreground process group).
+ * Example 1: this waits 5 sec, but does not execute ls:
+ * "echo $$; sleep 5; ls -l" + "kill -INT <pid>"
+ * Example 2: this does not wait and does not execute ls:
+ * "echo $$; sleep 5 & wait; ls -l" + "kill -INT <pid>"
+ * Example 3: this does not wait 5 sec, but executes ls:
+ * "sleep 5; ls -l" + press ^C
+ * Example 4: this does not wait and does not execute ls:
+ * "sleep 5 & wait; ls -l" + press ^C
+ *
+ * (What happens to signals which are IGN on shell start?)
+ * (What happens with signal mask on shell start?)
+ *
+ * Old implementation
+ * ==================
+ * We use in-kernel pending signal mask to determine which signals were sent.
+ * We block all signals which we don't want to take action immediately,
+ * i.e. we block all signals which need to have special handling as described
+ * above, and all signals which have traps set.
+ * After each pipe execution, we extract any pending signals via sigtimedwait()
+ * and act on them.
+ *
+ * unsigned special_sig_mask: a mask of such "special" signals
+ * sigset_t blocked_set: current blocked signal set
+ *
+ * "trap - SIGxxx":
+ * clear bit in blocked_set unless it is also in special_sig_mask
+ * "trap 'cmd' SIGxxx":
+ * set bit in blocked_set (even if 'cmd' is '')
+ * after [v]fork, if we plan to be a shell:
+ * unblock signals with special interactive handling
+ * (child shell is not interactive),
+ * unset all traps except '' (note: regardless of child shell's type - {}, (), etc)
+ * after [v]fork, if we plan to exec:
+ * POSIX says fork clears pending signal mask in child - no need to clear it.
+ * Restore blocked signal set to one inherited by shell just prior to exec.
+ *
+ * Note: as a result, we do not use signal handlers much. The only uses
+ * are to count SIGCHLDs
+ * and to restore tty pgrp on signal-induced exit.
+ *
+ * Note 2 (compat):
+ * Standard says "When a subshell is entered, traps that are not being ignored
+ * are set to the default actions". bash interprets it so that traps which
+ * are set to '' (ignore) are NOT reset to defaults. We do the same.
+ *
+ * Problem: the above approach makes it unwieldy to catch signals while
+ * we are in read builtin, or while we read commands from stdin:
+ * masked signals are not visible!
+ *
+ * New implementation
+ * ==================
+ * We record each signal we are interested in by installing signal handler
+ * for them - a bit like emulating kernel pending signal mask in userspace.
+ * We are interested in: signals which need to have special handling
+ * as described above, and all signals which have traps set.
+ * Signals are recorded in pending_set.
+ * After each pipe execution, we extract any pending signals
+ * and act on them.
+ *
+ * unsigned special_sig_mask: a mask of shell-special signals.
+ * unsigned fatal_sig_mask: a mask of signals on which we restore tty pgrp.
+ * char *traps[sig] if trap for sig is set (even if it's '').
+ * sigset_t pending_set: set of sigs we received.
+ *
+ * "trap - SIGxxx":
+ * if sig is in special_sig_mask, set handler back to:
+ * record_pending_signo, or to IGN if it's a tty stop signal
+ * if sig is in fatal_sig_mask, set handler back to sigexit.
+ * else: set handler back to SIG_DFL
+ * "trap 'cmd' SIGxxx":
+ * set handler to record_pending_signo.
+ * "trap '' SIGxxx":
+ * set handler to SIG_IGN.
+ * after [v]fork, if we plan to be a shell:
+ * set signals with special interactive handling to SIG_DFL
+ * (because child shell is not interactive),
+ * unset all traps except '' (note: regardless of child shell's type - {}, (), etc)
+ * after [v]fork, if we plan to exec:
+ * POSIX says fork clears pending signal mask in child - no need to clear it.
+ *
+ * To make wait builtin interruptible, we handle SIGCHLD as special signal,
+ * otherwise (if we leave it SIG_DFL) sigsuspend in wait builtin will not wake up on it.
+ *
+ * Note (compat):
+ * Standard says "When a subshell is entered, traps that are not being ignored
+ * are set to the default actions". bash interprets it so that traps which
+ * are set to '' (ignore) are NOT reset to defaults. We do the same.
+ */
+enum {
+ SPECIAL_INTERACTIVE_SIGS = 0
+ | (1 << SIGTERM)
+ | (1 << SIGINT)
+ | (1 << SIGHUP)
+ ,
+ SPECIAL_JOBSTOP_SIGS = 0
+#if ENABLE_HUSH_JOB
+ | (1 << SIGTTIN)
+ | (1 << SIGTTOU)
+ | (1 << SIGTSTP)
+#endif
+ ,
+};
+
+static void record_pending_signo(int sig)
+{
+ sigaddset(&G.pending_set, sig);
+#if ENABLE_FEATURE_EDITING
+ if (sig != SIGCHLD
+ || (G_traps && G_traps[SIGCHLD] && G_traps[SIGCHLD][0])
+ /* ^^^ if SIGCHLD, interrupt line reading only if it has a trap */
+ ) {
+ bb_got_signal = sig; /* for read_line_input: "we got a signal" */
+ }
+#endif
+#if ENABLE_HUSH_FAST
+ if (sig == SIGCHLD) {
+ G.count_SIGCHLD++;
+//bb_error_msg("[%d] SIGCHLD_handler: G.count_SIGCHLD:%d G.handled_SIGCHLD:%d", getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+ }
+#endif
+}
+
+static sighandler_t install_sighandler(int sig, sighandler_t handler)
+{
+ struct sigaction old_sa;
+
+ /* We could use signal() to install handlers... almost:
+ * except that we need to mask ALL signals while handlers run.
+ * I saw signal nesting in strace, race window isn't small.
+ * SA_RESTART is also needed, but in Linux, signal()
+ * sets SA_RESTART too.
+ */
+ /* memset(&G.sa, 0, sizeof(G.sa)); - already done */
+ /* sigfillset(&G.sa.sa_mask); - already done */
+ /* G.sa.sa_flags = SA_RESTART; - already done */
+ G.sa.sa_handler = handler;
+ sigaction(sig, &G.sa, &old_sa);
+ return old_sa.sa_handler;
+}
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+static void hush_exit(int exitcode) NORETURN;
+
+static void restore_ttypgrp_and__exit(void) NORETURN;
+static void restore_ttypgrp_and__exit(void)
+{
+ /* xfunc has failed! die die die */
+ /* no EXIT traps, this is an escape hatch! */
+ G.exiting = 1;
+ hush_exit(xfunc_error_retval);
+}
+
+#if ENABLE_HUSH_JOB
+
+/* Needed only on some libc:
+ * It was observed that on exit(), fgetc'ed buffered data
+ * gets "unwound" via lseek(fd, -NUM, SEEK_CUR).
+ * With the net effect that even after fork(), not vfork(),
+ * exit() in NOEXECed applet in "sh SCRIPT":
+ * noexec_applet_here
+ * echo END_OF_SCRIPT
+ * lseeks fd in input FILE object from EOF to "e" in "echo END_OF_SCRIPT".
+ * This makes "echo END_OF_SCRIPT" executed twice.
+ * Similar problems can be seen with msg_and_die_if_script() -> xfunc_die()
+ * and in `cmd` handling.
+ * If set as die_func(), this makes xfunc_die() exit via _exit(), not exit():
+ */
+static void fflush_and__exit(void) NORETURN;
+static void fflush_and__exit(void)
+{
+ fflush_all();
+ _exit(xfunc_error_retval);
+}
+
+/* After [v]fork, in child: do not restore tty pgrp on xfunc death */
+# define disable_restore_tty_pgrp_on_exit() (die_func = fflush_and__exit)
+/* After [v]fork, in parent: restore tty pgrp on xfunc death */
+# define enable_restore_tty_pgrp_on_exit() (die_func = restore_ttypgrp_and__exit)
+
+/* Restores tty foreground process group, and exits.
+ * May be called as signal handler for fatal signal
+ * (will resend signal to itself, producing correct exit state)
+ * or called directly with -EXITCODE.
+ * We also call it if xfunc is exiting.
+ */
+static void sigexit(int sig) NORETURN;
+static void sigexit(int sig)
+{
+ /* Careful: we can end up here after [v]fork. Do not restore
+ * tty pgrp then, only top-level shell process does that */
+ if (G_saved_tty_pgrp && getpid() == G.root_pid) {
+ /* Disable all signals: job control, SIGPIPE, etc.
+ * Mostly paranoid measure, to prevent infinite SIGTTOU.
+ */
+ sigprocmask_allsigs(SIG_BLOCK);
+ tcsetpgrp(G_interactive_fd, G_saved_tty_pgrp);
+ }
+
+ /* Not a signal, just exit */
+ if (sig <= 0)
+ _exit(- sig);
+
+ kill_myself_with_sig(sig); /* does not return */
+}
+#else
+
+# define disable_restore_tty_pgrp_on_exit() ((void)0)
+# define enable_restore_tty_pgrp_on_exit() ((void)0)
+
+#endif
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+static sighandler_t pick_sighandler(unsigned sig)
+{
+ sighandler_t handler = SIG_DFL;
+ if (sig < sizeof(unsigned)*8) {
+ unsigned sigmask = (1 << sig);
+
+#if ENABLE_HUSH_JOB
+ /* is sig fatal? */
+ if (G_fatal_sig_mask & sigmask)
+ handler = sigexit;
+ else
+#endif
+ /* sig has special handling? */
+ if (G.special_sig_mask & sigmask) {
+ handler = record_pending_signo;
+ /* TTIN/TTOU/TSTP can't be set to record_pending_signo
+ * in order to ignore them: they will be raised
+ * in an endless loop when we try to do some
+ * terminal ioctls! We do have to _ignore_ these.
+ */
+ if (SPECIAL_JOBSTOP_SIGS & sigmask)
+ handler = SIG_IGN;
+ }
+ }
+ return handler;
+}
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+/* Restores tty foreground process group, and exits. */
+static void hush_exit(int exitcode)
+{
+#if ENABLE_FEATURE_EDITING_SAVE_ON_EXIT
+ save_history(G.line_input_state); /* may be NULL */
+#endif
+
+ fflush_all();
+ if (G.exiting <= 0 && G_traps && G_traps[0] && G_traps[0][0]) {
+ char *argv[3];
+ /* argv[0] is unused */
+ argv[1] = xstrdup(G_traps[0]); /* copy, since EXIT trap handler may modify G_traps[0] */
+ argv[2] = NULL;
+ G.exiting = 1; /* prevent EXIT trap recursion */
+ /* Note: G_traps[0] is not cleared!
+ * "trap" will still show it, if executed
+ * in the handler */
+ builtin_eval(argv);
+ }
+
+#if ENABLE_FEATURE_CLEAN_UP
+ {
+ struct variable *cur_var;
+ if (G.cwd != bb_msg_unknown)
+ free((char*)G.cwd);
+ cur_var = G.top_var;
+ while (cur_var) {
+ struct variable *tmp = cur_var;
+ if (!cur_var->max_len)
+ free(cur_var->varstr);
+ cur_var = cur_var->next;
+ free(tmp);
+ }
+ }
+#endif
+
+ fflush_all();
+#if ENABLE_HUSH_JOB
+ sigexit(- (exitcode & 0xff));
+#else
+ _exit(exitcode);
+#endif
+}
+
+//TODO: return a mask of ALL handled sigs?
+static int check_and_run_traps(void)
+{
+ int last_sig = 0;
+
+ while (1) {
+ int sig;
+
+ if (sigisemptyset(&G.pending_set))
+ break;
+ sig = 0;
+ do {
+ sig++;
+ if (sigismember(&G.pending_set, sig)) {
+ sigdelset(&G.pending_set, sig);
+ goto got_sig;
+ }
+ } while (sig < NSIG);
+ break;
+ got_sig:
+#if ENABLE_HUSH_TRAP
+ if (G_traps && G_traps[sig]) {
+ debug_printf_exec("%s: sig:%d handler:'%s'\n", __func__, sig, G.traps[sig]);
+ if (G_traps[sig][0]) {
+ /* We have user-defined handler */
+ smalluint save_rcode;
+ int save_pre;
+ char *argv[3];
+ /* argv[0] is unused */
+ argv[1] = xstrdup(G_traps[sig]);
+ /* why strdup? trap can modify itself: trap 'trap "echo oops" INT' INT */
+ argv[2] = NULL;
+ save_pre = G.pre_trap_exitcode;
+ G.pre_trap_exitcode = save_rcode = G.last_exitcode;
+ builtin_eval(argv);
+ free(argv[1]);
+ G.pre_trap_exitcode = save_pre;
+ G.last_exitcode = save_rcode;
+# if ENABLE_HUSH_FUNCTIONS
+ if (G.return_exitcode >= 0) {
+ debug_printf_exec("trap exitcode:%d\n", G.return_exitcode);
+ G.last_exitcode = G.return_exitcode;
+ }
+# endif
+ last_sig = sig;
+ } /* else: "" trap, ignoring signal */
+ continue;
+ }
+#endif
+ /* not a trap: special action */
+ switch (sig) {
+ case SIGINT:
+ debug_printf_exec("%s: sig:%d default SIGINT handler\n", __func__, sig);
+ G.flag_SIGINT = 1;
+ last_sig = sig;
+ break;
+#if ENABLE_HUSH_JOB
+ case SIGHUP: {
+ /* if (G_interactive_fd) - no need to check, the handler
+ * is only installed if we *are* interactive */
+ {
+ /* bash compat: "Before exiting, an interactive
+ * shell resends the SIGHUP to all jobs, running
+ * or stopped. Stopped jobs are sent SIGCONT
+ * to ensure that they receive the SIGHUP."
+ */
+ struct pipe *job;
+ debug_printf_exec("%s: sig:%d default SIGHUP handler\n", __func__, sig);
+ /* bash is observed to signal whole process groups,
+ * not individual processes */
+ for (job = G.job_list; job; job = job->next) {
+ if (job->pgrp <= 0)
+ continue;
+ debug_printf_exec("HUPing pgrp %d\n", job->pgrp);
+ if (kill(- job->pgrp, SIGHUP) == 0)
+ kill(- job->pgrp, SIGCONT);
+ }
+ }
+ /* this restores tty pgrp, then kills us with SIGHUP */
+ sigexit(SIGHUP);
+ }
+#endif
+#if ENABLE_HUSH_FAST
+ case SIGCHLD:
+ debug_printf_exec("%s: sig:%d default SIGCHLD handler\n", __func__, sig);
+ G.count_SIGCHLD++;
+//bb_error_msg("[%d] check_and_run_traps: G.count_SIGCHLD:%d G.handled_SIGCHLD:%d", getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+ /* Note:
+ * We don't do 'last_sig = sig' here -> NOT returning this sig.
+ * This simplifies wait builtin a bit.
+ */
+ break;
+#endif
+ default: /* ignored: */
+ debug_printf_exec("%s: sig:%d default handling is to ignore\n", __func__, sig);
+ /* SIGTERM, SIGQUIT, SIGTTIN, SIGTTOU, SIGTSTP */
+ /* Note:
+ * We don't do 'last_sig = sig' here -> NOT returning this sig.
+ * Example: wait is not interrupted by TERM
+ * in interactive shell, because TERM is ignored.
+ */
+ break;
+ }
+ }
+ return last_sig;
+}
+
+
+static const char *get_cwd(int force)
+{
+ if (force || G.cwd == NULL) {
+ /* xrealloc_getcwd_or_warn(arg) calls free(arg),
+ * we must not try to free(bb_msg_unknown) */
+ if (G.cwd == bb_msg_unknown)
+ G.cwd = NULL;
+ G.cwd = xrealloc_getcwd_or_warn((char *)G.cwd);
+ if (!G.cwd)
+ G.cwd = bb_msg_unknown;
+ }
+ return G.cwd;
+}
+
+#endif /* !__U_BOOT__ */
+
+/*
+ * Shell and environment variable support
+ */
+static struct variable **get_ptr_to_local_var(const char *name)
+{
+ struct variable **pp;
+ struct variable *cur;
+
+ pp = &G.top_var;
+ while ((cur = *pp) != NULL) {
+ if (varcmp(cur->varstr, name) == 0)
+ return pp;
+ pp = &cur->next;
+ }
+ return NULL;
+}
+
+static const char* FAST_FUNC get_local_var_value(const char *name)
+{
+ struct variable **vpp;
+
+ if (G.expanded_assignments) {
+ char **cpp = G.expanded_assignments;
+ while (*cpp) {
+ char *cp = *cpp;
+ if (varcmp(cp, name) == 0)
+ return strchr(cp, '=') + 1;
+ cpp++;
+ }
+ }
+
+ vpp = get_ptr_to_local_var(name);
+ if (vpp)
+ return strchr((*vpp)->varstr, '=') + 1;
+
+#ifndef __U_BOOT__
+ if (strcmp(name, "PPID") == 0)
+ return utoa(G.root_ppid);
+#endif /* !__U_BOOT__ */
+ // bash compat: UID? EUID?
+#if ENABLE_HUSH_RANDOM_SUPPORT
+ if (strcmp(name, "RANDOM") == 0)
+ return utoa(next_random(&G.random_gen));
+#endif
+#if ENABLE_HUSH_LINENO_VAR
+ if (strcmp(name, "LINENO") == 0)
+ return utoa(G.execute_lineno);
+#endif
+#if BASH_EPOCH_VARS
+ {
+ const char *fmt = NULL;
+ if (strcmp(name, "EPOCHSECONDS") == 0)
+ fmt = "%llu";
+ else if (strcmp(name, "EPOCHREALTIME") == 0)
+ fmt = "%llu.%06u";
+ if (fmt) {
+ struct timeval tv;
+ xgettimeofday(&tv);
+ sprintf(G.epoch_buf, fmt, (unsigned long long)tv.tv_sec,
+ (unsigned)tv.tv_usec);
+ return G.epoch_buf;
+ }
+ }
+#endif
+ return NULL;
+}
+
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_GETOPTS
+static void handle_changed_special_names(const char *name)
+{
+ if (varcmp(name, "OPTIND") == 0) {
+ G.getopt_count = 0;
+ return;
+ }
+}
+#else
+/* Do not even bother evaluating arguments */
+# define handle_changed_special_names(...) ((void)0)
+#endif
+#else /* __U_BOOT__ */
+/* Do not even bother evaluating arguments */
+# define handle_changed_special_names(...) ((void)0)
+#endif /* __U_BOOT__ */
+
+/* str holds "NAME=VAL" and is expected to be malloced.
+ * We take ownership of it.
+ */
+#ifndef __U_BOOT__
+#define SETFLAG_EXPORT (1 << 0)
+#define SETFLAG_UNEXPORT (1 << 1)
+#define SETFLAG_MAKE_RO (1 << 2)
+#endif /* !__U_BOOT__ */
+#define SETFLAG_VARLVL_SHIFT 3
+#ifndef __U_BOOT__
+static int set_local_var(char *str, unsigned flags)
+#else /* __U_BOOT__ */
+int set_local_var_modern(char *str, int flags)
+#endif /* __U_BOOT__ */
+{
+ struct variable **cur_pp;
+ struct variable *cur;
+ char *free_me = NULL;
+ char *eq_sign;
+ int name_len;
+ int retval;
+#ifndef __U_BOOT__
+ unsigned local_lvl = (flags >> SETFLAG_VARLVL_SHIFT);
+#endif /* !__U_BOOT__ */
+
+ eq_sign = strchr(str, '=');
+ if (HUSH_DEBUG && !eq_sign)
+ bb_simple_error_msg_and_die("BUG in setvar");
+
+ name_len = eq_sign - str + 1; /* including '=' */
+ cur_pp = &G.top_var;
+ while ((cur = *cur_pp) != NULL) {
+ if (strncmp(cur->varstr, str, name_len) != 0) {
+ cur_pp = &cur->next;
+ continue;
+ }
+
+#ifndef __U_BOOT__
+ /* We found an existing var with this name */
+ if (cur->flg_read_only) {
+ bb_error_msg("%s: readonly variable", str);
+ free(str);
+//NOTE: in bash, assignment in "export READONLY_VAR=Z" fails, and sets $?=1,
+//but export per se succeeds (does put the var in env). We don't mimic that.
+ return -1;
+ }
+ if (flags & SETFLAG_UNEXPORT) { // && cur->flg_export ?
+ debug_printf_env("%s: unsetenv '%s'\n", __func__, str);
+ *eq_sign = '\0';
+ unsetenv(str);
+ *eq_sign = '=';
+ }
+ if (cur->var_nest_level < local_lvl) {
+ /* bash 3.2.33(1) and exported vars:
+ * # export z=z
+ * # f() { local z=a; env | grep ^z; }
+ * # f
+ * z=a
+ * # env | grep ^z
+ * z=z
+ */
+ if (cur->flg_export)
+ flags |= SETFLAG_EXPORT;
+ /* New variable is local ("local VAR=VAL" or
+ * "VAR=VAL cmd")
+ * and existing one is global, or local
+ * on a lower level that new one.
+ * Remove it from global variable list:
+ */
+ *cur_pp = cur->next;
+ if (G.shadowed_vars_pp) {
+ /* Save in "shadowed" list */
+ debug_printf_env("shadowing %s'%s'/%u by '%s'/%u\n",
+ cur->flg_export ? "exported " : "",
+ cur->varstr, cur->var_nest_level, str, local_lvl
+ );
+ cur->next = *G.shadowed_vars_pp;
+ *G.shadowed_vars_pp = cur;
+ } else {
+ /* Came from pseudo_exec_argv(), no need to save: delete it */
+ debug_printf_env("shadow-deleting %s'%s'/%u by '%s'/%u\n",
+ cur->flg_export ? "exported " : "",
+ cur->varstr, cur->var_nest_level, str, local_lvl
+ );
+ if (cur->max_len == 0) /* allocated "VAR=VAL"? */
+ free_me = cur->varstr; /* then free it later */
+ free(cur);
+ }
+ break;
+ }
+#endif /* !__U_BOOT__ */
+
+ if (strcmp(cur->varstr + name_len, eq_sign + 1) == 0) {
+ debug_printf_env("assignement '%s' does not change anything\n", str);
+ free_and_exp:
+ free(str);
+ goto exp;
+ }
+
+ /* Replace the value in the found "struct variable" */
+ if (cur->max_len != 0) {
+ if (cur->max_len >= strnlen(str, cur->max_len + 1)) {
+ /* This one is from startup env, reuse space */
+ debug_printf_env("reusing startup env for '%s'\n", str);
+ strcpy(cur->varstr, str);
+ goto free_and_exp;
+ }
+ /* Can't reuse */
+ cur->max_len = 0;
+ goto set_str_and_exp;
+ }
+ /* max_len == 0 signifies "malloced" var, which we can
+ * (and have to) free. But we can't free(cur->varstr) here:
+ * if cur->flg_export is 1, it is in the environment.
+ * We should either unsetenv+free, or wait until putenv,
+ * then putenv(new)+free(old).
+ */
+ free_me = cur->varstr;
+ goto set_str_and_exp;
+ }
+
+ /* Not found or shadowed - create new variable struct */
+#ifndef __U_BOOT__
+ debug_printf_env("%s: alloc new var '%s'/%u\n", __func__, str, local_lvl);
+#else /* __U_BOOT__ */
+ debug_printf_env("%s: alloc new var '%s'\n", __func__, str);
+#endif /* __U_BOOT__ */
+ cur = xzalloc(sizeof(*cur));
+#ifndef __U_BOOT__
+ cur->var_nest_level = local_lvl;
+#endif /* !__U_BOOT__ */
+ cur->next = *cur_pp;
+ *cur_pp = cur;
+
+ set_str_and_exp:
+ cur->varstr = str;
+ exp:
+#ifndef __U_BOOT__
+#if !BB_MMU || ENABLE_HUSH_READONLY
+ if (flags & SETFLAG_MAKE_RO) {
+ cur->flg_read_only = 1;
+ }
+#endif
+ if (flags & SETFLAG_EXPORT)
+ cur->flg_export = 1;
+#endif /* !__U_BOOT__ */
+ retval = 0;
+#ifndef __U_BOOT__
+ if (cur->flg_export) {
+ if (flags & SETFLAG_UNEXPORT) {
+ cur->flg_export = 0;
+ /* unsetenv was already done */
+ } else {
+ debug_printf_env("%s: putenv '%s'/%u\n", __func__, cur->varstr, cur->var_nest_level);
+ retval = putenv(cur->varstr);
+ /* fall through to "free(free_me)" -
+ * only now we can free old exported malloced string
+ */
+ }
+ }
+#endif /* !__U_BOOT__ */
+ free(free_me);
+
+ handle_changed_special_names(cur->varstr);
+
+ return retval;
+}
+
+#ifndef __U_BOOT__
+static int set_local_var0(char *str)
+{
+ return set_local_var(str, 0);
+}
+
+static void FAST_FUNC set_local_var_from_halves(const char *name, const char *val)
+{
+ char *var = xasprintf("%s=%s", name, val);
+ set_local_var0(var);
+}
+
+/* Used at startup and after each cd */
+static void set_pwd_var(unsigned flag)
+{
+ set_local_var(xasprintf("PWD=%s", get_cwd(/*force:*/ 1)), flag);
+}
+#endif /* !__U_BOOT__ */
+
+#if ENABLE_HUSH_UNSET || ENABLE_HUSH_GETOPTS
+static int unset_local_var(const char *name)
+{
+ struct variable *cur;
+ struct variable **cur_pp;
+
+ cur_pp = &G.top_var;
+ while ((cur = *cur_pp) != NULL) {
+ if (varcmp(cur->varstr, name) == 0) {
+ if (cur->flg_read_only) {
+ bb_error_msg("%s: readonly variable", name);
+ return EXIT_FAILURE;
+ }
+
+ *cur_pp = cur->next;
+ debug_printf_env("%s: unsetenv '%s'\n", __func__, cur->varstr);
+ bb_unsetenv(cur->varstr);
+ if (!cur->max_len)
+ free(cur->varstr);
+ free(cur);
+
+ break;
+ }
+ cur_pp = &cur->next;
+ }
+
+ /* Handle "unset LINENO" et al even if did not find the variable to unset */
+ handle_changed_special_names(name);
+
+ return EXIT_SUCCESS;
+}
+#endif
+
+
+#ifndef __U_BOOT__
+/*
+ * Helpers for "var1=val1 var2=val2 cmd" feature
+ */
+static void add_vars(struct variable *var)
+{
+ struct variable *next;
+
+ while (var) {
+ next = var->next;
+ var->next = G.top_var;
+ G.top_var = var;
+ if (var->flg_export) {
+ debug_printf_env("%s: restoring exported '%s'/%u\n", __func__, var->varstr, var->var_nest_level);
+ putenv(var->varstr);
+ } else {
+ debug_printf_env("%s: restoring variable '%s'/%u\n", __func__, var->varstr, var->var_nest_level);
+ }
+ var = next;
+ }
+}
+
+/* We put strings[i] into variable table and possibly putenv them.
+ * If variable is read only, we can free the strings[i]
+ * which attempts to overwrite it.
+ * The strings[] vector itself is freed.
+ */
+static void set_vars_and_save_old(char **strings)
+{
+ char **s;
+
+ if (!strings)
+ return;
+
+ s = strings;
+ while (*s) {
+ struct variable *var_p;
+ struct variable **var_pp;
+ char *eq;
+
+ eq = strchr(*s, '=');
+ if (HUSH_DEBUG && !eq)
+ bb_simple_error_msg_and_die("BUG in varexp4");
+ var_pp = get_ptr_to_local_var(*s);
+ if (var_pp) {
+ var_p = *var_pp;
+ if (var_p->flg_read_only) {
+ char **p;
+ bb_error_msg("%s: readonly variable", *s);
+ /*
+ * "VAR=V BLTIN" unsets VARs after BLTIN completes.
+ * If VAR is readonly, leaving it in the list
+ * after asssignment error (msg above)
+ * causes doubled error message later, on unset.
+ */
+ debug_printf_env("removing/freeing '%s' element\n", *s);
+ free(*s);
+ p = s;
+ do { *p = p[1]; p++; } while (*p);
+ goto next;
+ }
+ /* below, set_local_var() with nest level will
+ * "shadow" (remove) this variable from
+ * global linked list.
+ */
+ }
+ debug_printf_env("%s: env override '%s'/%u\n", __func__, *s, G.var_nest_level);
+ set_local_var(*s, (G.var_nest_level << SETFLAG_VARLVL_SHIFT) | SETFLAG_EXPORT);
+ s++;
+ next: ;
+ }
+ free(strings);
+}
+
+
+/*
+ * Unicode helper
+ */
+static void reinit_unicode_for_hush(void)
+{
+ /* Unicode support should be activated even if LANG is set
+ * _during_ shell execution, not only if it was set when
+ * shell was started. Therefore, re-check LANG every time:
+ */
+ if (ENABLE_FEATURE_CHECK_UNICODE_IN_ENV
+ || ENABLE_UNICODE_USING_LOCALE
+ ) {
+ const char *s = get_local_var_value("LC_ALL");
+ if (!s) s = get_local_var_value("LC_CTYPE");
+ if (!s) s = get_local_var_value("LANG");
+ reinit_unicode(s);
+ }
+}
+
+#endif /* !__U_BOOT__ */
+/*
+ * in_str support (strings, and "strings" read from files).
+ */
+
+#if ENABLE_HUSH_INTERACTIVE
+#ifndef __U_BOOT__
+/* To test correct lineedit/interactive behavior, type from command line:
+ * echo $P\
+ * \
+ * AT\
+ * H\
+ * \
+ * It exercises a lot of corner cases.
+ */
+static const char *setup_prompt_string(void)
+{
+ const char *prompt_str;
+
+ debug_printf_prompt("%s promptmode:%d\n", __func__, G.promptmode);
+
+# if ENABLE_FEATURE_EDITING_FANCY_PROMPT
+ prompt_str = get_local_var_value(G.promptmode == 0 ? "PS1" : "PS2");
+ if (!prompt_str)
+ prompt_str = "";
+# else
+ prompt_str = "> "; /* if PS2, else... */
+ if (G.promptmode == 0) { /* PS1 */
+ /* No fancy prompts supported, (re)generate "CURDIR $ " by hand */
+ free(G.PS1);
+ /* bash uses $PWD value, even if it is set by user.
+ * It uses current dir only if PWD is unset.
+ * We always use current dir. */
+ prompt_str = G.PS1 = xasprintf("%s %c ", get_cwd(0), (geteuid() != 0) ? '$' : '#');
+ }
+# endif
+ debug_printf("prompt_str '%s'\n", prompt_str);
+ return prompt_str;
+}
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+static int get_user_input(struct in_str *i)
+#else /* __U_BOOT__ */
+static void get_user_input(struct in_str *i)
+#endif /* __U_BOOT__ */
+{
+#ifndef __U_BOOT__
+# if ENABLE_FEATURE_EDITING
+ /* In EDITING case, this function reads next input line,
+ * saves it in i->p, then returns 1st char of it.
+ */
+ int r;
+ const char *prompt_str;
+
+ prompt_str = setup_prompt_string();
+ for (;;) {
+ reinit_unicode_for_hush();
+ G.flag_SIGINT = 0;
+
+ bb_got_signal = 0;
+ if (!sigisemptyset(&G.pending_set)) {
+ /* Whoops, already got a signal, do not call read_line_input */
+ bb_got_signal = r = -1;
+ } else {
+ /* For shell, LI_INTERRUPTIBLE is set:
+ * read_line_input will abort on either
+ * getting EINTR in poll() and bb_got_signal became != 0,
+ * or if it sees bb_got_signal != 0
+ * (IOW: if signal arrives before poll() is reached).
+ * Interactive testcases:
+ * (while kill -INT $$; do sleep 1; done) &
+ * #^^^ prints ^C, prints prompt, repeats
+ * trap 'echo I' int; (while kill -INT $$; do sleep 1; done) &
+ * #^^^ prints ^C, prints "I", prints prompt, repeats
+ * trap 'echo T' term; (while kill $$; do sleep 1; done) &
+ * #^^^ prints "T", prints prompt, repeats
+ * #(bash 5.0.17 exits after first "T", looks like a bug)
+ */
+ r = read_line_input(G.line_input_state, prompt_str,
+ G.user_input_buf, CONFIG_FEATURE_EDITING_MAX_LEN-1
+ );
+ /* read_line_input intercepts ^C, "convert" it to SIGINT */
+ if (r == 0)
+ raise(SIGINT);
+ }
+ /* bash prints ^C (before running a trap, if any)
+ * both on keyboard ^C and on real SIGINT (non-kbd generated).
+ */
+ if (sigismember(&G.pending_set, SIGINT)) {
+ write(STDOUT_FILENO, "^C\n", 3);
+ G.last_exitcode = 128 | SIGINT;
+ }
+ check_and_run_traps();
+ if (r == 0) /* keyboard ^C? */
+ continue; /* go back, read another input line */
+ if (r > 0) /* normal input? (no ^C, no ^D, no signals) */
+ break;
+ if (!bb_got_signal) {
+ /* r < 0: ^D/EOF/error detected (but not signal) */
+ /* ^D on interactive input goes to next line before exiting: */
+ write(STDOUT_FILENO, "\n", 1);
+ i->p = NULL;
+ i->peek_buf[0] = r = EOF;
+ return r;
+ }
+ /* it was a signal: go back, read another input line */
+ }
+ i->p = G.user_input_buf;
+ return (unsigned char)*i->p++;
+# else
+ /* In !EDITING case, this function gets called for every char.
+ * Buffering happens deeper in the call chain, in hfgetc(i->file).
+ */
+ int r;
+
+ for (;;) {
+ G.flag_SIGINT = 0;
+ if (i->last_char == '\0' || i->last_char == '\n') {
+ const char *prompt_str = setup_prompt_string();
+ /* Why check_and_run_traps here? Try this interactively:
+ * $ trap 'echo INT' INT; (sleep 2; kill -INT $$) &
+ * $ <[enter], repeatedly...>
+ * Without check_and_run_traps, handler never runs.
+ */
+ check_and_run_traps();
+ fputs_stdout(prompt_str);
+ fflush_all();
+ }
+ r = hfgetc(i->file);
+ /* In !ENABLE_FEATURE_EDITING we don't use read_line_input,
+ * no ^C masking happens during fgetc, no special code for ^C:
+ * it generates SIGINT as usual.
+ */
+ check_and_run_traps();
+ if (r != '\0' && !G.flag_SIGINT)
+ break;
+ if (G.flag_SIGINT) {
+ /* ^C or SIGINT: repeat */
+ /* bash prints ^C even on real SIGINT (non-kbd generated) */
+ /* kernel prints "^C" itself, just print newline: */
+ write(STDOUT_FILENO, "\n", 1);
+ G.last_exitcode = 128 | SIGINT;
+ }
+ }
+ return r;
+# endif
+#else /* __U_BOOT__ */
+ int n;
+ int promptme;
+ static char the_command[CONFIG_SYS_CBSIZE + 1];
+
+ bootretry_reset_cmd_timeout();
+ promptme = 1;
+ n = u_boot_cli_readline(i);
+
+# ifdef CONFIG_BOOT_RETRY_TIME
+ if (n == -2) {
+ puts("\nTimeout waiting for command\n");
+# ifdef CONFIG_RESET_TO_RETRY
+ do_reset(NULL, 0, 0, NULL);
+# else
+# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# endif
+ }
+# endif
+ if (n == -1 ) {
+ G.flag_repeat = 0;
+ promptme = 0;
+ }
+ n = strlen(console_buffer);
+ console_buffer[n] = '\n';
+ console_buffer[n+1]= '\0';
+ if (had_ctrlc())
+ G.flag_repeat = 0;
+ clear_ctrlc();
+ G.do_repeat = 0;
+#ifndef __U_BOOT__
+ if (G.promptmode == 1) {
+#else /* __U_BOOT__ */
+ if (!G.promptmode) {
+#endif /* __U_BOOT__ */
+ if (console_buffer[0] == '\n'&& G.flag_repeat == 0) {
+ strcpy(the_command, console_buffer);
+ }
+ else {
+ if (console_buffer[0] != '\n') {
+ strcpy(the_command, console_buffer);
+ G.flag_repeat = 1;
+ }
+ else {
+ G.do_repeat = 1;
+ }
+ }
+ i->p = the_command;
+ }
+ else {
+ if (console_buffer[0] != '\n') {
+ if (strlen(the_command) + strlen(console_buffer)
+ < CONFIG_SYS_CBSIZE) {
+ n = strlen(the_command);
+#ifdef __U_BOOT__
+ /*
+ * To avoid writing to bad places, we check if
+ * n is greater than 0.
+ * This bug was found by Harald Seiler.
+ */
+ if (n > 0)
+ the_command[n-1] = ' ';
+ strcpy(&the_command[n], console_buffer);
+#else /* !__U_BOOT__ */
+ the_command[n-1] = ' ';
+ strcpy(&the_command[n], console_buffer);
+#endif /* !__U_BOOT__ */
+ }
+ else {
+ the_command[0] = '\n';
+ the_command[1] = '\0';
+ G.flag_repeat = 0;
+ }
+ }
+ if (promptme == 0) {
+ the_command[0] = '\n';
+ the_command[1] = '\0';
+ }
+ i->p = console_buffer;
+ }
+#endif /* __U_BOOT__ */
+}
+/* This is the magic location that prints prompts
+ * and gets data back from the user */
+static int fgetc_interactive(struct in_str *i)
+{
+ int ch;
+#ifndef __U_BOOT__
+ /* If it's interactive stdin, get new line. */
+ if (G_interactive_fd && i->file == G.HFILE_stdin) {
+#endif /* !__U_BOOT__ */
+#ifndef __U_BOOT__
+ /* Returns first char (or EOF), the rest is in i->p[] */
+ ch = get_user_input(i);
+#else /* __U_BOOT__ */
+ /* Avoid garbage value and make clang happy. */
+ ch = 0;
+ /*
+ * get_user_input() does not return anything when used in
+ * U-Boot.
+ * So, we need to take the read character from i->p[].
+ */
+ get_user_input(i);
+ if (i->p && *i->p) {
+ ch = *i->p++;
+ }
+#endif /* __U_BOOT__ */
+ G.promptmode = 1; /* PS2 */
+ debug_printf_prompt("%s promptmode=%d\n", __func__, G.promptmode);
+#ifndef __U_BOOT__
+ } else {
+ /* Not stdin: script file, sourced file, etc */
+ do ch = hfgetc(i->file); while (ch == '\0');
+ }
+#endif /* !__U_BOOT__ */
+ return ch;
+}
+#else /* !INTERACTIVE */
+#ifndef __U_BOOT__
+static ALWAYS_INLINE int fgetc_interactive(struct in_str *i)
+{
+ int ch;
+ do ch = hfgetc(i->file); while (ch == '\0');
+ return ch;
+}
+#endif /* !__U_BOOT__ */
+#endif /* !INTERACTIVE */
+
+static int i_getch(struct in_str *i)
+{
+ int ch;
+
+#ifndef __U_BOOT__
+ if (!i->file) {
+ /* string-based in_str */
+ ch = (unsigned char)*i->p;
+ if (ch != '\0') {
+ i->p++;
+ i->last_char = ch;
+#if ENABLE_HUSH_LINENO_VAR
+ if (ch == '\n') {
+ G.parse_lineno++;
+ debug_printf_parse("G.parse_lineno++ = %u\n", G.parse_lineno);
+ }
+#endif
+ return ch;
+ }
+ return EOF;
+ }
+
+#endif /* !__U_BOOT__ */
+ /* FILE-based in_str */
+
+#if ENABLE_FEATURE_EDITING
+ /* This can be stdin, check line editing char[] buffer */
+ if (i->p && *i->p != '\0') {
+ ch = (unsigned char)*i->p++;
+ goto out;
+#ifndef __U_BOOT__
+ }
+#else /* __U_BOOT__ */
+ /*
+ * There are two ways for command to be called:
+ * 1. The first one is when they are typed by the user.
+ * 2. The second one is through run_command() (NOTE command run
+ * internally calls run_command()).
+ *
+ * In the second case, we do not get input from the user, so once we
+ * get a '\0', it means we need to stop.
+ * NOTE G.run_command_flags is only set on run_command call stack, so
+ * we use this to know if we come from user input or run_command().
+ */
+ } else if (i->p && *i->p == '\0' && G.run_command_flags){
+ return EOF;
+ }
+#endif /* __U_BOOT__ */
+#endif
+#ifndef __U_BOOT__
+ /* peek_buf[] is an int array, not char. Can contain EOF. */
+ ch = i->peek_buf[0];
+ if (ch != 0) {
+ int ch2 = i->peek_buf[1];
+ i->peek_buf[0] = ch2;
+ if (ch2 == 0) /* very likely, avoid redundant write */
+ goto out;
+ i->peek_buf[1] = 0;
+ goto out;
+ }
+
+#endif /* !__U_BOOT__ */
+ ch = fgetc_interactive(i);
+ out:
+ debug_printf("file_get: got '%c' %d\n", ch, ch);
+ i->last_char = ch;
+#if ENABLE_HUSH_LINENO_VAR
+ if (ch == '\n') {
+ G.parse_lineno++;
+ debug_printf_parse("G.parse_lineno++ = %u\n", G.parse_lineno);
+ }
+#endif
+ return ch;
+}
+
+static int i_peek(struct in_str *i)
+{
+#ifndef __U_BOOT__
+ int ch;
+
+ if (!i->file) {
+ /* string-based in_str */
+ /* Doesn't report EOF on NUL. None of the callers care. */
+ return (unsigned char)*i->p;
+ }
+
+ /* FILE-based in_str */
+
+#if ENABLE_FEATURE_EDITING && ENABLE_HUSH_INTERACTIVE
+ /* This can be stdin, check line editing char[] buffer */
+ if (i->p && *i->p != '\0')
+ return (unsigned char)*i->p;
+#endif
+ /* peek_buf[] is an int array, not char. Can contain EOF. */
+ ch = i->peek_buf[0];
+ if (ch != 0)
+ return ch;
+
+ /* Need to get a new char */
+ ch = fgetc_interactive(i);
+ debug_printf("file_peek: got '%c' %d\n", ch, ch);
+
+ /* Save it by either rolling back line editing buffer, or in i->peek_buf[0] */
+#if ENABLE_FEATURE_EDITING && ENABLE_HUSH_INTERACTIVE
+ if (i->p) {
+ i->p -= 1;
+ return ch;
+ }
+#endif
+ i->peek_buf[0] = ch;
+ /*i->peek_buf[1] = 0; - already is */
+ return ch;
+#else /* __U_BOOT__ */
+ /* string-based in_str */
+ /* Doesn't report EOF on NUL. None of the callers care. */
+ return (unsigned char)*i->p;
+#endif /* __U_BOOT__ */
+}
+
+/* Only ever called if i_peek() was called, and did not return EOF.
+ * IOW: we know the previous peek saw an ordinary char, not EOF, not NUL,
+ * not end-of-line. Therefore we never need to read a new editing line here.
+ */
+static int i_peek2(struct in_str *i)
+{
+#ifndef __U_BOOT__
+ int ch;
+#endif /* !__U_BOOT__ */
+
+ /* There are two cases when i->p[] buffer exists.
+ * (1) it's a string in_str.
+ * (2) It's a file, and we have a saved line editing buffer.
+ * In both cases, we know that i->p[0] exists and not NUL, and
+ * the peek2 result is in i->p[1].
+ */
+ if (i->p)
+ return (unsigned char)i->p[1];
+
+#ifndef __U_BOOT__
+ /* Now we know it is a file-based in_str. */
+
+ /* peek_buf[] is an int array, not char. Can contain EOF. */
+ /* Is there 2nd char? */
+ ch = i->peek_buf[1];
+ if (ch == 0) {
+ /* We did not read it yet, get it now */
+ do ch = hfgetc(i->file); while (ch == '\0');
+ i->peek_buf[1] = ch;
+ }
+
+ debug_printf("file_peek2: got '%c' %d\n", ch, ch);
+ return ch;
+#else
+ return 0;
+#endif /* __U_BOOT__ */
+}
+
+static int i_getch_and_eat_bkslash_nl(struct in_str *input)
+{
+ for (;;) {
+ int ch, ch2;
+
+ ch = i_getch(input);
+ if (ch != '\\')
+ return ch;
+ ch2 = i_peek(input);
+ if (ch2 != '\n')
+ return ch;
+ /* backslash+newline, skip it */
+ i_getch(input);
+ }
+}
+
+/* Note: this function _eats_ \<newline> pairs, safe to use plain
+ * i_getch() after it instead of i_getch_and_eat_bkslash_nl().
+ */
+static int i_peek_and_eat_bkslash_nl(struct in_str *input)
+{
+ for (;;) {
+ int ch, ch2;
+
+ ch = i_peek(input);
+ if (ch != '\\')
+ return ch;
+ ch2 = i_peek2(input);
+ if (ch2 != '\n')
+ return ch;
+ /* backslash+newline, skip it */
+ i_getch(input);
+ i_getch(input);
+ }
+}
+
+#ifndef __U_BOOT__
+static void setup_file_in_str(struct in_str *i, HFILE *fp)
+#else /* __U_BOOT__ */
+static void setup_file_in_str(struct in_str *i)
+#endif /* __U_BOOT__ */
+{
+ memset(i, 0, sizeof(*i));
+#ifndef __U_BOOT__
+ i->file = fp;
+ /* i->p = NULL; */
+#endif /* !__U_BOOT__ */
+}
+
+static void setup_string_in_str(struct in_str *i, const char *s)
+{
+ memset(i, 0, sizeof(*i));
+ /*i->file = NULL */;
+ i->p = s;
+}
+
+
+/*
+ * o_string support
+ */
+#define B_CHUNK (32 * sizeof(char*))
+
+static void o_reset_to_empty_unquoted(o_string *o)
+{
+ o->length = 0;
+ o->has_quoted_part = 0;
+ if (o->data)
+ o->data[0] = '\0';
+}
+
+static void o_free_and_set_NULL(o_string *o)
+{
+ free(o->data);
+ memset(o, 0, sizeof(*o));
+}
+
+static ALWAYS_INLINE void o_free(o_string *o)
+{
+ free(o->data);
+}
+
+static void o_grow_by(o_string *o, int len)
+{
+ if (o->length + len > o->maxlen) {
+ o->maxlen += (2 * len) | (B_CHUNK-1);
+ o->data = xrealloc(o->data, 1 + o->maxlen);
+ }
+}
+
+static void o_addchr(o_string *o, int ch)
+{
+ debug_printf("o_addchr: '%c' o->length=%d o=%p\n", ch, o->length, o);
+ if (o->length < o->maxlen) {
+ /* likely. avoid o_grow_by() call */
+ add:
+ o->data[o->length] = ch;
+ o->length++;
+ o->data[o->length] = '\0';
+ return;
+ }
+ o_grow_by(o, 1);
+ goto add;
+}
+
+#if 0
+/* Valid only if we know o_string is not empty */
+static void o_delchr(o_string *o)
+{
+ o->length--;
+ o->data[o->length] = '\0';
+}
+#endif
+
+static void o_addblock(o_string *o, const char *str, int len)
+{
+ o_grow_by(o, len);
+ ((char*)mempcpy(&o->data[o->length], str, len))[0] = '\0';
+ o->length += len;
+}
+
+static void o_addstr(o_string *o, const char *str)
+{
+ o_addblock(o, str, strlen(str));
+}
+
+#ifndef __U_BOOT__
+static void o_addstr_with_NUL(o_string *o, const char *str)
+{
+ o_addblock(o, str, strlen(str) + 1);
+}
+#endif /* !__U_BOOT__ */
+
+#if !BB_MMU
+static void nommu_addchr(o_string *o, int ch)
+{
+ if (o)
+ o_addchr(o, ch);
+}
+#else
+# define nommu_addchr(o, str) ((void)0)
+#endif
+
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_MODE_X
+static void x_mode_addchr(int ch)
+{
+ o_addchr(&G.x_mode_buf, ch);
+}
+static void x_mode_addstr(const char *str)
+{
+ o_addstr(&G.x_mode_buf, str);
+}
+static void x_mode_addblock(const char *str, int len)
+{
+ o_addblock(&G.x_mode_buf, str, len);
+}
+static void x_mode_prefix(void)
+{
+ int n = G.x_mode_depth;
+ do x_mode_addchr('+'); while (--n >= 0);
+}
+static void x_mode_flush(void)
+{
+ int len = G.x_mode_buf.length;
+ if (len <= 0)
+ return;
+ if (G.x_mode_fd > 0) {
+ G.x_mode_buf.data[len] = '\n';
+ full_write(G.x_mode_fd, G.x_mode_buf.data, len + 1);
+ }
+ G.x_mode_buf.length = 0;
+}
+#endif
+#endif /* !__U_BOOT__ */
+
+/*
+ * HUSH_BRACE_EXPANSION code needs corresponding quoting on variable expansion side.
+ * Currently, "v='{q,w}'; echo $v" erroneously expands braces in $v.
+ * Apparently, on unquoted $v bash still does globbing
+ * ("v='*.txt'; echo $v" prints all .txt files),
+ * but NOT brace expansion! Thus, there should be TWO independent
+ * quoting mechanisms on $v expansion side: one protects
+ * $v from brace expansion, and other additionally protects "$v" against globbing.
+ * We have only second one.
+ */
+
+#if ENABLE_HUSH_BRACE_EXPANSION
+# define MAYBE_BRACES "{}"
+#else
+# define MAYBE_BRACES ""
+#endif
+
+/* My analysis of quoting semantics tells me that state information
+ * is associated with a destination, not a source.
+ */
+static void o_addqchr(o_string *o, int ch)
+{
+ int sz = 1;
+ /* '-' is included because of this case:
+ * >filename0 >filename1 >filename9; v='-'; echo filename[0"$v"9]
+ */
+ char *found = strchr("*?[-\\" MAYBE_BRACES, ch);
+ if (found)
+ sz++;
+ o_grow_by(o, sz);
+ if (found) {
+ o->data[o->length] = '\\';
+ o->length++;
+ }
+ o->data[o->length] = ch;
+ o->length++;
+ o->data[o->length] = '\0';
+}
+
+static void o_addQchr(o_string *o, int ch)
+{
+ int sz = 1;
+ if ((o->o_expflags & EXP_FLAG_ESC_GLOB_CHARS)
+ && strchr("*?[-\\" MAYBE_BRACES, ch)
+ ) {
+ sz++;
+ o->data[o->length] = '\\';
+ o->length++;
+ }
+ o_grow_by(o, sz);
+ o->data[o->length] = ch;
+ o->length++;
+ o->data[o->length] = '\0';
+}
+
+static void o_addqblock(o_string *o, const char *str, int len)
+{
+ while (len) {
+ char ch;
+ int sz;
+ int ordinary_cnt = strcspn(str, "*?[-\\" MAYBE_BRACES);
+ if (ordinary_cnt > len) /* paranoia */
+ ordinary_cnt = len;
+ o_addblock(o, str, ordinary_cnt);
+ if (ordinary_cnt == len)
+ return; /* NUL is already added by o_addblock */
+ str += ordinary_cnt;
+ len -= ordinary_cnt + 1; /* we are processing + 1 char below */
+
+ ch = *str++;
+ sz = 1;
+ if (ch) { /* it is necessarily one of "*?[-\\" MAYBE_BRACES */
+ sz++;
+ o->data[o->length] = '\\';
+ o->length++;
+ }
+ o_grow_by(o, sz);
+ o->data[o->length] = ch;
+ o->length++;
+ }
+ o->data[o->length] = '\0';
+}
+
+static void o_addQblock(o_string *o, const char *str, int len)
+{
+ if (!(o->o_expflags & EXP_FLAG_ESC_GLOB_CHARS)) {
+ o_addblock(o, str, len);
+ return;
+ }
+ o_addqblock(o, str, len);
+}
+
+static void o_addQstr(o_string *o, const char *str)
+{
+ o_addQblock(o, str, strlen(str));
+}
+
+/* A special kind of o_string for $VAR and `cmd` expansion.
+ * It contains char* list[] at the beginning, which is grown in 16 element
+ * increments. Actual string data starts at the next multiple of 16 * (char*).
+ * list[i] contains an INDEX (int!) into this string data.
+ * It means that if list[] needs to grow, data needs to be moved higher up
+ * but list[i]'s need not be modified.
+ * NB: remembering how many list[i]'s you have there is crucial.
+ * o_finalize_list() operation post-processes this structure - calculates
+ * and stores actual char* ptrs in list[]. Oh, it NULL terminates it as well.
+ */
+#if DEBUG_EXPAND || DEBUG_GLOB
+static void debug_print_list(const char *prefix, o_string *o, int n)
+{
+ char **list = (char**)o->data;
+ int string_start = ((n + 0xf) & ~0xf) * sizeof(list[0]);
+ int i = 0;
+
+ indent();
+ fdprintf(2, "%s: list:%p n:%d string_start:%d length:%d maxlen:%d glob:%d quoted:%d escape:%d\n",
+ prefix, list, n, string_start, o->length, o->maxlen,
+ !!(o->o_expflags & EXP_FLAG_GLOB),
+ o->has_quoted_part,
+ !!(o->o_expflags & EXP_FLAG_ESC_GLOB_CHARS));
+ while (i < n) {
+ indent();
+ fdprintf(2, " list[%d]=%d '%s' %p\n", i, (int)(uintptr_t)list[i],
+ o->data + (int)(uintptr_t)list[i] + string_start,
+ o->data + (int)(uintptr_t)list[i] + string_start);
+ i++;
+ }
+ if (n) {
+ const char *p = o->data + (int)(uintptr_t)list[n - 1] + string_start;
+ indent();
+#ifndef __U_BOOT__
+ fdprintf(2, " total_sz:%ld\n", (long)((p + strlen(p) + 1) - o->data));
+#else /* __U_BOOT__ */
+ printf(" total_sz:%ld\n", (long)((p + strlen(p) + 1) - o->data));
+#endif /* __U_BOOT__ */
+ }
+}
+#else
+# define debug_print_list(prefix, o, n) ((void)0)
+#endif
+
+/* n = o_save_ptr_helper(str, n) "starts new string" by storing an index value
+ * in list[n] so that it points past last stored byte so far.
+ * It returns n+1. */
+static int o_save_ptr_helper(o_string *o, int n)
+{
+ char **list = (char**)o->data;
+ int string_start;
+ int string_len;
+
+ if (!o->has_empty_slot) {
+ string_start = ((n + 0xf) & ~0xf) * sizeof(list[0]);
+ string_len = o->length - string_start;
+ if (!(n & 0xf)) { /* 0, 0x10, 0x20...? */
+ debug_printf_list("list[%d]=%d string_start=%d (growing)\n", n, string_len, string_start);
+ /* list[n] points to string_start, make space for 16 more pointers */
+ o->maxlen += 0x10 * sizeof(list[0]);
+ o->data = xrealloc(o->data, o->maxlen + 1);
+ list = (char**)o->data;
+ memmove(list + n + 0x10, list + n, string_len);
+ /*
+ * expand_on_ifs() has a "previous argv[] ends in IFS?"
+ * check. (grep for -prev-ifs-check-).
+ * Ensure that argv[-1][last] is not garbage
+ * but zero bytes, to save index check there.
+ */
+ list[n + 0x10 - 1] = 0;
+ o->length += 0x10 * sizeof(list[0]);
+ } else {
+ debug_printf_list("list[%d]=%d string_start=%d\n",
+ n, string_len, string_start);
+ }
+ } else {
+ /* We have empty slot at list[n], reuse without growth */
+ string_start = ((n+1 + 0xf) & ~0xf) * sizeof(list[0]); /* NB: n+1! */
+ string_len = o->length - string_start;
+ debug_printf_list("list[%d]=%d string_start=%d (empty slot)\n",
+ n, string_len, string_start);
+ o->has_empty_slot = 0;
+ }
+ o->has_quoted_part = 0;
+ list[n] = (char*)(uintptr_t)string_len;
+ return n + 1;
+}
+
+/* "What was our last o_save_ptr'ed position (byte offset relative o->data)?" */
+static int o_get_last_ptr(o_string *o, int n)
+{
+ char **list = (char**)o->data;
+ int string_start = ((n + 0xf) & ~0xf) * sizeof(list[0]);
+
+ return ((int)(uintptr_t)list[n-1]) + string_start;
+}
+
+/*
+ * Globbing routines.
+ *
+ * Most words in commands need to be globbed, even ones which are
+ * (single or double) quoted. This stems from the possiblity of
+ * constructs like "abc"* and 'abc'* - these should be globbed.
+ * Having a different code path for fully-quoted strings ("abc",
+ * 'abc') would only help performance-wise, but we still need
+ * code for partially-quoted strings.
+ *
+ * Unfortunately, if we want to match bash and ash behavior in all cases,
+ * the logic can't be "shell-syntax argument is first transformed
+ * to a string, then globbed, and if globbing does not match anything,
+ * it is used verbatim". Here are two examples where it fails:
+ *
+ * echo 'b\*'?
+ *
+ * The globbing can't be avoided (because of '?' at the end).
+ * The glob pattern is: b\\\*? - IOW, both \ and * are literals
+ * and are glob-escaped. If this does not match, bash/ash print b\*?
+ * - IOW: they "unbackslash" the glob pattern.
+ * Now, look at this:
+ *
+ * v='\\\*'; echo b$v?
+ *
+ * The glob pattern is the same here: b\\\*? - the unquoted $v expansion
+ * should be used as glob pattern with no changes. However, if glob
+ * does not match, bash/ash print b\\\*? - NOT THE SAME as first example!
+ *
+ * ash implements this by having an encoded representation of the word
+ * to glob, which IS NOT THE SAME as the glob pattern - it has more data.
+ * Glob pattern is derived from it. If glob fails, the decision what result
+ * should be is made using that encoded representation. Not glob pattern.
+ */
+
+#if ENABLE_HUSH_BRACE_EXPANSION
+/* There in a GNU extension, GLOB_BRACE, but it is not usable:
+ * first, it processes even {a} (no commas), second,
+ * I didn't manage to make it return strings when they don't match
+ * existing files. Need to re-implement it.
+ */
+
+/* Helper */
+static int glob_needed(const char *s)
+{
+ while (*s) {
+ if (*s == '\\') {
+ if (!s[1])
+ return 0;
+ s += 2;
+ continue;
+ }
+ if (*s == '*' || *s == '[' || *s == '?' || *s == '{')
+ return 1;
+ s++;
+ }
+ return 0;
+}
+/* Return pointer to next closing brace or to comma */
+static const char *next_brace_sub(const char *cp)
+{
+ unsigned depth = 0;
+ cp++;
+ while (*cp != '\0') {
+ if (*cp == '\\') {
+ if (*++cp == '\0')
+ break;
+ cp++;
+ continue;
+ }
+ if ((*cp == '}' && depth-- == 0) || (*cp == ',' && depth == 0))
+ break;
+ if (*cp++ == '{')
+ depth++;
+ }
+
+ return *cp != '\0' ? cp : NULL;
+}
+/* Recursive brace globber. Note: may garble pattern[]. */
+static int glob_brace(char *pattern, o_string *o, int n)
+{
+ char *new_pattern_buf;
+ const char *begin;
+ const char *next;
+ const char *rest;
+ const char *p;
+ size_t rest_len;
+
+ debug_printf_glob("glob_brace('%s')\n", pattern);
+
+ begin = pattern;
+ while (1) {
+ if (*begin == '\0')
+ goto simple_glob;
+ if (*begin == '{') {
+ /* Find the first sub-pattern and at the same time
+ * find the rest after the closing brace */
+ next = next_brace_sub(begin);
+ if (next == NULL) {
+ /* An illegal expression */
+ goto simple_glob;
+ }
+ if (*next == '}') {
+ /* "{abc}" with no commas - illegal
+ * brace expr, disregard and skip it */
+ begin = next + 1;
+ continue;
+ }
+ break;
+ }
+ if (*begin == '\\' && begin[1] != '\0')
+ begin++;
+ begin++;
+ }
+ debug_printf_glob("begin:%s\n", begin);
+ debug_printf_glob("next:%s\n", next);
+
+ /* Now find the end of the whole brace expression */
+ rest = next;
+ while (*rest != '}') {
+ rest = next_brace_sub(rest);
+ if (rest == NULL) {
+ /* An illegal expression */
+ goto simple_glob;
+ }
+ debug_printf_glob("rest:%s\n", rest);
+ }
+ rest_len = strlen(++rest) + 1;
+
+ /* We are sure the brace expression is well-formed */
+
+ /* Allocate working buffer large enough for our work */
+ new_pattern_buf = xmalloc(strlen(pattern));
+
+ /* We have a brace expression. BEGIN points to the opening {,
+ * NEXT points past the terminator of the first element, and REST
+ * points past the final }. We will accumulate result names from
+ * recursive runs for each brace alternative in the buffer using
+ * GLOB_APPEND. */
+
+ p = begin + 1;
+ while (1) {
+ /* Construct the new glob expression */
+ memcpy(
+ mempcpy(
+ mempcpy(new_pattern_buf,
+ /* We know the prefix for all sub-patterns */
+ pattern, begin - pattern),
+ p, next - p),
+ rest, rest_len);
+
+ /* Note: glob_brace() may garble new_pattern_buf[].
+ * That's why we re-copy prefix every time (1st memcpy above).
+ */
+ n = glob_brace(new_pattern_buf, o, n);
+ if (*next == '}') {
+ /* We saw the last entry */
+ break;
+ }
+ p = next + 1;
+ next = next_brace_sub(next);
+ }
+ free(new_pattern_buf);
+ return n;
+
+ simple_glob:
+ {
+ int gr;
+ glob_t globdata;
+
+ memset(&globdata, 0, sizeof(globdata));
+ gr = glob(pattern, 0, NULL, &globdata);
+ debug_printf_glob("glob('%s'):%d\n", pattern, gr);
+ if (gr != 0) {
+ if (gr == GLOB_NOMATCH) {
+ globfree(&globdata);
+ /* NB: garbles parameter */
+ unbackslash(pattern);
+ o_addstr_with_NUL(o, pattern);
+ debug_printf_glob("glob pattern '%s' is literal\n", pattern);
+ return o_save_ptr_helper(o, n);
+ }
+ if (gr == GLOB_NOSPACE)
+ bb_die_memory_exhausted();
+ /* GLOB_ABORTED? Only happens with GLOB_ERR flag,
+ * but we didn't specify it. Paranoia again. */
+ bb_error_msg_and_die("glob error %d on '%s'", gr, pattern);
+ }
+ if (globdata.gl_pathv && globdata.gl_pathv[0]) {
+ char **argv = globdata.gl_pathv;
+ while (1) {
+ o_addstr_with_NUL(o, *argv);
+ n = o_save_ptr_helper(o, n);
+ argv++;
+ if (!*argv)
+ break;
+ }
+ }
+ globfree(&globdata);
+ }
+ return n;
+}
+/* Performs globbing on last list[],
+ * saving each result as a new list[].
+ */
+static int perform_glob(o_string *o, int n)
+{
+ char *pattern, *copy;
+
+ debug_printf_glob("start perform_glob: n:%d o->data:%p\n", n, o->data);
+ if (!o->data)
+ return o_save_ptr_helper(o, n);
+ pattern = o->data + o_get_last_ptr(o, n);
+ debug_printf_glob("glob pattern '%s'\n", pattern);
+ if (!glob_needed(pattern)) {
+ /* unbackslash last string in o in place, fix length */
+ o->length = unbackslash(pattern) - o->data;
+ debug_printf_glob("glob pattern '%s' is literal\n", pattern);
+ return o_save_ptr_helper(o, n);
+ }
+
+ copy = xstrdup(pattern);
+ /* "forget" pattern in o */
+ o->length = pattern - o->data;
+ n = glob_brace(copy, o, n);
+ free(copy);
+ if (DEBUG_GLOB)
+ debug_print_list("perform_glob returning", o, n);
+ return n;
+}
+
+#else /* !HUSH_BRACE_EXPANSION */
+
+/* Helper */
+static int glob_needed(const char *s)
+{
+ while (*s) {
+ if (*s == '\\') {
+ if (!s[1])
+ return 0;
+ s += 2;
+ continue;
+ }
+ if (*s == '*' || *s == '[' || *s == '?')
+ return 1;
+ s++;
+ }
+ return 0;
+}
+/* Performs globbing on last list[],
+ * saving each result as a new list[].
+ */
+static int perform_glob(o_string *o, int n)
+{
+#ifndef __U_BOOT__
+ glob_t globdata;
+ int gr;
+#endif /* __U_BOOT__ */
+ char *pattern;
+
+ debug_printf_glob("start perform_glob: n:%d o->data:%p\n", n, o->data);
+ if (!o->data)
+ return o_save_ptr_helper(o, n);
+ pattern = o->data + o_get_last_ptr(o, n);
+ debug_printf_glob("glob pattern '%s'\n", pattern);
+ if (!glob_needed(pattern)) {
+#ifndef __U_BOOT__
+ literal:
+#endif /* __U_BOOT__ */
+ /* unbackslash last string in o in place, fix length */
+ o->length = unbackslash(pattern) - o->data;
+ debug_printf_glob("glob pattern '%s' is literal\n", pattern);
+ return o_save_ptr_helper(o, n);
+ }
+
+#ifndef __U_BOOT__
+ memset(&globdata, 0, sizeof(globdata));
+ /* Can't use GLOB_NOCHECK: it does not unescape the string.
+ * If we glob "*.\*" and don't find anything, we need
+ * to fall back to using literal "*.*", but GLOB_NOCHECK
+ * will return "*.\*"!
+ */
+ gr = glob(pattern, 0, NULL, &globdata);
+ debug_printf_glob("glob('%s'):%d\n", pattern, gr);
+ if (gr != 0) {
+ if (gr == GLOB_NOMATCH) {
+ globfree(&globdata);
+ goto literal;
+ }
+ if (gr == GLOB_NOSPACE)
+ bb_die_memory_exhausted();
+ /* GLOB_ABORTED? Only happens with GLOB_ERR flag,
+ * but we didn't specify it. Paranoia again. */
+ bb_error_msg_and_die("glob error %d on '%s'", gr, pattern);
+ }
+ if (globdata.gl_pathv && globdata.gl_pathv[0]) {
+ char **argv = globdata.gl_pathv;
+ /* "forget" pattern in o */
+ o->length = pattern - o->data;
+ while (1) {
+ o_addstr_with_NUL(o, *argv);
+ n = o_save_ptr_helper(o, n);
+ argv++;
+ if (!*argv)
+ break;
+ }
+ }
+ globfree(&globdata);
+ if (DEBUG_GLOB)
+ debug_print_list("perform_glob returning", o, n);
+ return n;
+#else /* __U_BOOT__ */
+ /*
+ * NOTE We only use perform glob to call unbackslash to remove backslash
+ * from string once expanded.
+ * So, it seems OK to return this if no previous return was done.
+ */
+ return o_save_ptr_helper(o, n);
+#endif /* __U_BOOT__ */
+}
+
+#endif /* !HUSH_BRACE_EXPANSION */
+
+/* If o->o_expflags & EXP_FLAG_GLOB, glob the string so far remembered.
+ * Otherwise, just finish current list[] and start new */
+static int o_save_ptr(o_string *o, int n)
+{
+ if (o->o_expflags & EXP_FLAG_GLOB) {
+ /* If o->has_empty_slot, list[n] was already globbed
+ * (if it was requested back then when it was filled)
+ * so don't do that again! */
+ if (!o->has_empty_slot)
+ return perform_glob(o, n); /* o_save_ptr_helper is inside */
+ }
+ return o_save_ptr_helper(o, n);
+}
+
+/* "Please convert list[n] to real char* ptrs, and NULL terminate it." */
+static char **o_finalize_list(o_string *o, int n)
+{
+ char **list;
+ int string_start;
+
+ if (DEBUG_EXPAND)
+ debug_print_list("finalized", o, n);
+ debug_printf_expand("finalized n:%d\n", n);
+ list = (char**)o->data;
+ string_start = ((n + 0xf) & ~0xf) * sizeof(list[0]);
+ list[--n] = NULL;
+ while (n) {
+ n--;
+ list[n] = o->data + (int)(uintptr_t)list[n] + string_start;
+ }
+ return list;
+}
+
+static void free_pipe_list(struct pipe *pi);
+
+/* Returns pi->next - next pipe in the list */
+static struct pipe *free_pipe(struct pipe *pi)
+{
+ struct pipe *next;
+ int i;
+
+#ifndef __U_BOOT__
+ debug_printf_clean("free_pipe (pid %d)\n", getpid());
+#endif /* !__U_BOOT__ */
+ for (i = 0; i < pi->num_cmds; i++) {
+ struct command *command;
+#ifndef __U_BOOT__
+ struct redir_struct *r, *rnext;
+#endif /* !__U_BOOT__ */
+
+ command = &pi->cmds[i];
+ debug_printf_clean(" command %d:\n", i);
+ if (command->argv) {
+ if (DEBUG_CLEAN) {
+ int a;
+ char **p;
+ for (a = 0, p = command->argv; *p; a++, p++) {
+ debug_printf_clean(" argv[%d] = %s\n", a, *p);
+ }
+ }
+ free_strings(command->argv);
+ //command->argv = NULL;
+ }
+ /* not "else if": on syntax error, we may have both! */
+ if (command->group) {
+ debug_printf_clean(" begin group (cmd_type:%d)\n",
+ command->cmd_type);
+ free_pipe_list(command->group);
+ debug_printf_clean(" end group\n");
+ //command->group = NULL;
+ }
+ /* else is crucial here.
+ * If group != NULL, child_func is meaningless */
+#if ENABLE_HUSH_FUNCTIONS
+ else if (command->child_func) {
+ debug_printf_exec("cmd %p releases child func at %p\n", command, command->child_func);
+ command->child_func->parent_cmd = NULL;
+ }
+#endif
+#if !BB_MMU
+ free(command->group_as_string);
+ //command->group_as_string = NULL;
+#endif
+#ifndef __U_BOOT__
+ for (r = command->redirects; r; r = rnext) {
+ debug_printf_clean(" redirect %d%s",
+ r->rd_fd, redir_table[r->rd_type].descrip);
+ /* guard against the case >$FOO, where foo is unset or blank */
+ if (r->rd_filename) {
+ debug_printf_clean(" fname:'%s'\n", r->rd_filename);
+ free(r->rd_filename);
+ //r->rd_filename = NULL;
+ }
+ debug_printf_clean(" rd_dup:%d\n", r->rd_dup);
+ rnext = r->next;
+ free(r);
+ }
+ //command->redirects = NULL;
+#endif /* !__U_BOOT__ */
+ }
+ free(pi->cmds); /* children are an array, they get freed all at once */
+ //pi->cmds = NULL;
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_JOB
+ free(pi->cmdtext);
+ //pi->cmdtext = NULL;
+#endif
+#endif /* !__U_BOOT__ */
+
+ next = pi->next;
+ free(pi);
+ return next;
+}
+
+static void free_pipe_list(struct pipe *pi)
+{
+ while (pi) {
+#if HAS_KEYWORDS
+ debug_printf_clean("pipe reserved word %d\n", pi->res_word);
+#endif
+ debug_printf_clean("pipe followup code %d\n", pi->followup);
+ pi = free_pipe(pi);
+ }
+}
+
+
+/*** Parsing routines ***/
+
+#ifndef debug_print_tree
+static void debug_print_tree(struct pipe *pi, int lvl)
+{
+ static const char *const PIPE[] ALIGN_PTR = {
+ [PIPE_SEQ] = "SEQ",
+ [PIPE_AND] = "AND",
+ [PIPE_OR ] = "OR" ,
+ [PIPE_BG ] = "BG" ,
+ };
+ static const char *RES[] = {
+ [RES_NONE ] = "NONE" ,
+# if ENABLE_HUSH_IF
+ [RES_IF ] = "IF" ,
+ [RES_THEN ] = "THEN" ,
+ [RES_ELIF ] = "ELIF" ,
+ [RES_ELSE ] = "ELSE" ,
+ [RES_FI ] = "FI" ,
+# endif
+# if ENABLE_HUSH_LOOPS
+ [RES_FOR ] = "FOR" ,
+ [RES_WHILE] = "WHILE",
+ [RES_UNTIL] = "UNTIL",
+ [RES_DO ] = "DO" ,
+ [RES_DONE ] = "DONE" ,
+# endif
+# if ENABLE_HUSH_LOOPS || ENABLE_HUSH_CASE
+ [RES_IN ] = "IN" ,
+# endif
+# if ENABLE_HUSH_CASE
+ [RES_CASE ] = "CASE" ,
+ [RES_CASE_IN ] = "CASE_IN" ,
+ [RES_MATCH] = "MATCH",
+ [RES_CASE_BODY] = "CASE_BODY",
+ [RES_ESAC ] = "ESAC" ,
+# endif
+ [RES_XXXX ] = "XXXX" ,
+ [RES_SNTX ] = "SNTX" ,
+ };
+ static const char *const CMDTYPE[] ALIGN_PTR = {
+ "{}",
+ "()",
+ "[noglob]",
+# if ENABLE_HUSH_FUNCTIONS
+ "func()",
+# endif
+ };
+
+ int pin, prn;
+
+ pin = 0;
+ while (pi) {
+ fdprintf(2, "%*spipe %d #cmds:%d %sres_word=%s followup=%d %s\n",
+ lvl*2, "",
+ pin,
+ pi->num_cmds,
+ (IF_HAS_KEYWORDS(pi->pi_inverted ? "! " :) ""),
+ RES[pi->res_word],
+ pi->followup, PIPE[pi->followup]
+ );
+ prn = 0;
+ while (prn < pi->num_cmds) {
+ struct command *command = &pi->cmds[prn];
+ char **argv = command->argv;
+
+ fdprintf(2, "%*s cmd %d assignment_cnt:%d",
+ lvl*2, "", prn,
+ command->assignment_cnt);
+# if ENABLE_HUSH_LINENO_VAR
+ fdprintf(2, " LINENO:%u", command->lineno);
+# endif
+ if (command->group) {
+ fdprintf(2, " group %s: (argv=%p)%s%s\n",
+ CMDTYPE[command->cmd_type],
+ argv
+# if !BB_MMU
+ , " group_as_string:", command->group_as_string
+# else
+ , "", ""
+# endif
+ );
+ debug_print_tree(command->group, lvl+1);
+ prn++;
+ continue;
+ }
+ if (argv) while (*argv) {
+ fdprintf(2, " '%s'", *argv);
+ argv++;
+ }
+#ifndef __U_BOOT__
+ if (command->redirects)
+ fdprintf(2, " {redir}");
+#endif /* __U_BOOT__ */
+ fdprintf(2, "\n");
+ prn++;
+ }
+ pi = pi->next;
+ pin++;
+ }
+}
+#endif /* debug_print_tree */
+
+static struct pipe *new_pipe(void)
+{
+ struct pipe *pi;
+ pi = xzalloc(sizeof(struct pipe));
+ /*pi->res_word = RES_NONE; - RES_NONE is 0 anyway */
+ return pi;
+}
+
+/* Command (member of a pipe) is complete, or we start a new pipe
+ * if ctx->command is NULL.
+ * No errors possible here.
+ */
+static int done_command(struct parse_context *ctx)
+{
+ /* The command is really already in the pipe structure, so
+ * advance the pipe counter and make a new, null command. */
+ struct pipe *pi = ctx->pipe;
+ struct command *command = ctx->command;
+
+#if 0 /* Instead we emit error message at run time */
+ if (ctx->pending_redirect) {
+ /* For example, "cmd >" (no filename to redirect to) */
+ syntax_error("invalid redirect");
+ ctx->pending_redirect = NULL;
+ }
+#endif
+
+ if (command) {
+ if (IS_NULL_CMD(command)) {
+ debug_printf_parse("done_command: skipping null cmd, num_cmds=%d\n", pi->num_cmds);
+ goto clear_and_ret;
+ }
+ pi->num_cmds++;
+ debug_printf_parse("done_command: ++num_cmds=%d\n", pi->num_cmds);
+ //debug_print_tree(ctx->list_head, 20);
+ } else {
+ debug_printf_parse("done_command: initializing, num_cmds=%d\n", pi->num_cmds);
+ }
+
+ /* Only real trickiness here is that the uncommitted
+ * command structure is not counted in pi->num_cmds. */
+ pi->cmds = xrealloc(pi->cmds, sizeof(*pi->cmds) * (pi->num_cmds+1));
+ ctx->command = command = &pi->cmds[pi->num_cmds];
+ clear_and_ret:
+ memset(command, 0, sizeof(*command));
+#if ENABLE_HUSH_LINENO_VAR
+ command->lineno = G.parse_lineno;
+ debug_printf_parse("command->lineno = G.parse_lineno (%u)\n", G.parse_lineno);
+#endif
+ return pi->num_cmds; /* used only for 0/nonzero check */
+}
+
+static void done_pipe(struct parse_context *ctx, pipe_style type)
+{
+ int not_null;
+
+ debug_printf_parse("done_pipe entered, followup %d\n", type);
+ /* Close previous command */
+ not_null = done_command(ctx);
+#if HAS_KEYWORDS
+ ctx->pipe->pi_inverted = ctx->ctx_inverted;
+ ctx->ctx_inverted = 0;
+ ctx->pipe->res_word = ctx->ctx_res_w;
+#endif
+ if (type == PIPE_BG && ctx->list_head != ctx->pipe) {
+ /* Necessary since && and || have precedence over &:
+ * "cmd1 && cmd2 &" must spawn both cmds, not only cmd2,
+ * in a backgrounded subshell.
+ */
+ struct pipe *pi;
+ struct command *command;
+
+ /* Is this actually this construct, all pipes end with && or ||? */
+ pi = ctx->list_head;
+ while (pi != ctx->pipe) {
+ if (pi->followup != PIPE_AND && pi->followup != PIPE_OR)
+ goto no_conv;
+ pi = pi->next;
+ }
+
+ debug_printf_parse("BG with more than one pipe, converting to { p1 &&...pN; } &\n");
+ pi->followup = PIPE_SEQ; /* close pN _not_ with "&"! */
+ pi = xzalloc(sizeof(*pi));
+ pi->followup = PIPE_BG;
+ pi->num_cmds = 1;
+ pi->cmds = xzalloc(sizeof(pi->cmds[0]));
+ command = &pi->cmds[0];
+ if (CMD_NORMAL != 0) /* "if xzalloc didn't do that already" */
+ command->cmd_type = CMD_NORMAL;
+ command->group = ctx->list_head;
+#if !BB_MMU
+ command->group_as_string = xstrndup(
+ ctx->as_string.data,
+ ctx->as_string.length - 1 /* do not copy last char, "&" */
+ );
+#endif
+ /* Replace all pipes in ctx with one newly created */
+ ctx->list_head = ctx->pipe = pi;
+ /* for cases like "cmd && &", do not be tricked by last command
+ * being null - the entire {...} & is NOT null! */
+ not_null = 1;
+ } else {
+ no_conv:
+ ctx->pipe->followup = type;
+ }
+
+ /* Without this check, even just <enter> on command line generates
+ * tree of three NOPs (!). Which is harmless but annoying.
+ * IOW: it is safe to do it unconditionally. */
+ if (not_null
+#if ENABLE_HUSH_IF
+ || ctx->ctx_res_w == RES_FI
+#endif
+#if ENABLE_HUSH_LOOPS
+ || ctx->ctx_res_w == RES_DONE
+ || ctx->ctx_res_w == RES_FOR
+ || ctx->ctx_res_w == RES_IN
+#endif
+#if ENABLE_HUSH_CASE
+ || ctx->ctx_res_w == RES_ESAC
+#endif
+ ) {
+ struct pipe *new_p;
+ debug_printf_parse("done_pipe: adding new pipe: "
+#ifndef __U_BOOT__
+ "not_null:%d ctx->ctx_res_w:%d\n",
+ not_null, ctx->ctx_res_w);
+#else /* __U_BOOT__ */
+ "not_null:%d\n",
+ not_null);
+#endif /* __U_BOOT__ */
+ new_p = new_pipe();
+ ctx->pipe->next = new_p;
+ ctx->pipe = new_p;
+ /* RES_THEN, RES_DO etc are "sticky" -
+ * they remain set for pipes inside if/while.
+ * This is used to control execution.
+ * RES_FOR and RES_IN are NOT sticky (needed to support
+ * cases where variable or value happens to match a keyword):
+ */
+#if ENABLE_HUSH_LOOPS
+ if (ctx->ctx_res_w == RES_FOR
+ || ctx->ctx_res_w == RES_IN)
+ ctx->ctx_res_w = RES_NONE;
+#endif
+#if ENABLE_HUSH_CASE
+ if (ctx->ctx_res_w == RES_MATCH)
+ ctx->ctx_res_w = RES_CASE_BODY;
+ if (ctx->ctx_res_w == RES_CASE)
+ ctx->ctx_res_w = RES_CASE_IN;
+#endif
+ ctx->command = NULL; /* trick done_command below */
+ /* Create the memory for command, roughly:
+ * ctx->pipe->cmds = new struct command;
+ * ctx->command = &ctx->pipe->cmds[0];
+ */
+ done_command(ctx);
+ //debug_print_tree(ctx->list_head, 10);
+ }
+ debug_printf_parse("done_pipe return\n");
+}
+
+static void initialize_context(struct parse_context *ctx)
+{
+ memset(ctx, 0, sizeof(*ctx));
+ if (MAYBE_ASSIGNMENT != 0)
+ ctx->is_assignment = MAYBE_ASSIGNMENT;
+ ctx->pipe = ctx->list_head = new_pipe();
+ /* Create the memory for command, roughly:
+ * ctx->pipe->cmds = new struct command;
+ * ctx->command = &ctx->pipe->cmds[0];
+ */
+ done_command(ctx);
+}
+
+/* If a reserved word is found and processed, parse context is modified
+ * and 1 is returned.
+ */
+#if HAS_KEYWORDS
+struct reserved_combo {
+ char literal[6];
+ unsigned char res;
+ unsigned char assignment_flag;
+ uint32_t flag;
+};
+enum {
+ FLAG_END = (1 << RES_NONE ),
+# if ENABLE_HUSH_IF
+ FLAG_IF = (1 << RES_IF ),
+ FLAG_THEN = (1 << RES_THEN ),
+ FLAG_ELIF = (1 << RES_ELIF ),
+ FLAG_ELSE = (1 << RES_ELSE ),
+ FLAG_FI = (1 << RES_FI ),
+# endif
+# if ENABLE_HUSH_LOOPS
+ FLAG_FOR = (1 << RES_FOR ),
+ FLAG_WHILE = (1 << RES_WHILE),
+ FLAG_UNTIL = (1 << RES_UNTIL),
+ FLAG_DO = (1 << RES_DO ),
+ FLAG_DONE = (1 << RES_DONE ),
+ FLAG_IN = (1 << RES_IN ),
+# endif
+# if ENABLE_HUSH_CASE
+ FLAG_MATCH = (1 << RES_MATCH),
+ FLAG_ESAC = (1 << RES_ESAC ),
+# endif
+ FLAG_START = (1 << RES_XXXX ),
+};
+
+static const struct reserved_combo* match_reserved_word(o_string *word)
+{
+ /* Mostly a list of accepted follow-up reserved words.
+ * FLAG_END means we are done with the sequence, and are ready
+ * to turn the compound list into a command.
+ * FLAG_START means the word must start a new compound list.
+ */
+ static const struct reserved_combo reserved_list[] ALIGN4 = {
+# if ENABLE_HUSH_IF
+ { "!", RES_NONE, NOT_ASSIGNMENT , 0 },
+ { "if", RES_IF, MAYBE_ASSIGNMENT, FLAG_THEN | FLAG_START },
+ { "then", RES_THEN, MAYBE_ASSIGNMENT, FLAG_ELIF | FLAG_ELSE | FLAG_FI },
+ { "elif", RES_ELIF, MAYBE_ASSIGNMENT, FLAG_THEN },
+ { "else", RES_ELSE, MAYBE_ASSIGNMENT, FLAG_FI },
+ { "fi", RES_FI, NOT_ASSIGNMENT , FLAG_END },
+# endif
+# if ENABLE_HUSH_LOOPS
+ { "for", RES_FOR, NOT_ASSIGNMENT , FLAG_IN | FLAG_DO | FLAG_START },
+ { "while", RES_WHILE, MAYBE_ASSIGNMENT, FLAG_DO | FLAG_START },
+ { "until", RES_UNTIL, MAYBE_ASSIGNMENT, FLAG_DO | FLAG_START },
+ { "in", RES_IN, NOT_ASSIGNMENT , FLAG_DO },
+ { "do", RES_DO, MAYBE_ASSIGNMENT, FLAG_DONE },
+ { "done", RES_DONE, NOT_ASSIGNMENT , FLAG_END },
+# endif
+# if ENABLE_HUSH_CASE
+ { "case", RES_CASE, NOT_ASSIGNMENT , FLAG_MATCH | FLAG_START },
+ { "esac", RES_ESAC, NOT_ASSIGNMENT , FLAG_END },
+# endif
+ };
+ const struct reserved_combo *r;
+
+ for (r = reserved_list; r < reserved_list + ARRAY_SIZE(reserved_list); r++) {
+ if (strcmp(word->data, r->literal) == 0)
+ return r;
+ }
+ return NULL;
+}
+/* Return NULL: not a keyword, else: keyword
+ */
+static const struct reserved_combo* reserved_word(struct parse_context *ctx)
+{
+# if ENABLE_HUSH_CASE
+ static const struct reserved_combo reserved_match = {
+ "", RES_MATCH, NOT_ASSIGNMENT , FLAG_MATCH | FLAG_ESAC
+ };
+# endif
+ const struct reserved_combo *r;
+
+ if (ctx->word.has_quoted_part)
+ return 0;
+ r = match_reserved_word(&ctx->word);
+ if (!r)
+ return r; /* NULL */
+
+ debug_printf("found reserved word %s, res %d\n", r->literal, r->res);
+# if ENABLE_HUSH_CASE
+ if (r->res == RES_IN && ctx->ctx_res_w == RES_CASE_IN) {
+ /* "case word IN ..." - IN part starts first MATCH part */
+ r = &reserved_match;
+ } else
+# endif
+ if (r->flag == 0) { /* '!' */
+ if (ctx->ctx_inverted) { /* bash doesn't accept '! ! true' */
+ syntax_error("! ! command");
+ ctx->ctx_res_w = RES_SNTX;
+ }
+ ctx->ctx_inverted = 1;
+ return r;
+ }
+ if (r->flag & FLAG_START) {
+ struct parse_context *old;
+
+ old = xmemdup(ctx, sizeof(*ctx));
+ debug_printf_parse("push stack %p\n", old);
+ initialize_context(ctx);
+ ctx->stack = old;
+ } else if (/*ctx->ctx_res_w == RES_NONE ||*/ !(ctx->old_flag & (1 << r->res))) {
+ syntax_error_at(ctx->word.data);
+ ctx->ctx_res_w = RES_SNTX;
+ return r;
+ } else {
+ /* "{...} fi" is ok. "{...} if" is not
+ * Example:
+ * if { echo foo; } then { echo bar; } fi */
+ if (ctx->command->group)
+ done_pipe(ctx, PIPE_SEQ);
+ }
+
+ ctx->ctx_res_w = r->res;
+ ctx->old_flag = r->flag;
+ ctx->is_assignment = r->assignment_flag;
+ debug_printf_parse("ctx->is_assignment='%s'\n", assignment_flag[ctx->is_assignment]);
+
+ if (ctx->old_flag & FLAG_END) {
+ struct parse_context *old;
+
+ done_pipe(ctx, PIPE_SEQ);
+ debug_printf_parse("pop stack %p\n", ctx->stack);
+ old = ctx->stack;
+ old->command->group = ctx->list_head;
+ old->command->cmd_type = CMD_NORMAL;
+# if !BB_MMU
+ /* At this point, the compound command's string is in
+ * ctx->as_string... except for the leading keyword!
+ * Consider this example: "echo a | if true; then echo a; fi"
+ * ctx->as_string will contain "true; then echo a; fi",
+ * with "if " remaining in old->as_string!
+ */
+ {
+ char *str;
+ int len = old->as_string.length;
+ /* Concatenate halves */
+ o_addstr(&old->as_string, ctx->as_string.data);
+ o_free(&ctx->as_string);
+ /* Find where leading keyword starts in first half */
+ str = old->as_string.data + len;
+ if (str > old->as_string.data)
+ str--; /* skip whitespace after keyword */
+ while (str > old->as_string.data && isalpha(str[-1]))
+ str--;
+ /* Ugh, we're done with this horrid hack */
+ old->command->group_as_string = xstrdup(str);
+ debug_printf_parse("pop, remembering as:'%s'\n",
+ old->command->group_as_string);
+ }
+# endif
+ *ctx = *old; /* physical copy */
+ free(old);
+ }
+ return r;
+}
+#endif /* HAS_KEYWORDS */
+
+/* Word is complete, look at it and update parsing context.
+ * Normal return is 0. Syntax errors return 1.
+ * Note: on return, word is reset, but not o_free'd!
+ */
+static int done_word(struct parse_context *ctx)
+{
+ struct command *command = ctx->command;
+
+ debug_printf_parse("done_word entered: '%s' %p\n", ctx->word.data, command);
+ if (ctx->word.length == 0 && !ctx->word.has_quoted_part) {
+ debug_printf_parse("done_word return 0: true null, ignored\n");
+ return 0;
+ }
+
+#ifndef __U_BOOT__
+ if (ctx->pending_redirect) {
+ /* We do not glob in e.g. >*.tmp case. bash seems to glob here
+ * only if run as "bash", not "sh" */
+ /* http://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html
+ * "2.7 Redirection
+ * If the redirection operator is "<<" or "<<-", the word
+ * that follows the redirection operator shall be
+ * subjected to quote removal; it is unspecified whether
+ * any of the other expansions occur. For the other
+ * redirection operators, the word that follows the
+ * redirection operator shall be subjected to tilde
+ * expansion, parameter expansion, command substitution,
+ * arithmetic expansion, and quote removal.
+ * Pathname expansion shall not be performed
+ * on the word by a non-interactive shell; an interactive
+ * shell may perform it, but shall do so only when
+ * the expansion would result in one word."
+ */
+//bash does not do parameter/command substitution or arithmetic expansion
+//for _heredoc_ redirection word: these constructs look for exact eof marker
+// as written:
+// <<EOF$t
+// <<EOF$((1))
+// <<EOF`true` [this case also makes heredoc "quoted", a-la <<"EOF". Probably bash-4.3.43 bug]
+
+ ctx->pending_redirect->rd_filename = xstrdup(ctx->word.data);
+ /* Cater for >\file case:
+ * >\a creates file a; >\\a, >"\a", >"\\a" create file \a
+ * Same with heredocs:
+ * for <<\H delim is H; <<\\H, <<"\H", <<"\\H" - \H
+ */
+ if (ctx->pending_redirect->rd_type == REDIRECT_HEREDOC) {
+ unbackslash(ctx->pending_redirect->rd_filename);
+ /* Is it <<"HEREDOC"? */
+ if (ctx->word.has_quoted_part) {
+ ctx->pending_redirect->rd_dup |= HEREDOC_QUOTED;
+ }
+ }
+ debug_printf_parse("word stored in rd_filename: '%s'\n", ctx->word.data);
+ ctx->pending_redirect = NULL;
+ } else {
+#endif /* !__U_BOOT__ */
+#if HAS_KEYWORDS
+# if ENABLE_HUSH_CASE
+ if (ctx->ctx_dsemicolon
+ && strcmp(ctx->word.data, "esac") != 0 /* not "... pattern) cmd;; esac" */
+ ) {
+ /* already done when ctx_dsemicolon was set to 1: */
+ /* ctx->ctx_res_w = RES_MATCH; */
+ ctx->ctx_dsemicolon = 0;
+ } else
+# endif
+# if defined(CMD_TEST2_SINGLEWORD_NOGLOB)
+ if (command->cmd_type == CMD_TEST2_SINGLEWORD_NOGLOB
+ && strcmp(ctx->word.data, "]]") == 0
+ ) {
+ /* allow "[[ ]] >file" etc */
+ command->cmd_type = CMD_SINGLEWORD_NOGLOB;
+ } else
+# endif
+ if (!command->argv /* if it's the first word... */
+# if ENABLE_HUSH_LOOPS
+ && ctx->ctx_res_w != RES_FOR /* ...not after FOR or IN */
+ && ctx->ctx_res_w != RES_IN
+# endif
+# if ENABLE_HUSH_CASE
+ && ctx->ctx_res_w != RES_CASE
+# endif
+ ) {
+ const struct reserved_combo *reserved;
+ reserved = reserved_word(ctx);
+ debug_printf_parse("checking for reserved-ness: %d\n", !!reserved);
+ if (reserved) {
+# if ENABLE_HUSH_LINENO_VAR
+/* Case:
+ * "while ...; do
+ * cmd ..."
+ * If we don't close the pipe _now_, immediately after "do", lineno logic
+ * sees "cmd" as starting at "do" - i.e., at the previous line.
+ */
+ if (0
+ IF_HUSH_IF(|| reserved->res == RES_THEN)
+ IF_HUSH_IF(|| reserved->res == RES_ELIF)
+ IF_HUSH_IF(|| reserved->res == RES_ELSE)
+ IF_HUSH_LOOPS(|| reserved->res == RES_DO)
+ ) {
+ done_pipe(ctx, PIPE_SEQ);
+ }
+# endif
+ o_reset_to_empty_unquoted(&ctx->word);
+ debug_printf_parse("done_word return %d\n",
+ (ctx->ctx_res_w == RES_SNTX));
+ return (ctx->ctx_res_w == RES_SNTX);
+ }
+# if defined(CMD_TEST2_SINGLEWORD_NOGLOB)
+ if (strcmp(ctx->word.data, "[[") == 0) {
+ command->cmd_type = CMD_TEST2_SINGLEWORD_NOGLOB;
+ } else
+# endif
+# if defined(CMD_SINGLEWORD_NOGLOB)
+ if (0
+ /* In bash, local/export/readonly are special, args
+ * are assignments and therefore expansion of them
+ * should be "one-word" expansion:
+ * $ export i=`echo 'a b'` # one arg: "i=a b"
+ * compare with:
+ * $ ls i=`echo 'a b'` # two args: "i=a" and "b"
+ * ls: cannot access i=a: No such file or directory
+ * ls: cannot access b: No such file or directory
+ * Note: bash 3.2.33(1) does this only if export word
+ * itself is not quoted:
+ * $ export i=`echo 'aaa bbb'`; echo "$i"
+ * aaa bbb
+ * $ "export" i=`echo 'aaa bbb'`; echo "$i"
+ * aaa
+ */
+ IF_HUSH_LOCAL( || strcmp(ctx->word.data, "local") == 0)
+ IF_HUSH_EXPORT( || strcmp(ctx->word.data, "export") == 0)
+ IF_HUSH_READONLY(|| strcmp(ctx->word.data, "readonly") == 0)
+ ) {
+ command->cmd_type = CMD_SINGLEWORD_NOGLOB;
+ }
+# else
+ { /* empty block to pair "if ... else" */ }
+# endif
+ }
+#endif /* HAS_KEYWORDS */
+
+ if (command->group) {
+ /* "{ echo foo; } echo bar" - bad */
+ syntax_error_at(ctx->word.data);
+ debug_printf_parse("done_word return 1: syntax error, "
+ "groups and arglists don't mix\n");
+ return 1;
+ }
+
+ /* If this word wasn't an assignment, next ones definitely
+ * can't be assignments. Even if they look like ones. */
+ if (ctx->is_assignment != DEFINITELY_ASSIGNMENT
+ && ctx->is_assignment != WORD_IS_KEYWORD
+ ) {
+ ctx->is_assignment = NOT_ASSIGNMENT;
+ } else {
+ if (ctx->is_assignment == DEFINITELY_ASSIGNMENT) {
+ command->assignment_cnt++;
+ debug_printf_parse("++assignment_cnt=%d\n", command->assignment_cnt);
+ }
+ debug_printf_parse("ctx->is_assignment was:'%s'\n", assignment_flag[ctx->is_assignment]);
+ ctx->is_assignment = MAYBE_ASSIGNMENT;
+ }
+ debug_printf_parse("ctx->is_assignment='%s'\n", assignment_flag[ctx->is_assignment]);
+ command->argv = add_string_to_strings(command->argv, xstrdup(ctx->word.data));
+#ifdef __U_BOOT__
+ command->argc++;
+#endif /* __U_BOOT__ */
+ debug_print_strings("word appended to argv", command->argv);
+
+#ifndef __U_BOOT__
+ }
+#endif /* !__U_BOOT__ */
+
+#if ENABLE_HUSH_LOOPS
+ if (ctx->ctx_res_w == RES_FOR) {
+ if (ctx->word.has_quoted_part
+ || endofname(command->argv[0])[0] != '\0'
+ ) {
+ /* bash says just "not a valid identifier" */
+ syntax_error("bad for loop variable");
+ return 1;
+ }
+ /* Force FOR to have just one word (variable name) */
+ /* NB: basically, this makes hush see "for v in ..."
+ * syntax as if it is "for v; in ...". FOR and IN become
+ * two pipe structs in parse tree. */
+ done_pipe(ctx, PIPE_SEQ);
+ }
+#endif
+#if ENABLE_HUSH_CASE
+ /* Force CASE to have just one word */
+ if (ctx->ctx_res_w == RES_CASE) {
+ done_pipe(ctx, PIPE_SEQ);
+ }
+#endif
+
+ o_reset_to_empty_unquoted(&ctx->word);
+
+ debug_printf_parse("done_word return 0\n");
+ return 0;
+}
+
+
+#ifndef __U_BOOT__
+/* Peek ahead in the input to find out if we have a "&n" construct,
+ * as in "2>&1", that represents duplicating a file descriptor.
+ * Return:
+ * REDIRFD_CLOSE if >&- "close fd" construct is seen,
+ * REDIRFD_SYNTAX_ERR if syntax error,
+ * REDIRFD_TO_FILE if no & was seen,
+ * or the number found.
+ */
+#if BB_MMU
+#define parse_redir_right_fd(as_string, input) \
+ parse_redir_right_fd(input)
+#endif
+static int parse_redir_right_fd(o_string *as_string, struct in_str *input)
+{
+ int ch, d, ok;
+
+ ch = i_peek(input);
+ if (ch != '&')
+ return REDIRFD_TO_FILE;
+
+ ch = i_getch(input); /* get the & */
+ nommu_addchr(as_string, ch);
+ ch = i_peek(input);
+ if (ch == '-') {
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ return REDIRFD_CLOSE;
+ }
+ d = 0;
+ ok = 0;
+ while (ch != EOF && isdigit(ch)) {
+ d = d*10 + (ch-'0');
+ ok = 1;
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ ch = i_peek(input);
+ }
+ if (ok) return d;
+
+//TODO: this is the place to catch ">&file" bashism (redirect both fd 1 and 2)
+
+ bb_simple_error_msg("ambiguous redirect");
+ return REDIRFD_SYNTAX_ERR;
+}
+
+/* Return code is 0 normal, 1 if a syntax error is detected
+ */
+static int parse_redirect(struct parse_context *ctx,
+ int fd,
+ redir_type style,
+ struct in_str *input)
+{
+ struct command *command = ctx->command;
+ struct redir_struct *redir;
+ struct redir_struct **redirp;
+ int dup_num;
+
+ dup_num = REDIRFD_TO_FILE;
+ if (style != REDIRECT_HEREDOC) {
+ /* Check for a '>&1' type redirect */
+ dup_num = parse_redir_right_fd(&ctx->as_string, input);
+ if (dup_num == REDIRFD_SYNTAX_ERR)
+ return 1;
+ } else {
+ int ch = i_peek_and_eat_bkslash_nl(input);
+ dup_num = (ch == '-'); /* HEREDOC_SKIPTABS bit is 1 */
+ if (dup_num) { /* <<-... */
+ ch = i_getch(input);
+ nommu_addchr(&ctx->as_string, ch);
+ ch = i_peek(input);
+ }
+ }
+
+ if (style == REDIRECT_OVERWRITE && dup_num == REDIRFD_TO_FILE) {
+ int ch = i_peek_and_eat_bkslash_nl(input);
+ if (ch == '|') {
+ /* >|FILE redirect ("clobbering" >).
+ * Since we do not support "set -o noclobber" yet,
+ * >| and > are the same for now. Just eat |.
+ */
+ ch = i_getch(input);
+ nommu_addchr(&ctx->as_string, ch);
+ }
+ }
+
+ /* Create a new redir_struct and append it to the linked list */
+ redirp = &command->redirects;
+ while ((redir = *redirp) != NULL) {
+ redirp = &(redir->next);
+ }
+ *redirp = redir = xzalloc(sizeof(*redir));
+ /* redir->next = NULL; */
+ /* redir->rd_filename = NULL; */
+ redir->rd_type = style;
+ redir->rd_fd = (fd == -1) ? redir_table[style].default_fd : fd;
+
+ debug_printf_parse("redirect type %d %s\n", redir->rd_fd,
+ redir_table[style].descrip);
+
+ redir->rd_dup = dup_num;
+ if (style != REDIRECT_HEREDOC && dup_num != REDIRFD_TO_FILE) {
+ /* Erik had a check here that the file descriptor in question
+ * is legit; I postpone that to "run time"
+ * A "-" representation of "close me" shows up as a -3 here */
+ debug_printf_parse("duplicating redirect '%d>&%d'\n",
+ redir->rd_fd, redir->rd_dup);
+ } else {
+#if 0 /* Instead we emit error message at run time */
+ if (ctx->pending_redirect) {
+ /* For example, "cmd > <file" */
+ syntax_error("invalid redirect");
+ }
+#endif
+ /* Set ctx->pending_redirect, so we know what to do at the
+ * end of the next parsed word. */
+ ctx->pending_redirect = redir;
+ }
+ return 0;
+}
+
+/* If a redirect is immediately preceded by a number, that number is
+ * supposed to tell which file descriptor to redirect. This routine
+ * looks for such preceding numbers. In an ideal world this routine
+ * needs to handle all the following classes of redirects...
+ * echo 2>foo # redirects fd 2 to file "foo", nothing passed to echo
+ * echo 49>foo # redirects fd 49 to file "foo", nothing passed to echo
+ * echo -2>foo # redirects fd 1 to file "foo", "-2" passed to echo
+ * echo 49x>foo # redirects fd 1 to file "foo", "49x" passed to echo
+ *
+ * http://www.opengroup.org/onlinepubs/009695399/utilities/xcu_chap02.html
+ * "2.7 Redirection
+ * ... If n is quoted, the number shall not be recognized as part of
+ * the redirection expression. For example:
+ * echo \2>a
+ * writes the character 2 into file a"
+ * We are getting it right by setting ->has_quoted_part on any \<char>
+ *
+ * A -1 return means no valid number was found,
+ * the caller should use the appropriate default for this redirection.
+ */
+static int redirect_opt_num(o_string *o)
+{
+ int num;
+
+ if (o->data == NULL)
+ return -1;
+ num = bb_strtou(o->data, NULL, 10);
+ if (errno || num < 0)
+ return -1;
+ o_reset_to_empty_unquoted(o);
+ return num;
+}
+
+#if BB_MMU
+#define fetch_till_str(as_string, input, word, skip_tabs) \
+ fetch_till_str(input, word, skip_tabs)
+#endif
+static char *fetch_till_str(o_string *as_string,
+ struct in_str *input,
+ const char *word,
+ int heredoc_flags)
+{
+ o_string heredoc = NULL_O_STRING;
+ unsigned past_EOL;
+ int prev = 0; /* not \ */
+ int ch;
+
+ /* Starting with "" is necessary for this case:
+ * cat <<EOF
+ *
+ * xxx
+ * EOF
+ */
+ heredoc.data = xzalloc(1); /* start as "", not as NULL */
+
+ goto jump_in;
+
+ while (1) {
+ ch = i_getch(input);
+ if (ch != EOF)
+ nommu_addchr(as_string, ch);
+ if (ch == '\n' || ch == EOF) {
+ check_heredoc_end:
+#ifndef __U_BOOT__
+ if ((heredoc_flags & HEREDOC_QUOTED) || prev != '\\') {
+#else /* __U_BOOT__ */
+ if (prev != '\\') {
+#endif
+ /* End-of-line, and not a line continuation */
+ if (strcmp(heredoc.data + past_EOL, word) == 0) {
+ heredoc.data[past_EOL] = '\0';
+ debug_printf_heredoc("parsed '%s' heredoc '%s'\n", word, heredoc.data);
+ return heredoc.data;
+ }
+ if (ch == '\n') {
+ /* This is a new line.
+ * Remember position and backslash-escaping status.
+ */
+ o_addchr(&heredoc, ch);
+ prev = ch;
+ jump_in:
+ past_EOL = heredoc.length;
+ /* Get 1st char of next line, possibly skipping leading tabs */
+ do {
+ ch = i_getch(input);
+ if (ch != EOF)
+ nommu_addchr(as_string, ch);
+#ifndef __U_BOOT__
+ } while ((heredoc_flags & HEREDOC_SKIPTABS) && ch == '\t');
+#else /* __U_BOOT__ */
+ } while (ch == '\t');
+#endif
+ /* If this immediately ended the line,
+ * go back to end-of-line checks.
+ */
+ if (ch == '\n')
+ goto check_heredoc_end;
+ }
+ } else {
+ /* Backslash-line continuation in an unquoted
+ * heredoc. This does not need special handling
+ * for heredoc body (unquoted heredocs are
+ * expanded on "execution" and that would take
+ * care of this case too), but not the case
+ * of line continuation *in terminator*:
+ * cat <<EOF
+ * Ok1
+ * EO\
+ * F
+ */
+ heredoc.data[--heredoc.length] = '\0';
+ prev = 0; /* not '\' */
+ continue;
+ }
+ }
+ if (ch == EOF) {
+ o_free(&heredoc);
+ return NULL; /* error */
+ }
+ o_addchr(&heredoc, ch);
+ nommu_addchr(as_string, ch);
+ if (prev == '\\' && ch == '\\')
+ /* Correctly handle foo\\<eol> (not a line cont.) */
+ prev = 0; /* not '\' */
+ else
+ prev = ch;
+ }
+}
+#endif /* !__U_BOOT__ */
+
+/* Look at entire parse tree for not-yet-loaded REDIRECT_HEREDOCs
+ * and load them all. There should be exactly heredoc_cnt of them.
+ */
+#if BB_MMU
+#define fetch_heredocs(as_string, pi, heredoc_cnt, input) \
+ fetch_heredocs(pi, heredoc_cnt, input)
+#endif
+static int fetch_heredocs(o_string *as_string, struct pipe *pi, int heredoc_cnt, struct in_str *input)
+{
+ while (pi && heredoc_cnt) {
+ int i;
+ struct command *cmd = pi->cmds;
+
+ debug_printf_heredoc("fetch_heredocs: num_cmds:%d cmd argv0:'%s'\n",
+ pi->num_cmds,
+ cmd->argv ? cmd->argv[0] : "NONE"
+ );
+ for (i = 0; i < pi->num_cmds; i++) {
+#ifndef __U_BOOT__
+ struct redir_struct *redir = cmd->redirects;
+
+#endif /* !__U_BOOT__ */
+ debug_printf_heredoc("fetch_heredocs: %d cmd argv0:'%s'\n",
+ i, cmd->argv ? cmd->argv[0] : "NONE");
+#ifndef __U_BOOT__
+ while (redir) {
+ if (redir->rd_type == REDIRECT_HEREDOC) {
+ char *p;
+
+ redir->rd_type = REDIRECT_HEREDOC2;
+ /* redir->rd_dup is (ab)used to indicate <<- */
+ p = fetch_till_str(as_string, input,
+ redir->rd_filename, redir->rd_dup);
+ if (!p) {
+ syntax_error("unexpected EOF in here document");
+ return -1;
+ }
+ free(redir->rd_filename);
+ redir->rd_filename = p;
+ heredoc_cnt--;
+ }
+ redir = redir->next;
+ }
+#endif /* !__U_BOOT__ */
+ if (cmd->group) {
+ //bb_error_msg("%s:%u heredoc_cnt:%d", __func__, __LINE__, heredoc_cnt);
+ heredoc_cnt = fetch_heredocs(as_string, cmd->group, heredoc_cnt, input);
+ //bb_error_msg("%s:%u heredoc_cnt:%d", __func__, __LINE__, heredoc_cnt);
+ if (heredoc_cnt < 0)
+ return heredoc_cnt; /* error */
+ }
+ cmd++;
+ }
+ pi = pi->next;
+ }
+ return heredoc_cnt;
+}
+
+
+static int run_list(struct pipe *pi);
+#if BB_MMU
+#define parse_stream(pstring, heredoc_cnt_ptr, input, end_trigger) \
+ parse_stream(heredoc_cnt_ptr, input, end_trigger)
+#endif
+static struct pipe *parse_stream(char **pstring,
+ int *heredoc_cnt_ptr,
+ struct in_str *input,
+ int end_trigger);
+
+/* Returns number of heredocs not yet consumed,
+ * or -1 on error.
+ */
+static int parse_group(struct parse_context *ctx,
+ struct in_str *input, int ch)
+{
+ /* ctx->word contains characters seen prior to ( or {.
+ * Typically it's empty, but for function defs,
+ * it contains function name (without '()'). */
+#if BB_MMU
+# define as_string NULL
+#else
+ char *as_string = NULL;
+#endif
+ struct pipe *pipe_list;
+ int heredoc_cnt = 0;
+ int endch;
+ struct command *command = ctx->command;
+
+ debug_printf_parse("parse_group entered\n");
+#if ENABLE_HUSH_FUNCTIONS
+ if (ch == '(' && !ctx->word.has_quoted_part) {
+ if (ctx->word.length)
+ if (done_word(ctx))
+ return -1;
+ if (!command->argv)
+ goto skip; /* (... */
+ if (command->argv[1]) { /* word word ... (... */
+ syntax_error_unexpected_ch('(');
+ return -1;
+ }
+ /* it is "word(..." or "word (..." */
+ do
+ ch = i_getch(input);
+ while (ch == ' ' || ch == '\t');
+ if (ch != ')') {
+ syntax_error_unexpected_ch(ch);
+ return -1;
+ }
+ nommu_addchr(&ctx->as_string, ch);
+ do
+ ch = i_getch(input);
+ while (ch == ' ' || ch == '\t' || ch == '\n');
+ if (ch != '{' && ch != '(') {
+ syntax_error_unexpected_ch(ch);
+ return -1;
+ }
+//bash allows functions named "123", "..", "return"!
+// if (endofname(command->argv[0])[0] != '\0') {
+// syntax_error("bad function name");
+// return -1;
+// }
+ nommu_addchr(&ctx->as_string, ch);
+ command->cmd_type = CMD_FUNCDEF;
+ goto skip;
+ }
+#endif
+
+#if 0 /* Prevented by caller */
+ if (command->argv /* word [word]{... */
+ || ctx->word.length /* word{... */
+ || ctx->word.has_quoted_part /* ""{... */
+ ) {
+ syntax_error(NULL);
+ debug_printf_parse("parse_group return -1: "
+ "syntax error, groups and arglists don't mix\n");
+ return -1;
+ }
+#endif
+
+#ifndef __U_BOOT__
+ IF_HUSH_FUNCTIONS(skip:)
+#endif /* !__U_BOOT__ */
+
+ endch = '}';
+ if (ch == '(') {
+ endch = ')';
+#ifndef __U_BOOT__
+ IF_HUSH_FUNCTIONS(if (command->cmd_type != CMD_FUNCDEF))
+ command->cmd_type = CMD_SUBSHELL;
+#endif /* !__U_BOOT__ */
+ } else {
+ /* bash does not allow "{echo...", requires whitespace */
+ ch = i_peek(input);
+ if (ch != ' ' && ch != '\t' && ch != '\n'
+ && ch != '(' /* but "{(..." is allowed (without whitespace) */
+ ) {
+ syntax_error_unexpected_ch(ch);
+ return -1;
+ }
+ if (ch != '(') {
+ ch = i_getch(input);
+ nommu_addchr(&ctx->as_string, ch);
+ }
+ }
+
+ debug_printf_heredoc("calling parse_stream, heredoc_cnt:%d\n", heredoc_cnt);
+ pipe_list = parse_stream(&as_string, &heredoc_cnt, input, endch);
+ debug_printf_heredoc("parse_stream returned: heredoc_cnt:%d\n", heredoc_cnt);
+#if !BB_MMU
+ if (as_string)
+ o_addstr(&ctx->as_string, as_string);
+#endif
+
+ /* empty ()/{} or parse error? */
+ if (!pipe_list || pipe_list == ERR_PTR) {
+ /* parse_stream already emitted error msg */
+ if (!BB_MMU)
+ free(as_string);
+ debug_printf_parse("parse_group return -1: "
+ "parse_stream returned %p\n", pipe_list);
+ return -1;
+ }
+#if !BB_MMU
+ as_string[strlen(as_string) - 1] = '\0'; /* plink ')' or '}' */
+ command->group_as_string = as_string;
+ debug_printf_parse("end of group, remembering as:'%s'\n",
+ command->group_as_string);
+#endif
+
+#if ENABLE_HUSH_FUNCTIONS
+ /* Convert "f() (cmds)" to "f() {(cmds)}" */
+ if (command->cmd_type == CMD_FUNCDEF && endch == ')') {
+ struct command *cmd2;
+
+ cmd2 = xzalloc(sizeof(*cmd2));
+ cmd2->cmd_type = CMD_SUBSHELL;
+ cmd2->group = pipe_list;
+# if !BB_MMU
+//UNTESTED!
+ cmd2->group_as_string = command->group_as_string;
+ command->group_as_string = xasprintf("(%s)", command->group_as_string);
+# endif
+
+ pipe_list = new_pipe();
+ pipe_list->cmds = cmd2;
+ pipe_list->num_cmds = 1;
+ }
+#endif
+
+ command->group = pipe_list;
+
+ debug_printf_parse("parse_group return %d\n", heredoc_cnt);
+ return heredoc_cnt;
+ /* command remains "open", available for possible redirects */
+#undef as_string
+}
+
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_TICK || ENABLE_FEATURE_SH_MATH || ENABLE_HUSH_DOLLAR_OPS
+/* Subroutines for copying $(...) and `...` things */
+/* '...' */
+static int add_till_single_quote(o_string *dest, struct in_str *input)
+{
+ while (1) {
+ int ch = i_getch(input);
+ if (ch == EOF) {
+ syntax_error_unterm_ch('\'');
+ return 0;
+ }
+ if (ch == '\'')
+ return 1;
+ o_addchr(dest, ch);
+ }
+}
+static int add_till_single_quote_dquoted(o_string *dest, struct in_str *input)
+{
+ while (1) {
+ int ch = i_getch(input);
+ if (ch == EOF) {
+ syntax_error_unterm_ch('\'');
+ return 0;
+ }
+ if (ch == '\'')
+ return 1;
+ o_addqchr(dest, ch);
+ }
+}
+
+/* "...\"...`..`...." - do we need to handle "...$(..)..." too? */
+static int add_till_backquote(o_string *dest, struct in_str *input, int in_dquote);
+static int add_till_double_quote(o_string *dest, struct in_str *input)
+{
+ while (1) {
+ int ch = i_getch(input);
+ if (ch == EOF) {
+ syntax_error_unterm_ch('"');
+ return 0;
+ }
+ if (ch == '"')
+ return 1;
+ if (ch == '\\') { /* \x. Copy both chars. */
+ o_addchr(dest, ch);
+ ch = i_getch(input);
+ }
+ o_addchr(dest, ch);
+ if (ch == '`') {
+ if (!add_till_backquote(dest, input, /*in_dquote:*/ 1))
+ return 0;
+ o_addchr(dest, ch);
+ continue;
+ }
+ //if (ch == '$') ...
+ }
+}
+
+
+/* Process `cmd` - copy contents until "`" is seen. Complicated by
+ * \` quoting.
+ * "Within the backquoted style of command substitution, backslash
+ * shall retain its literal meaning, except when followed by: '$', '`', or '\'.
+ * The search for the matching backquote shall be satisfied by the first
+ * backquote found without a preceding backslash; during this search,
+ * if a non-escaped backquote is encountered within a shell comment,
+ * a here-document, an embedded command substitution of the $(command)
+ * form, or a quoted string, undefined results occur. A single-quoted
+ * or double-quoted string that begins, but does not end, within the
+ * "`...`" sequence produces undefined results."
+ * Example Output
+ * echo `echo '\'TEST\`echo ZZ\`BEST` \TESTZZBEST
+ */
+static int add_till_backquote(o_string *dest, struct in_str *input, int in_dquote)
+{
+ while (1) {
+ int ch = i_getch(input);
+ if (ch == '`')
+ return 1;
+ if (ch == '\\') {
+ /* \x. Copy both unless it is \`, \$, \\ and maybe \" */
+ ch = i_getch(input);
+ if (ch != '`'
+ && ch != '$'
+ && ch != '\\'
+ && (!in_dquote || ch != '"')
+ ) {
+ o_addchr(dest, '\\');
+ }
+ }
+ if (ch == EOF) {
+ syntax_error_unterm_ch('`');
+ return 0;
+ }
+ o_addchr(dest, ch);
+ }
+}
+/* Process $(cmd) - copy contents until ")" is seen. Complicated by
+ * quoting and nested ()s.
+ * "With the $(command) style of command substitution, all characters
+ * following the open parenthesis to the matching closing parenthesis
+ * constitute the command. Any valid shell script can be used for command,
+ * except a script consisting solely of redirections which produces
+ * unspecified results."
+ * Example Output
+ * echo $(echo '(TEST)' BEST) (TEST) BEST
+ * echo $(echo 'TEST)' BEST) TEST) BEST
+ * echo $(echo \(\(TEST\) BEST) ((TEST) BEST
+ *
+ * Also adapted to eat ${var%...} and $((...)) constructs, since ... part
+ * can contain arbitrary constructs, just like $(cmd).
+ * In bash compat mode, it needs to also be able to stop on ':' or '/'
+ * for ${var:N[:M]} and ${var/P[/R]} parsing.
+ */
+#define DOUBLE_CLOSE_CHAR_FLAG 0x80
+static int add_till_closing_bracket(o_string *dest, struct in_str *input, unsigned end_ch)
+{
+ int ch;
+ char dbl = end_ch & DOUBLE_CLOSE_CHAR_FLAG;
+# if BASH_SUBSTR || BASH_PATTERN_SUBST
+ char end_char2 = end_ch >> 8;
+# endif
+ end_ch &= (DOUBLE_CLOSE_CHAR_FLAG - 1);
+
+# if ENABLE_HUSH_INTERACTIVE
+ G.promptmode = 1; /* PS2 */
+# endif
+ debug_printf_prompt("%s promptmode=%d\n", __func__, G.promptmode);
+
+ while (1) {
+ ch = i_getch(input);
+ if (ch == EOF) {
+ syntax_error_unterm_ch(end_ch);
+ return 0;
+ }
+ if (ch == end_ch
+# if BASH_SUBSTR || BASH_PATTERN_SUBST
+ || ch == end_char2
+# endif
+ ) {
+ if (!dbl)
+ break;
+ /* we look for closing )) of $((EXPR)) */
+ if (i_peek_and_eat_bkslash_nl(input) == end_ch) {
+ i_getch(input); /* eat second ')' */
+ break;
+ }
+ }
+ o_addchr(dest, ch);
+ //bb_error_msg("%s:o_addchr('%c')", __func__, ch);
+ if (ch == '(' || ch == '{') {
+ ch = (ch == '(' ? ')' : '}');
+ if (!add_till_closing_bracket(dest, input, ch))
+ return 0;
+ o_addchr(dest, ch);
+ continue;
+ }
+ if (ch == '\'') {
+ if (!add_till_single_quote(dest, input))
+ return 0;
+ o_addchr(dest, ch);
+ continue;
+ }
+ if (ch == '"') {
+ if (!add_till_double_quote(dest, input))
+ return 0;
+ o_addchr(dest, ch);
+ continue;
+ }
+ if (ch == '`') {
+ if (!add_till_backquote(dest, input, /*in_dquote:*/ 0))
+ return 0;
+ o_addchr(dest, ch);
+ continue;
+ }
+ if (ch == '\\') {
+ /* \x. Copy verbatim. Important for \(, \) */
+ ch = i_getch(input);
+ if (ch == EOF) {
+ syntax_error_unterm_ch(end_ch);
+ return 0;
+ }
+# if 0
+ if (ch == '\n') {
+ /* "backslash+newline", ignore both */
+ o_delchr(dest); /* undo insertion of '\' */
+ continue;
+ }
+# endif
+ o_addchr(dest, ch);
+ //bb_error_msg("%s:o_addchr('%c') after '\\'", __func__, ch);
+ continue;
+ }
+ }
+ debug_printf_parse("%s return '%s' ch:'%c'\n", __func__, dest->data, ch);
+ return ch;
+}
+#endif /* ENABLE_HUSH_TICK || ENABLE_FEATURE_SH_MATH || ENABLE_HUSH_DOLLAR_OPS */
+
+#if BASH_DOLLAR_SQUOTE
+/* Return code: 1 for "found and parsed", 0 for "seen something else" */
+# if BB_MMU
+#define parse_dollar_squote(as_string, dest, input) \
+ parse_dollar_squote(dest, input)
+#define as_string NULL
+# endif
+static int parse_dollar_squote(o_string *as_string, o_string *dest, struct in_str *input)
+{
+ int start;
+ int ch = i_peek_and_eat_bkslash_nl(input); /* first character after the $ */
+ debug_printf_parse("parse_dollar_squote entered: ch='%c'\n", ch);
+ if (ch != '\'')
+ return 0;
+
+ dest->has_quoted_part = 1;
+ start = dest->length;
+
+ ch = i_getch(input); /* eat ' */
+ nommu_addchr(as_string, ch);
+ while (1) {
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ if (ch == EOF) {
+ syntax_error_unterm_ch('\'');
+ return 0;
+ }
+ if (ch == '\'')
+ break;
+ if (ch == SPECIAL_VAR_SYMBOL) {
+ /* Convert raw ^C to corresponding special variable reference */
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(dest, SPECIAL_VAR_QUOTED_SVS);
+ /* will addchr() another SPECIAL_VAR_SYMBOL (see after the if() block) */
+ } else if (ch == '\\') {
+ static const char C_escapes[] ALIGN1 = "nrbtfav""x\\01234567";
+
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ if (strchr(C_escapes, ch)) {
+ char buf[4];
+ char *p = buf;
+ int cnt = 2;
+
+ buf[0] = ch;
+ if ((unsigned char)(ch - '0') <= 7) { /* \ooo */
+ do {
+ ch = i_peek(input);
+ if ((unsigned char)(ch - '0') > 7)
+ break;
+ *++p = ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ } while (--cnt != 0);
+ } else if (ch == 'x') { /* \xHH */
+ do {
+ ch = i_peek(input);
+ if (!isxdigit(ch))
+ break;
+ *++p = ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ } while (--cnt != 0);
+ if (cnt == 2) { /* \x but next char is "bad" */
+ ch = 'x';
+ goto unrecognized;
+ }
+ } /* else simple seq like \\ or \t */
+ *++p = '\0';
+ p = buf;
+ ch = bb_process_escape_sequence((void*)&p);
+ //bb_error_msg("buf:'%s' ch:%x", buf, ch);
+ if (ch == '\0')
+ continue; /* bash compat: $'...\0...' emits nothing */
+ } else { /* unrecognized "\z": encode both chars unless ' or " */
+ if (ch != '\'' && ch != '"') {
+ unrecognized:
+ o_addqchr(dest, '\\');
+ }
+ }
+ } /* if (\...) */
+ o_addqchr(dest, ch);
+ }
+
+ if (dest->length == start) {
+ /* $'', $'\0', $'\000\x00' and the like */
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ }
+
+ return 1;
+# undef as_string
+}
+#else
+# define parse_dollar_squote(as_string, dest, input) 0
+#endif /* BASH_DOLLAR_SQUOTE */
+#endif /* !__U_BOOT__ */
+
+/* Return code: 0 for OK, 1 for syntax error */
+#if BB_MMU
+#define parse_dollar(as_string, dest, input, quote_mask) \
+ parse_dollar(dest, input, quote_mask)
+#define as_string NULL
+#endif
+static int parse_dollar(o_string *as_string,
+ o_string *dest,
+ struct in_str *input, unsigned char quote_mask)
+{
+ int ch = i_peek_and_eat_bkslash_nl(input); /* first character after the $ */
+
+ debug_printf_parse("parse_dollar entered: ch='%c' quote_mask:0x%x\n", ch, quote_mask);
+ if (isalpha(ch)) {
+ make_var:
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ /*make_var1:*/
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ while (1) {
+ debug_printf_parse(": '%c'\n", ch);
+ o_addchr(dest, ch | quote_mask);
+ quote_mask = 0;
+ ch = i_peek_and_eat_bkslash_nl(input);
+ if (!isalnum(ch) && ch != '_') {
+ /* End of variable name reached */
+ break;
+ }
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ }
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ } else if (isdigit(ch)) {
+ make_one_char_var:
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ debug_printf_parse(": '%c'\n", ch);
+ o_addchr(dest, ch | quote_mask);
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ } else switch (ch) {
+#ifndef __U_BOOT__
+ case '$': /* pid */
+ case '!': /* last bg pid */
+#endif /* !__U_BOOT__ */
+ case '?': /* last exit code */
+ case '#': /* number of args */
+ case '*': /* args */
+ case '@': /* args */
+ case '-': /* $- option flags set by set builtin or shell options (-i etc) */
+ goto make_one_char_var;
+ case '{': {
+ char len_single_ch;
+
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+
+ ch = i_getch(input); /* eat '{' */
+ nommu_addchr(as_string, ch);
+
+ ch = i_getch_and_eat_bkslash_nl(input); /* first char after '{' */
+ /* It should be ${?}, or ${#var},
+ * or even ${?+subst} - operator acting on a special variable,
+ * or the beginning of variable name.
+ */
+ if (ch == EOF
+ || (!strchr(_SPECIAL_VARS_STR, ch) && !isalnum(ch)) /* not one of those */
+ ) {
+ bad_dollar_syntax:
+ syntax_error_unterm_str("${name}");
+ debug_printf_parse("parse_dollar return 0: unterminated ${name}\n");
+ return 0;
+ }
+ nommu_addchr(as_string, ch);
+ len_single_ch = ch;
+ ch |= quote_mask;
+
+ /* It's possible to just call add_till_closing_bracket() at this point.
+ * However, this regresses some of our testsuite cases
+ * which check invalid constructs like ${%}.
+ * Oh well... let's check that the var name part is fine... */
+
+ if (isdigit(len_single_ch)
+ || (len_single_ch == '#' && isdigit(i_peek_and_eat_bkslash_nl(input)))
+ ) {
+ /* Execution engine uses plain xatoi_positive()
+ * to interpret ${NNN} and {#NNN},
+ * check syntax here in the parser.
+ * (bash does not support expressions in ${#NN},
+ * e.g. ${#$var} and {#1:+WORD} are not supported).
+ */
+ unsigned cnt = 9; /* max 9 digits for ${NN} and 8 for {#NN} */
+ while (1) {
+ o_addchr(dest, ch);
+ debug_printf_parse(": '%c'\n", ch);
+ ch = i_getch_and_eat_bkslash_nl(input);
+ nommu_addchr(as_string, ch);
+ if (ch == '}')
+ break;
+ if (--cnt == 0)
+ goto bad_dollar_syntax;
+ if (len_single_ch != '#' && strchr(VAR_SUBST_OPS, ch))
+ /* ${NN<op>...} is valid */
+ goto eat_until_closing;
+ if (!isdigit(ch))
+ goto bad_dollar_syntax;
+ }
+ } else
+ while (1) {
+ unsigned pos;
+
+ o_addchr(dest, ch);
+ debug_printf_parse(": '%c'\n", ch);
+
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ if (ch == '}')
+ break;
+#ifndef __U_BOOT__
+ if (!isalnum(ch) && ch != '_') {
+#else /* __U_BOOT__ */
+ /*
+ * In several places in U-Boot, we use variable like
+ * foo# (e.g. serial#), particularly in env.
+ * So, we need to authorize # to appear inside
+ * variable name and then expand this variable.
+ * NOTE Having # in variable name is not permitted in
+ * upstream hush but expansion will be done (even though
+ * the result will be empty).
+ */
+ if (!isalnum(ch) && ch != '_' && ch != '#') {
+#endif /* __U_BOOT__ */
+ unsigned end_ch;
+#ifndef __U_BOOT__
+ unsigned char last_ch;
+#endif /* !__U_BOOT__ */
+ /* handle parameter expansions
+ * http://www.opengroup.org/onlinepubs/009695399/utilities/xcu_chap02.html#tag_02_06_02
+ */
+ if (!strchr(VAR_SUBST_OPS, ch)) { /* ${var<bad_char>... */
+ if (len_single_ch != '#'
+ /*|| !strchr(SPECIAL_VARS_STR, ch) - disallow errors like ${#+} ? */
+ || i_peek(input) != '}'
+ ) {
+ goto bad_dollar_syntax;
+ }
+ /* else: it's "length of C" ${#C} op,
+ * where C is a single char
+ * special var name, e.g. ${#!}.
+ */
+ }
+ eat_until_closing:
+ /* Eat everything until closing '}' (or ':') */
+ end_ch = '}';
+#ifndef __U_BOOT__
+ if (BASH_SUBSTR
+ && ch == ':'
+ && !strchr(MINUS_PLUS_EQUAL_QUESTION, i_peek(input))
+ ) {
+ /* It's ${var:N[:M]} thing */
+ end_ch = '}' * 0x100 + ':';
+ }
+ if (BASH_PATTERN_SUBST
+ && ch == '/'
+ ) {
+ /* It's ${var/[/]pattern[/repl]} thing */
+ if (i_peek(input) == '/') { /* ${var//pattern[/repl]}? */
+ i_getch(input);
+ nommu_addchr(as_string, '/');
+ ch = '\\';
+ }
+ end_ch = '}' * 0x100 + '/';
+ }
+#endif /* !__U_BOOT__ */
+ o_addchr(dest, ch);
+ /* The pattern can't be empty.
+ * IOW: if the first char after "${v//" is a slash,
+ * it does not terminate the pattern - it's the first char of the pattern:
+ * v=/dev/ram; echo ${v////-} prints -dev-ram (pattern is "/")
+ * v=/dev/ram; echo ${v///r/-} prints /dev-am (pattern is "/r")
+ */
+ if (i_peek(input) == '/') {
+ o_addchr(dest, i_getch(input));
+ }
+#ifndef __U_BOOT__
+ again:
+#endif /* !__U_BOOT__ */
+ if (!BB_MMU)
+ pos = dest->length;
+#if ENABLE_HUSH_DOLLAR_OPS
+#ifndef __U_BOOT__
+ last_ch = add_till_closing_bracket(dest, input, end_ch);
+ if (last_ch == 0) /* error? */
+ return 0;
+#endif /* !__U_BOOT__ */
+#else
+# error Simple code to only allow ${var} is not implemented
+#endif
+ if (as_string) {
+ o_addstr(as_string, dest->data + pos);
+#ifndef __U_BOOT__
+ o_addchr(as_string, last_ch);
+#endif /* !__U_BOOT__ */
+ }
+
+#ifndef __U_BOOT__
+ if ((BASH_SUBSTR || BASH_PATTERN_SUBST)
+ && (end_ch & 0xff00)
+ ) {
+ /* close the first block: */
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ /* while parsing N from ${var:N[:M]}
+ * or pattern from ${var/[/]pattern[/repl]} */
+ if ((end_ch & 0xff) == last_ch) {
+ /* got ':' or '/'- parse the rest */
+ end_ch = '}';
+ goto again;
+ }
+ /* got '}' */
+ if (BASH_SUBSTR && end_ch == '}' * 0x100 + ':') {
+ /* it's ${var:N} - emulate :999999999 */
+ o_addstr(dest, "999999999");
+ } /* else: it's ${var/[/]pattern} */
+ }
+#endif /* !__U_BOOT__ */
+ break;
+ }
+ len_single_ch = 0; /* it can't be ${#C} op */
+ }
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ break;
+ }
+#if ENABLE_FEATURE_SH_MATH || ENABLE_HUSH_TICK
+ case '(': {
+ unsigned pos;
+
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+# if ENABLE_FEATURE_SH_MATH
+ if (i_peek_and_eat_bkslash_nl(input) == '(') {
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(dest, quote_mask | '+');
+ if (!BB_MMU)
+ pos = dest->length;
+ if (!add_till_closing_bracket(dest, input, ')' | DOUBLE_CLOSE_CHAR_FLAG))
+ return 0; /* error */
+ if (as_string) {
+ o_addstr(as_string, dest->data + pos);
+ o_addchr(as_string, ')');
+ o_addchr(as_string, ')');
+ }
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ break;
+ }
+# endif
+# if ENABLE_HUSH_TICK
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(dest, quote_mask | '`');
+ if (!BB_MMU)
+ pos = dest->length;
+ if (!add_till_closing_bracket(dest, input, ')'))
+ return 0; /* error */
+ if (as_string) {
+ o_addstr(as_string, dest->data + pos);
+ o_addchr(as_string, ')');
+ }
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+# endif
+ break;
+ }
+#endif
+ case '_':
+ goto make_var;
+#if 0
+ /* TODO: $_: */
+ /* $_ Shell or shell script name; or last argument of last command
+ * (if last command wasn't a pipe; if it was, bash sets $_ to "");
+ * but in command's env, set to full pathname used to invoke it */
+ ch = i_getch(input);
+ nommu_addchr(as_string, ch);
+ ch = i_peek_and_eat_bkslash_nl(input);
+ if (isalnum(ch)) { /* it's $_name or $_123 */
+ ch = '_';
+ goto make_var1;
+ }
+ /* else: it's $_ */
+#endif
+ default:
+ o_addQchr(dest, '$');
+ }
+ debug_printf_parse("parse_dollar return 1 (ok)\n");
+ return 1;
+#undef as_string
+}
+
+#if BB_MMU
+#define encode_string(as_string, dest, input, dquote_end) \
+ encode_string(dest, input, dquote_end)
+#define as_string NULL
+#endif
+static int encode_string(o_string *as_string,
+ o_string *dest,
+ struct in_str *input,
+ int dquote_end)
+{
+ int ch;
+ int next;
+
+ again:
+ ch = i_getch(input);
+ if (ch != EOF)
+ nommu_addchr(as_string, ch);
+ if (ch == dquote_end) { /* may be only '"' or EOF */
+ debug_printf_parse("encode_string return 1 (ok)\n");
+ return 1;
+ }
+ /* note: can't move it above ch == dquote_end check! */
+ if (ch == EOF) {
+ syntax_error_unterm_ch('"');
+ return 0; /* error */
+ }
+ next = '\0';
+ if (ch != '\n') {
+ next = i_peek(input);
+ }
+ debug_printf_parse("\" ch=%c (%d) escape=%d\n",
+ ch, ch, !!(dest->o_expflags & EXP_FLAG_ESC_GLOB_CHARS));
+ if (ch == '\\') {
+ if (next == EOF) {
+ /* Testcase: in interactive shell a file with
+ * echo "unterminated string\<eof>
+ * is sourced.
+ */
+ syntax_error_unterm_ch('"');
+ return 0; /* error */
+ }
+ /* bash:
+ * "The backslash retains its special meaning [in "..."]
+ * only when followed by one of the following characters:
+ * $, `, ", \, or <newline>. A double quote may be quoted
+ * within double quotes by preceding it with a backslash."
+ * NB: in (unquoted) heredoc, above does not apply to ",
+ * therefore we check for it by "next == dquote_end" cond.
+ */
+ if (next == dquote_end || strchr("$`\\\n", next)) {
+ ch = i_getch(input); /* eat next */
+ if (ch == '\n')
+ goto again; /* skip \<newline> */
+ } /* else: ch remains == '\\', and we double it below: */
+ o_addqchr(dest, ch); /* \c if c is a glob char, else just c */
+ nommu_addchr(as_string, ch);
+ goto again;
+ }
+ if (ch == '$') {
+ //if (parse_dollar_squote(as_string, dest, input))
+ // goto again;
+ if (!parse_dollar(as_string, dest, input, /*quote_mask:*/ 0x80)) {
+ debug_printf_parse("encode_string return 0: "
+ "parse_dollar returned 0 (error)\n");
+ return 0;
+ }
+ goto again;
+ }
+#if ENABLE_HUSH_TICK
+ if (ch == '`') {
+ //unsigned pos = dest->length;
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(dest, 0x80 | '`');
+ if (!add_till_backquote(dest, input, /*in_dquote:*/ dquote_end == '"'))
+ return 0; /* error */
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ //debug_printf_subst("SUBST RES3 '%s'\n", dest->data + pos);
+ goto again;
+ }
+#endif
+ o_addQchr(dest, ch);
+ if (ch == SPECIAL_VAR_SYMBOL) {
+ /* Convert "^C" to corresponding special variable reference */
+ o_addchr(dest, SPECIAL_VAR_QUOTED_SVS);
+ o_addchr(dest, SPECIAL_VAR_SYMBOL);
+ }
+ goto again;
+#undef as_string
+}
+
+/*
+ * Scan input until EOF or end_trigger char.
+ * Return a list of pipes to execute, or NULL on EOF
+ * or if end_trigger character is met.
+ * On syntax error, exit if shell is not interactive,
+ * reset parsing machinery and start parsing anew,
+ * or return ERR_PTR.
+ */
+static struct pipe *parse_stream(char **pstring,
+ int *heredoc_cnt_ptr,
+ struct in_str *input,
+ int end_trigger)
+{
+ struct parse_context ctx;
+ int heredoc_cnt;
+
+ /* Single-quote triggers a bypass of the main loop until its mate is
+ * found. When recursing, quote state is passed in via ctx.word.o_expflags.
+ */
+ debug_printf_parse("parse_stream entered, end_trigger='%c'\n",
+ end_trigger ? end_trigger : 'X');
+ debug_enter();
+
+ initialize_context(&ctx);
+
+ /* If very first arg is "" or '', ctx.word.data may end up NULL.
+ * Preventing this:
+ */
+ ctx.word.data = xzalloc(1); /* start as "", not as NULL */
+
+ /* We used to separate words on $IFS here. This was wrong.
+ * $IFS is used only for word splitting when $var is expanded,
+ * here we should use blank chars as separators, not $IFS
+ */
+
+ heredoc_cnt = 0;
+ while (1) {
+ const char *is_blank;
+ const char *is_special;
+ int ch;
+ int next;
+#ifndef __U_BOOT__
+ int redir_fd;
+ redir_type redir_style;
+#endif /* !__U_BOOT__ */
+
+ ch = i_getch(input);
+ debug_printf_parse(": ch=%c (%d) escape=%d\n",
+ ch, ch, !!(ctx.word.o_expflags & EXP_FLAG_ESC_GLOB_CHARS));
+ if (ch == EOF) {
+ struct pipe *pi;
+
+ if (heredoc_cnt) {
+ syntax_error_unterm_str("here document");
+ goto parse_error_exitcode1;
+ }
+ if (end_trigger == ')') {
+ syntax_error_unterm_ch('(');
+ goto parse_error_exitcode1;
+ }
+ if (end_trigger == '}') {
+ syntax_error_unterm_ch('{');
+ goto parse_error_exitcode1;
+ }
+
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ o_free_and_set_NULL(&ctx.word);
+ done_pipe(&ctx, PIPE_SEQ);
+ pi = ctx.list_head;
+ /* If we got nothing... */
+ /* (this makes bare "&" cmd a no-op.
+ * bash says: "syntax error near unexpected token '&'") */
+ if (pi->num_cmds == 0
+ IF_HAS_KEYWORDS(&& pi->res_word == RES_NONE)
+ ) {
+ free_pipe_list(pi);
+ pi = NULL;
+ }
+#if !BB_MMU
+ debug_printf_parse("as_string1 '%s'\n", ctx.as_string.data);
+ if (pstring)
+ *pstring = ctx.as_string.data;
+ else
+ o_free(&ctx.as_string);
+#endif
+ // heredoc_cnt must be 0 here anyway
+ //if (heredoc_cnt_ptr)
+ // *heredoc_cnt_ptr = heredoc_cnt;
+ debug_leave();
+ debug_printf_heredoc("parse_stream return heredoc_cnt:%d\n", heredoc_cnt);
+ debug_printf_parse("parse_stream return %p\n", pi);
+ return pi;
+ }
+
+ /* Handle "'" and "\" first, as they won't play nice with
+ * i_peek_and_eat_bkslash_nl() anyway:
+ * echo z\\
+ * and
+ * echo '\
+ * '
+ * would break.
+ */
+ if (ch == '\\') {
+ ch = i_getch(input);
+ if (ch == '\n')
+ continue; /* drop \<newline>, get next char */
+ nommu_addchr(&ctx.as_string, '\\');
+ if (ch == SPECIAL_VAR_SYMBOL) {
+ nommu_addchr(&ctx.as_string, ch);
+ /* Convert \^C to corresponding special variable reference */
+ goto case_SPECIAL_VAR_SYMBOL;
+ }
+ o_addchr(&ctx.word, '\\');
+ if (ch == EOF) {
+ /* Testcase: eval 'echo Ok\' */
+ /* bash-4.3.43 was removing backslash,
+ * but 4.4.19 retains it, most other shells too
+ */
+ continue; /* get next char */
+ }
+ /* Example: echo Hello \2>file
+ * we need to know that word 2 is quoted
+ */
+ ctx.word.has_quoted_part = 1;
+ nommu_addchr(&ctx.as_string, ch);
+ o_addchr(&ctx.word, ch);
+ continue; /* get next char */
+ }
+ nommu_addchr(&ctx.as_string, ch);
+ if (ch == '\'') {
+ ctx.word.has_quoted_part = 1;
+ next = i_getch(input);
+#ifndef __U_BOOT__
+ if (next == '\'' && !ctx.pending_redirect)
+ goto insert_empty_quoted_str_marker;
+#endif /* !__U_BOOT__ */
+
+ ch = next;
+ while (1) {
+ if (ch == EOF) {
+ syntax_error_unterm_ch('\'');
+ goto parse_error_exitcode1;
+ }
+ nommu_addchr(&ctx.as_string, ch);
+ if (ch == '\'')
+ break;
+ if (ch == SPECIAL_VAR_SYMBOL) {
+ /* Convert raw ^C to corresponding special variable reference */
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ o_addchr(&ctx.word, SPECIAL_VAR_QUOTED_SVS);
+ }
+ o_addqchr(&ctx.word, ch);
+ ch = i_getch(input);
+ }
+ continue; /* get next char */
+ }
+
+ next = '\0';
+ if (ch != '\n')
+ next = i_peek_and_eat_bkslash_nl(input);
+
+ is_special = "{}<>&|();#" /* special outside of "str" */
+#ifndef __U_BOOT__
+ "$\"" IF_HUSH_TICK("`") /* always special */
+#else /* __U_BOOT__ */
+ "$\""
+#endif /* __U_BOOT__ */
+ SPECIAL_VAR_SYMBOL_STR;
+#if defined(CMD_TEST2_SINGLEWORD_NOGLOB)
+ if (ctx.command->cmd_type == CMD_TEST2_SINGLEWORD_NOGLOB) {
+ /* In [[ ]], {}<>&|() are not special */
+ is_special += 8;
+ } else
+#endif
+ /* Are { and } special here? */
+ if (ctx.command->argv /* word [word]{... - non-special */
+ || ctx.word.length /* word{... - non-special */
+ || ctx.word.has_quoted_part /* ""{... - non-special */
+ || (next != ';' /* }; - special */
+ && next != ')' /* }) - special */
+ && next != '(' /* {( - special */
+ && next != '&' /* }& and }&& ... - special */
+ && next != '|' /* }|| ... - special */
+ && !strchr(defifs, next) /* {word - non-special */
+ )
+ ) {
+ /* They are not special, skip "{}" */
+ is_special += 2;
+ }
+ is_special = strchr(is_special, ch);
+ is_blank = strchr(defifs, ch);
+
+ if (!is_special && !is_blank) { /* ordinary char */
+ ordinary_char:
+ o_addQchr(&ctx.word, ch);
+ if ((ctx.is_assignment == MAYBE_ASSIGNMENT
+ || ctx.is_assignment == WORD_IS_KEYWORD)
+ && ch == '='
+ && endofname(ctx.word.data)[0] == '='
+ ) {
+ ctx.is_assignment = DEFINITELY_ASSIGNMENT;
+ debug_printf_parse("ctx.is_assignment='%s'\n", assignment_flag[ctx.is_assignment]);
+ }
+ continue;
+ }
+
+ if (is_blank) {
+#if ENABLE_HUSH_LINENO_VAR
+/* Case:
+ * "while ...; do<whitespace><newline>
+ * cmd ..."
+ * would think that "cmd" starts in <whitespace> -
+ * i.e., at the previous line.
+ * We need to skip all whitespace before newlines.
+ */
+ while (ch != '\n') {
+ next = i_peek(input);
+ if (next != ' ' && next != '\t' && next != '\n')
+ break; /* next char is not ws */
+ ch = i_getch(input);
+ }
+ /* ch == last eaten whitespace char */
+#endif
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ if (ch == '\n') {
+ /* Is this a case when newline is simply ignored?
+ * Some examples:
+ * "cmd | <newline> cmd ..."
+ * "case ... in <newline> word) ..."
+ */
+ if (IS_NULL_CMD(ctx.command)
+ && ctx.word.length == 0
+ && !ctx.word.has_quoted_part
+ && heredoc_cnt == 0
+ ) {
+ /* This newline can be ignored. But...
+ * Without check #1, interactive shell
+ * ignores even bare <newline>,
+ * and shows the continuation prompt:
+ * ps1_prompt$ <enter>
+ * ps2> _ <=== wrong, should be ps1
+ * Without check #2, "cmd & <newline>"
+ * is similarly mistreated.
+ * (BTW, this makes "cmd & cmd"
+ * and "cmd && cmd" non-orthogonal.
+ * Really, ask yourself, why
+ * "cmd && <newline>" doesn't start
+ * cmd but waits for more input?
+ * The only reason is that it might be
+ * a "cmd1 && <nl> cmd2 &" construct,
+ * cmd1 may need to run in BG).
+ */
+ struct pipe *pi = ctx.list_head;
+ if (pi->num_cmds != 0 /* check #1 */
+ && pi->followup != PIPE_BG /* check #2 */
+ ) {
+ continue;
+ }
+ }
+ /* Treat newline as a command separator. */
+ done_pipe(&ctx, PIPE_SEQ);
+ debug_printf_heredoc("heredoc_cnt:%d\n", heredoc_cnt);
+ if (heredoc_cnt) {
+ heredoc_cnt = fetch_heredocs(&ctx.as_string, ctx.list_head, heredoc_cnt, input);
+ if (heredoc_cnt != 0)
+ goto parse_error_exitcode1;
+ }
+ ctx.is_assignment = MAYBE_ASSIGNMENT;
+ debug_printf_parse("ctx.is_assignment='%s'\n", assignment_flag[ctx.is_assignment]);
+ ch = ';';
+ /* note: if (is_blank) continue;
+ * will still trigger for us */
+ }
+ }
+
+ /* "cmd}" or "cmd }..." without semicolon or &:
+ * } is an ordinary char in this case, even inside { cmd; }
+ * Pathological example: { ""}; } should exec "}" cmd
+ */
+#ifndef __U_BOOT__
+ if (ch == '}') {
+#else /* __U_BOOT__ */
+ if (ch == '}' || ch == ')') {
+#endif /* __U_BOOT__ */
+ if (ctx.word.length != 0 /* word} */
+ || ctx.word.has_quoted_part /* ""} */
+ ) {
+ goto ordinary_char;
+ }
+ if (!IS_NULL_CMD(ctx.command)) { /* cmd } */
+ /* Generally, there should be semicolon: "cmd; }"
+ * However, bash allows to omit it if "cmd" is
+ * a group. Examples:
+ * { { echo 1; } }
+ * {(echo 1)}
+ * { echo 0 >&2 | { echo 1; } }
+ * { while false; do :; done }
+ * { case a in b) ;; esac }
+ */
+ if (ctx.command->group)
+ goto term_group;
+ goto ordinary_char;
+ }
+ if (!IS_NULL_PIPE(ctx.pipe)) /* cmd | } */
+ /* Can't be an end of {cmd}, skip the check */
+ goto skip_end_trigger;
+ /* else: } does terminate a group */
+ }
+ term_group:
+ if (end_trigger && end_trigger == ch
+ && (ch != ';' || heredoc_cnt == 0)
+#if ENABLE_HUSH_CASE
+ && (ch != ')'
+ || ctx.ctx_res_w != RES_MATCH
+ || (!ctx.word.has_quoted_part && strcmp(ctx.word.data, "esac") == 0)
+ )
+#endif
+ ) {
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ done_pipe(&ctx, PIPE_SEQ);
+ ctx.is_assignment = MAYBE_ASSIGNMENT;
+ debug_printf_parse("ctx.is_assignment='%s'\n", assignment_flag[ctx.is_assignment]);
+ /* Do we sit outside of any if's, loops or case's? */
+ if (!HAS_KEYWORDS
+ IF_HAS_KEYWORDS(|| (ctx.ctx_res_w == RES_NONE && ctx.old_flag == 0))
+ ) {
+ o_free_and_set_NULL(&ctx.word);
+#if !BB_MMU
+ debug_printf_parse("as_string2 '%s'\n", ctx.as_string.data);
+ if (pstring)
+ *pstring = ctx.as_string.data;
+ else
+ o_free(&ctx.as_string);
+#endif
+ if (ch != ';' && IS_NULL_PIPE(ctx.list_head)) {
+ /* Example: bare "{ }", "()" */
+ G.last_exitcode = 2; /* bash compat */
+ syntax_error_unexpected_ch(ch);
+ goto parse_error;
+ }
+ if (heredoc_cnt_ptr)
+ *heredoc_cnt_ptr = heredoc_cnt;
+ debug_printf_heredoc("parse_stream return heredoc_cnt:%d\n", heredoc_cnt);
+ debug_printf_parse("parse_stream return %p: "
+ "end_trigger char found\n",
+ ctx.list_head);
+ debug_leave();
+ return ctx.list_head;
+ }
+ }
+
+ if (is_blank)
+ continue;
+
+ /* Catch <, > before deciding whether this word is
+ * an assignment. a=1 2>z b=2: b=2 is still assignment */
+ switch (ch) {
+#ifndef __U_BOOT__
+ case '>':
+ redir_fd = redirect_opt_num(&ctx.word);
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ redir_style = REDIRECT_OVERWRITE;
+ if (next == '>') {
+ redir_style = REDIRECT_APPEND;
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ }
+#if 0
+ else if (next == '(') {
+ syntax_error(">(process) not supported");
+ goto parse_error_exitcode1;
+ }
+#endif
+ if (parse_redirect(&ctx, redir_fd, redir_style, input))
+ goto parse_error_exitcode1;
+ continue; /* get next char */
+ case '<':
+ redir_fd = redirect_opt_num(&ctx.word);
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ redir_style = REDIRECT_INPUT;
+ if (next == '<') {
+ redir_style = REDIRECT_HEREDOC;
+ heredoc_cnt++;
+ debug_printf_heredoc("++heredoc_cnt=%d\n", heredoc_cnt);
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ } else if (next == '>') {
+ redir_style = REDIRECT_IO;
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ }
+#if 0
+ else if (next == '(') {
+ syntax_error("<(process) not supported");
+ goto parse_error_exitcode1;
+ }
+#endif
+ if (parse_redirect(&ctx, redir_fd, redir_style, input))
+ goto parse_error_exitcode1;
+ continue; /* get next char */
+#else /* __U_BOOT__ */
+ /*
+ * In U-Boot, '<' and '>' can be used in test command to test if
+ * a string is, alphabetically, before or after another.
+ * In 2021 Busybox hush, we will keep the same behavior and so not treat
+ * them as redirection operator.
+ *
+ * Indeed, in U-Boot, tests are handled by the test command and not by the
+ * shell code.
+ * So, better to give this character as input to test command.
+ *
+ * NOTE In my opinion, when you use '<' or '>' I am almost sure
+ * you wanted to use "-gt" or "-lt" in place, so thinking to
+ * escape these will make you should check your code (sh syntax
+ * at this level is, for me, error prone).
+ */
+ case '>':
+ fallthrough;
+ case '<':
+ o_addQchr(&ctx.word, ch);
+ continue;
+#endif /* __U_BOOT__ */
+ case '#':
+ if (ctx.word.length == 0 && !ctx.word.has_quoted_part) {
+ /* skip "#comment" */
+ /* note: we do not add it to &ctx.as_string */
+/* TODO: in bash:
+ * comment inside $() goes to the next \n, even inside quoted string (!):
+ * cmd "$(cmd2 #comment)" - syntax error
+ * cmd "`cmd2 #comment`" - ok
+ * We accept both (comment ends where command subst ends, in both cases).
+ */
+ while (1) {
+ ch = i_peek(input);
+ if (ch == '\n') {
+ nommu_addchr(&ctx.as_string, '\n');
+ break;
+ }
+ ch = i_getch(input);
+ if (ch == EOF)
+ break;
+ }
+ continue; /* get next char */
+ }
+ break;
+ }
+ skip_end_trigger:
+
+ if (ctx.is_assignment == MAYBE_ASSIGNMENT
+#ifndef __U_BOOT__
+ /* check that we are not in word in "a=1 2>word b=1": */
+ && !ctx.pending_redirect
+#endif /* !__U_BOOT__ */
+ ) {
+ /* ch is a special char and thus this word
+ * cannot be an assignment */
+ ctx.is_assignment = NOT_ASSIGNMENT;
+ debug_printf_parse("ctx.is_assignment='%s'\n", assignment_flag[ctx.is_assignment]);
+ }
+
+ /* Note: nommu_addchr(&ctx.as_string, ch) is already done */
+
+ switch (ch) {
+ case_SPECIAL_VAR_SYMBOL:
+ case SPECIAL_VAR_SYMBOL:
+ /* Convert raw ^C to corresponding special variable reference */
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ o_addchr(&ctx.word, SPECIAL_VAR_QUOTED_SVS);
+ /* fall through */
+ case '#':
+ /* non-comment #: "echo a#b" etc */
+ o_addchr(&ctx.word, ch);
+ continue; /* get next char */
+ case '$':
+#ifndef __U_BOOT__
+ if (parse_dollar_squote(&ctx.as_string, &ctx.word, input))
+ continue; /* get next char */
+#endif /* !__U_BOOT__ */
+ if (!parse_dollar(&ctx.as_string, &ctx.word, input, /*quote_mask:*/ 0)) {
+ debug_printf_parse("parse_stream parse error: "
+ "parse_dollar returned 0 (error)\n");
+ goto parse_error_exitcode1;
+ }
+ continue; /* get next char */
+ case '"':
+ ctx.word.has_quoted_part = 1;
+#ifndef __U_BOOT__
+ if (next == '"' && !ctx.pending_redirect) {
+#else /* __U_BOOT__ */
+ if (next == '"') {
+#endif /* __U_BOOT__ */
+ i_getch(input); /* eat second " */
+#ifndef __U_BOOT__
+ insert_empty_quoted_str_marker:
+#endif /* !__U_BOOT__ */
+ nommu_addchr(&ctx.as_string, next);
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ continue; /* get next char */
+ }
+ if (ctx.is_assignment == NOT_ASSIGNMENT)
+ ctx.word.o_expflags |= EXP_FLAG_ESC_GLOB_CHARS;
+ if (!encode_string(&ctx.as_string, &ctx.word, input, '"'))
+ goto parse_error_exitcode1;
+ ctx.word.o_expflags &= ~EXP_FLAG_ESC_GLOB_CHARS;
+ continue; /* get next char */
+#if ENABLE_HUSH_TICK
+ case '`': {
+ USE_FOR_NOMMU(unsigned pos;)
+
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ o_addchr(&ctx.word, '`');
+ USE_FOR_NOMMU(pos = ctx.word.length;)
+ if (!add_till_backquote(&ctx.word, input, /*in_dquote:*/ 0))
+ goto parse_error_exitcode1;
+# if !BB_MMU
+ o_addstr(&ctx.as_string, ctx.word.data + pos);
+ o_addchr(&ctx.as_string, '`');
+# endif
+ o_addchr(&ctx.word, SPECIAL_VAR_SYMBOL);
+ //debug_printf_subst("SUBST RES3 '%s'\n", ctx.word.data + pos);
+ continue; /* get next char */
+ }
+#endif
+ case ';':
+#if ENABLE_HUSH_CASE
+ case_semi:
+#endif
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ done_pipe(&ctx, PIPE_SEQ);
+#if ENABLE_HUSH_CASE
+ /* Eat multiple semicolons, detect
+ * whether it means something special */
+ while (1) {
+ ch = i_peek_and_eat_bkslash_nl(input);
+ if (ch != ';')
+ break;
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ if (ctx.ctx_res_w == RES_CASE_BODY) {
+ ctx.ctx_dsemicolon = 1;
+ ctx.ctx_res_w = RES_MATCH;
+ break;
+ }
+ }
+#endif
+ new_cmd:
+ /* We just finished a cmd. New one may start
+ * with an assignment */
+ ctx.is_assignment = MAYBE_ASSIGNMENT;
+ debug_printf_parse("ctx.is_assignment='%s'\n", assignment_flag[ctx.is_assignment]);
+ continue; /* get next char */
+ case '&':
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+ if (next == '&') {
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ done_pipe(&ctx, PIPE_AND);
+ } else {
+ done_pipe(&ctx, PIPE_BG);
+ }
+ goto new_cmd;
+ case '|':
+ if (done_word(&ctx)) {
+ goto parse_error_exitcode1;
+ }
+#if ENABLE_HUSH_CASE
+ if (ctx.ctx_res_w == RES_MATCH)
+ break; /* we are in case's "word | word)" */
+#endif
+ if (next == '|') { /* || */
+ ch = i_getch(input);
+ nommu_addchr(&ctx.as_string, ch);
+ done_pipe(&ctx, PIPE_OR);
+ } else {
+ /* we could pick up a file descriptor choice here
+ * with redirect_opt_num(), but bash doesn't do it.
+ * "echo foo 2| cat" yields "foo 2". */
+ done_command(&ctx);
+ }
+ goto new_cmd;
+ case '(':
+#if ENABLE_HUSH_CASE
+ /* "case... in [(]word)..." - skip '(' */
+ if (ctx.ctx_res_w == RES_MATCH
+ && ctx.command->argv == NULL /* not (word|(... */
+ && ctx.word.length == 0 /* not word(... */
+ && ctx.word.has_quoted_part == 0 /* not ""(... */
+ ) {
+ continue; /* get next char */
+ }
+#endif
+ /* fall through */
+ case '{': {
+ int n = parse_group(&ctx, input, ch);
+ if (n < 0) {
+ goto parse_error_exitcode1;
+ }
+ debug_printf_heredoc("parse_group done, needs heredocs:%d\n", n);
+ heredoc_cnt += n;
+ goto new_cmd;
+ }
+ case ')':
+#if ENABLE_HUSH_CASE
+ if (ctx.ctx_res_w == RES_MATCH)
+ goto case_semi;
+#endif
+ case '}':
+ /* proper use of this character is caught by end_trigger:
+ * if we see {, we call parse_group(..., end_trigger='}')
+ * and it will match } earlier (not here). */
+ G.last_exitcode = 2;
+ syntax_error_unexpected_ch(ch);
+ goto parse_error;
+ default:
+ if (HUSH_DEBUG)
+ bb_error_msg_and_die("BUG: unexpected %c", ch);
+ }
+ } /* while (1) */
+
+ parse_error_exitcode1:
+ G.last_exitcode = 1;
+ parse_error:
+ {
+ struct parse_context *pctx;
+ IF_HAS_KEYWORDS(struct parse_context *p2;)
+
+ /* Clean up allocated tree.
+ * Sample for finding leaks on syntax error recovery path.
+ * Run it from interactive shell, watch pmap `pidof hush`.
+ * while if false; then false; fi; do break; fi
+ * Samples to catch leaks at execution:
+ * while if (true | { true;}); then echo ok; fi; do break; done
+ * while if (true | { true;}); then echo ok; fi; do (if echo ok; break; then :; fi) | cat; break; done
+ */
+ pctx = &ctx;
+ do {
+ /* Update pipe/command counts,
+ * otherwise freeing may miss some */
+ done_pipe(pctx, PIPE_SEQ);
+ debug_printf_clean("freeing list %p from ctx %p\n",
+ pctx->list_head, pctx);
+ debug_print_tree(pctx->list_head, 0);
+ free_pipe_list(pctx->list_head);
+ debug_printf_clean("freed list %p\n", pctx->list_head);
+#if !BB_MMU
+ o_free(&pctx->as_string);
+#endif
+ IF_HAS_KEYWORDS(p2 = pctx->stack;)
+ if (pctx != &ctx) {
+ free(pctx);
+ }
+ IF_HAS_KEYWORDS(pctx = p2;)
+ } while (HAS_KEYWORDS && pctx);
+
+ o_free(&ctx.word);
+#if !BB_MMU
+ if (pstring)
+ *pstring = NULL;
+#endif
+ debug_leave();
+ return ERR_PTR;
+ }
+}
+
+
+/*** Execution routines ***/
+
+/* Expansion can recurse, need forward decls: */
+#if !BASH_PATTERN_SUBST && !ENABLE_HUSH_CASE
+#define expand_string_to_string(str, EXP_flags, do_unbackslash) \
+ expand_string_to_string(str)
+#endif
+static char *expand_string_to_string(const char *str, int EXP_flags, int do_unbackslash);
+#if ENABLE_HUSH_TICK
+static int process_command_subs(o_string *dest, const char *s);
+#endif
+static int expand_vars_to_list(o_string *output, int n, char *arg);
+
+/* expand_strvec_to_strvec() takes a list of strings, expands
+ * all variable references within and returns a pointer to
+ * a list of expanded strings, possibly with larger number
+ * of strings. (Think VAR="a b"; echo $VAR).
+ * This new list is allocated as a single malloc block.
+ * NULL-terminated list of char* pointers is at the beginning of it,
+ * followed by strings themselves.
+ * Caller can deallocate entire list by single free(list). */
+
+/* A horde of its helpers come first: */
+
+static void o_addblock_duplicate_backslash(o_string *o, const char *str, int len)
+{
+ while (--len >= 0) {
+ char c = *str++;
+
+#if ENABLE_HUSH_BRACE_EXPANSION
+ if (c == '{' || c == '}') {
+ /* { -> \{, } -> \} */
+ o_addchr(o, '\\');
+ /* And now we want to add { or } and continue:
+ * o_addchr(o, c);
+ * continue;
+ * luckily, just falling through achieves this.
+ */
+ }
+#endif
+ o_addchr(o, c);
+ if (c == '\\') {
+ /* \z -> \\\z; \<eol> -> \\<eol> */
+ o_addchr(o, '\\');
+ if (len) {
+ len--;
+ o_addchr(o, '\\');
+ o_addchr(o, *str++);
+ }
+ }
+ }
+}
+
+/* Store given string, finalizing the word and starting new one whenever
+ * we encounter IFS char(s). This is used for expanding variable values.
+ * End-of-string does NOT finalize word: think about 'echo -$VAR-'.
+ * Return in output->ended_in_ifs:
+ * 1 - ended with IFS char, else 0 (this includes case of empty str).
+ */
+static int expand_on_ifs(o_string *output, int n, const char *str)
+{
+ int last_is_ifs = 0;
+
+ while (1) {
+ int word_len;
+
+ if (!*str) /* EOL - do not finalize word */
+ break;
+ word_len = strcspn(str, G.ifs);
+ if (word_len) {
+ /* We have WORD_LEN leading non-IFS chars */
+ if (!(output->o_expflags & EXP_FLAG_GLOB)) {
+ o_addblock(output, str, word_len);
+ } else {
+ /* Protect backslashes against globbing up :)
+ * Example: "v='\*'; echo b$v" prints "b\*"
+ * (and does not try to glob on "*")
+ */
+ o_addblock_duplicate_backslash(output, str, word_len);
+ /*/ Why can't we do it easier? */
+ /*o_addblock(output, str, word_len); - WRONG: "v='\*'; echo Z$v" prints "Z*" instead of "Z\*" */
+ /*o_addqblock(output, str, word_len); - WRONG: "v='*'; echo Z$v" prints "Z*" instead of Z* files */
+ }
+ last_is_ifs = 0;
+ str += word_len;
+ if (!*str) /* EOL - do not finalize word */
+ break;
+ }
+
+ /* We know str here points to at least one IFS char */
+ last_is_ifs = 1;
+ str += strspn(str, G.ifs_whitespace); /* skip IFS whitespace chars */
+ if (!*str) /* EOL - do not finalize word */
+ break;
+
+ if (G.ifs_whitespace != G.ifs /* usually false ($IFS is usually all whitespace), */
+ && strchr(G.ifs, *str) /* the second check would fail */
+ ) {
+ /* This is a non-whitespace $IFS char */
+ /* Skip it and IFS whitespace chars, start new word */
+ str++;
+ str += strspn(str, G.ifs_whitespace);
+ goto new_word;
+ }
+
+ /* Start new word... but not always! */
+ /* Case "v=' a'; echo ''$v": we do need to finalize empty word: */
+ if (output->has_quoted_part
+ /*
+ * Case "v=' a'; echo $v":
+ * here nothing precedes the space in $v expansion,
+ * therefore we should not finish the word
+ * (IOW: if there *is* word to finalize, only then do it):
+ * It's okay if this accesses the byte before first argv[]:
+ * past call to o_save_ptr() cleared it to zero byte
+ * (grep for -prev-ifs-check-).
+ */
+ || output->data[output->length - 1]
+ ) {
+ new_word:
+ o_addchr(output, '\0');
+ debug_print_list("expand_on_ifs", output, n);
+ n = o_save_ptr(output, n);
+ }
+ }
+
+ output->ended_in_ifs = last_is_ifs;
+ debug_print_list("expand_on_ifs[1]", output, n);
+ return n;
+}
+
+#ifndef __U_BOOT__
+/* Helper to expand $((...)) and heredoc body. These act as if
+ * they are in double quotes, with the exception that they are not :).
+ * Just the rules are similar: "expand only $var and `cmd`"
+ *
+ * Returns malloced string.
+ * As an optimization, we return NULL if expansion is not needed.
+ */
+static char *encode_then_expand_string(const char *str)
+{
+ char *exp_str;
+ struct in_str input;
+ o_string dest = NULL_O_STRING;
+ const char *cp;
+
+ cp = str;
+ for (;;) {
+ if (!*cp) return NULL; /* string has no special chars */
+ if (*cp == '$') break;
+ if (*cp == '\\') break;
+#if ENABLE_HUSH_TICK
+ if (*cp == '`') break;
+#endif
+ cp++;
+ }
+
+ /* We need to expand. Example:
+ * echo $(($a + `echo 1`)) $((1 + $((2)) ))
+ */
+ setup_string_in_str(&input, str);
+ encode_string(NULL, &dest, &input, EOF);
+//TODO: error check (encode_string returns 0 on error)?
+ //bb_error_msg("'%s' -> '%s'", str, dest.data);
+ exp_str = expand_string_to_string(dest.data,
+ EXP_FLAG_ESC_GLOB_CHARS,
+ /*unbackslash:*/ 1
+ );
+ //bb_error_msg("'%s' -> '%s'", dest.data, exp_str);
+ o_free(&dest);
+ return exp_str;
+}
+
+static const char *first_special_char_in_vararg(const char *cp)
+{
+ for (;;) {
+ if (!*cp) return NULL; /* string has no special chars */
+ if (*cp == '$') return cp;
+ if (*cp == '\\') return cp;
+ if (*cp == '\'') return cp;
+ if (*cp == '"') return cp;
+#if ENABLE_HUSH_TICK
+ if (*cp == '`') return cp;
+#endif
+ /* dquoted "${x:+ARG}" should not glob, therefore
+ * '*' et al require some non-literal processing: */
+ if (*cp == '*') return cp;
+ if (*cp == '?') return cp;
+ if (*cp == '[') return cp;
+ cp++;
+ }
+}
+
+/* Expanding ARG in ${var#ARG}, ${var%ARG}, or ${var/ARG/ARG}.
+ * These can contain single- and double-quoted strings,
+ * and treated as if the ARG string is initially unquoted. IOW:
+ * ${var#ARG} and "${var#ARG}" treat ARG the same (ARG can even be
+ * a dquoted string: "${var#"zz"}"), the difference only comes later
+ * (word splitting and globbing of the ${var...} result).
+ */
+#if !BASH_PATTERN_SUBST
+#define encode_then_expand_vararg(str, handle_squotes, do_unbackslash) \
+ encode_then_expand_vararg(str, handle_squotes)
+#endif
+static char *encode_then_expand_vararg(const char *str, int handle_squotes, int do_unbackslash)
+{
+#if !BASH_PATTERN_SUBST && ENABLE_HUSH_CASE
+ const int do_unbackslash = 0;
+#endif
+ char *exp_str;
+ struct in_str input;
+ o_string dest = NULL_O_STRING;
+
+ if (!first_special_char_in_vararg(str)) {
+ /* string has no special chars */
+ return NULL;
+ }
+
+ setup_string_in_str(&input, str);
+ dest.data = xzalloc(1); /* start as "", not as NULL */
+ exp_str = NULL;
+
+ for (;;) {
+ int ch;
+
+ ch = i_getch(&input);
+ debug_printf_parse("%s: ch=%c (%d) escape=%d\n",
+ __func__, ch, ch, !!dest.o_expflags);
+
+ if (!dest.o_expflags) {
+ if (ch == EOF)
+ break;
+ if (handle_squotes && ch == '\'') {
+ if (!add_till_single_quote_dquoted(&dest, &input))
+ goto ret; /* error */
+ continue;
+ }
+ }
+ if (ch == EOF) {
+ syntax_error_unterm_ch('"');
+ goto ret; /* error */
+ }
+ if (ch == '"') {
+ dest.o_expflags ^= EXP_FLAG_ESC_GLOB_CHARS;
+ continue;
+ }
+ if (ch == '\\') {
+ ch = i_getch(&input);
+ if (ch == EOF) {
+//example? error message? syntax_error_unterm_ch('"');
+ debug_printf_parse("%s: error: \\<eof>\n", __func__);
+ goto ret;
+ }
+ o_addqchr(&dest, ch);
+ continue;
+ }
+ if (ch == '$') {
+ if (parse_dollar_squote(NULL, &dest, &input))
+ continue;
+ if (!parse_dollar(NULL, &dest, &input, /*quote_mask:*/ 0x80)) {
+ debug_printf_parse("%s: error: parse_dollar returned 0 (error)\n", __func__);
+ goto ret;
+ }
+ continue;
+ }
+#if ENABLE_HUSH_TICK
+ if (ch == '`') {
+ //unsigned pos = dest->length;
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(&dest, 0x80 | '`');
+ if (!add_till_backquote(&dest, &input,
+ /*in_dquote:*/ dest.o_expflags /* nonzero if EXP_FLAG_ESC_GLOB_CHARS set */
+ )
+ ) {
+ goto ret; /* error */
+ }
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ //debug_printf_subst("SUBST RES3 '%s'\n", dest->data + pos);
+ continue;
+ }
+#endif
+ o_addQchr(&dest, ch);
+ } /* for (;;) */
+
+ debug_printf_parse("encode: '%s' -> '%s'\n", str, dest.data);
+ exp_str = expand_string_to_string(dest.data,
+ do_unbackslash ? EXP_FLAG_ESC_GLOB_CHARS : 0,
+ do_unbackslash
+ );
+ ret:
+ debug_printf_parse("expand: '%s' -> '%s'\n", dest.data, exp_str);
+ o_free(&dest);
+ return exp_str;
+}
+
+/* Expanding ARG in ${var+ARG}, ${var-ARG}
+ */
+static NOINLINE int encode_then_append_var_plusminus(o_string *output, int n,
+ char *str, int dquoted)
+{
+ struct in_str input;
+ o_string dest = NULL_O_STRING;
+
+ if (!first_special_char_in_vararg(str)
+ && '\0' == str[strcspn(str, G.ifs)]
+ ) {
+ /* string has no special chars
+ * && string has no $IFS chars
+ */
+ if (dquoted) {
+ /* Prints 1 (quoted expansion is a "" word, not nothing):
+ * set -- "${notexist-}"; echo $#
+ */
+ output->has_quoted_part = 1;
+ }
+ return expand_vars_to_list(output, n, str);
+ }
+
+ setup_string_in_str(&input, str);
+
+ for (;;) {
+ int ch;
+
+ ch = i_getch(&input);
+ debug_printf_parse("%s: ch=%c (%d) escape=%x\n",
+ __func__, ch, ch, dest.o_expflags);
+
+ if (!dest.o_expflags) {
+ if (ch == EOF)
+ break;
+ if (!dquoted && !(output->o_expflags & EXP_FLAG_SINGLEWORD) && strchr(G.ifs, ch)) {
+ /* PREFIX${x:d${e}f ...} and we met space: expand "d${e}f" and start new word.
+ * do not assume we are at the start of the word (PREFIX above).
+ */
+ if (dest.data) {
+ n = expand_vars_to_list(output, n, dest.data);
+ o_free_and_set_NULL(&dest);
+ o_addchr(output, '\0');
+ n = o_save_ptr(output, n); /* create next word */
+ } else
+ if (output->length != o_get_last_ptr(output, n)
+ || output->has_quoted_part
+ ) {
+ /* For these cases:
+ * f() { for i; do echo "|$i|"; done; }; x=x
+ * f a${x:+ }b # 1st condition
+ * |a|
+ * |b|
+ * f ""${x:+ }b # 2nd condition
+ * ||
+ * |b|
+ */
+ o_addchr(output, '\0');
+ n = o_save_ptr(output, n); /* create next word */
+ }
+ continue;
+ }
+ if (!dquoted && ch == '\'') {
+ if (!add_till_single_quote_dquoted(&dest, &input))
+ goto ret; /* error */
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ continue;
+ }
+ }
+ if (ch == EOF) {
+ syntax_error_unterm_ch('"');
+ goto ret; /* error */
+ }
+ if (ch == '"') {
+ dest.o_expflags ^= EXP_FLAG_ESC_GLOB_CHARS;
+ if (dest.o_expflags) {
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ }
+ continue;
+ }
+ if (ch == '\\') {
+ ch = i_getch(&input);
+ if (ch == EOF) {
+//example? error message? syntax_error_unterm_ch('"');
+ debug_printf_parse("%s: error: \\<eof>\n", __func__);
+ goto ret;
+ }
+ o_addqchr(&dest, ch);
+ continue;
+ }
+ if (ch == '$') {
+ if (!parse_dollar(NULL, &dest, &input, /*quote_mask:*/ (dest.o_expflags || dquoted) ? 0x80 : 0)) {
+ debug_printf_parse("%s: error: parse_dollar returned 0 (error)\n", __func__);
+ goto ret;
+ }
+ continue;
+ }
+#if ENABLE_HUSH_TICK
+ if (ch == '`') {
+ //unsigned pos = dest->length;
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ o_addchr(&dest, (dest.o_expflags || dquoted) ? 0x80 | '`' : '`');
+ if (!add_till_backquote(&dest, &input,
+ /*in_dquote:*/ dest.o_expflags /* nonzero if EXP_FLAG_ESC_GLOB_CHARS set */
+ )
+ ) {
+ goto ret; /* error */
+ }
+ o_addchr(&dest, SPECIAL_VAR_SYMBOL);
+ //debug_printf_subst("SUBST RES3 '%s'\n", dest->data + pos);
+ continue;
+ }
+#endif
+ if (dquoted) {
+ /* Always glob-protect if in dquotes:
+ * x=x; echo "${x:+/bin/c*}" - prints: /bin/c*
+ * x=x; echo "${x:+"/bin/c*"}" - prints: /bin/c*
+ */
+ o_addqchr(&dest, ch);
+ } else {
+ /* Glob-protect only if char is quoted:
+ * x=x; echo ${x:+/bin/c*} - prints many filenames
+ * x=x; echo ${x:+"/bin/c*"} - prints: /bin/c*
+ */
+ o_addQchr(&dest, ch);
+ }
+ } /* for (;;) */
+
+ if (dest.data) {
+ n = expand_vars_to_list(output, n, dest.data);
+ }
+ ret:
+ o_free(&dest);
+ return n;
+}
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+#if ENABLE_FEATURE_SH_MATH
+static arith_t expand_and_evaluate_arith(const char *arg, const char **errmsg_p)
+{
+ arith_state_t math_state;
+ arith_t res;
+ char *exp_str;
+
+ math_state.lookupvar = get_local_var_value;
+ math_state.setvar = set_local_var_from_halves;
+ //math_state.endofname = endofname;
+ exp_str = encode_then_expand_string(arg);
+ res = arith(&math_state, exp_str ? exp_str : arg);
+ free(exp_str);
+ if (errmsg_p)
+ *errmsg_p = math_state.errmsg;
+ if (math_state.errmsg)
+ msg_and_die_if_script(math_state.errmsg);
+ return res;
+}
+#endif
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+#if BASH_PATTERN_SUBST
+/* ${var/[/]pattern[/repl]} helpers */
+static char *strstr_pattern(char *val, const char *pattern, int *size)
+{
+ int first_escaped = (pattern[0] == '\\' && pattern[1]);
+ /* "first_escaped" trick allows to treat e.g. "\*no_glob_chars"
+ * as literal too (as it is semi-common, and easy to accomodate
+ * by just using str + 1).
+ */
+ int sz = strcspn(pattern + first_escaped * 2, "*?[\\");
+ if ((pattern + first_escaped * 2)[sz] == '\0') {
+ /* Optimization for trivial patterns.
+ * Testcase for very slow replace (performs about 22k replaces):
+ * x=::::::::::::::::::::::
+ * x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;x=$x$x;echo ${#x}
+ * echo "${x//:/|}"
+ */
+ *size = sz + first_escaped;
+ return strstr(val, pattern + first_escaped);
+ }
+
+ while (1) {
+ char *end = scan_and_match(val, pattern, SCAN_MOVE_FROM_RIGHT + SCAN_MATCH_LEFT_HALF);
+ debug_printf_varexp("val:'%s' pattern:'%s' end:'%s'\n", val, pattern, end);
+ if (end) {
+ *size = end - val;
+ return val;
+ }
+ if (*val == '\0')
+ return NULL;
+ /* Optimization: if "*pat" did not match the start of "string",
+ * we know that "tring", "ring" etc will not match too:
+ */
+ if (pattern[0] == '*')
+ return NULL;
+ val++;
+ }
+}
+static char *replace_pattern(char *val, const char *pattern, const char *repl, char exp_op)
+{
+ char *result = NULL;
+ unsigned res_len = 0;
+ unsigned repl_len = strlen(repl);
+
+ /* Null pattern never matches, including if "var" is empty */
+ if (!pattern[0])
+ return result; /* NULL, no replaces happened */
+
+ while (1) {
+ int size;
+ char *s = strstr_pattern(val, pattern, &size);
+ if (!s)
+ break;
+
+ result = xrealloc(result, res_len + (s - val) + repl_len + 1);
+ strcpy(mempcpy(result + res_len, val, s - val), repl);
+ res_len += (s - val) + repl_len;
+ debug_printf_varexp("val:'%s' s:'%s' result:'%s'\n", val, s, result);
+
+ val = s + size;
+ if (exp_op == '/')
+ break;
+ }
+ if (*val && result) {
+ result = xrealloc(result, res_len + strlen(val) + 1);
+ strcpy(result + res_len, val);
+ debug_printf_varexp("val:'%s' result:'%s'\n", val, result);
+ }
+ debug_printf_varexp("result:'%s'\n", result);
+ return result;
+}
+#endif /* BASH_PATTERN_SUBST */
+#endif /* !__U_BOOT__ */
+
+static int append_str_maybe_ifs_split(o_string *output, int n,
+ int first_ch, const char *val)
+{
+ if (!(first_ch & 0x80)) { /* unquoted $VAR */
+ debug_printf_expand("unquoted '%s', output->o_escape:%d\n", val,
+ !!(output->o_expflags & EXP_FLAG_ESC_GLOB_CHARS));
+ if (val && val[0])
+ n = expand_on_ifs(output, n, val);
+ } else { /* quoted "$VAR" */
+ output->has_quoted_part = 1;
+ debug_printf_expand("quoted '%s', output->o_escape:%d\n", val,
+ !!(output->o_expflags & EXP_FLAG_ESC_GLOB_CHARS));
+ if (val && val[0])
+ o_addQstr(output, val);
+ }
+ return n;
+}
+
+/* Handle <SPECIAL_VAR_SYMBOL>varname...<SPECIAL_VAR_SYMBOL> construct.
+ */
+static NOINLINE int expand_one_var(o_string *output, int n,
+ int first_ch, char *arg, char **pp)
+{
+ const char *val;
+ char *to_be_freed;
+ char *p;
+ char *var;
+ char exp_op;
+ char exp_save = exp_save; /* for compiler */
+ char *exp_saveptr; /* points to expansion operator */
+ char *exp_word = exp_word; /* for compiler */
+ char arg0;
+
+ val = NULL;
+ to_be_freed = NULL;
+ p = *pp;
+ *p = '\0'; /* replace trailing SPECIAL_VAR_SYMBOL */
+ var = arg;
+ exp_saveptr = arg[1] ? strchr(VAR_ENCODED_SUBST_OPS, arg[1]) : NULL;
+ arg0 = arg[0];
+ arg[0] = (arg0 & 0x7f);
+ exp_op = 0;
+
+ if (arg[0] == '#' && arg[1] /* ${#...} but not ${#} */
+ && (!exp_saveptr /* and ( not(${#<op_char>...}) */
+ || (arg[2] == '\0' && strchr(SPECIAL_VARS_STR, arg[1])) /* or ${#C} "len of $C" ) */
+ ) /* NB: skipping ^^^specvar check mishandles ${#::2} */
+ ) {
+ /* It must be length operator: ${#var} */
+ var++;
+ exp_op = 'L';
+ } else {
+ /* Maybe handle parameter expansion */
+ if (exp_saveptr /* if 2nd char is one of expansion operators */
+ && strchr(NUMERIC_SPECVARS_STR, arg[0]) /* 1st char is special variable */
+ ) {
+ /* ${?:0}, ${#[:]%0} etc */
+ exp_saveptr = var + 1;
+ } else {
+ /* ${?}, ${var}, ${var:0}, ${var[:]%0} etc */
+ exp_saveptr = var+1 + strcspn(var+1, VAR_ENCODED_SUBST_OPS);
+ }
+ exp_op = exp_save = *exp_saveptr;
+#ifndef __U_BOOT__
+ if (exp_op) {
+ exp_word = exp_saveptr + 1;
+ if (exp_op == ':') {
+ exp_op = *exp_word++;
+//TODO: try ${var:} and ${var:bogus} in non-bash config
+ if (BASH_SUBSTR
+ && (!exp_op || !strchr(MINUS_PLUS_EQUAL_QUESTION, exp_op))
+ ) {
+ /* oops... it's ${var:N[:M]}, not ${var:?xxx} or some such */
+ exp_op = ':';
+ exp_word--;
+ }
+ }
+ *exp_saveptr = '\0';
+ } /* else: it's not an expansion op, but bare ${var} */
+#endif /* !__U_BOOT__ */
+ }
+
+ /* Look up the variable in question */
+ if (isdigit(var[0])) {
+ /* parse_dollar should have vetted var for us */
+#ifndef __U_BOOT__
+ int nn = xatoi_positive(var);
+#else /* __U_BOOT__ */
+ int nn = simple_strtoul(var, NULL, 10);
+#endif /* __U_BOOT__ */
+ if (nn < G.global_argc)
+ val = G.global_argv[nn];
+ /* else val remains NULL: $N with too big N */
+ } else {
+ switch (var[0]) {
+#ifndef __U_BOOT__
+ case '$': /* pid */
+ val = utoa(G.root_pid);
+ break;
+ case '!': /* bg pid */
+ val = G.last_bg_pid ? utoa(G.last_bg_pid) : "";
+ break;
+#endif /* !__U_BOOT__ */
+ case '?': /* exitcode */
+ val = utoa(G.last_exitcode);
+ break;
+ case '#': /* argc */
+ val = utoa(G.global_argc ? G.global_argc-1 : 0);
+ break;
+#ifndef __U_BOOT__
+ case '-': { /* active options */
+ /* Check set_mode() to see what option chars we support */
+ char *cp;
+ val = cp = G.optstring_buf;
+ if (G.o_opt[OPT_O_ERREXIT])
+ *cp++ = 'e';
+ if (G_interactive_fd)
+ *cp++ = 'i';
+ if (G_x_mode)
+ *cp++ = 'x';
+ /* If G.o_opt[OPT_O_NOEXEC] is true,
+ * commands read but are not executed,
+ * so $- can not execute too, 'n' is never seen in $-.
+ */
+ if (G.opt_c)
+ *cp++ = 'c';
+ if (G.opt_s)
+ *cp++ = 's';
+ *cp = '\0';
+ break;
+ }
+#endif /* !__U_BOOT__ */
+ default:
+#ifndef __U_BOOT__
+ val = get_local_var_value(var);
+#else /* __U_BOOT__ */
+ /*
+ * Environment variable set with setenv* have to be
+ * expanded.
+ * So, we first search if the variable exists in
+ * environment, if this is not the case, we default to
+ * local value.
+ */
+ val = env_get(var);
+ if (!val)
+ val = get_local_var_value(var);
+#endif /* __U_BOOT__ */
+ }
+ }
+
+#ifndef __U_BOOT__
+ /* Handle any expansions */
+ if (exp_op == 'L') {
+ reinit_unicode_for_hush();
+ debug_printf_expand("expand: length(%s)=", val);
+ val = utoa(val ? unicode_strlen(val) : 0);
+ debug_printf_expand("%s\n", val);
+ } else if (exp_op) {
+ if (exp_op == '%' || exp_op == '#') {
+ /* Standard-mandated substring removal ops:
+ * ${parameter%word} - remove smallest suffix pattern
+ * ${parameter%%word} - remove largest suffix pattern
+ * ${parameter#word} - remove smallest prefix pattern
+ * ${parameter##word} - remove largest prefix pattern
+ *
+ * Word is expanded to produce a glob pattern.
+ * Then var's value is matched to it and matching part removed.
+ */
+ /* bash compat: if x is "" and no shrinking of it is possible,
+ * inner ${...} is not evaluated. Example:
+ * unset b; : ${a%${b=B}}; echo $b
+ * assignment b=B only happens if $a is not "".
+ */
+ if (val && val[0]) {
+ char *t;
+ char *exp_exp_word;
+ char *loc;
+ unsigned scan_flags = pick_scan(exp_op, *exp_word);
+ if (exp_op == *exp_word) /* ## or %% */
+ exp_word++;
+ debug_printf_expand("expand: exp_word:'%s'\n", exp_word);
+ exp_exp_word = encode_then_expand_vararg(exp_word, /*handle_squotes:*/ 1, /*unbackslash:*/ 0);
+ if (exp_exp_word)
+ exp_word = exp_exp_word;
+ debug_printf_expand("expand: exp_word:'%s'\n", exp_word);
+ /*
+ * HACK ALERT. We depend here on the fact that
+ * G.global_argv and results of utoa and get_local_var_value
+ * are actually in writable memory:
+ * scan_and_match momentarily stores NULs there.
+ */
+ t = (char*)val;
+ loc = scan_and_match(t, exp_word, scan_flags);
+ debug_printf_expand("op:%c str:'%s' pat:'%s' res:'%s'\n", exp_op, t, exp_word, loc);
+ free(exp_exp_word);
+ if (loc) { /* match was found */
+ if (scan_flags & SCAN_MATCH_LEFT_HALF) /* #[#] */
+ val = loc; /* take right part */
+ else /* %[%] */
+ val = to_be_freed = xstrndup(val, loc - val); /* left */
+ }
+ }
+ }
+#if BASH_PATTERN_SUBST
+ else if (exp_op == '/' || exp_op == '\\') {
+ /* It's ${var/[/]pattern[/repl]} thing.
+ * Note that in encoded form it has TWO parts:
+ * var/pattern<SPECIAL_VAR_SYMBOL>repl<SPECIAL_VAR_SYMBOL>
+ * and if // is used, it is encoded as \:
+ * var\pattern<SPECIAL_VAR_SYMBOL>repl<SPECIAL_VAR_SYMBOL>
+ */
+ /* bash compat: if var is "", both pattern and repl
+ * are still evaluated, if it is unset, then not:
+ * unset b; a=; : ${a/z/${b=3}}; echo $b # b=3
+ * unset b; unset a; : ${a/z/${b=3}}; echo $b # b not set
+ */
+ if (val /*&& val[0]*/) {
+ /* pattern uses non-standard expansion.
+ * repl should be unbackslashed and globbed
+ * by the usual expansion rules:
+ * >az >bz
+ * v='a bz'; echo "${v/a*z/a*z}" #prints "a*z"
+ * v='a bz'; echo "${v/a*z/\z}" #prints "z"
+ * v='a bz'; echo ${v/a*z/a*z} #prints "az"
+ * v='a bz'; echo ${v/a*z/\z} #prints "z"
+ * (note that a*z _pattern_ is never globbed!)
+ */
+ char *pattern, *repl, *t;
+ pattern = encode_then_expand_vararg(exp_word, /*handle_squotes:*/ 1, /*unbackslash:*/ 0);
+ if (!pattern)
+ pattern = xstrdup(exp_word);
+ debug_printf_varexp("pattern:'%s'->'%s'\n", exp_word, pattern);
+ *p++ = SPECIAL_VAR_SYMBOL;
+ exp_word = p;
+ p = strchr(p, SPECIAL_VAR_SYMBOL);
+ *p = '\0';
+ repl = encode_then_expand_vararg(exp_word, /*handle_squotes:*/ 1, /*unbackslash:*/ 1);
+ debug_printf_varexp("repl:'%s'->'%s'\n", exp_word, repl);
+ /* HACK ALERT. We depend here on the fact that
+ * G.global_argv and results of utoa and get_local_var_value
+ * are actually in writable memory:
+ * replace_pattern momentarily stores NULs there. */
+ t = (char*)val;
+ to_be_freed = replace_pattern(t,
+ pattern,
+ (repl ? repl : exp_word),
+ exp_op);
+ if (to_be_freed) /* at least one replace happened */
+ val = to_be_freed;
+ free(pattern);
+ free(repl);
+ } else {
+ /* Unset variable always gives nothing */
+ // a=; echo ${a/*/w} # "w"
+ // unset a; echo ${a/*/w} # ""
+ /* Just skip "replace" part */
+ *p++ = SPECIAL_VAR_SYMBOL;
+ p = strchr(p, SPECIAL_VAR_SYMBOL);
+ *p = '\0';
+ }
+ }
+#endif /* BASH_PATTERN_SUBST */
+ else if (exp_op == ':') {
+#if BASH_SUBSTR && ENABLE_FEATURE_SH_MATH
+ /* It's ${var:N[:M]} bashism.
+ * Note that in encoded form it has TWO parts:
+ * var:N<SPECIAL_VAR_SYMBOL>M<SPECIAL_VAR_SYMBOL>
+ */
+ arith_t beg, len;
+ unsigned vallen;
+ const char *errmsg;
+
+ beg = expand_and_evaluate_arith(exp_word, &errmsg);
+ if (errmsg)
+ goto empty_result;
+ debug_printf_varexp("beg:'%s'=%lld\n", exp_word, (long long)beg);
+ *p++ = SPECIAL_VAR_SYMBOL;
+ exp_word = p;
+ p = strchr(p, SPECIAL_VAR_SYMBOL);
+ *p = '\0';
+ vallen = val ? strlen(val) : 0;
+ if (beg < 0) {
+ /* negative beg counts from the end */
+ beg = (arith_t)vallen + beg;
+ }
+ /* If expansion will be empty, do not even evaluate len */
+ if (!val || beg < 0 || beg > vallen) {
+ /* Why > vallen, not >=? bash:
+ * unset b; a=ab; : ${a:2:${b=3}}; echo $b # "", b=3 (!!!)
+ * unset b; a=a; : ${a:2:${b=3}}; echo $b # "", b not set
+ */
+ goto empty_result;
+ }
+ len = expand_and_evaluate_arith(exp_word, &errmsg);
+ if (errmsg)
+ goto empty_result;
+ debug_printf_varexp("len:'%s'=%lld\n", exp_word, (long long)len);
+ debug_printf_varexp("from val:'%s'\n", val);
+ if (len < 0) {
+ /* in bash, len=-n means strlen()-n */
+ len = (arith_t)vallen - beg + len;
+ if (len < 0) /* bash compat */
+ msg_and_die_if_script("%s: substring expression < 0", var);
+ }
+ if (len <= 0 || !val /*|| beg >= vallen*/) {
+ empty_result:
+ val = NULL;
+ } else {
+ /* Paranoia. What if user entered 9999999999999
+ * which fits in arith_t but not int? */
+ if (len > INT_MAX)
+ len = INT_MAX;
+ val = to_be_freed = xstrndup(val + beg, len);
+ }
+ debug_printf_varexp("val:'%s'\n", val);
+#else /* not (HUSH_SUBSTR_EXPANSION && FEATURE_SH_MATH) */
+ msg_and_die_if_script("malformed ${%s:...}", var);
+ val = NULL;
+#endif
+ } else { /* one of "-=+?" */
+ /* Standard-mandated substitution ops:
+ * ${var?word} - indicate error if unset
+ * If var is unset, word (or a message indicating it is unset
+ * if word is null) is written to standard error
+ * and the shell exits with a non-zero exit status.
+ * Otherwise, the value of var is substituted.
+ * ${var-word} - use default value
+ * If var is unset, word is substituted.
+ * ${var=word} - assign and use default value
+ * If var is unset, word is assigned to var.
+ * In all cases, final value of var is substituted.
+ * ${var+word} - use alternative value
+ * If var is unset, null is substituted.
+ * Otherwise, word is substituted.
+ *
+ * Word is subjected to tilde expansion, parameter expansion,
+ * command substitution, and arithmetic expansion.
+ * If word is not needed, it is not expanded.
+ *
+ * Colon forms (${var:-word}, ${var:=word} etc) do the same,
+ * but also treat null var as if it is unset.
+ *
+ * Word-splitting and single quote behavior:
+ *
+ * $ f() { for i; do echo "|$i|"; done; }
+ *
+ * $ x=; f ${x:?'x y' z}; echo $?
+ * bash: x: x y z # neither f nor "echo $?" executes
+ * (if interactive, bash does not exit, but merely aborts to prompt. $? is set to 1)
+ * $ x=; f "${x:?'x y' z}"
+ * bash: x: x y z # dash prints: dash: x: 'x y' z
+ *
+ * $ x=; f ${x:='x y' z}
+ * |x|
+ * |y|
+ * |z|
+ * $ x=; f "${x:='x y' z}"
+ * |'x y' z|
+ *
+ * $ x=x; f ${x:+'x y' z}
+ * |x y|
+ * |z|
+ * $ x=x; f "${x:+'x y' z}"
+ * |'x y' z|
+ *
+ * $ x=; f ${x:-'x y' z}
+ * |x y|
+ * |z|
+ * $ x=; f "${x:-'x y' z}"
+ * |'x y' z|
+ */
+ int use_word = (!val || ((exp_save == ':') && !val[0]));
+ if (exp_op == '+')
+ use_word = !use_word;
+ debug_printf_expand("expand: op:%c (null:%s) test:%i\n", exp_op,
+ (exp_save == ':') ? "true" : "false", use_word);
+ if (use_word) {
+ if (exp_op == '+' || exp_op == '-') {
+ /* ${var+word} - use alternative value */
+ /* ${var-word} - use default value */
+ n = encode_then_append_var_plusminus(output, n, exp_word,
+ /*dquoted:*/ (arg0 & 0x80)
+ );
+ val = NULL;
+ } else {
+ /* ${var?word} - indicate error if unset */
+ /* ${var=word} - assign and use default value */
+ to_be_freed = encode_then_expand_vararg(exp_word,
+ /*handle_squotes:*/ !(arg0 & 0x80),
+ /*unbackslash:*/ 0
+ );
+ if (to_be_freed)
+ exp_word = to_be_freed;
+ if (exp_op == '?') {
+ /* mimic bash message */
+ msg_and_die_if_script("%s: %s",
+ var,
+ exp_word[0]
+ ? exp_word
+ : "parameter null or not set"
+ /* ash has more specific messages, a-la: */
+ /*: (exp_save == ':' ? "parameter null or not set" : "parameter not set")*/
+ );
+//TODO: how interactive bash aborts expansion mid-command?
+//It aborts the entire line, returns to prompt:
+// $ f() { for i; do echo "|$i|"; done; }; x=; f "${x:?'x y' z}"; echo YO
+// bash: x: x y z
+// $
+// ("echo YO" is not executed, neither the f function call)
+ } else {
+ val = exp_word;
+ }
+ if (exp_op == '=') {
+ /* ${var=[word]} or ${var:=[word]} */
+ if (isdigit(var[0]) || var[0] == '#') {
+ /* mimic bash message */
+ msg_and_die_if_script("$%s: cannot assign in this way", var);
+ val = NULL;
+ } else {
+ char *new_var = xasprintf("%s=%s", var, val);
+ set_local_var0(new_var);
+ }
+ }
+ }
+ }
+ } /* one of "-=+?" */
+
+ *exp_saveptr = exp_save;
+ } /* if (exp_op) */
+
+#endif /* !__U_BOOT__ */
+ arg[0] = arg0;
+ *pp = p;
+
+ n = append_str_maybe_ifs_split(output, n, first_ch, val);
+
+ free(to_be_freed);
+ return n;
+}
+
+/* Expand all variable references in given string, adding words to list[]
+ * at n, n+1,... positions. Return updated n (so that list[n] is next one
+ * to be filled). This routine is extremely tricky: has to deal with
+ * variables/parameters with whitespace, $* and $@, and constructs like
+ * 'echo -$*-'. If you play here, you must run testsuite afterwards! */
+static NOINLINE int expand_vars_to_list(o_string *output, int n, char *arg)
+{
+ /* output->o_expflags & EXP_FLAG_SINGLEWORD (0x80) if we are in
+ * expansion of right-hand side of assignment == 1-element expand.
+ */
+ char cant_be_null = 0; /* only bit 0x80 matters */
+ char *p;
+
+ debug_printf_expand("expand_vars_to_list: arg:'%s' singleword:%x\n", arg,
+ !!(output->o_expflags & EXP_FLAG_SINGLEWORD));
+ debug_print_list("expand_vars_to_list[0]", output, n);
+
+ while ((p = strchr(arg, SPECIAL_VAR_SYMBOL)) != NULL) {
+ char first_ch;
+#if ENABLE_FEATURE_SH_MATH
+ char arith_buf[sizeof(arith_t)*3 + 2];
+#endif
+
+ if (output->ended_in_ifs) {
+ o_addchr(output, '\0');
+ n = o_save_ptr(output, n);
+ output->ended_in_ifs = 0;
+ }
+
+ o_addblock(output, arg, p - arg);
+ debug_print_list("expand_vars_to_list[1]", output, n);
+ arg = ++p;
+ p = strchr(p, SPECIAL_VAR_SYMBOL);
+
+ /* Fetch special var name (if it is indeed one of them)
+ * and quote bit, force the bit on if singleword expansion -
+ * important for not getting v=$@ expand to many words. */
+ first_ch = arg[0] | (output->o_expflags & EXP_FLAG_SINGLEWORD);
+
+ /* Is this variable quoted and thus expansion can't be null?
+ * "$@" is special. Even if quoted, it can still
+ * expand to nothing (not even an empty string),
+ * thus it is excluded. */
+ if ((first_ch & 0x7f) != '@')
+ cant_be_null |= first_ch;
+
+ switch (first_ch & 0x7f) {
+ /* Highest bit in first_ch indicates that var is double-quoted */
+ case '*':
+ case '@': {
+ int i;
+#ifndef __U_BOOT__
+ if (!G.global_argv[1])
+#else /* __U_BOOT__ */
+ if (!G.global_argv || !G.global_argv[1])
+#endif /* __U_BOOT__ */
+ break;
+ i = 1;
+ cant_be_null |= first_ch; /* do it for "$@" _now_, when we know it's not empty */
+ if (!(first_ch & 0x80)) { /* unquoted $* or $@ */
+ while (G.global_argv[i]) {
+ n = expand_on_ifs(output, n, G.global_argv[i]);
+ debug_printf_expand("expand_vars_to_list: argv %d (last %d)\n", i, G.global_argc - 1);
+ if (G.global_argv[i++][0] && G.global_argv[i]) {
+ /* this argv[] is not empty and not last:
+ * put terminating NUL, start new word */
+ o_addchr(output, '\0');
+ debug_print_list("expand_vars_to_list[2]", output, n);
+ n = o_save_ptr(output, n);
+ debug_print_list("expand_vars_to_list[3]", output, n);
+ }
+ }
+ } else
+ /* If EXP_FLAG_SINGLEWORD, we handle assignment 'a=....$@.....'
+ * and in this case should treat it like '$*' - see 'else...' below */
+ if (first_ch == (char)('@'|0x80) /* quoted $@ */
+ && !(output->o_expflags & EXP_FLAG_SINGLEWORD) /* not v="$@" case */
+ ) {
+ while (1) {
+ o_addQstr(output, G.global_argv[i]);
+ if (++i >= G.global_argc)
+ break;
+ o_addchr(output, '\0');
+ debug_print_list("expand_vars_to_list[4]", output, n);
+ n = o_save_ptr(output, n);
+ }
+ } else { /* quoted $* (or v="$@" case): add as one word */
+ while (1) {
+ o_addQstr(output, G.global_argv[i]);
+ if (!G.global_argv[++i])
+ break;
+ if (G.ifs[0])
+ o_addchr(output, G.ifs[0]);
+ }
+ output->has_quoted_part = 1;
+ }
+ break;
+ }
+ case SPECIAL_VAR_SYMBOL: {
+ /* <SPECIAL_VAR_SYMBOL><SPECIAL_VAR_SYMBOL> */
+ /* "Empty variable", used to make "" etc to not disappear */
+ output->has_quoted_part = 1;
+ cant_be_null = 0x80;
+ arg++;
+ break;
+ }
+ case SPECIAL_VAR_QUOTED_SVS:
+ /* <SPECIAL_VAR_SYMBOL><SPECIAL_VAR_QUOTED_SVS><SPECIAL_VAR_SYMBOL> */
+ /* "^C variable", represents literal ^C char (possible in scripts) */
+ o_addchr(output, SPECIAL_VAR_SYMBOL);
+ arg++;
+ break;
+#if ENABLE_HUSH_TICK
+ case '`': {
+ /* <SPECIAL_VAR_SYMBOL>`cmd<SPECIAL_VAR_SYMBOL> */
+ o_string subst_result = NULL_O_STRING;
+
+ *p = '\0'; /* replace trailing <SPECIAL_VAR_SYMBOL> */
+ arg++;
+ /* Can't just stuff it into output o_string,
+ * expanded result may need to be globbed
+ * and $IFS-split */
+ debug_printf_subst("SUBST '%s' first_ch %x\n", arg, first_ch);
+ G.last_exitcode = process_command_subs(&subst_result, arg);
+ G.expand_exitcode = G.last_exitcode;
+ debug_printf_subst("SUBST RES:%d '%s'\n", G.last_exitcode, subst_result.data);
+ n = append_str_maybe_ifs_split(output, n, first_ch, subst_result.data);
+ o_free(&subst_result);
+ break;
+ }
+#endif
+#if ENABLE_FEATURE_SH_MATH
+ case '+': {
+ /* <SPECIAL_VAR_SYMBOL>+arith<SPECIAL_VAR_SYMBOL> */
+ arith_t res;
+
+ arg++; /* skip '+' */
+ *p = '\0'; /* replace trailing <SPECIAL_VAR_SYMBOL> */
+ debug_printf_subst("ARITH '%s' first_ch %x\n", arg, first_ch);
+ res = expand_and_evaluate_arith(arg, NULL);
+ debug_printf_subst("ARITH RES '"ARITH_FMT"'\n", res);
+ sprintf(arith_buf, ARITH_FMT, res);
+ if (res < 0
+ && first_ch == (char)('+'|0x80)
+ /* && (output->o_expflags & EXP_FLAG_ESC_GLOB_CHARS) */
+ ) {
+ /* Quoted negative ariths, like filename[0"$((-9))"],
+ * should not be interpreted as glob ranges.
+ * Convert leading '-' to '\-':
+ */
+ o_grow_by(output, 1);
+ output->data[output->length++] = '\\';
+ }
+ o_addstr(output, arith_buf);
+ break;
+ }
+#endif
+ default:
+ /* <SPECIAL_VAR_SYMBOL>varname[ops]<SPECIAL_VAR_SYMBOL> */
+ n = expand_one_var(output, n, first_ch, arg, &p);
+ break;
+ } /* switch (char after <SPECIAL_VAR_SYMBOL>) */
+
+ /* Restore NULL'ed SPECIAL_VAR_SYMBOL.
+ * Do the check to avoid writing to a const string. */
+ if (*p != SPECIAL_VAR_SYMBOL)
+ *p = SPECIAL_VAR_SYMBOL;
+ arg = ++p;
+ } /* end of "while (SPECIAL_VAR_SYMBOL is found) ..." */
+
+ if (*arg) {
+ /* handle trailing string */
+ if (output->ended_in_ifs) {
+ o_addchr(output, '\0');
+ n = o_save_ptr(output, n);
+ }
+ debug_print_list("expand_vars_to_list[a]", output, n);
+ /* this part is literal, and it was already pre-quoted
+ * if needed (much earlier), do not use o_addQstr here!
+ */
+ o_addstr(output, arg);
+ debug_print_list("expand_vars_to_list[b]", output, n);
+ } else
+ if (output->length == o_get_last_ptr(output, n) /* expansion is empty */
+ && !(cant_be_null & 0x80) /* and all vars were not quoted */
+ && !output->has_quoted_part
+ ) {
+ n--;
+ /* allow to reuse list[n] later without re-growth */
+ output->has_empty_slot = 1;
+ }
+
+ return n;
+}
+
+static char **expand_variables(char **argv, unsigned expflags)
+{
+ int n;
+ char **list;
+ o_string output = NULL_O_STRING;
+
+ output.o_expflags = expflags;
+
+ n = 0;
+ for (;;) {
+ /* go to next list[n] */
+ output.ended_in_ifs = 0;
+ n = o_save_ptr(&output, n);
+
+ if (!*argv)
+ break;
+
+ /* expand argv[i] */
+ n = expand_vars_to_list(&output, n, *argv++);
+ /* if (!output->has_empty_slot) -- need this?? */
+ o_addchr(&output, '\0');
+ }
+ debug_print_list("expand_variables", &output, n);
+
+ /* output.data (malloced in one block) gets returned in "list" */
+ list = o_finalize_list(&output, n);
+ debug_print_strings("expand_variables[1]", list);
+ return list;
+}
+
+static char **expand_strvec_to_strvec(char **argv)
+{
+ return expand_variables(argv, EXP_FLAG_GLOB | EXP_FLAG_ESC_GLOB_CHARS);
+}
+
+#if defined(CMD_SINGLEWORD_NOGLOB) || defined(CMD_TEST2_SINGLEWORD_NOGLOB)
+static char **expand_strvec_to_strvec_singleword_noglob(char **argv)
+{
+ return expand_variables(argv, EXP_FLAG_SINGLEWORD);
+}
+#endif
+
+/* Used for expansion of right hand of assignments,
+ * $((...)), heredocs, variable expansion parts.
+ *
+ * NB: should NOT do globbing!
+ * "export v=/bin/c*; env | grep ^v=" outputs "v=/bin/c*"
+ */
+static char *expand_string_to_string(const char *str, int EXP_flags, int do_unbackslash)
+{
+#if !BASH_PATTERN_SUBST && !ENABLE_HUSH_CASE
+ const int do_unbackslash = 1;
+ const int EXP_flags = EXP_FLAG_ESC_GLOB_CHARS;
+#endif
+ char *argv[2], **list;
+
+ debug_printf_expand("string_to_string<='%s'\n", str);
+ /* This is generally an optimization, but it also
+ * handles "", which otherwise trips over !list[0] check below.
+ * (is this ever happens that we actually get str="" here?)
+ */
+ if (!strchr(str, SPECIAL_VAR_SYMBOL) && !strchr(str, '\\')) {
+ //TODO: Can use on strings with \ too, just unbackslash() them?
+ debug_printf_expand("string_to_string(fast)=>'%s'\n", str);
+ return xstrdup(str);
+ }
+
+ argv[0] = (char*)str;
+ argv[1] = NULL;
+ list = expand_variables(argv, EXP_flags | EXP_FLAG_SINGLEWORD);
+ if (!list[0]) {
+ /* Example where it happens:
+ * x=; echo ${x:-"$@"}
+ */
+ ((char*)list)[0] = '\0';
+ } else {
+ if (HUSH_DEBUG)
+ if (list[1])
+ bb_simple_error_msg_and_die("BUG in varexp2");
+ /* actually, just move string 2*sizeof(char*) bytes back */
+ overlapping_strcpy((char*)list, list[0]);
+ if (do_unbackslash)
+ unbackslash((char*)list);
+ }
+ debug_printf_expand("string_to_string=>'%s'\n", (char*)list);
+ return (char*)list;
+}
+
+#if 0
+static char* expand_strvec_to_string(char **argv)
+{
+ char **list;
+
+ list = expand_variables(argv, EXP_FLAG_SINGLEWORD);
+ /* Convert all NULs to spaces */
+ if (list[0]) {
+ int n = 1;
+ while (list[n]) {
+ if (HUSH_DEBUG)
+ if (list[n-1] + strlen(list[n-1]) + 1 != list[n])
+ bb_error_msg_and_die("BUG in varexp3");
+ /* bash uses ' ' regardless of $IFS contents */
+ list[n][-1] = ' ';
+ n++;
+ }
+ }
+ overlapping_strcpy((char*)list, list[0] ? list[0] : "");
+ debug_printf_expand("strvec_to_string='%s'\n", (char*)list);
+ return (char*)list;
+}
+#endif
+
+#ifndef __U_BOOT__
+static char **expand_assignments(char **argv, int count)
+{
+ int i;
+ char **p;
+
+ G.expanded_assignments = p = NULL;
+ /* Expand assignments into one string each */
+ for (i = 0; i < count; i++) {
+ p = add_string_to_strings(p,
+ expand_string_to_string(argv[i],
+ EXP_FLAG_ESC_GLOB_CHARS,
+ /*unbackslash:*/ 1
+ )
+ );
+ G.expanded_assignments = p;
+ }
+ G.expanded_assignments = NULL;
+ return p;
+}
+
+
+static void switch_off_special_sigs(unsigned mask)
+{
+ unsigned sig = 0;
+ while ((mask >>= 1) != 0) {
+ sig++;
+ if (!(mask & 1))
+ continue;
+#if ENABLE_HUSH_TRAP
+ if (G_traps) {
+ if (G_traps[sig] && !G_traps[sig][0])
+ /* trap is '', has to remain SIG_IGN */
+ continue;
+ free(G_traps[sig]);
+ G_traps[sig] = NULL;
+ }
+#endif
+ /* We are here only if no trap or trap was not '' */
+ install_sighandler(sig, SIG_DFL);
+ }
+}
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+#if BB_MMU
+/* never called */
+void re_execute_shell(char ***to_free, const char *s,
+ char *g_argv0, char **g_argv,
+ char **builtin_argv) NORETURN;
+
+static void reset_traps_to_defaults(void)
+{
+ /* This function is always called in a child shell
+ * after fork (not vfork, NOMMU doesn't use this function).
+ */
+ IF_HUSH_TRAP(unsigned sig;)
+ unsigned mask;
+
+ /* Child shells are not interactive.
+ * SIGTTIN/SIGTTOU/SIGTSTP should not have special handling.
+ * Testcase: (while :; do :; done) + ^Z should background.
+ * Same goes for SIGTERM, SIGHUP, SIGINT.
+ */
+ mask = (G.special_sig_mask & SPECIAL_INTERACTIVE_SIGS) | G_fatal_sig_mask;
+ if (!G_traps && !mask)
+ return; /* already no traps and no special sigs */
+
+ /* Switch off special sigs */
+ switch_off_special_sigs(mask);
+# if ENABLE_HUSH_JOB
+ G_fatal_sig_mask = 0;
+# endif
+ G.special_sig_mask &= ~SPECIAL_INTERACTIVE_SIGS;
+ /* SIGQUIT,SIGCHLD and maybe SPECIAL_JOBSTOP_SIGS
+ * remain set in G.special_sig_mask */
+
+# if ENABLE_HUSH_TRAP
+ if (!G_traps)
+ return;
+
+ /* Reset all sigs to default except ones with empty traps */
+ for (sig = 0; sig < NSIG; sig++) {
+ if (!G_traps[sig])
+ continue; /* no trap: nothing to do */
+ if (!G_traps[sig][0])
+ continue; /* empty trap: has to remain SIG_IGN */
+ /* sig has non-empty trap, reset it: */
+ free(G_traps[sig]);
+ G_traps[sig] = NULL;
+ /* There is no signal for trap 0 (EXIT) */
+ if (sig == 0)
+ continue;
+ install_sighandler(sig, pick_sighandler(sig));
+ }
+# endif
+}
+
+#else /* !BB_MMU */
+
+static void re_execute_shell(char ***to_free, const char *s,
+ char *g_argv0, char **g_argv,
+ char **builtin_argv) NORETURN;
+static void re_execute_shell(char ***to_free, const char *s,
+ char *g_argv0, char **g_argv,
+ char **builtin_argv)
+{
+# define NOMMU_HACK_FMT ("-$%x:%x:%x:%x:%x:%llx" IF_HUSH_LOOPS(":%x"))
+ /* delims + 2 * (number of bytes in printed hex numbers) */
+ char param_buf[sizeof(NOMMU_HACK_FMT) + 2 * (sizeof(int)*6 + sizeof(long long)*1)];
+ char *heredoc_argv[4];
+ struct variable *cur;
+# if ENABLE_HUSH_FUNCTIONS
+ struct function *funcp;
+# endif
+ char **argv, **pp;
+ unsigned cnt;
+ unsigned long long empty_trap_mask;
+
+ if (!g_argv0) { /* heredoc */
+ argv = heredoc_argv;
+ argv[0] = (char *) G.argv0_for_re_execing;
+ argv[1] = (char *) "-<";
+ argv[2] = (char *) s;
+ argv[3] = NULL;
+ pp = &argv[3]; /* used as pointer to empty environment */
+ goto do_exec;
+ }
+
+ cnt = 0;
+ pp = builtin_argv;
+ if (pp) while (*pp++)
+ cnt++;
+
+ empty_trap_mask = 0;
+ if (G_traps) {
+ int sig;
+ for (sig = 1; sig < NSIG; sig++) {
+ if (G_traps[sig] && !G_traps[sig][0])
+ empty_trap_mask |= 1LL << sig;
+ }
+ }
+
+ sprintf(param_buf, NOMMU_HACK_FMT
+ , (unsigned) G.root_pid
+ , (unsigned) G.root_ppid
+ , (unsigned) G.last_bg_pid
+ , (unsigned) G.last_exitcode
+ , cnt
+ , empty_trap_mask
+ IF_HUSH_LOOPS(, G.depth_of_loop)
+ );
+# undef NOMMU_HACK_FMT
+ /* 1:hush 2:-$<pid>:<pid>:<exitcode>:<etc...> <vars...> <funcs...>
+ * 3:-c 4:<cmd> 5:<arg0> <argN...> 6:NULL
+ */
+ cnt += 6;
+ for (cur = G.top_var; cur; cur = cur->next) {
+ if (!cur->flg_export || cur->flg_read_only)
+ cnt += 2;
+ }
+# if ENABLE_HUSH_LINENO_VAR
+ cnt += 2;
+# endif
+# if ENABLE_HUSH_FUNCTIONS
+ for (funcp = G.top_func; funcp; funcp = funcp->next)
+ cnt += 3;
+# endif
+ pp = g_argv;
+ while (*pp++)
+ cnt++;
+ *to_free = argv = pp = xzalloc(sizeof(argv[0]) * cnt);
+ *pp++ = (char *) G.argv0_for_re_execing;
+ *pp++ = param_buf;
+ for (cur = G.top_var; cur; cur = cur->next) {
+ if (strcmp(cur->varstr, hush_version_str) == 0)
+ continue;
+ if (cur->flg_read_only) {
+ *pp++ = (char *) "-R";
+ *pp++ = cur->varstr;
+ } else if (!cur->flg_export) {
+ *pp++ = (char *) "-V";
+ *pp++ = cur->varstr;
+ }
+ }
+# if ENABLE_HUSH_LINENO_VAR
+ *pp++ = (char *) "-L";
+ *pp++ = utoa(G.execute_lineno);
+# endif
+# if ENABLE_HUSH_FUNCTIONS
+ for (funcp = G.top_func; funcp; funcp = funcp->next) {
+ *pp++ = (char *) "-F";
+ *pp++ = funcp->name;
+ *pp++ = funcp->body_as_string;
+ }
+# endif
+ /* We can pass activated traps here. Say, -Tnn:trap_string
+ *
+ * However, POSIX says that subshells reset signals with traps
+ * to SIG_DFL.
+ * I tested bash-3.2 and it not only does that with true subshells
+ * of the form ( list ), but with any forked children shells.
+ * I set trap "echo W" WINCH; and then tried:
+ *
+ * { echo 1; sleep 20; echo 2; } &
+ * while true; do echo 1; sleep 20; echo 2; break; done &
+ * true | { echo 1; sleep 20; echo 2; } | cat
+ *
+ * In all these cases sending SIGWINCH to the child shell
+ * did not run the trap. If I add trap "echo V" WINCH;
+ * _inside_ group (just before echo 1), it works.
+ *
+ * I conclude it means we don't need to pass active traps here.
+ */
+ *pp++ = (char *) "-c";
+ *pp++ = (char *) s;
+ if (builtin_argv) {
+ while (*++builtin_argv)
+ *pp++ = *builtin_argv;
+ *pp++ = (char *) "";
+ }
+ *pp++ = g_argv0;
+ while (*g_argv)
+ *pp++ = *g_argv++;
+ /* *pp = NULL; - is already there */
+ pp = environ;
+
+ do_exec:
+ debug_printf_exec("re_execute_shell pid:%d cmd:'%s'\n", getpid(), s);
+ /* Don't propagate SIG_IGN to the child */
+ if (SPECIAL_JOBSTOP_SIGS != 0)
+ switch_off_special_sigs(G.special_sig_mask & SPECIAL_JOBSTOP_SIGS);
+ execve(bb_busybox_exec_path, argv, pp);
+ /* Fallback. Useful for init=/bin/hush usage etc */
+ if (argv[0][0] == '/')
+ execve(argv[0], argv, pp);
+ xfunc_error_retval = 127;
+ bb_simple_error_msg_and_die("can't re-execute the shell");
+}
+#endif /* !BB_MMU */
+
+#endif /* !__U_BOOT__ */
+
+static int run_and_free_list(struct pipe *pi);
+
+/* Executing from string: eval, sh -c '...'
+ * or from file: /etc/profile, . file, sh <script>, sh (intereactive)
+ * end_trigger controls how often we stop parsing
+ * NUL: parse all, execute, return
+ * ';': parse till ';' or newline, execute, repeat till EOF
+ */
+#ifndef __U_BOOT__
+static void parse_and_run_stream(struct in_str *inp, int end_trigger)
+#else /* __U_BOOT__ */
+static int parse_and_run_stream(struct in_str *inp, int end_trigger)
+#endif /* __U_BOOT__ */
+{
+ /* Why we need empty flag?
+ * An obscure corner case "false; ``; echo $?":
+ * empty command in `` should still set $? to 0.
+ * But we can't just set $? to 0 at the start,
+ * this breaks "false; echo `echo $?`" case.
+ */
+ bool empty = 1;
+#ifndef __U_BOOT__
+ while (1) {
+#else /* __U_BOOT__ */
+ do {
+#endif /* __U_BOOT__ */
+ struct pipe *pipe_list;
+
+#if ENABLE_HUSH_INTERACTIVE
+ if (end_trigger == ';') {
+ G.promptmode = 0; /* PS1 */
+ debug_printf_prompt("%s promptmode=%d\n", __func__, G.promptmode);
+ }
+#endif
+ pipe_list = parse_stream(NULL, NULL, inp, end_trigger);
+ if (!pipe_list || pipe_list == ERR_PTR) { /* EOF/error */
+ /* If we are in "big" script
+ * (not in `cmd` or something similar)...
+ */
+ if (pipe_list == ERR_PTR && end_trigger == ';') {
+ /* Discard cached input (rest of line) */
+ int ch = inp->last_char;
+ while (ch != EOF && ch != '\n') {
+ //bb_error_msg("Discarded:'%c'", ch);
+ ch = i_getch(inp);
+ }
+ /* Force prompt */
+ inp->p = NULL;
+ /* This stream isn't empty */
+ empty = 0;
+ continue;
+ }
+ if (!pipe_list && empty)
+ G.last_exitcode = 0;
+ break;
+ }
+ debug_print_tree(pipe_list, 0);
+ debug_printf_exec("parse_and_run_stream: run_and_free_list\n");
+#ifndef __U_BOOT__
+ run_and_free_list(pipe_list);
+#else /* __U_BOOT__ */
+ int rcode = run_and_free_list(pipe_list);
+ /*
+ * We reset input string to not run the following command, so running
+ * 'exit; echo foo' does not print foo.
+ */
+ if (rcode <= EXIT_RET_CODE)
+ setup_file_in_str(inp);
+#endif /* __U_BOOT__ */
+ empty = 0;
+ if (G_flag_return_in_progress == 1)
+ break;
+#ifndef __U_BOOT__
+ }
+#else /* __U_BOOT__ */
+ /*
+ * This do/while is needed by run_command to avoid looping on a command
+ * with syntax error.
+ */
+ } while (!(G.run_command_flags & FLAG_EXIT_FROM_LOOP));
+
+ return G.last_exitcode;
+#endif /* __U_BOOT__ */
+}
+
+#ifndef __U_BOOT__
+static void parse_and_run_string(const char *s)
+#else /* __U_BOOT__ */
+static int parse_and_run_string(const char *s)
+#endif /* __U_BOOT__ */
+{
+ struct in_str input;
+#ifndef __U_BOOT__
+ IF_HUSH_LINENO_VAR(unsigned sv = G.parse_lineno;)
+#else /* __U_BOOT__ */
+ //IF_HUSH_LINENO_VAR(unsigned sv = G.parse_lineno;)
+#endif /* __U_BOOT__ */
+
+ setup_string_in_str(&input, s);
+#ifndef __U_BOOT__
+ parse_and_run_stream(&input, '\0');
+#else /* __U_BOOT__ */
+ return parse_and_run_stream(&input, '\0');
+#endif /* __U_BOOT__ */
+#ifndef __U_BOOT__
+ IF_HUSH_LINENO_VAR(unsigned sv = G.parse_lineno;)
+#else /* __U_BOOT__ */
+ //IF_HUSH_LINENO_VAR(unsigned sv = G.parse_lineno;)
+#endif /* __U_BOOT__ */
+}
+
+#ifdef __U_BOOT__
+int parse_string_outer_modern(const char *cmd, int flags)
+{
+ int ret;
+ int old_flags;
+
+ /*
+ * Keep old values of run_command to be able to restore them once
+ * command was executed.
+ */
+ old_flags = G.run_command_flags;
+ G.run_command_flags = flags;
+
+ ret = parse_and_run_string(cmd);
+
+ G.run_command_flags = old_flags;
+
+ return ret;
+}
+#endif /* __U_BOOT__ */
+#ifndef __U_BOOT__
+static void parse_and_run_file(HFILE *fp)
+#else /* __U_BOOT__ */
+void parse_and_run_file(void)
+#endif /* __U_BOOT__ */
+{
+ struct in_str input;
+#ifndef __U_BOOT__
+ IF_HUSH_LINENO_VAR(unsigned sv = G.parse_lineno;)
+
+ IF_HUSH_LINENO_VAR(G.parse_lineno = 1;)
+ setup_file_in_str(&input, fp);
+#else /* __U_BOOT__ */
+ setup_file_in_str(&input);
+#endif /* __U_BOOT__ */
+ parse_and_run_stream(&input, ';');
+#ifndef __U_BOOT__
+ IF_HUSH_LINENO_VAR(G.parse_lineno = sv;)
+#endif /* !__U_BOOT__ */
+}
+
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_TICK
+static int generate_stream_from_string(const char *s, pid_t *pid_p)
+{
+ pid_t pid;
+ int channel[2];
+# if !BB_MMU
+ char **to_free = NULL;
+# endif
+
+ xpipe(channel);
+ pid = BB_MMU ? xfork() : xvfork();
+ if (pid == 0) { /* child */
+ disable_restore_tty_pgrp_on_exit();
+ /* Process substitution is not considered to be usual
+ * 'command execution'.
+ * SUSv3 says ctrl-Z should be ignored, ctrl-C should not.
+ */
+ bb_signals(0
+ + (1 << SIGTSTP)
+ + (1 << SIGTTIN)
+ + (1 << SIGTTOU)
+ , SIG_IGN);
+ close(channel[0]); /* NB: close _first_, then move fd! */
+ xmove_fd(channel[1], 1);
+# if ENABLE_HUSH_TRAP
+ /* Awful hack for `trap` or $(trap).
+ *
+ * http://www.opengroup.org/onlinepubs/009695399/utilities/trap.html
+ * contains an example where "trap" is executed in a subshell:
+ *
+ * save_traps=$(trap)
+ * ...
+ * eval "$save_traps"
+ *
+ * Standard does not say that "trap" in subshell shall print
+ * parent shell's traps. It only says that its output
+ * must have suitable form, but then, in the above example
+ * (which is not supposed to be normative), it implies that.
+ *
+ * bash (and probably other shell) does implement it
+ * (traps are reset to defaults, but "trap" still shows them),
+ * but as a result, "trap" logic is hopelessly messed up:
+ *
+ * # trap
+ * trap -- 'echo Ho' SIGWINCH <--- we have a handler
+ * # (trap) <--- trap is in subshell - no output (correct, traps are reset)
+ * # true | trap <--- trap is in subshell - no output (ditto)
+ * # echo `true | trap` <--- in subshell - output (but traps are reset!)
+ * trap -- 'echo Ho' SIGWINCH
+ * # echo `(trap)` <--- in subshell in subshell - output
+ * trap -- 'echo Ho' SIGWINCH
+ * # echo `true | (trap)` <--- in subshell in subshell in subshell - output!
+ * trap -- 'echo Ho' SIGWINCH
+ *
+ * The rules when to forget and when to not forget traps
+ * get really complex and nonsensical.
+ *
+ * Our solution: ONLY bare $(trap) or `trap` is special.
+ */
+ s = skip_whitespace(s);
+ if (is_prefixed_with(s, "trap")
+ && skip_whitespace(s + 4)[0] == '\0'
+ ) {
+ static const char *const argv[] ALIGN_PTR = { NULL, NULL };
+ builtin_trap((char**)argv);
+ fflush_all(); /* important */
+ _exit(0);
+ }
+# endif
+# if BB_MMU
+ /* Prevent it from trying to handle ctrl-z etc */
+ IF_HUSH_JOB(G.run_list_level = 1;)
+ CLEAR_RANDOM_T(&G.random_gen); /* or else $RANDOM repeats in child */
+ reset_traps_to_defaults();
+ IF_HUSH_MODE_X(G.x_mode_depth++;)
+ //bb_error_msg("%s: ++x_mode_depth=%d", __func__, G.x_mode_depth);
+ parse_and_run_string(s);
+ _exit(G.last_exitcode);
+# else
+ /* We re-execute after vfork on NOMMU. This makes this script safe:
+ * yes "0123456789012345678901234567890" | dd bs=32 count=64k >BIG
+ * huge=`cat BIG` # was blocking here forever
+ * echo OK
+ */
+ re_execute_shell(&to_free,
+ s,
+ G.global_argv[0],
+ G.global_argv + 1,
+ NULL);
+# endif
+ }
+
+ /* parent */
+ *pid_p = pid;
+# if ENABLE_HUSH_FAST
+ G.count_SIGCHLD++;
+//bb_error_msg("[%d] fork in generate_stream_from_string:"
+// " G.count_SIGCHLD:%d G.handled_SIGCHLD:%d",
+// getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+# endif
+ enable_restore_tty_pgrp_on_exit();
+# if !BB_MMU
+ free(to_free);
+# endif
+ close(channel[1]);
+ return channel[0];
+}
+
+/* Return code is exit status of the process that is run. */
+static int process_command_subs(o_string *dest, const char *s)
+{
+ FILE *fp;
+ pid_t pid;
+ int status, ch, eol_cnt;
+
+ fp = xfdopen_for_read(generate_stream_from_string(s, &pid));
+
+ /* Now send results of command back into original context */
+ eol_cnt = 0;
+ while ((ch = getc(fp)) != EOF) {
+ if (ch == '\0')
+ continue;
+ if (ch == '\n') {
+ eol_cnt++;
+ continue;
+ }
+ while (eol_cnt) {
+ o_addchr(dest, '\n');
+ eol_cnt--;
+ }
+ o_addQchr(dest, ch);
+ }
+
+ debug_printf("done reading from `cmd` pipe, closing it\n");
+ fclose(fp);
+ /* We need to extract exitcode. Test case
+ * "true; echo `sleep 1; false` $?"
+ * should print 1 */
+ safe_waitpid(pid, &status, 0);
+ debug_printf("child exited. returning its exitcode:%d\n", WEXITSTATUS(status));
+ return WEXITSTATUS(status);
+}
+#endif /* ENABLE_HUSH_TICK */
+
+
+static void setup_heredoc(struct redir_struct *redir)
+{
+ struct fd_pair pair;
+ pid_t pid;
+ int len, written;
+ /* the _body_ of heredoc (misleading field name) */
+ const char *heredoc = redir->rd_filename;
+ char *expanded;
+#if !BB_MMU
+ char **to_free;
+#endif
+
+ expanded = NULL;
+ if (!(redir->rd_dup & HEREDOC_QUOTED)) {
+ expanded = encode_then_expand_string(heredoc);
+ if (expanded)
+ heredoc = expanded;
+ }
+ len = strlen(heredoc);
+
+ close(redir->rd_fd); /* often saves dup2+close in xmove_fd */
+ xpiped_pair(pair);
+ xmove_fd(pair.rd, redir->rd_fd);
+
+ /* Try writing without forking. Newer kernels have
+ * dynamically growing pipes. Must use non-blocking write! */
+ ndelay_on(pair.wr);
+ while (1) {
+ written = write(pair.wr, heredoc, len);
+ if (written <= 0)
+ break;
+ len -= written;
+ if (len == 0) {
+ close(pair.wr);
+ free(expanded);
+ return;
+ }
+ heredoc += written;
+ }
+ ndelay_off(pair.wr);
+
+ /* Okay, pipe buffer was not big enough */
+ /* Note: we must not create a stray child (bastard? :)
+ * for the unsuspecting parent process. Child creates a grandchild
+ * and exits before parent execs the process which consumes heredoc
+ * (that exec happens after we return from this function) */
+#if !BB_MMU
+ to_free = NULL;
+#endif
+ pid = xvfork();
+ if (pid == 0) {
+ /* child */
+ disable_restore_tty_pgrp_on_exit();
+ pid = BB_MMU ? xfork() : xvfork();
+ if (pid != 0)
+ _exit(0);
+ /* grandchild */
+ close(redir->rd_fd); /* read side of the pipe */
+#if BB_MMU
+ full_write(pair.wr, heredoc, len); /* may loop or block */
+ _exit(0);
+#else
+ /* Delegate blocking writes to another process */
+ xmove_fd(pair.wr, STDOUT_FILENO);
+ re_execute_shell(&to_free, heredoc, NULL, NULL, NULL);
+#endif
+ }
+ /* parent */
+#if ENABLE_HUSH_FAST
+ G.count_SIGCHLD++;
+//bb_error_msg("[%d] fork in setup_heredoc: G.count_SIGCHLD:%d G.handled_SIGCHLD:%d", getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+#endif
+ enable_restore_tty_pgrp_on_exit();
+#if !BB_MMU
+ free(to_free);
+#endif
+ close(pair.wr);
+ free(expanded);
+ wait(NULL); /* wait till child has died */
+}
+
+struct squirrel {
+ int orig_fd;
+ int moved_to;
+ /* moved_to = n: fd was moved to n; restore back to orig_fd after redir */
+ /* moved_to = -1: fd was opened by redirect; close orig_fd after redir */
+};
+
+static struct squirrel *append_squirrel(struct squirrel *sq, int i, int orig, int moved)
+{
+ sq = xrealloc(sq, (i + 2) * sizeof(sq[0]));
+ sq[i].orig_fd = orig;
+ sq[i].moved_to = moved;
+ sq[i+1].orig_fd = -1; /* end marker */
+ return sq;
+}
+
+static struct squirrel *add_squirrel(struct squirrel *sq, int fd, int avoid_fd)
+{
+ int moved_to;
+ int i;
+
+ i = 0;
+ if (sq) for (; sq[i].orig_fd >= 0; i++) {
+ /* If we collide with an already moved fd... */
+ if (fd == sq[i].moved_to) {
+ sq[i].moved_to = dup_CLOEXEC(sq[i].moved_to, avoid_fd);
+ debug_printf_redir("redirect_fd %d: already busy, moving to %d\n", fd, sq[i].moved_to);
+ if (sq[i].moved_to < 0) /* what? */
+ xfunc_die();
+ return sq;
+ }
+ if (fd == sq[i].orig_fd) {
+ /* Example: echo Hello >/dev/null 1>&2 */
+ debug_printf_redir("redirect_fd %d: already moved\n", fd);
+ return sq;
+ }
+ }
+
+ /* If this fd is open, we move and remember it; if it's closed, moved_to = -1 */
+ moved_to = dup_CLOEXEC(fd, avoid_fd);
+ debug_printf_redir("redirect_fd %d: previous fd is moved to %d (-1 if it was closed)\n", fd, moved_to);
+ if (moved_to < 0 && errno != EBADF)
+ xfunc_die();
+ return append_squirrel(sq, i, fd, moved_to);
+}
+
+static struct squirrel *add_squirrel_closed(struct squirrel *sq, int fd)
+{
+ int i;
+
+ i = 0;
+ if (sq) for (; sq[i].orig_fd >= 0; i++) {
+ /* If we collide with an already moved fd... */
+ if (fd == sq[i].orig_fd) {
+ /* Examples:
+ * "echo 3>FILE 3>&- 3>FILE"
+ * "echo 3>&- 3>FILE"
+ * No need for last redirect to insert
+ * another "need to close 3" indicator.
+ */
+ debug_printf_redir("redirect_fd %d: already moved or closed\n", fd);
+ return sq;
+ }
+ }
+
+ debug_printf_redir("redirect_fd %d: previous fd was closed\n", fd);
+ return append_squirrel(sq, i, fd, -1);
+}
+
+/* fd: redirect wants this fd to be used (e.g. 3>file).
+ * Move all conflicting internally used fds,
+ * and remember them so that we can restore them later.
+ */
+static int save_fd_on_redirect(int fd, int avoid_fd, struct squirrel **sqp)
+{
+ if (avoid_fd < 9) /* the important case here is that it can be -1 */
+ avoid_fd = 9;
+
+#if ENABLE_HUSH_INTERACTIVE
+ if (fd != 0 /* don't trigger for G_interactive_fd == 0 (that's "not interactive" flag) */
+ && fd == G_interactive_fd
+ ) {
+ /* Testcase: "ls -l /proc/$$/fd 255>&-" should work */
+ G_interactive_fd = xdup_CLOEXEC_and_close(G_interactive_fd, avoid_fd);
+ debug_printf_redir("redirect_fd %d: matches interactive_fd, moving it to %d\n", fd, G_interactive_fd);
+ return 1; /* "we closed fd" */
+ }
+#endif
+ /* Are we called from setup_redirects(squirrel==NULL)
+ * in redirect in a [v]forked child?
+ */
+ if (sqp == NULL) {
+ /* No need to move script fds.
+ * For NOMMU case, it's actively wrong: we'd change ->fd
+ * fields in memory for the parent, but parent's fds
+ * aren't moved, it would use wrong fd!
+ * Reproducer: "cmd 3>FILE" in script.
+ * If we would call move_HFILEs_on_redirect(), child would:
+ * fcntl64(3, F_DUPFD_CLOEXEC, 10) = 10
+ * close(3) = 0
+ * and change ->fd to 10 if fd#3 is a script fd. WRONG.
+ */
+ //bb_error_msg("sqp == NULL: [v]forked child");
+ return 0;
+ }
+
+ /* If this one of script's fds? */
+ if (move_HFILEs_on_redirect(fd, avoid_fd))
+ return 1; /* yes. "we closed fd" (actually moved it) */
+
+ /* Are we called for "exec 3>FILE"? Came through
+ * redirect_and_varexp_helper(squirrel=ERR_PTR) -> setup_redirects(ERR_PTR)
+ * This case used to fail for this script:
+ * exec 3>FILE
+ * echo Ok
+ * ...100000 more lines...
+ * echo Ok
+ * as follows:
+ * read(3, "exec 3>FILE\necho Ok\necho Ok"..., 1024) = 1024
+ * open("FILE", O_WRONLY|O_CREAT|O_TRUNC|O_LARGEFILE, 0666) = 4
+ * dup2(4, 3) = 3
+ * ^^^^^^^^ oops, we lost fd#3 opened to our script!
+ * close(4) = 0
+ * write(1, "Ok\n", 3) = 3
+ * ... = 3
+ * write(1, "Ok\n", 3) = 3
+ * read(3, 0x94fbc08, 1024) = -1 EBADF (Bad file descriptor)
+ * ^^^^^^^^ oops, wrong fd!!!
+ * With this case separate from sqp == NULL and *after* move_HFILEs,
+ * it now works:
+ */
+ if (sqp == ERR_PTR) {
+ /* Don't preserve redirected fds: exec is _meant_ to change these */
+ //bb_error_msg("sqp == ERR_PTR: exec >FILE");
+ return 0;
+ }
+
+ /* Check whether it collides with any open fds (e.g. stdio), save fds as needed */
+ *sqp = add_squirrel(*sqp, fd, avoid_fd);
+ return 0; /* "we did not close fd" */
+}
+
+static void restore_redirects(struct squirrel *sq)
+{
+ if (sq) {
+ int i;
+ for (i = 0; sq[i].orig_fd >= 0; i++) {
+ if (sq[i].moved_to >= 0) {
+ /* We simply die on error */
+ debug_printf_redir("restoring redirected fd from %d to %d\n", sq[i].moved_to, sq[i].orig_fd);
+ xmove_fd(sq[i].moved_to, sq[i].orig_fd);
+ } else {
+ /* cmd1 9>FILE; cmd2_should_see_fd9_closed */
+ debug_printf_redir("restoring redirected fd %d: closing it\n", sq[i].orig_fd);
+ close(sq[i].orig_fd);
+ }
+ }
+ free(sq);
+ }
+ if (G.HFILE_stdin
+ && G.HFILE_stdin->fd > STDIN_FILENO
+ /* we compare > STDIN, not == STDIN, since hfgetc()
+ * closes fd and sets ->fd to -1 if EOF is reached.
+ * Testcase: echo 'pwd' | hush
+ */
+ ) {
+ /* Testcase: interactive "read r <FILE; echo $r; read r; echo $r".
+ * Redirect moves ->fd to e.g. 10,
+ * and it is not restored above (we do not restore script fds
+ * after redirects, we just use new, "moved" fds).
+ * However for stdin, get_user_input() -> read_line_input(),
+ * and read builtin, depend on fd == STDIN_FILENO.
+ */
+ debug_printf_redir("restoring %d to stdin\n", G.HFILE_stdin->fd);
+ xmove_fd(G.HFILE_stdin->fd, STDIN_FILENO);
+ G.HFILE_stdin->fd = STDIN_FILENO;
+ }
+
+ /* If moved, G_interactive_fd stays on new fd, not restoring it */
+}
+
+#if ENABLE_FEATURE_SH_STANDALONE && BB_MMU
+static void close_saved_fds_and_FILE_fds(void)
+{
+ if (G_interactive_fd)
+ close(G_interactive_fd);
+ close_all_HFILE_list();
+}
+#endif
+
+static int internally_opened_fd(int fd, struct squirrel *sq)
+{
+ int i;
+
+#if ENABLE_HUSH_INTERACTIVE
+ if (fd == G_interactive_fd)
+ return 1;
+#endif
+ /* If this one of script's fds? */
+ if (fd_in_HFILEs(fd))
+ return 1;
+
+ if (sq) for (i = 0; sq[i].orig_fd >= 0; i++) {
+ if (fd == sq[i].moved_to)
+ return 1;
+ }
+ return 0;
+}
+
+/* squirrel != NULL means we squirrel away copies of stdin, stdout,
+ * and stderr if they are redirected. */
+static int setup_redirects(struct command *prog, struct squirrel **sqp)
+{
+ struct redir_struct *redir;
+
+ for (redir = prog->redirects; redir; redir = redir->next) {
+ int newfd;
+ int closed;
+
+ if (redir->rd_type == REDIRECT_HEREDOC2) {
+ /* "rd_fd<<HERE" case */
+ save_fd_on_redirect(redir->rd_fd, /*avoid:*/ 0, sqp);
+ /* for REDIRECT_HEREDOC2, rd_filename holds _contents_
+ * of the heredoc */
+ debug_printf_redir("set heredoc '%s'\n",
+ redir->rd_filename);
+ setup_heredoc(redir);
+ continue;
+ }
+
+ if (redir->rd_dup == REDIRFD_TO_FILE) {
+ /* "rd_fd<*>file" case (<*> is <,>,>>,<>) */
+ char *p;
+ int mode;
+
+ if (redir->rd_filename == NULL) {
+ /* Examples:
+ * "cmd >" (no filename)
+ * "cmd > <file" (2nd redirect starts too early)
+ */
+ syntax_error("invalid redirect");
+ continue;
+ }
+ mode = redir_table[redir->rd_type].mode;
+ p = expand_string_to_string(redir->rd_filename,
+ EXP_FLAG_ESC_GLOB_CHARS, /*unbackslash:*/ 1);
+ newfd = open_or_warn(p, mode);
+ free(p);
+ if (newfd < 0) {
+ /* Error message from open_or_warn can be lost
+ * if stderr has been redirected, but bash
+ * and ash both lose it as well
+ * (though zsh doesn't!)
+ */
+ return 1;
+ }
+ if (newfd == redir->rd_fd && sqp) {
+ /* open() gave us precisely the fd we wanted.
+ * This means that this fd was not busy
+ * (not opened to anywhere).
+ * Remember to close it on restore:
+ */
+ *sqp = add_squirrel_closed(*sqp, newfd);
+ debug_printf_redir("redir to previously closed fd %d\n", newfd);
+ }
+ } else {
+ /* "rd_fd>&rd_dup" or "rd_fd>&-" case */
+ newfd = redir->rd_dup;
+ }
+
+ if (newfd == redir->rd_fd)
+ continue;
+
+ /* if "N>FILE": move newfd to redir->rd_fd */
+ /* if "N>&M": dup newfd to redir->rd_fd */
+ /* if "N>&-": close redir->rd_fd (newfd is REDIRFD_CLOSE) */
+
+ closed = save_fd_on_redirect(redir->rd_fd, /*avoid:*/ newfd, sqp);
+ if (newfd == REDIRFD_CLOSE) {
+ /* "N>&-" means "close me" */
+ if (!closed) {
+ /* ^^^ optimization: saving may already
+ * have closed it. If not... */
+ close(redir->rd_fd);
+ }
+ /* Sometimes we do another close on restore, getting EBADF.
+ * Consider "echo 3>FILE 3>&-"
+ * first redirect remembers "need to close 3",
+ * and second redirect closes 3! Restore code then closes 3 again.
+ */
+ } else {
+ /* if newfd is a script fd or saved fd, simulate EBADF */
+ if (internally_opened_fd(newfd, sqp && sqp != ERR_PTR ? *sqp : NULL)) {
+ //errno = EBADF;
+ //bb_perror_msg_and_die("can't duplicate file descriptor");
+ newfd = -1; /* same effect as code above */
+ }
+ xdup2(newfd, redir->rd_fd);
+ if (redir->rd_dup == REDIRFD_TO_FILE)
+ /* "rd_fd > FILE" */
+ close(newfd);
+ /* else: "rd_fd > rd_dup" */
+ }
+ }
+ return 0;
+}
+
+static char *find_in_path(const char *arg)
+{
+ char *ret = NULL;
+ const char *PATH = get_local_var_value("PATH");
+
+ if (!PATH)
+ return NULL;
+
+ while (1) {
+ const char *end = strchrnul(PATH, ':');
+ int sz = end - PATH; /* must be int! */
+
+ free(ret);
+ if (sz != 0) {
+ ret = xasprintf("%.*s/%s", sz, PATH, arg);
+ } else {
+ /* We have xxx::yyyy in $PATH,
+ * it means "use current dir" */
+ ret = xstrdup(arg);
+ }
+ if (access(ret, F_OK) == 0)
+ break;
+
+ if (*end == '\0') {
+ free(ret);
+ return NULL;
+ }
+ PATH = end + 1;
+ }
+
+ return ret;
+}
+
+static const struct built_in_command *find_builtin_helper(const char *name,
+ const struct built_in_command *x,
+ const struct built_in_command *end)
+{
+ while (x != end) {
+ if (strcmp(name, x->b_cmd) != 0) {
+ x++;
+ continue;
+ }
+ debug_printf_exec("found builtin '%s'\n", name);
+ return x;
+ }
+ return NULL;
+}
+static const struct built_in_command *find_builtin1(const char *name)
+{
+ return find_builtin_helper(name, bltins1, &bltins1[ARRAY_SIZE(bltins1)]);
+}
+static const struct built_in_command *find_builtin(const char *name)
+{
+ const struct built_in_command *x = find_builtin1(name);
+ if (x)
+ return x;
+ return find_builtin_helper(name, bltins2, &bltins2[ARRAY_SIZE(bltins2)]);
+}
+
+#if ENABLE_HUSH_JOB && ENABLE_FEATURE_TAB_COMPLETION
+static const char * FAST_FUNC hush_command_name(int i)
+{
+ if (/*i >= 0 && */ i < ARRAY_SIZE(bltins1)) {
+ return bltins1[i].b_cmd;
+ }
+ i -= ARRAY_SIZE(bltins1);
+ if (i < ARRAY_SIZE(bltins2)) {
+ return bltins2[i].b_cmd;
+ }
+# if ENABLE_HUSH_FUNCTIONS
+ {
+ struct function *funcp;
+ i -= ARRAY_SIZE(bltins2);
+ for (funcp = G.top_func; funcp; funcp = funcp->next) {
+ if (--i < 0)
+ return funcp->name;
+ }
+ }
+# endif
+ return NULL;
+}
+#endif
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+static void remove_nested_vars(void)
+{
+ struct variable *cur;
+ struct variable **cur_pp;
+
+ cur_pp = &G.top_var;
+ while ((cur = *cur_pp) != NULL) {
+ if (cur->var_nest_level <= G.var_nest_level) {
+ cur_pp = &cur->next;
+ continue;
+ }
+ /* Unexport */
+ if (cur->flg_export) {
+ debug_printf_env("unexporting nested '%s'/%u\n", cur->varstr, cur->var_nest_level);
+ bb_unsetenv(cur->varstr);
+ }
+ /* Remove from global list */
+ *cur_pp = cur->next;
+ /* Free */
+ if (!cur->max_len) {
+ debug_printf_env("freeing nested '%s'/%u\n", cur->varstr, cur->var_nest_level);
+ free(cur->varstr);
+ }
+ free(cur);
+ }
+}
+
+static void enter_var_nest_level(void)
+{
+ G.var_nest_level++;
+ debug_printf_env("var_nest_level++ %u\n", G.var_nest_level);
+
+ /* Try: f() { echo -n .; f; }; f
+ * struct variable::var_nest_level is uint16_t,
+ * thus limiting recursion to < 2^16.
+ * In any case, with 8 Mbyte stack SEGV happens
+ * not too long after 2^16 recursions anyway.
+ */
+ if (G.var_nest_level > 0xff00)
+ bb_error_msg_and_die("fatal recursion (depth %u)", G.var_nest_level);
+}
+
+static void leave_var_nest_level(void)
+{
+ G.var_nest_level--;
+ debug_printf_env("var_nest_level-- %u\n", G.var_nest_level);
+ if (HUSH_DEBUG && (int)G.var_nest_level < 0)
+ bb_simple_error_msg_and_die("BUG: nesting underflow");
+
+ remove_nested_vars();
+}
+#endif /* __U_BOOT__ */
+
+#if ENABLE_HUSH_FUNCTIONS
+static struct function **find_function_slot(const char *name)
+{
+ struct function *funcp;
+ struct function **funcpp = &G.top_func;
+
+ while ((funcp = *funcpp) != NULL) {
+ if (strcmp(name, funcp->name) == 0) {
+ debug_printf_exec("found function '%s'\n", name);
+ break;
+ }
+ funcpp = &funcp->next;
+ }
+ return funcpp;
+}
+
+static ALWAYS_INLINE const struct function *find_function(const char *name)
+{
+ const struct function *funcp = *find_function_slot(name);
+ return funcp;
+}
+
+/* Note: takes ownership on name ptr */
+static struct function *new_function(char *name)
+{
+ struct function **funcpp = find_function_slot(name);
+ struct function *funcp = *funcpp;
+
+ if (funcp != NULL) {
+ struct command *cmd = funcp->parent_cmd;
+ debug_printf_exec("func %p parent_cmd %p\n", funcp, cmd);
+ if (!cmd) {
+ debug_printf_exec("freeing & replacing function '%s'\n", funcp->name);
+ free(funcp->name);
+ /* Note: if !funcp->body, do not free body_as_string!
+ * This is a special case of "-F name body" function:
+ * body_as_string was not malloced! */
+ if (funcp->body) {
+ free_pipe_list(funcp->body);
+# if !BB_MMU
+ free(funcp->body_as_string);
+# endif
+ }
+ } else {
+ debug_printf_exec("reinserting in tree & replacing function '%s'\n", funcp->name);
+ cmd->argv[0] = funcp->name;
+ cmd->group = funcp->body;
+# if !BB_MMU
+ cmd->group_as_string = funcp->body_as_string;
+# endif
+ }
+ } else {
+ debug_printf_exec("remembering new function '%s'\n", name);
+ funcp = *funcpp = xzalloc(sizeof(*funcp));
+ /*funcp->next = NULL;*/
+ }
+
+ funcp->name = name;
+ return funcp;
+}
+
+# if ENABLE_HUSH_UNSET
+static void unset_func(const char *name)
+{
+ struct function **funcpp = find_function_slot(name);
+ struct function *funcp = *funcpp;
+
+ if (funcp != NULL) {
+ debug_printf_exec("freeing function '%s'\n", funcp->name);
+ *funcpp = funcp->next;
+ /* funcp is unlinked now, deleting it.
+ * Note: if !funcp->body, the function was created by
+ * "-F name body", do not free ->body_as_string
+ * and ->name as they were not malloced. */
+ if (funcp->body) {
+ free_pipe_list(funcp->body);
+ free(funcp->name);
+# if !BB_MMU
+ free(funcp->body_as_string);
+# endif
+ }
+ free(funcp);
+ }
+}
+# endif
+
+# if BB_MMU
+#define exec_function(to_free, funcp, argv) \
+ exec_function(funcp, argv)
+# endif
+static void exec_function(char ***to_free,
+ const struct function *funcp,
+ char **argv) NORETURN;
+static void exec_function(char ***to_free,
+ const struct function *funcp,
+ char **argv)
+{
+# if BB_MMU
+ int n;
+
+ argv[0] = G.global_argv[0];
+ G.global_argv = argv;
+ G.global_argc = n = 1 + string_array_len(argv + 1);
+
+// Example when we are here: "cmd | func"
+// func will run with saved-redirect fds open.
+// $ f() { echo /proc/self/fd/*; }
+// $ true | f
+// /proc/self/fd/0 /proc/self/fd/1 /proc/self/fd/2 /proc/self/fd/255 /proc/self/fd/3
+// stdio^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ G_interactive_fd^ DIR fd for glob
+// Same in script:
+// $ . ./SCRIPT
+// /proc/self/fd/0 /proc/self/fd/1 /proc/self/fd/2 /proc/self/fd/255 /proc/self/fd/3 /proc/self/fd/4
+// stdio^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ G_interactive_fd^ opened ./SCRIPT DIR fd for glob
+// They are CLOEXEC so external programs won't see them, but
+// for "more correctness" we might want to close those extra fds here:
+//? close_saved_fds_and_FILE_fds();
+
+ /* "we are in a function, ok to use return" */
+ G_flag_return_in_progress = -1;
+ enter_var_nest_level();
+ IF_HUSH_LOCAL(G.func_nest_level++;)
+
+ /* On MMU, funcp->body is always non-NULL */
+ n = run_list(funcp->body);
+ _exit(n);
+# else
+//? close_saved_fds_and_FILE_fds();
+
+//TODO: check whether "true | func_with_return" works
+
+ re_execute_shell(to_free,
+ funcp->body_as_string,
+ G.global_argv[0],
+ argv + 1,
+ NULL);
+# endif
+}
+
+static int run_function(const struct function *funcp, char **argv)
+{
+ int rc;
+ save_arg_t sv;
+ smallint sv_flg;
+
+ save_and_replace_G_args(&sv, argv);
+
+ /* "We are in function, ok to use return" */
+ sv_flg = G_flag_return_in_progress;
+ G_flag_return_in_progress = -1;
+
+ /* Make "local" variables properly shadow previous ones */
+ IF_HUSH_LOCAL(enter_var_nest_level();)
+ IF_HUSH_LOCAL(G.func_nest_level++;)
+
+ /* On MMU, funcp->body is always non-NULL */
+# if !BB_MMU
+ if (!funcp->body) {
+ /* Function defined by -F */
+ parse_and_run_string(funcp->body_as_string);
+ rc = G.last_exitcode;
+ } else
+# endif
+ {
+ rc = run_list(funcp->body);
+ }
+
+ IF_HUSH_LOCAL(G.func_nest_level--;)
+ IF_HUSH_LOCAL(leave_var_nest_level();)
+
+ G_flag_return_in_progress = sv_flg;
+# if ENABLE_HUSH_TRAP
+ debug_printf_exec("G.return_exitcode=-1\n");
+ G.return_exitcode = -1; /* invalidate stashed return value */
+# endif
+
+ restore_G_args(&sv, argv);
+
+ return rc;
+}
+#endif /* ENABLE_HUSH_FUNCTIONS */
+
+
+#ifndef __U_BOOT__
+#if BB_MMU
+#define exec_builtin(to_free, x, argv) \
+ exec_builtin(x, argv)
+#else
+#define exec_builtin(to_free, x, argv) \
+ exec_builtin(to_free, argv)
+#endif
+static void exec_builtin(char ***to_free,
+ const struct built_in_command *x,
+ char **argv) NORETURN;
+static void exec_builtin(char ***to_free,
+ const struct built_in_command *x,
+ char **argv)
+{
+#if BB_MMU
+ int rcode;
+//? close_saved_fds_and_FILE_fds();
+ rcode = x->b_function(argv);
+ fflush_all();
+ _exit(rcode);
+#else
+ fflush_all();
+ /* On NOMMU, we must never block!
+ * Example: { sleep 99 | read line; } & echo Ok
+ */
+ re_execute_shell(to_free,
+ argv[0],
+ G.global_argv[0],
+ G.global_argv + 1,
+ argv);
+#endif
+}
+#endif /* !__U_BOOT__ */
+
+
+#ifndef __U_BOOT__
+static void execvp_or_die(char **argv) NORETURN;
+static void execvp_or_die(char **argv)
+{
+ int e;
+ debug_printf_exec("execing '%s'\n", argv[0]);
+ /* Don't propagate SIG_IGN to the child */
+ if (SPECIAL_JOBSTOP_SIGS != 0)
+ switch_off_special_sigs(G.special_sig_mask & SPECIAL_JOBSTOP_SIGS);
+ execvp(argv[0], argv);
+ e = 2;
+ if (errno == EACCES) e = 126;
+ if (errno == ENOENT) e = 127;
+ bb_perror_msg("can't execute '%s'", argv[0]);
+ _exit(e);
+}
+
+#if ENABLE_HUSH_MODE_X
+static void x_mode_print_optionally_squoted(const char *str)
+{
+ unsigned len;
+ const char *cp;
+
+ cp = str;
+
+ /* the set of chars which-cause-string-to-be-squoted mimics bash */
+ /* test a char with: bash -c 'set -x; echo "CH"' */
+ if (str[strcspn(str, "\\\"'`$(){}[]<>;#&|~*?!^"
+ " " "\001\002\003\004\005\006\007"
+ "\010\011\012\013\014\015\016\017"
+ "\020\021\022\023\024\025\026\027"
+ "\030\031\032\033\034\035\036\037"
+ )
+ ] == '\0'
+ ) {
+ /* string has no special chars */
+ x_mode_addstr(str);
+ return;
+ }
+
+ cp = str;
+ for (;;) {
+ /* print '....' up to EOL or first squote */
+ len = (int)(strchrnul(cp, '\'') - cp);
+ if (len != 0) {
+ x_mode_addchr('\'');
+ x_mode_addblock(cp, len);
+ x_mode_addchr('\'');
+ cp += len;
+ }
+ if (*cp == '\0')
+ break;
+ /* string contains squote(s), print them as \' */
+ x_mode_addchr('\\');
+ x_mode_addchr('\'');
+ cp++;
+ }
+}
+static void dump_cmd_in_x_mode(char **argv)
+{
+ if (G_x_mode && argv) {
+ unsigned n;
+
+ /* "+[+++...][ cmd...]\n\0" */
+ x_mode_prefix();
+ n = 0;
+ while (argv[n]) {
+ x_mode_addchr(' ');
+ if (argv[n][0] == '\0') {
+ x_mode_addchr('\'');
+ x_mode_addchr('\'');
+ } else {
+ x_mode_print_optionally_squoted(argv[n]);
+ }
+ n++;
+ }
+ x_mode_flush();
+ }
+}
+#else
+# define dump_cmd_in_x_mode(argv) ((void)0)
+#endif
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_COMMAND
+static void if_command_vV_print_and_exit(char opt_vV, char *cmd, const char *explanation)
+{
+ char *to_free;
+
+ if (!opt_vV)
+ return;
+
+ to_free = NULL;
+ if (!explanation) {
+ char *path = getenv("PATH");
+ explanation = to_free = find_executable(cmd, &path); /* path == NULL is ok */
+ if (!explanation)
+ _exit(1); /* PROG was not found */
+ if (opt_vV != 'V')
+ cmd = to_free; /* -v PROG prints "/path/to/PROG" */
+ }
+ printf((opt_vV == 'V') ? "%s is %s\n" : "%s\n", cmd, explanation);
+ free(to_free);
+ fflush_all();
+ _exit(0);
+}
+#else
+# define if_command_vV_print_and_exit(a,b,c) ((void)0)
+#endif
+#endif /* !__U_BOOT__ */
+
+#if BB_MMU
+#define pseudo_exec_argv(nommu_save, argv, assignment_cnt, argv_expanded) \
+ pseudo_exec_argv(argv, assignment_cnt, argv_expanded)
+#define pseudo_exec(nommu_save, command, argv_expanded) \
+ pseudo_exec(command, argv_expanded)
+#endif
+
+#ifndef __U_BOOT__
+/* Called after [v]fork() in run_pipe, or from builtin_exec.
+ * Never returns.
+ * Don't exit() here. If you don't exec, use _exit instead.
+ * The at_exit handlers apparently confuse the calling process,
+ * in particular stdin handling. Not sure why? -- because of vfork! (vda)
+ */
+static void pseudo_exec_argv(nommu_save_t *nommu_save,
+ char **argv, int assignment_cnt,
+ char **argv_expanded) NORETURN;
+static NOINLINE void pseudo_exec_argv(nommu_save_t *nommu_save,
+ char **argv, int assignment_cnt,
+ char **argv_expanded)
+{
+ const struct built_in_command *x;
+ struct variable **sv_shadowed;
+ char **new_env;
+ IF_HUSH_COMMAND(char opt_vV = 0;)
+ IF_HUSH_FUNCTIONS(const struct function *funcp;)
+
+ new_env = expand_assignments(argv, assignment_cnt);
+ dump_cmd_in_x_mode(new_env);
+
+ if (!argv[assignment_cnt]) {
+ /* Case when we are here: ... | var=val | ...
+ * (note that we do not exit early, i.e., do not optimize out
+ * expand_assignments(): think about ... | var=`sleep 1` | ...
+ */
+ free_strings(new_env);
+ _exit_SUCCESS();
+ }
+
+ sv_shadowed = G.shadowed_vars_pp;
+#if BB_MMU
+ G.shadowed_vars_pp = NULL; /* "don't save, free them instead" */
+#else
+ G.shadowed_vars_pp = &nommu_save->old_vars;
+ G.var_nest_level++;
+#endif
+ set_vars_and_save_old(new_env);
+ G.shadowed_vars_pp = sv_shadowed;
+
+ if (argv_expanded) {
+ argv = argv_expanded;
+ } else {
+ argv = expand_strvec_to_strvec(argv + assignment_cnt);
+#if !BB_MMU
+ nommu_save->argv = argv;
+#endif
+ }
+ dump_cmd_in_x_mode(argv);
+
+#if ENABLE_FEATURE_SH_STANDALONE || BB_MMU
+ if (strchr(argv[0], '/') != NULL)
+ goto skip;
+#endif
+
+#if ENABLE_HUSH_FUNCTIONS
+ /* Check if the command matches any functions (this goes before bltins) */
+ funcp = find_function(argv[0]);
+ if (funcp)
+ exec_function(&nommu_save->argv_from_re_execing, funcp, argv);
+#endif
+
+#if ENABLE_HUSH_COMMAND
+ /* "command BAR": run BAR without looking it up among functions
+ * "command -v BAR": print "BAR" or "/path/to/BAR"; or exit 1
+ * "command -V BAR": print "BAR is {a function,a shell builtin,/path/to/BAR}"
+ */
+ while (strcmp(argv[0], "command") == 0 && argv[1]) {
+ char *p;
+
+ argv++;
+ p = *argv;
+ if (p[0] != '-' || !p[1])
+ continue; /* bash allows "command command command [-OPT] BAR" */
+
+ for (;;) {
+ p++;
+ switch (*p) {
+ case '\0':
+ argv++;
+ p = *argv;
+ if (p[0] != '-' || !p[1])
+ goto after_opts;
+ continue; /* next arg is also -opts, process it too */
+ case 'v':
+ case 'V':
+ opt_vV = *p;
+ continue;
+ default:
+ bb_error_msg_and_die("%s: %s: invalid option", "command", argv[0]);
+ }
+ }
+ }
+ after_opts:
+# if ENABLE_HUSH_FUNCTIONS
+ if (opt_vV && find_function(argv[0]))
+ if_command_vV_print_and_exit(opt_vV, argv[0], "a function");
+# endif
+#endif
+
+ /* Check if the command matches any of the builtins.
+ * Depending on context, this might be redundant. But it's
+ * easier to waste a few CPU cycles than it is to figure out
+ * if this is one of those cases.
+ */
+ /* Why "BB_MMU ? :" difference in logic? -
+ * On NOMMU, it is more expensive to re-execute shell
+ * just in order to run echo or test builtin.
+ * It's better to skip it here and run corresponding
+ * non-builtin later. */
+ x = BB_MMU ? find_builtin(argv[0]) : find_builtin1(argv[0]);
+ if (x) {
+ if_command_vV_print_and_exit(opt_vV, argv[0], "a shell builtin");
+ exec_builtin(&nommu_save->argv_from_re_execing, x, argv);
+ }
+
+#if ENABLE_FEATURE_SH_STANDALONE
+ /* Check if the command matches any busybox applets */
+ {
+ int a = find_applet_by_name(argv[0]);
+ if (a >= 0) {
+ if_command_vV_print_and_exit(opt_vV, argv[0], "an applet");
+# if BB_MMU /* see above why on NOMMU it is not allowed */
+ if (APPLET_IS_NOEXEC(a)) {
+ /* Do not leak open fds from opened script files etc.
+ * Testcase: interactive "ls -l /proc/self/fd"
+ * should not show tty fd open.
+ */
+ close_saved_fds_and_FILE_fds();
+//FIXME: should also close saved redir fds
+//This casuses test failures in
+//redir_children_should_not_see_saved_fd_2.tests
+//redir_children_should_not_see_saved_fd_3.tests
+//if you replace "busybox find" with just "find" in them
+ /* Without this, "rm -i FILE" can't be ^C'ed: */
+ switch_off_special_sigs(G.special_sig_mask);
+ debug_printf_exec("running applet '%s'\n", argv[0]);
+ run_noexec_applet_and_exit(a, argv[0], argv);
+ }
+# endif
+ /* Re-exec ourselves */
+ debug_printf_exec("re-execing applet '%s'\n", argv[0]);
+ /* Don't propagate SIG_IGN to the child */
+ if (SPECIAL_JOBSTOP_SIGS != 0)
+ switch_off_special_sigs(G.special_sig_mask & SPECIAL_JOBSTOP_SIGS);
+ execv(bb_busybox_exec_path, argv);
+ /* If they called chroot or otherwise made the binary no longer
+ * executable, fall through */
+ }
+ }
+#endif
+
+#if ENABLE_FEATURE_SH_STANDALONE || BB_MMU
+ skip:
+#endif
+ if_command_vV_print_and_exit(opt_vV, argv[0], NULL);
+ execvp_or_die(argv);
+}
+
+/* Called after [v]fork() in run_pipe
+ */
+static void pseudo_exec(nommu_save_t *nommu_save,
+ struct command *command,
+ char **argv_expanded) NORETURN;
+static void pseudo_exec(nommu_save_t *nommu_save,
+ struct command *command,
+ char **argv_expanded)
+{
+#if ENABLE_HUSH_FUNCTIONS
+ if (command->cmd_type == CMD_FUNCDEF) {
+ /* Ignore funcdefs in pipes:
+ * true | f() { cmd }
+ */
+ _exit(0);
+ }
+#endif
+
+ if (command->argv) {
+ pseudo_exec_argv(nommu_save, command->argv,
+ command->assignment_cnt, argv_expanded);
+ }
+
+ if (command->group) {
+ /* Cases when we are here:
+ * ( list )
+ * { list } &
+ * ... | ( list ) | ...
+ * ... | { list } | ...
+ */
+#if BB_MMU
+ int rcode;
+ debug_printf_exec("pseudo_exec: run_list\n");
+ reset_traps_to_defaults();
+ rcode = run_list(command->group);
+ /* OK to leak memory by not calling free_pipe_list,
+ * since this process is about to exit */
+ _exit(rcode);
+#else
+ re_execute_shell(&nommu_save->argv_from_re_execing,
+ command->group_as_string,
+ G.global_argv[0],
+ G.global_argv + 1,
+ NULL);
+#endif
+ }
+
+ /* Case when we are here: ... | >file */
+ debug_printf_exec("pseudo_exec'ed null command\n");
+ _exit_SUCCESS();
+}
+
+#if ENABLE_HUSH_JOB
+static const char *get_cmdtext(struct pipe *pi)
+{
+ char **argv;
+ char *p;
+ int len;
+
+ /* This is subtle. ->cmdtext is created only on first backgrounding.
+ * (Think "cat, <ctrl-z>, fg, <ctrl-z>, fg, <ctrl-z>...." here...)
+ * On subsequent bg argv is trashed, but we won't use it */
+ if (pi->cmdtext)
+ return pi->cmdtext;
+
+ argv = pi->cmds[0].argv;
+ if (!argv) {
+ pi->cmdtext = xzalloc(1);
+ return pi->cmdtext;
+ }
+ len = 0;
+ do {
+ len += strlen(*argv) + 1;
+ } while (*++argv);
+ p = xmalloc(len);
+ pi->cmdtext = p;
+ argv = pi->cmds[0].argv;
+ do {
+ p = stpcpy(p, *argv);
+ *p++ = ' ';
+ } while (*++argv);
+ p[-1] = '\0';
+ return pi->cmdtext;
+}
+
+static void remove_job_from_table(struct pipe *pi)
+{
+ struct pipe *prev_pipe;
+
+ if (pi == G.job_list) {
+ G.job_list = pi->next;
+ } else {
+ prev_pipe = G.job_list;
+ while (prev_pipe->next != pi)
+ prev_pipe = prev_pipe->next;
+ prev_pipe->next = pi->next;
+ }
+ G.last_jobid = 0;
+ if (G.job_list)
+ G.last_jobid = G.job_list->jobid;
+}
+
+static void delete_finished_job(struct pipe *pi)
+{
+ remove_job_from_table(pi);
+ free_pipe(pi);
+}
+
+static void clean_up_last_dead_job(void)
+{
+ if (G.job_list && !G.job_list->alive_cmds)
+ delete_finished_job(G.job_list);
+}
+
+static void insert_job_into_table(struct pipe *pi)
+{
+ struct pipe *job, **jobp;
+ int i;
+
+ clean_up_last_dead_job();
+
+ /* Find the end of the list, and find next job ID to use */
+ i = 0;
+ jobp = &G.job_list;
+ while ((job = *jobp) != NULL) {
+ if (job->jobid > i)
+ i = job->jobid;
+ jobp = &job->next;
+ }
+ pi->jobid = i + 1;
+
+ /* Create a new job struct at the end */
+ job = *jobp = xmemdup(pi, sizeof(*pi));
+ job->next = NULL;
+ job->cmds = xzalloc(sizeof(pi->cmds[0]) * pi->num_cmds);
+ /* Cannot copy entire pi->cmds[] vector! This causes double frees */
+ for (i = 0; i < pi->num_cmds; i++) {
+ job->cmds[i].pid = pi->cmds[i].pid;
+ /* all other fields are not used and stay zero */
+ }
+ job->cmdtext = xstrdup(get_cmdtext(pi));
+
+ if (G_interactive_fd)
+ printf("[%u] %u %s\n", job->jobid, (unsigned)job->cmds[0].pid, job->cmdtext);
+ G.last_jobid = job->jobid;
+}
+#endif /* JOB */
+
+static int job_exited_or_stopped(struct pipe *pi)
+{
+ int rcode, i;
+
+ if (pi->alive_cmds != pi->stopped_cmds)
+ return -1;
+
+ /* All processes in fg pipe have exited or stopped */
+ rcode = 0;
+ i = pi->num_cmds;
+ while (--i >= 0) {
+ rcode = pi->cmds[i].cmd_exitcode;
+ /* usually last process gives overall exitstatus,
+ * but with "set -o pipefail", last *failed* process does */
+ if (G.o_opt[OPT_O_PIPEFAIL] == 0 || rcode != 0)
+ break;
+ }
+ IF_HAS_KEYWORDS(if (pi->pi_inverted) rcode = !rcode;)
+ return rcode;
+}
+
+static int process_wait_result(struct pipe *fg_pipe, pid_t childpid, int status)
+{
+#if ENABLE_HUSH_JOB
+ struct pipe *pi;
+#endif
+ int i, dead;
+
+ dead = WIFEXITED(status) || WIFSIGNALED(status);
+
+#if DEBUG_JOBS
+ if (WIFSTOPPED(status))
+ debug_printf_jobs("pid %d stopped by sig %d (exitcode %d)\n",
+ childpid, WSTOPSIG(status), WEXITSTATUS(status));
+ if (WIFSIGNALED(status))
+ debug_printf_jobs("pid %d killed by sig %d (exitcode %d)\n",
+ childpid, WTERMSIG(status), WEXITSTATUS(status));
+ if (WIFEXITED(status))
+ debug_printf_jobs("pid %d exited, exitcode %d\n",
+ childpid, WEXITSTATUS(status));
+#endif
+ /* Were we asked to wait for a fg pipe? */
+ if (fg_pipe) {
+ i = fg_pipe->num_cmds;
+
+ while (--i >= 0) {
+ int rcode;
+
+ debug_printf_jobs("check pid %d\n", fg_pipe->cmds[i].pid);
+ if (fg_pipe->cmds[i].pid != childpid)
+ continue;
+ if (dead) {
+ int ex;
+ fg_pipe->cmds[i].pid = 0;
+ fg_pipe->alive_cmds--;
+ ex = WEXITSTATUS(status);
+ /* bash prints killer signal's name for *last*
+ * process in pipe (prints just newline for SIGINT/SIGPIPE).
+ * Mimic this. Example: "sleep 5" + (^\ or kill -QUIT)
+ */
+ if (WIFSIGNALED(status)) {
+ int sig = WTERMSIG(status);
+#if ENABLE_HUSH_JOB
+ if (G.run_list_level == 1
+ /* ^^^^^ Do not print in nested contexts, example:
+ * echo `sleep 1; sh -c 'kill -9 $$'` - prints "137", NOT "Killed 137"
+ */
+ && i == fg_pipe->num_cmds-1
+ ) {
+ /* strsignal() is for bash compat. ~600 bloat versus bbox's get_signame() */
+ puts(sig == SIGINT || sig == SIGPIPE ? "" : strsignal(sig));
+ }
+#endif
+ /* TODO: if (WCOREDUMP(status)) + " (core dumped)"; */
+ /* MIPS has 128 sigs (1..128), if sig==128,
+ * 128 + sig would result in exitcode 256 -> 0!
+ */
+ ex = 128 | sig;
+ }
+ fg_pipe->cmds[i].cmd_exitcode = ex;
+ } else {
+ fg_pipe->stopped_cmds++;
+ }
+ debug_printf_jobs("fg_pipe: alive_cmds %d stopped_cmds %d\n",
+ fg_pipe->alive_cmds, fg_pipe->stopped_cmds);
+ rcode = job_exited_or_stopped(fg_pipe);
+ if (rcode >= 0) {
+/* Note: *non-interactive* bash does not continue if all processes in fg pipe
+ * are stopped. Testcase: "cat | cat" in a script (not on command line!)
+ * and "killall -STOP cat" */
+ if (G_interactive_fd) {
+#if ENABLE_HUSH_JOB
+ if (fg_pipe->alive_cmds != 0)
+ insert_job_into_table(fg_pipe);
+#endif
+ return rcode;
+ }
+ if (fg_pipe->alive_cmds == 0)
+ return rcode;
+ }
+ /* There are still running processes in the fg_pipe */
+ return -1;
+ }
+ /* It wasn't in fg_pipe, look for process in bg pipes */
+ }
+
+#if ENABLE_HUSH_JOB
+ /* We were asked to wait for bg or orphaned children */
+ /* No need to remember exitcode in this case */
+ for (pi = G.job_list; pi; pi = pi->next) {
+ for (i = 0; i < pi->num_cmds; i++) {
+ if (pi->cmds[i].pid == childpid)
+ goto found_pi_and_prognum;
+ }
+ }
+ /* Happens when shell is used as init process (init=/bin/sh) */
+ debug_printf("checkjobs: pid %d was not in our list!\n", childpid);
+ return -1; /* this wasn't a process from fg_pipe */
+
+ found_pi_and_prognum:
+ if (dead) {
+ /* child exited */
+ int rcode = WEXITSTATUS(status);
+ if (WIFSIGNALED(status))
+ /* NB: not 128 + sig, MIPS has sig 128 */
+ rcode = 128 | WTERMSIG(status);
+ pi->cmds[i].cmd_exitcode = rcode;
+ if (G.last_bg_pid == pi->cmds[i].pid)
+ G.last_bg_pid_exitcode = rcode;
+ pi->cmds[i].pid = 0;
+ pi->alive_cmds--;
+ if (!pi->alive_cmds) {
+# if ENABLE_HUSH_BASH_COMPAT
+ G.dead_job_exitcode = job_exited_or_stopped(pi);
+# endif
+ if (G_interactive_fd) {
+ printf(JOB_STATUS_FORMAT, pi->jobid,
+ "Done", pi->cmdtext);
+ delete_finished_job(pi);
+ } else {
+/*
+ * bash deletes finished jobs from job table only in interactive mode,
+ * after "jobs" cmd, or if pid of a new process matches one of the old ones
+ * (see cleanup_dead_jobs(), delete_old_job(), J_NOTIFIED in bash source).
+ * Testcase script: "(exit 3) & sleep 1; wait %1; echo $?" prints 3 in bash.
+ * We only retain one "dead" job, if it's the single job on the list.
+ * This covers most of real-world scenarios where this is useful.
+ */
+ if (pi != G.job_list)
+ delete_finished_job(pi);
+ }
+ }
+ } else {
+ /* child stopped */
+ pi->stopped_cmds++;
+ }
+#endif
+ return -1; /* this wasn't a process from fg_pipe */
+}
+
+/* Check to see if any processes have exited -- if they have,
+ * figure out why and see if a job has completed.
+ *
+ * If non-NULL fg_pipe: wait for its completion or stop.
+ * Return its exitcode or zero if stopped.
+ *
+ * Alternatively (fg_pipe == NULL, waitfor_pid != 0):
+ * waitpid(WNOHANG), if waitfor_pid exits or stops, return exitcode+1,
+ * else return <0 if waitpid errors out (e.g. ECHILD: nothing to wait for)
+ * or 0 if no children changed status.
+ *
+ * Alternatively (fg_pipe == NULL, waitfor_pid == 0),
+ * return <0 if waitpid errors out (e.g. ECHILD: nothing to wait for)
+ * or 0 if no children changed status.
+ */
+static int checkjobs(struct pipe *fg_pipe, pid_t waitfor_pid)
+{
+ int attributes;
+ int status;
+ int rcode = 0;
+
+ debug_printf_jobs("checkjobs %p\n", fg_pipe);
+
+ attributes = WUNTRACED;
+ if (fg_pipe == NULL)
+ attributes |= WNOHANG;
+
+ errno = 0;
+#if ENABLE_HUSH_FAST
+ if (G.handled_SIGCHLD == G.count_SIGCHLD) {
+//bb_error_msg("[%d] checkjobs: G.count_SIGCHLD:%d G.handled_SIGCHLD:%d children?:%d fg_pipe:%p",
+//getpid(), G.count_SIGCHLD, G.handled_SIGCHLD, G.we_have_children, fg_pipe);
+ /* There was neither fork nor SIGCHLD since last waitpid */
+ /* Avoid doing waitpid syscall if possible */
+ if (!G.we_have_children) {
+ errno = ECHILD;
+ return -1;
+ }
+ if (fg_pipe == NULL) { /* is WNOHANG set? */
+ /* We have children, but they did not exit
+ * or stop yet (we saw no SIGCHLD) */
+ return 0;
+ }
+ /* else: !WNOHANG, waitpid will block, can't short-circuit */
+ }
+#endif
+
+/* Do we do this right?
+ * bash-3.00# sleep 20 | false
+ * <ctrl-Z pressed>
+ * [3]+ Stopped sleep 20 | false
+ * bash-3.00# echo $?
+ * 1 <========== bg pipe is not fully done, but exitcode is already known!
+ * [hush 1.14.0: yes we do it right]
+ */
+ while (1) {
+ pid_t childpid;
+#if ENABLE_HUSH_FAST
+ int i;
+ i = G.count_SIGCHLD;
+#endif
+ childpid = waitpid(-1, &status, attributes);
+ if (childpid <= 0) {
+ if (childpid && errno != ECHILD)
+ bb_simple_perror_msg("waitpid");
+#if ENABLE_HUSH_FAST
+ else { /* Until next SIGCHLD, waitpid's are useless */
+ G.we_have_children = (childpid == 0);
+ G.handled_SIGCHLD = i;
+//bb_error_msg("[%d] checkjobs: waitpid returned <= 0, G.count_SIGCHLD:%d G.handled_SIGCHLD:%d", getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+ }
+#endif
+ /* ECHILD (no children), or 0 (no change in children status) */
+ rcode = childpid;
+ break;
+ }
+ rcode = process_wait_result(fg_pipe, childpid, status);
+ if (rcode >= 0) {
+ /* fg_pipe exited or stopped */
+ break;
+ }
+ if (childpid == waitfor_pid) { /* "wait PID" */
+ debug_printf_exec("childpid==waitfor_pid:%d status:0x%08x\n", childpid, status);
+ rcode = WEXITSTATUS(status);
+ if (WIFSIGNALED(status))
+ rcode = 128 | WTERMSIG(status);
+ if (WIFSTOPPED(status))
+ /* bash: "cmd & wait $!" and cmd stops: $? = 128 | stopsig */
+ rcode = 128 | WSTOPSIG(status);
+ rcode++;
+ break; /* "wait PID" called us, give it exitcode+1 */
+ }
+#if ENABLE_HUSH_BASH_COMPAT
+ if (-1 == waitfor_pid /* "wait -n" (wait for any one job) */
+ && G.dead_job_exitcode >= 0 /* some job did finish */
+ ) {
+ debug_printf_exec("waitfor_pid:-1\n");
+ rcode = G.dead_job_exitcode + 1;
+ break;
+ }
+#endif
+ /* This wasn't one of our processes, or */
+ /* fg_pipe still has running processes, do waitpid again */
+ } /* while (waitpid succeeds)... */
+
+ return rcode;
+}
+
+#if ENABLE_HUSH_JOB
+static int checkjobs_and_fg_shell(struct pipe *fg_pipe)
+{
+ pid_t p;
+ int rcode = checkjobs(fg_pipe, 0 /*(no pid to wait for)*/);
+ if (G_saved_tty_pgrp) {
+ /* Job finished, move the shell to the foreground */
+ p = getpgrp(); /* our process group id */
+ debug_printf_jobs("fg'ing ourself: getpgrp()=%d\n", (int)p);
+ tcsetpgrp(G_interactive_fd, p);
+ }
+ return rcode;
+}
+#endif
+
+/* Start all the jobs, but don't wait for anything to finish.
+ * See checkjobs().
+ *
+ * Return code is normally -1, when the caller has to wait for children
+ * to finish to determine the exit status of the pipe. If the pipe
+ * is a simple builtin command, however, the action is done by the
+ * time run_pipe returns, and the exit code is provided as the
+ * return value.
+ *
+ * Returns -1 only if started some children. IOW: we have to
+ * mask out retvals of builtins etc with 0xff!
+ *
+ * The only case when we do not need to [v]fork is when the pipe
+ * is single, non-backgrounded, non-subshell command. Examples:
+ * cmd ; ... { list } ; ...
+ * cmd && ... { list } && ...
+ * cmd || ... { list } || ...
+ * If it is, then we can run cmd as a builtin, NOFORK,
+ * or (if SH_STANDALONE) an applet, and we can run the { list }
+ * with run_list. If it isn't one of these, we fork and exec cmd.
+ *
+ * Cases when we must fork:
+ * non-single: cmd | cmd
+ * backgrounded: cmd & { list } &
+ * subshell: ( list ) [&]
+ */
+#if !ENABLE_HUSH_MODE_X
+#define redirect_and_varexp_helper(command, sqp, argv_expanded) \
+ redirect_and_varexp_helper(command, sqp)
+#endif
+static int redirect_and_varexp_helper(
+ struct command *command,
+ struct squirrel **sqp,
+ char **argv_expanded)
+{
+ /* Assignments occur before redirects. Try:
+ * a=`sleep 1` sleep 2 3>/qwe/rty
+ */
+
+ char **new_env = expand_assignments(command->argv, command->assignment_cnt);
+ dump_cmd_in_x_mode(new_env);
+ dump_cmd_in_x_mode(argv_expanded);
+ /* this takes ownership of new_env[i] elements, and frees new_env: */
+ set_vars_and_save_old(new_env);
+
+ return setup_redirects(command, sqp);
+}
+#endif /* !__U_BOOT__ */
+
+static NOINLINE int run_pipe(struct pipe *pi)
+{
+ static const char *const null_ptr = NULL;
+
+ int cmd_no;
+#ifndef __U_BOOT__
+ int next_infd;
+#endif /* !__U_BOOT__ */
+ struct command *command;
+ char **argv_expanded;
+ char **argv;
+#ifndef __U_BOOT__
+ struct squirrel *squirrel = NULL;
+#endif /* !__U_BOOT__ */
+ int rcode;
+
+#ifdef __U_BOOT__
+ /*
+ * Set rcode here to avoid returning a garbage value in the middle of
+ * the function.
+ * Also, if an error occurs, rcode value would be changed and last
+ * return will signal the error.
+ */
+ rcode = 0;
+#endif /* __U_BOOT__ */
+
+ debug_printf_exec("run_pipe start: members:%d\n", pi->num_cmds);
+ debug_enter();
+
+ /* Testcase: set -- q w e; (IFS='' echo "$*"; IFS=''; echo "$*"); echo "$*"
+ * Result should be 3 lines: q w e, qwe, q w e
+ */
+ if (G.ifs_whitespace != G.ifs)
+ free(G.ifs_whitespace);
+ G.ifs = get_local_var_value("IFS");
+ if (G.ifs) {
+ char *p;
+ G.ifs_whitespace = (char*)G.ifs;
+ p = skip_whitespace(G.ifs);
+ if (*p) {
+ /* Not all $IFS is whitespace */
+ char *d;
+ int len = p - G.ifs;
+ p = skip_non_whitespace(p);
+ G.ifs_whitespace = xmalloc(len + strlen(p) + 1); /* can overestimate */
+ d = mempcpy(G.ifs_whitespace, G.ifs, len);
+ while (*p) {
+ if (isspace(*p))
+ *d++ = *p;
+ p++;
+ }
+ *d = '\0';
+ }
+ } else {
+ G.ifs = defifs;
+ G.ifs_whitespace = (char*)G.ifs;
+ }
+
+#ifndef __U_BOOT__
+ IF_HUSH_JOB(pi->pgrp = -1;)
+ pi->stopped_cmds = 0;
+#endif /* !__U_BOOT__ */
+ command = &pi->cmds[0];
+ argv_expanded = NULL;
+
+#ifndef __U_BOOT__
+ if (pi->num_cmds != 1
+ || pi->followup == PIPE_BG
+ || command->cmd_type == CMD_SUBSHELL
+ ) {
+ goto must_fork;
+ }
+
+ pi->alive_cmds = 1;
+#endif /* !__U_BOOT__ */
+
+ debug_printf_exec(": group:%p argv:'%s'\n",
+ command->group, command->argv ? command->argv[0] : "NONE");
+
+ if (command->group) {
+#if ENABLE_HUSH_FUNCTIONS
+ if (command->cmd_type == CMD_FUNCDEF) {
+ /* "executing" func () { list } */
+ struct function *funcp;
+
+ funcp = new_function(command->argv[0]);
+ /* funcp->name is already set to argv[0] */
+ funcp->body = command->group;
+# if !BB_MMU
+ funcp->body_as_string = command->group_as_string;
+ command->group_as_string = NULL;
+# endif
+ command->group = NULL;
+ command->argv[0] = NULL;
+ debug_printf_exec("cmd %p has child func at %p\n", command, funcp);
+ funcp->parent_cmd = command;
+ command->child_func = funcp;
+
+ debug_printf_exec("run_pipe: return EXIT_SUCCESS\n");
+ debug_leave();
+ return EXIT_SUCCESS;
+ }
+#endif
+ /* { list } */
+ debug_printf_exec("non-subshell group\n");
+ rcode = 1; /* exitcode if redir failed */
+#ifndef __U_BOOT__
+ if (setup_redirects(command, &squirrel) == 0) {
+#endif /* !__U_BOOT__ */
+ debug_printf_exec(": run_list\n");
+//FIXME: we need to pass squirrel down into run_list()
+//for SH_STANDALONE case, or else this construct:
+// { find /proc/self/fd; true; } >FILE; cmd2
+//has no way of closing saved fd#1 for "find",
+//and in SH_STANDALONE mode, "find" is not execed,
+//therefore CLOEXEC on saved fd does not help.
+ rcode = run_list(command->group) & 0xff;
+#ifndef __U_BOOT__
+ }
+ restore_redirects(squirrel);
+#endif /* !__U_BOOT__ */
+ IF_HAS_KEYWORDS(if (pi->pi_inverted) rcode = !rcode;)
+ debug_leave();
+ debug_printf_exec("run_pipe: return %d\n", rcode);
+ return rcode;
+ }
+
+ argv = command->argv ? command->argv : (char **) &null_ptr;
+ {
+#ifndef __U_BOOT__
+ const struct built_in_command *x;
+ IF_HUSH_FUNCTIONS(const struct function *funcp;)
+ IF_NOT_HUSH_FUNCTIONS(enum { funcp = 0 };)
+ struct variable **sv_shadowed;
+#endif /* !__U_BOOT__ */
+ struct variable *old_vars;
+
+#if ENABLE_HUSH_LINENO_VAR
+ G.execute_lineno = command->lineno;
+#endif
+
+ if (argv[command->assignment_cnt] == NULL) {
+ /* Assignments, but no command.
+ * Ensure redirects take effect (that is, create files).
+ * Try "a=t >file"
+ */
+ unsigned i;
+ G.expand_exitcode = 0;
+ only_assignments:
+#ifndef __U_BOOT__
+ rcode = setup_redirects(command, &squirrel);
+ restore_redirects(squirrel);
+#endif /* !__U_BOOT__ */
+
+ /* Set shell variables */
+ i = 0;
+ while (i < command->assignment_cnt) {
+ char *p = expand_string_to_string(argv[i],
+ EXP_FLAG_ESC_GLOB_CHARS,
+ /*unbackslash:*/ 1
+ );
+#if ENABLE_HUSH_MODE_X
+ if (G_x_mode) {
+ char *eq;
+ if (i == 0)
+ x_mode_prefix();
+ x_mode_addchr(' ');
+ eq = strchrnul(p, '=');
+ if (*eq) eq++;
+ x_mode_addblock(p, (eq - p));
+ x_mode_print_optionally_squoted(eq);
+ x_mode_flush();
+ }
+#endif
+ debug_printf_env("set shell var:'%s'->'%s'\n", *argv, p);
+#ifndef __U_BOOT__
+ if (set_local_var0(p)) {
+#else /* __U_BOOT__ */
+ if (set_local_var_modern(p, /*flag:*/ 0)) {
+#endif
+ /* assignment to readonly var / putenv error? */
+ rcode = 1;
+ }
+ i++;
+ }
+ /* Redirect error sets $? to 1. Otherwise,
+ * if evaluating assignment value set $?, retain it.
+ * Else, clear $?:
+ * false; q=`exit 2`; echo $? - should print 2
+ * false; x=1; echo $? - should print 0
+ * Because of the 2nd case, we can't just use G.last_exitcode.
+ */
+ if (rcode == 0)
+ rcode = G.expand_exitcode;
+ IF_HAS_KEYWORDS(if (pi->pi_inverted) rcode = !rcode;)
+ debug_leave();
+ debug_printf_exec("run_pipe: return %d\n", rcode);
+ return rcode;
+ }
+
+ /* Expand the rest into (possibly) many strings each */
+#if defined(CMD_TEST2_SINGLEWORD_NOGLOB)
+ if (command->cmd_type == CMD_TEST2_SINGLEWORD_NOGLOB)
+ argv_expanded = expand_strvec_to_strvec_singleword_noglob(argv + command->assignment_cnt);
+ else
+#endif
+#if defined(CMD_SINGLEWORD_NOGLOB)
+ if (command->cmd_type == CMD_SINGLEWORD_NOGLOB)
+ argv_expanded = expand_strvec_to_strvec_singleword_noglob(argv + command->assignment_cnt);
+ else
+#endif
+ argv_expanded = expand_strvec_to_strvec(argv + command->assignment_cnt);
+
+ /* If someone gives us an empty string: `cmd with empty output` */
+ if (!argv_expanded[0]) {
+ free(argv_expanded);
+ /* `false` still has to set exitcode 1 */
+ G.expand_exitcode = G.last_exitcode;
+ goto only_assignments;
+ }
+
+ old_vars = NULL;
+#ifndef __U_BOOT__
+ sv_shadowed = G.shadowed_vars_pp;
+
+ /* Check if argv[0] matches any functions (this goes before bltins) */
+ IF_HUSH_FUNCTIONS(funcp = find_function(argv_expanded[0]);)
+ IF_HUSH_FUNCTIONS(x = NULL;)
+ IF_HUSH_FUNCTIONS(if (!funcp))
+ x = find_builtin(argv_expanded[0]);
+ if (x || funcp) {
+ if (x && x->b_function == builtin_exec && argv_expanded[1] == NULL) {
+ debug_printf("exec with redirects only\n");
+ /*
+ * Variable assignments are executed, but then "forgotten":
+ * a=`sleep 1;echo A` exec 3>&-; echo $a
+ * sleeps, but prints nothing.
+ */
+ enter_var_nest_level();
+ G.shadowed_vars_pp = &old_vars;
+ rcode = redirect_and_varexp_helper(command,
+ /*squirrel:*/ ERR_PTR,
+ argv_expanded
+ );
+ G.shadowed_vars_pp = sv_shadowed;
+ /* rcode=1 can be if redir file can't be opened */
+
+ goto clean_up_and_ret1;
+ }
+
+ /* Bump var nesting, or this will leak exported $a:
+ * a=b true; env | grep ^a=
+ */
+ enter_var_nest_level();
+ /* Collect all variables "shadowed" by helper
+ * (IOW: old vars overridden by "var1=val1 var2=val2 cmd..." syntax)
+ * into old_vars list:
+ */
+ G.shadowed_vars_pp = &old_vars;
+ rcode = redirect_and_varexp_helper(command, &squirrel, argv_expanded);
+ if (rcode == 0) {
+ if (!funcp) {
+ /* Do not collect *to old_vars list* vars shadowed
+ * by e.g. "local VAR" builtin (collect them
+ * in the previously nested list instead):
+ * don't want them to be restored immediately
+ * after "local" completes.
+ */
+ G.shadowed_vars_pp = sv_shadowed;
+
+ debug_printf_exec(": builtin '%s' '%s'...\n",
+ x->b_cmd, argv_expanded[1]);
+ fflush_all();
+ rcode = x->b_function(argv_expanded) & 0xff;
+ fflush_all();
+ }
+#if ENABLE_HUSH_FUNCTIONS
+ else {
+ debug_printf_exec(": function '%s' '%s'...\n",
+ funcp->name, argv_expanded[1]);
+ rcode = run_function(funcp, argv_expanded) & 0xff;
+ /*
+ * But do collect *to old_vars list* vars shadowed
+ * within function execution. To that end, restore
+ * this pointer _after_ function run:
+ */
+ G.shadowed_vars_pp = sv_shadowed;
+ }
+#endif
+ }
+ } else
+ if (ENABLE_FEATURE_SH_NOFORK && NUM_APPLETS > 1) {
+ int n = find_applet_by_name(argv_expanded[0]);
+ if (n < 0 || !APPLET_IS_NOFORK(n))
+ goto must_fork;
+
+ enter_var_nest_level();
+ /* Collect all variables "shadowed" by helper into old_vars list */
+ G.shadowed_vars_pp = &old_vars;
+ rcode = redirect_and_varexp_helper(command, &squirrel, argv_expanded);
+ G.shadowed_vars_pp = sv_shadowed;
+
+ if (rcode == 0) {
+ debug_printf_exec(": run_nofork_applet '%s' '%s'...\n",
+ argv_expanded[0], argv_expanded[1]);
+ /*
+ * Note: signals (^C) can't interrupt here.
+ * We remember them and they will be acted upon
+ * after applet returns.
+ * This makes applets which can run for a long time
+ * and/or wait for user input ineligible for NOFORK:
+ * for example, "yes" or "rm" (rm -i waits for input).
+ */
+ rcode = run_nofork_applet(n, argv_expanded);
+ }
+ } else
+ goto must_fork;
+
+ restore_redirects(squirrel);
+ clean_up_and_ret1:
+ leave_var_nest_level();
+ add_vars(old_vars);
+
+ /*
+ * Try "usleep 99999999" + ^C + "echo $?"
+ * with FEATURE_SH_NOFORK=y.
+ */
+ if (!funcp) {
+ /* It was builtin or nofork.
+ * if this would be a real fork/execed program,
+ * it should have died if a fatal sig was received.
+ * But OTOH, there was no separate process,
+ * the sig was sent to _shell_, not to non-existing
+ * child.
+ * Let's just handle ^C only, this one is obvious:
+ * we aren't ok with exitcode 0 when ^C was pressed
+ * during builtin/nofork.
+ */
+ if (sigismember(&G.pending_set, SIGINT))
+ rcode = 128 | SIGINT;
+ }
+ free(argv_expanded);
+ IF_HAS_KEYWORDS(if (pi->pi_inverted) rcode = !rcode;)
+ debug_leave();
+ debug_printf_exec("run_pipe return %d\n", rcode);
+ return rcode;
+#endif /* !__U_BOOT__ */
+ }
+
+#ifndef __U_BOOT__
+ must_fork:
+ /* NB: argv_expanded may already be created, and that
+ * might include `cmd` runs! Do not rerun it! We *must*
+ * use argv_expanded if it's non-NULL */
+
+ /* Going to fork a child per each pipe member */
+ pi->alive_cmds = 0;
+ next_infd = 0;
+#endif /* !__U_BOOT__ */
+
+ cmd_no = 0;
+ while (cmd_no < pi->num_cmds) {
+#ifndef __U_BOOT__
+ struct fd_pair pipefds;
+#if !BB_MMU
+ int sv_var_nest_level = G.var_nest_level;
+ volatile nommu_save_t nommu_save;
+ nommu_save.old_vars = NULL;
+ nommu_save.argv = NULL;
+ nommu_save.argv_from_re_execing = NULL;
+#endif
+#endif /* !__U_BOOT__ */
+ command = &pi->cmds[cmd_no];
+ cmd_no++;
+
+#ifdef __U_BOOT__
+ /* Replace argv and argc by expanded if it exists. */
+ if (argv_expanded) {
+ /*
+ * We need to save a pointer to argv, we will restore it
+ * later, so it will be freed when pipe is freed.
+ */
+ argv = command->argv;
+
+ /*
+ * After expansion, there can be more or less argument, so we need to
+ * update argc, for example:
+ * - More arguments:
+ * foo='bar quuz'
+ * echo $foo
+ * - Less arguments:
+ * echo $foo (if foo was never set)
+ */
+ command->argc = list_size(argv_expanded);
+ command->argv = argv_expanded;
+ }
+#endif /* __U_BOOT__ */
+ if (command->argv) {
+ debug_printf_exec(": pipe member '%s' '%s'...\n",
+ command->argv[0], command->argv[1]);
+ } else {
+ debug_printf_exec(": pipe member with no argv\n");
+ }
+
+#ifndef __U_BOOT__
+ /* pipes are inserted between pairs of commands */
+ pipefds.rd = 0;
+ pipefds.wr = 1;
+ if (cmd_no < pi->num_cmds)
+ xpiped_pair(pipefds);
+
+#if ENABLE_HUSH_LINENO_VAR
+ G.execute_lineno = command->lineno;
+#endif
+
+ command->pid = BB_MMU ? fork() : vfork();
+ if (!command->pid) { /* child */
+#if ENABLE_HUSH_JOB
+ disable_restore_tty_pgrp_on_exit();
+ CLEAR_RANDOM_T(&G.random_gen); /* or else $RANDOM repeats in child */
+
+ /* Every child adds itself to new process group
+ * with pgid == pid_of_first_child_in_pipe */
+ if (G.run_list_level == 1 && G_interactive_fd) {
+ pid_t pgrp;
+ pgrp = pi->pgrp;
+ if (pgrp < 0) /* true for 1st process only */
+ pgrp = getpid();
+ if (setpgid(0, pgrp) == 0
+ && pi->followup != PIPE_BG
+ && G_saved_tty_pgrp /* we have ctty */
+ ) {
+ /* We do it in *every* child, not just first,
+ * to avoid races */
+ tcsetpgrp(G_interactive_fd, pgrp);
+ }
+ }
+#endif
+ if (pi->alive_cmds == 0 && pi->followup == PIPE_BG) {
+ /* 1st cmd in backgrounded pipe
+ * should have its stdin /dev/null'ed */
+ close(0);
+ if (open(bb_dev_null, O_RDONLY))
+ xopen("/", O_RDONLY);
+ } else {
+ xmove_fd(next_infd, 0);
+ }
+ xmove_fd(pipefds.wr, 1);
+ if (pipefds.rd > 1)
+ close(pipefds.rd);
+ /* Like bash, explicit redirects override pipes,
+ * and the pipe fd (fd#1) is available for dup'ing:
+ * "cmd1 2>&1 | cmd2": fd#1 is duped to fd#2, thus stderr
+ * of cmd1 goes into pipe.
+ */
+ if (setup_redirects(command, NULL)) {
+ /* Happens when redir file can't be opened:
+ * $ hush -c 'echo FOO >&2 | echo BAR 3>/qwe/rty; echo BAZ'
+ * FOO
+ * hush: can't open '/qwe/rty': No such file or directory
+ * BAZ
+ * (echo BAR is not executed, it hits _exit(1) below)
+ */
+ _exit(1);
+ }
+
+ /* Stores to nommu_save list of env vars putenv'ed
+ * (NOMMU, on MMU we don't need that) */
+ /* cast away volatility... */
+ pseudo_exec((nommu_save_t*) &nommu_save, command, argv_expanded);
+ /* pseudo_exec() does not return */
+ }
+
+ /* parent or error */
+#if ENABLE_HUSH_FAST
+ G.count_SIGCHLD++;
+//bb_error_msg("[%d] fork in run_pipe: G.count_SIGCHLD:%d G.handled_SIGCHLD:%d", getpid(), G.count_SIGCHLD, G.handled_SIGCHLD);
+#endif
+ enable_restore_tty_pgrp_on_exit();
+#if !BB_MMU
+ /* Clean up after vforked child */
+ free(nommu_save.argv);
+ free(nommu_save.argv_from_re_execing);
+ G.var_nest_level = sv_var_nest_level;
+ remove_nested_vars();
+ add_vars(nommu_save.old_vars);
+#endif
+ free(argv_expanded);
+ argv_expanded = NULL;
+ if (command->pid < 0) { /* [v]fork failed */
+ /* Clearly indicate, was it fork or vfork */
+ bb_simple_perror_msg(BB_MMU ? "vfork"+1 : "vfork");
+ } else {
+ pi->alive_cmds++;
+#if ENABLE_HUSH_JOB
+ /* Second and next children need to know pid of first one */
+ if (pi->pgrp < 0)
+ pi->pgrp = command->pid;
+#endif
+ }
+
+ if (cmd_no > 1)
+ close(next_infd);
+ if (cmd_no < pi->num_cmds)
+ close(pipefds.wr);
+ /* Pass read (output) pipe end to next iteration */
+ next_infd = pipefds.rd;
+#else /* __U_BOOT__ */
+ /* Process the command */
+ rcode = cmd_process(G.do_repeat ? CMD_FLAG_REPEAT : 0,
+ command->argc, command->argv,
+ &(G.flag_repeat), NULL);
+
+ if (argv_expanded) {
+ /*
+ * expand_strvec_to_strvec() allocates memory to expand
+ * argv, we need to free it.
+ */
+ free(argv_expanded);
+
+ /*
+ * We also restore command->argv to its original value
+ * so no memory leak happens.
+ */
+ command->argv = argv;
+
+ /*
+ * NOTE argc exists only in U-Boot, so argv freeing does
+ * not rely on it as this code exists in BusyBox.
+ */
+ }
+#endif /* __U_BOOT__ */
+ }
+
+#ifndef __U_BOOT__
+ if (!pi->alive_cmds) {
+ debug_leave();
+ debug_printf_exec("run_pipe return 1 (all forks failed, no children)\n");
+ return 1;
+ }
+#endif /* __U_BOOT__ */
+
+ debug_leave();
+#ifndef __U_BOOT__
+ debug_printf_exec("run_pipe return -1 (%u children started)\n", pi->alive_cmds);
+ return -1;
+#else /* __U_BOOT__ */
+ debug_printf_exec("run_pipe return %d\n", rcode);
+ return rcode;
+#endif /* __U_BOOT__ */
+}
+
+/* NB: called by pseudo_exec, and therefore must not modify any
+ * global data until exec/_exit (we can be a child after vfork!) */
+static int run_list(struct pipe *pi)
+{
+#if ENABLE_HUSH_CASE
+ char *case_word = NULL;
+#endif
+#if ENABLE_HUSH_LOOPS
+ struct pipe *loop_top = NULL;
+ char **for_lcur = NULL;
+ char **for_list = NULL;
+#endif
+ smallint last_followup;
+ smalluint rcode;
+#if ENABLE_HUSH_IF || ENABLE_HUSH_CASE
+ smalluint cond_code = 0;
+#else
+ enum { cond_code = 0 };
+#endif
+#if HAS_KEYWORDS
+ smallint rword; /* RES_foo */
+ smallint last_rword; /* ditto */
+#endif
+
+#ifndef __U_BOOT__
+ debug_printf_exec("run_list lvl %d start\n", G.run_list_level);
+ debug_enter();
+#endif /* !__U_BOOT__ */
+
+#if ENABLE_HUSH_LOOPS
+ /* Check syntax for "for" */
+ {
+ struct pipe *cpipe;
+ for (cpipe = pi; cpipe; cpipe = cpipe->next) {
+ if (cpipe->res_word != RES_FOR && cpipe->res_word != RES_IN)
+ continue;
+ /* current word is FOR or IN (BOLD in comments below) */
+ if (cpipe->next == NULL) {
+ syntax_error("malformed for");
+ debug_leave();
+ debug_printf_exec("run_list lvl %d return 1\n", G.run_list_level);
+ return 1;
+ }
+ /* "FOR v; do ..." and "for v IN a b; do..." are ok */
+ if (cpipe->next->res_word == RES_DO)
+ continue;
+ /* next word is not "do". It must be "in" then ("FOR v in ...") */
+ if (cpipe->res_word == RES_IN /* "for v IN a b; not_do..."? */
+ || cpipe->next->res_word != RES_IN /* FOR v not_do_and_not_in..."? */
+ ) {
+ syntax_error("malformed for");
+ debug_leave();
+ debug_printf_exec("run_list lvl %d return 1\n", G.run_list_level);
+ return 1;
+ }
+ }
+ }
+#endif
+
+ /* Past this point, all code paths should jump to ret: label
+ * in order to return, no direct "return" statements please.
+ * This helps to ensure that no memory is leaked. */
+
+#if ENABLE_HUSH_JOB
+ G.run_list_level++;
+#endif
+
+#if HAS_KEYWORDS
+ rword = RES_NONE;
+ last_rword = RES_XXXX;
+#endif
+ last_followup = PIPE_SEQ;
+ rcode = G.last_exitcode;
+
+ /* Go through list of pipes, (maybe) executing them. */
+#ifndef __U_BOOT__
+ for (; pi; pi = IF_HUSH_LOOPS(rword == RES_DONE ? loop_top : ) pi->next) {
+#else /* __U_BOOT__ */
+ for (; pi; pi = rword == RES_DONE ? loop_top : pi->next) {
+#endif /* __U_BOOT__ */
+ int r;
+ int sv_errexit_depth;
+
+#ifndef __U_BOOT__
+ if (G.flag_SIGINT)
+ break;
+ if (G_flag_return_in_progress == 1)
+ break;
+#endif /* !__U_BOOT__ */
+
+ IF_HAS_KEYWORDS(rword = pi->res_word;)
+ debug_printf_exec(": rword:%d cond_code:%d last_rword:%d\n",
+ rword, cond_code, last_rword);
+
+ sv_errexit_depth = G.errexit_depth;
+ if (
+#if ENABLE_HUSH_IF
+ rword == RES_IF || rword == RES_ELIF ||
+#endif
+ pi->followup != PIPE_SEQ
+ ) {
+ G.errexit_depth++;
+ }
+#if ENABLE_HUSH_LOOPS
+ if ((rword == RES_WHILE || rword == RES_UNTIL || rword == RES_FOR)
+ && loop_top == NULL /* avoid bumping G.depth_of_loop twice */
+ ) {
+ /* start of a loop: remember where loop starts */
+ loop_top = pi;
+ G.depth_of_loop++;
+ }
+#endif
+ /* Still in the same "if...", "then..." or "do..." branch? */
+ if (IF_HAS_KEYWORDS(rword == last_rword &&) 1) {
+ if ((rcode == 0 && last_followup == PIPE_OR)
+ || (rcode != 0 && last_followup == PIPE_AND)
+ ) {
+ /* It is "<true> || CMD" or "<false> && CMD"
+ * and we should not execute CMD */
+ debug_printf_exec("skipped cmd because of || or &&\n");
+ last_followup = pi->followup;
+ goto dont_check_jobs_but_continue;
+ }
+ }
+ last_followup = pi->followup;
+#if ENABLE_HUSH_IF
+ if (cond_code != 0) {
+ if (rword == RES_THEN) {
+ /* if false; then ... fi has exitcode 0! */
+ G.last_exitcode = rcode = EXIT_SUCCESS;
+ /* "if <false> THEN cmd": skip cmd */
+ debug_printf_exec("skipped THEN cmd because IF condition was false\n");
+ last_rword = rword;
+ continue;
+ }
+ } else {
+ if (rword == RES_ELSE
+ || (rword == RES_ELIF && last_rword != RES_ELIF)
+ ) {
+ /* "if <true> then ... ELSE/ELIF cmd":
+ * skip cmd and all following ones */
+ debug_printf_exec("skipped ELSE/ELIF branch because IF condition was true\n");
+ break;
+ }
+ //if (rword == RES_THEN): "if <true> THEN cmd", run cmd (fall through)
+ }
+#endif
+ IF_HAS_KEYWORDS(last_rword = rword;)
+#if ENABLE_HUSH_LOOPS
+ if (rword == RES_FOR) { /* && pi->num_cmds - always == 1 */
+ if (!for_lcur) {
+ /* first loop through for */
+
+ static const char encoded_dollar_at[] ALIGN1 = {
+ SPECIAL_VAR_SYMBOL, '@' | 0x80, SPECIAL_VAR_SYMBOL, '\0'
+ }; /* encoded representation of "$@" */
+ static const char *const encoded_dollar_at_argv[] ALIGN_PTR = {
+ encoded_dollar_at, NULL
+ }; /* argv list with one element: "$@" */
+ char **vals;
+
+ G.last_exitcode = rcode = EXIT_SUCCESS;
+ vals = (char**)encoded_dollar_at_argv;
+ if (pi->next->res_word == RES_IN) {
+ /* if no variable values after "in" we skip "for" */
+ if (!pi->next->cmds[0].argv) {
+ debug_printf_exec(": null FOR: exitcode EXIT_SUCCESS\n");
+ break;
+ }
+ vals = pi->next->cmds[0].argv;
+ } /* else: "for var; do..." -> assume "$@" list */
+ /* create list of variable values */
+ debug_print_strings("for_list made from", vals);
+ for_list = expand_strvec_to_strvec(vals);
+ for_lcur = for_list;
+ debug_print_strings("for_list", for_list);
+ }
+ if (!*for_lcur) {
+ /* "for" loop is over, clean up */
+ free(for_list);
+ for_list = NULL;
+ for_lcur = NULL;
+ break;
+ }
+ /* Insert next value from for_lcur */
+ /* note: *for_lcur already has quotes removed, $var expanded, etc */
+#ifndef __U_BOOT__
+ set_local_var_from_halves(pi->cmds[0].argv[0], *for_lcur++);
+#else /* __U_BOOT__ */
+ /* We cannot use xasprintf, so we emulate it. */
+ char *full_var;
+ char *var = pi->cmds[0].argv[0];
+ char *val = *for_lcur++;
+
+ /* + 1 to take into account =. */
+ full_var = xmalloc(strlen(var) + strlen(val) + 1);
+ sprintf(full_var, "%s=%s", var, val);
+
+ set_local_var_modern(full_var, /*flag:*/ 0);
+#endif /* __U_BOOT__ */
+ continue;
+ }
+ if (rword == RES_IN) {
+ continue; /* "for v IN list;..." - "in" has no cmds anyway */
+ }
+ if (rword == RES_DONE) {
+ continue; /* "done" has no cmds too */
+ }
+#endif
+#if ENABLE_HUSH_CASE
+ if (rword == RES_CASE) {
+ debug_printf_exec("CASE cond_code:%d\n", cond_code);
+ case_word = expand_string_to_string(pi->cmds->argv[0],
+ EXP_FLAG_ESC_GLOB_CHARS, /*unbackslash:*/ 1);
+ debug_printf_exec("CASE word1:'%s'\n", case_word);
+ //unbackslash(case_word);
+ //debug_printf_exec("CASE word2:'%s'\n", case_word);
+ continue;
+ }
+ if (rword == RES_MATCH) {
+ char **argv;
+
+ debug_printf_exec("MATCH cond_code:%d\n", cond_code);
+ if (!case_word) /* "case ... matched_word) ... WORD)": we executed selected branch, stop */
+ break;
+ /* all prev words didn't match, does this one match? */
+ argv = pi->cmds->argv;
+ while (*argv) {
+ char *pattern;
+ debug_printf_exec("expand_string_to_string('%s')\n", *argv);
+ pattern = expand_string_to_string(*argv,
+ EXP_FLAG_ESC_GLOB_CHARS,
+ /*unbackslash:*/ 0
+ );
+ /* TODO: which FNM_xxx flags to use? */
+ cond_code = (fnmatch(pattern, case_word, /*flags:*/ 0) != 0);
+ debug_printf_exec("cond_code=fnmatch(pattern:'%s',str:'%s'):%d\n",
+ pattern, case_word, cond_code);
+ free(pattern);
+ if (cond_code == 0) {
+ /* match! we will execute this branch */
+ free(case_word);
+ case_word = NULL; /* make future "word)" stop */
+ break;
+ }
+ argv++;
+ }
+ continue;
+ }
+ if (rword == RES_CASE_BODY) { /* inside of a case branch */
+ debug_printf_exec("CASE_BODY cond_code:%d\n", cond_code);
+ if (cond_code != 0)
+ continue; /* not matched yet, skip this pipe */
+ }
+ if (rword == RES_ESAC) {
+ debug_printf_exec("ESAC cond_code:%d\n", cond_code);
+ if (case_word) {
+ /* "case" did not match anything: still set $? (to 0) */
+ G.last_exitcode = rcode = EXIT_SUCCESS;
+ }
+ }
+#endif
+ /* Just pressing <enter> in shell should check for jobs.
+ * OTOH, in non-interactive shell this is useless
+ * and only leads to extra job checks */
+ if (pi->num_cmds == 0) {
+#ifndef __U_BOOT__
+ if (G_interactive_fd)
+ goto check_jobs_and_continue;
+#endif /* !__U_BOOT__ */
+ continue;
+ }
+
+ /* After analyzing all keywords and conditions, we decided
+ * to execute this pipe. NB: have to do checkjobs(NULL)
+ * after run_pipe to collect any background children,
+ * even if list execution is to be stopped. */
+ debug_printf_exec(": run_pipe with %d members\n", pi->num_cmds);
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_LOOPS
+ G.flag_break_continue = 0;
+#endif
+#endif /* !__U_BOOT__ */
+#ifndef __U_BOOT__
+ rcode = r = G.o_opt[OPT_O_NOEXEC] ? 0 : run_pipe(pi);
+ /* NB: rcode is a smalluint, r is int */
+#else /* __U_BOOT__ */
+ rcode = r = run_pipe(pi); /* NB: rcode is a smalluint, r is int */
+ if (r <= EXIT_RET_CODE) {
+ int previous_rcode = G.last_exitcode;
+ /*
+ * This magic is to get the exit code given by the user.
+ * Contrary to old shell code, we use + EXIT_RET_CODE as EXIT_RET_CODE
+ * equals -2.
+ */
+ G.last_exitcode = -r + EXIT_RET_CODE;
+
+ /*
+ * This case deals with the following:
+ * => setenv inner 'echo entry inner; exit; echo inner done'
+ * => setenv outer 'echo entry outer; run inner; echo outer done'
+ * => run outer
+ * So, if we are in inner, we need to break and not run the other
+ * commands.
+ * Otherwise, we just continue in outer.
+ * As return code are propagated, we use the previous value to check if
+ * exit was just called or was propagated.
+ */
+ if (previous_rcode != r) {
+ /*
+ * If run from run_command, run_command_flags will be set, so we check
+ * this to know if we are in main input shell.
+ */
+ if (!G.run_command_flags)
+ printf("exit not allowed from main input shell.\n");
+
+ break;
+ }
+ continue;
+ }
+#endif /* __U_BOOT__ */
+ if (r != -1) {
+ /* We ran a builtin, function, or group.
+ * rcode is already known
+ * and we don't need to wait for anything. */
+ debug_printf_exec(": builtin/func exitcode %d\n", rcode);
+ G.last_exitcode = rcode;
+#ifndef __U_BOOT__
+ check_and_run_traps();
+#endif /* !__U_BOOT__ */
+#if ENABLE_HUSH_TRAP && ENABLE_HUSH_FUNCTIONS
+ rcode = G.last_exitcode; /* "return" in trap can change it, read back */
+#endif
+#ifndef __U_BOOT__
+#if ENABLE_HUSH_LOOPS
+ /* Was it "break" or "continue"? */
+ if (G.flag_break_continue) {
+ smallint fbc = G.flag_break_continue;
+ /* We might fall into outer *loop*,
+ * don't want to break it too */
+ if (loop_top) {
+ G.depth_break_continue--;
+ if (G.depth_break_continue == 0)
+ G.flag_break_continue = 0;
+ /* else: e.g. "continue 2" should *break* once, *then* continue */
+ } /* else: "while... do... { we are here (innermost list is not a loop!) };...done" */
+ if (G.depth_break_continue != 0 || fbc == BC_BREAK) {
+ checkjobs(NULL, 0 /*(no pid to wait for)*/);
+ break;
+ }
+ /* "continue": simulate end of loop */
+ rword = RES_DONE;
+ continue;
+ }
+#endif
+ if (G_flag_return_in_progress == 1) {
+ checkjobs(NULL, 0 /*(no pid to wait for)*/);
+ break;
+ }
+
+ } else if (pi->followup == PIPE_BG) {
+ /* What does bash do with attempts to background builtins? */
+ /* even bash 3.2 doesn't do that well with nested bg:
+ * try "{ { sleep 10; echo DEEP; } & echo HERE; } &".
+ * I'm NOT treating inner &'s as jobs */
+#if ENABLE_HUSH_JOB
+ if (G.run_list_level == 1)
+ insert_job_into_table(pi);
+#endif
+ /* Last command's pid goes to $! */
+ G.last_bg_pid = pi->cmds[pi->num_cmds - 1].pid;
+ G.last_bg_pid_exitcode = 0;
+ debug_printf_exec(": cmd&: exitcode EXIT_SUCCESS\n");
+/* Check pi->pi_inverted? "! sleep 1 & echo $?": bash says 1. dash and ash say 0 */
+ rcode = EXIT_SUCCESS;
+ goto check_traps;
+ } else {
+#if ENABLE_HUSH_JOB
+ if (G.run_list_level == 1 && G_interactive_fd) {
+ /* Waits for completion, then fg's main shell */
+ rcode = checkjobs_and_fg_shell(pi);
+ debug_printf_exec(": checkjobs_and_fg_shell exitcode %d\n", rcode);
+ goto check_traps;
+ }
+#endif
+ /* This one just waits for completion */
+ rcode = checkjobs(pi, 0 /*(no pid to wait for)*/);
+ debug_printf_exec(": checkjobs exitcode %d\n", rcode);
+ check_traps:
+ G.last_exitcode = rcode;
+ check_and_run_traps();
+#if ENABLE_HUSH_TRAP && ENABLE_HUSH_FUNCTIONS
+ rcode = G.last_exitcode; /* "return" in trap can change it, read back */
+#endif
+ }
+#endif /* !__U_BOOT__ */
+
+#ifndef __U_BOOT__
+ /* Handle "set -e" */
+ if (rcode != 0 && G.o_opt[OPT_O_ERREXIT]) {
+ debug_printf_exec("ERREXIT:1 errexit_depth:%d\n", G.errexit_depth);
+ if (G.errexit_depth == 0)
+ hush_exit(rcode);
+ }
+#else /* __U_BOOT__ */
+ } /* if (r != -1) */
+#endif /* __U_BOOT__ */
+ G.errexit_depth = sv_errexit_depth;
+
+ /* Analyze how result affects subsequent commands */
+#if ENABLE_HUSH_IF
+ if (rword == RES_IF || rword == RES_ELIF) {
+ debug_printf_exec("cond_code=rcode:%d\n", rcode);
+ cond_code = rcode;
+ }
+#endif
+#ifndef __U_BOOT__
+ check_jobs_and_continue:
+ checkjobs(NULL, 0 /*(no pid to wait for)*/);
+#endif /* !__U_BOOT__ */
+ dont_check_jobs_but_continue: ;
+#if ENABLE_HUSH_LOOPS
+ /* Beware of "while false; true; do ..."! */
+ if (pi->next
+ && (pi->next->res_word == RES_DO || pi->next->res_word == RES_DONE)
+ /* check for RES_DONE is needed for "while ...; do \n done" case */
+ ) {
+ if (rword == RES_WHILE) {
+ if (rcode) {
+ /* "while false; do...done" - exitcode 0 */
+ G.last_exitcode = rcode = EXIT_SUCCESS;
+ debug_printf_exec(": while expr is false: breaking (exitcode:EXIT_SUCCESS)\n");
+ break;
+ }
+ }
+ if (rword == RES_UNTIL) {
+ if (!rcode) {
+ debug_printf_exec(": until expr is true: breaking\n");
+ break;
+ }
+ }
+ }
+#endif
+ } /* for (pi) */
+
+#if ENABLE_HUSH_JOB
+ G.run_list_level--;
+#endif
+#if ENABLE_HUSH_LOOPS
+ if (loop_top)
+ G.depth_of_loop--;
+ free(for_list);
+#endif
+#if ENABLE_HUSH_CASE
+ free(case_word);
+#endif
+#ifndef __U_BOOT__
+ debug_leave();
+ debug_printf_exec("run_list lvl %d return %d\n", G.run_list_level, rcode);
+#endif /* !__U_BOOT__ */
+ return rcode;
+}
+
+/* Select which version we will use */
+static int run_and_free_list(struct pipe *pi)
+{
+ int rcode = 0;
+ debug_printf_exec("run_and_free_list entered\n");
+#ifndef __U_BOOT__
+ if (!G.o_opt[OPT_O_NOEXEC]) {
+#endif /* !__U_BOOT__ */
+ debug_printf_exec(": run_list: 1st pipe with %d cmds\n", pi->num_cmds);
+ rcode = run_list(pi);
+#ifndef __U_BOOT__
+ }
+#endif /* !__U_BOOT__ */
+ /* free_pipe_list has the side effect of clearing memory.
+ * In the long run that function can be merged with run_list,
+ * but doing that now would hobble the debugging effort. */
+ free_pipe_list(pi);
+ debug_printf_exec("run_and_free_list return %d\n", rcode);
+ return rcode;
+}
+
+
+#ifndef __U_BOOT__
+static void install_sighandlers(unsigned mask)
+{
+ sighandler_t old_handler;
+ unsigned sig = 0;
+ while ((mask >>= 1) != 0) {
+ sig++;
+ if (!(mask & 1))
+ continue;
+ old_handler = install_sighandler(sig, pick_sighandler(sig));
+ /* POSIX allows shell to re-enable SIGCHLD
+ * even if it was SIG_IGN on entry.
+ * Therefore we skip IGN check for it:
+ */
+ if (sig == SIGCHLD)
+ continue;
+ /* Interactive bash re-enables SIGHUP which is SIG_IGNed on entry.
+ * Try:
+ * trap '' hup; bash; echo RET # type "kill -hup $$", see SIGHUP having effect
+ * trap '' hup; bash -c 'kill -hup $$; echo ALIVE' # here SIGHUP is SIG_IGNed
+ */
+ if (sig == SIGHUP && G_interactive_fd)
+ continue;
+ /* Unless one of the above signals, is it SIG_IGN? */
+ if (old_handler == SIG_IGN) {
+ /* oops... restore back to IGN, and record this fact */
+ install_sighandler(sig, old_handler);
+#if ENABLE_HUSH_TRAP
+ if (!G_traps)
+ G_traps = xzalloc(sizeof(G_traps[0]) * NSIG);
+ free(G_traps[sig]);
+ G_traps[sig] = xzalloc(1); /* == xstrdup(""); */
+#endif
+ }
+ }
+}
+
+/* Called a few times only (or even once if "sh -c") */
+static void install_special_sighandlers(void)
+{
+ unsigned mask;
+
+ /* Which signals are shell-special? */
+ mask = (1 << SIGQUIT) | (1 << SIGCHLD);
+ if (G_interactive_fd) {
+ mask |= SPECIAL_INTERACTIVE_SIGS;
+ if (G_saved_tty_pgrp) /* we have ctty, job control sigs work */
+ mask |= SPECIAL_JOBSTOP_SIGS;
+ }
+ /* Careful, do not re-install handlers we already installed */
+ if (G.special_sig_mask != mask) {
+ unsigned diff = mask & ~G.special_sig_mask;
+ G.special_sig_mask = mask;
+ install_sighandlers(diff);
+ }
+}
+
+#if ENABLE_HUSH_JOB
+/* helper */
+/* Set handlers to restore tty pgrp and exit */
+static void install_fatal_sighandlers(void)
+{
+ unsigned mask;
+
+ /* We will restore tty pgrp on these signals */
+ mask = 0
+ /*+ (1 << SIGILL ) * HUSH_DEBUG*/
+ /*+ (1 << SIGFPE ) * HUSH_DEBUG*/
+ + (1 << SIGBUS ) * HUSH_DEBUG
+ + (1 << SIGSEGV) * HUSH_DEBUG
+ /*+ (1 << SIGTRAP) * HUSH_DEBUG*/
+ + (1 << SIGABRT)
+ /* bash 3.2 seems to handle these just like 'fatal' ones */
+ + (1 << SIGPIPE)
+ + (1 << SIGALRM)
+ /* if we are interactive, SIGHUP, SIGTERM and SIGINT are special sigs.
+ * if we aren't interactive... but in this case
+ * we never want to restore pgrp on exit, and this fn is not called
+ */
+ /*+ (1 << SIGHUP )*/
+ /*+ (1 << SIGTERM)*/
+ /*+ (1 << SIGINT )*/
+ ;
+ G_fatal_sig_mask = mask;
+
+ install_sighandlers(mask);
+}
+#endif
+
+static int set_mode(int state, char mode, const char *o_opt)
+{
+ int idx;
+ switch (mode) {
+ case 'n':
+ /* set -n has no effect in interactive shell */
+ /* Try: while set -n; do echo $-; done */
+ if (!G_interactive_fd)
+ G.o_opt[OPT_O_NOEXEC] = state;
+ break;
+ case 'x':
+ IF_HUSH_MODE_X(G_x_mode = state;)
+ IF_HUSH_MODE_X(if (G.x_mode_fd <= 0) G.x_mode_fd = dup_CLOEXEC(2, 10);)
+ break;
+ case 'e':
+ G.o_opt[OPT_O_ERREXIT] = state;
+ break;
+ case 'o':
+ if (!o_opt) {
+ /* "set -o" or "set +o" without parameter.
+ * in bash, set -o produces this output:
+ * pipefail off
+ * and set +o:
+ * set +o pipefail
+ * We always use the second form.
+ */
+ const char *p = o_opt_strings;
+ idx = 0;
+ while (*p) {
+ printf("set %co %s\n", (G.o_opt[idx] ? '-' : '+'), p);
+ idx++;
+ p += strlen(p) + 1;
+ }
+ break;
+ }
+ idx = index_in_strings(o_opt_strings, o_opt);
+ if (idx >= 0) {
+ G.o_opt[idx] = state;
+ break;
+ }
+ /* fall through to error */
+ default:
+ return EXIT_FAILURE;
+ }
+ return EXIT_SUCCESS;
+}
+
+int hush_main(int argc, char **argv) MAIN_EXTERNALLY_VISIBLE;
+int hush_main(int argc, char **argv)
+{
+ pid_t cached_getpid;
+ enum {
+ OPT_login = (1 << 0),
+ };
+ unsigned flags;
+#if !BB_MMU
+ unsigned builtin_argc = 0;
+#endif
+ char **e;
+ struct variable *cur_var;
+ struct variable *shell_ver;
+
+ INIT_G();
+ if (EXIT_SUCCESS != 0) /* if EXIT_SUCCESS == 0, it is already done */
+ G.last_exitcode = EXIT_SUCCESS;
+#if !BB_MMU
+ /* "Big heredoc" support via "sh -< STRING" invocation.
+ * Check it first (do not bother to run the usual init code,
+ * it is not needed for this case).
+ */
+ if (argv[1]
+ && argv[1][0] == '-' && argv[1][1] == '<' /*&& !argv[1][2]*/
+ /*&& argv[2] && !argv[3] - we don't check some conditions */
+ ) {
+ full_write1_str(argv[2]);
+ _exit(0);
+ }
+ G.argv0_for_re_execing = argv[0];
+#endif
+#if ENABLE_HUSH_TRAP
+# if ENABLE_HUSH_FUNCTIONS
+ G.return_exitcode = -1;
+# endif
+ G.pre_trap_exitcode = -1;
+#endif
+
+#if ENABLE_HUSH_FAST
+ G.count_SIGCHLD++; /* ensure it is != G.handled_SIGCHLD */
+#endif
+
+ cached_getpid = getpid(); /* for tcsetpgrp() during init */
+ G.root_pid = cached_getpid; /* for $PID (NOMMU can override via -$HEXPID:HEXPPID:...) */
+ G.root_ppid = getppid(); /* for $PPID (NOMMU can override) */
+
+ /* Deal with HUSH_VERSION */
+ debug_printf_env("unsetenv '%s'\n", "HUSH_VERSION");
+ unsetenv("HUSH_VERSION"); /* in case it exists in initial env */
+ shell_ver = xzalloc(sizeof(*shell_ver));
+ shell_ver->flg_export = 1;
+ shell_ver->flg_read_only = 1;
+ /* Code which handles ${var<op>...} needs writable values for all variables,
+ * therefore we xstrdup: */
+ shell_ver->varstr = xstrdup(hush_version_str);
+
+ /* Create shell local variables from the values
+ * currently living in the environment */
+ G.top_var = shell_ver;
+ cur_var = G.top_var;
+ e = environ;
+ if (e) while (*e) {
+ char *value = strchr(*e, '=');
+ if (value) { /* paranoia */
+ cur_var->next = xzalloc(sizeof(*cur_var));
+ cur_var = cur_var->next;
+ cur_var->varstr = *e;
+ cur_var->max_len = strlen(*e);
+ cur_var->flg_export = 1;
+ }
+ e++;
+ }
+ /* (Re)insert HUSH_VERSION into env (AFTER we scanned the env!) */
+ debug_printf_env("putenv '%s'\n", shell_ver->varstr);
+ putenv(shell_ver->varstr);
+
+ /* Export PWD */
+ set_pwd_var(SETFLAG_EXPORT);
+
+#if BASH_HOSTNAME_VAR
+ /* Set (but not export) HOSTNAME unless already set */
+ if (!get_local_var_value("HOSTNAME")) {
+ struct utsname uts;
+ uname(&uts);
+ set_local_var_from_halves("HOSTNAME", uts.nodename);
+ }
+#endif
+ /* IFS is not inherited from the parent environment */
+ set_local_var_from_halves("IFS", defifs);
+
+ if (!get_local_var_value("PATH"))
+ set_local_var_from_halves("PATH", bb_default_root_path);
+
+ /* PS1/PS2 are set later, if we determine that we are interactive */
+
+ /* bash also exports SHLVL and _,
+ * and sets (but doesn't export) the following variables:
+ * BASH=/bin/bash
+ * BASH_VERSINFO=([0]="3" [1]="2" [2]="0" [3]="1" [4]="release" [5]="i386-pc-linux-gnu")
+ * BASH_VERSION='3.2.0(1)-release'
+ * HOSTTYPE=i386
+ * MACHTYPE=i386-pc-linux-gnu
+ * OSTYPE=linux-gnu
+ * PPID=<NNNNN> - we also do it elsewhere
+ * EUID=<NNNNN>
+ * UID=<NNNNN>
+ * GROUPS=()
+ * LINES=<NNN>
+ * COLUMNS=<NNN>
+ * BASH_ARGC=()
+ * BASH_ARGV=()
+ * BASH_LINENO=()
+ * BASH_SOURCE=()
+ * DIRSTACK=()
+ * PIPESTATUS=([0]="0")
+ * HISTFILE=/<xxx>/.bash_history
+ * HISTFILESIZE=500
+ * HISTSIZE=500
+ * MAILCHECK=60
+ * PATH=/usr/gnu/bin:/usr/local/bin:/bin:/usr/bin:.
+ * SHELL=/bin/bash
+ * SHELLOPTS=braceexpand:emacs:hashall:histexpand:history:interactive-comments:monitor
+ * TERM=dumb
+ * OPTERR=1
+ * OPTIND=1
+ * PS4='+ '
+ */
+
+#if NUM_SCRIPTS > 0
+ if (argc < 0) {
+ char *script = get_script_content(-argc - 1);
+ G.global_argv = argv;
+ G.global_argc = string_array_len(argv);
+ //install_special_sighandlers(); - needed?
+ parse_and_run_string(script);
+ goto final_return;
+ }
+#endif
+
+ /* Initialize some more globals to non-zero values */
+ die_func = restore_ttypgrp_and__exit;
+
+ /* Shell is non-interactive at first. We need to call
+ * install_special_sighandlers() if we are going to execute "sh <script>",
+ * "sh -c <cmds>" or login shell's /etc/profile and friends.
+ * If we later decide that we are interactive, we run install_special_sighandlers()
+ * in order to intercept (more) signals.
+ */
+
+ /* Parse options */
+ /* http://www.opengroup.org/onlinepubs/9699919799/utilities/sh.html */
+ flags = (argv[0] && argv[0][0] == '-') ? OPT_login : 0;
+ while (1) {
+ int opt = getopt(argc, argv, "+" /* stop at 1st non-option */
+ "cexinsl"
+#if !BB_MMU
+ "$:R:V:"
+# if ENABLE_HUSH_LINENO_VAR
+ "L:"
+# endif
+# if ENABLE_HUSH_FUNCTIONS
+ "F:"
+# endif
+#endif
+ );
+ if (opt <= 0)
+ break;
+ switch (opt) {
+ case 'c':
+ /* Note: -c is not an option with param!
+ * "hush -c -l SCRIPT" is valid. "hush -cSCRIPT" is not.
+ */
+ G.opt_c = 1;
+ break;
+ case 'i':
+ /* Well, we cannot just declare interactiveness,
+ * we have to have some stuff (ctty, etc) */
+ /* G_interactive_fd++; */
+//There are a few cases where bash -i -c 'SCRIPT'
+//has visible effect (differs from bash -c 'SCRIPT'):
+//it ignores TERM:
+// bash -i -c 'kill $$; echo ALIVE'
+// ALIVE
+//it resets SIG_IGNed HUP to SIG_DFL:
+// trap '' hup; bash -i -c 'kill -hup $$; echo ALIVE'
+// Hangup [the message is not printed by bash, it's the shell which started it]
+//is talkative about jobs and exiting:
+// bash -i -c 'sleep 1 & exit'
+// [1] 16170
+// exit
+//includes $ENV file (only if run as "sh"):
+// echo last >/tmp/ENV; ENV=/tmp/ENV sh -i -c 'echo HERE'
+// last: cannot open /var/log/wtmp: No such file or directory
+// HERE
+//(under "bash", it's the opposite: it runs $BASH_ENV file only *without* -i).
+//
+//ash -i -c 'sleep 3; sleep 3', on ^C, drops into a prompt instead of exiting
+//(this may be a bug, bash does not do this).
+//(ash -i -c 'sleep 3' won't show this, the last command gets auto-"exec"ed)
+//
+//None of the above feel like useful features people would rely on.
+ break;
+ case 's':
+ G.opt_s = 1;
+ break;
+ case 'l':
+ flags |= OPT_login;
+ break;
+#if !BB_MMU
+ case '$': {
+ unsigned long long empty_trap_mask;
+
+ G.root_pid = bb_strtou(optarg, &optarg, 16);
+ optarg++;
+ G.root_ppid = bb_strtou(optarg, &optarg, 16);
+ optarg++;
+ G.last_bg_pid = bb_strtou(optarg, &optarg, 16);
+ optarg++;
+ G.last_exitcode = bb_strtou(optarg, &optarg, 16);
+ optarg++;
+ builtin_argc = bb_strtou(optarg, &optarg, 16);
+ optarg++;
+ empty_trap_mask = bb_strtoull(optarg, &optarg, 16);
+ if (empty_trap_mask != 0) {
+ IF_HUSH_TRAP(int sig;)
+ install_special_sighandlers();
+# if ENABLE_HUSH_TRAP
+ G_traps = xzalloc(sizeof(G_traps[0]) * NSIG);
+ for (sig = 1; sig < NSIG; sig++) {
+ if (empty_trap_mask & (1LL << sig)) {
+ G_traps[sig] = xzalloc(1); /* == xstrdup(""); */
+ install_sighandler(sig, SIG_IGN);
+ }
+ }
+# endif
+ }
+# if ENABLE_HUSH_LOOPS
+ optarg++;
+ G.depth_of_loop = bb_strtou(optarg, &optarg, 16);
+# endif
+ /* Suppress "killed by signal" message, -$ hack is used
+ * for subshells: echo `sh -c 'kill -9 $$'`
+ * should be silent.
+ */
+ IF_HUSH_JOB(G.run_list_level = 1;)
+# if ENABLE_HUSH_FUNCTIONS
+ /* nommu uses re-exec trick for "... | func | ...",
+ * should allow "return".
+ * This accidentally allows returns in subshells.
+ */
+ G_flag_return_in_progress = -1;
+# endif
+ break;
+ }
+ case 'R':
+ case 'V':
+ set_local_var(xstrdup(optarg), opt == 'R' ? SETFLAG_MAKE_RO : 0);
+ break;
+# if ENABLE_HUSH_LINENO_VAR
+ case 'L':
+ G.parse_lineno = xatou(optarg);
+ break;
+# endif
+# if ENABLE_HUSH_FUNCTIONS
+ case 'F': {
+ struct function *funcp = new_function(optarg);
+ /* funcp->name is already set to optarg */
+ /* funcp->body is set to NULL. It's a special case. */
+ funcp->body_as_string = argv[optind];
+ optind++;
+ break;
+ }
+# endif
+#endif
+ /*case '?': invalid option encountered (set_mode('?') will fail) */
+ /*case 'n':*/
+ /*case 'x':*/
+ /*case 'e':*/
+ default:
+ if (set_mode(1, opt, NULL) == 0) /* no error */
+ break;
+ bb_show_usage();
+ }
+ } /* option parsing loop */
+
+ /* Skip options. Try "hush -l": $1 should not be "-l"! */
+ G.global_argc = argc - (optind - 1);
+ G.global_argv = argv + (optind - 1);
+ G.global_argv[0] = argv[0];
+
+ /* If we are login shell... */
+ if (flags & OPT_login) {
+ const char *hp = NULL;
+ HFILE *input;
+
+ debug_printf("sourcing /etc/profile\n");
+ input = hfopen("/etc/profile");
+ run_profile:
+ if (input != NULL) {
+ install_special_sighandlers();
+ parse_and_run_file(input);
+ hfclose(input);
+ }
+ /* bash: after sourcing /etc/profile,
+ * tries to source (in the given order):
+ * ~/.bash_profile, ~/.bash_login, ~/.profile,
+ * stopping on first found. --noprofile turns this off.
+ * bash also sources ~/.bash_logout on exit.
+ * If called as sh, skips .bash_XXX files.
+ */
+ if (!hp) { /* unless we looped on the "goto" already */
+ hp = get_local_var_value("HOME");
+ if (hp && hp[0]) {
+ debug_printf("sourcing ~/.profile\n");
+ hp = concat_path_file(hp, ".profile");
+ input = hfopen(hp);
+ free((char*)hp);
+ goto run_profile;
+ }
+ }
+ }
+
+#ifndef __U_BOOT__
+ /* -c takes effect *after* -l */
+ if (G.opt_c) {
+ /* Possibilities:
+ * sh ... -c 'script'
+ * sh ... -c 'script' ARG0 [ARG1...]
+ * On NOMMU, if builtin_argc != 0,
+ * sh ... -c 'builtin' BARGV... "" ARG0 [ARG1...]
+ * "" needs to be replaced with NULL
+ * and BARGV vector fed to builtin function.
+ * Note: the form without ARG0 never happens:
+ * sh ... -c 'builtin' BARGV... ""
+ */
+ char *script;
+
+ install_special_sighandlers();
+
+ G.global_argc--;
+ G.global_argv++;
+#if !BB_MMU
+ if (builtin_argc) {
+ /* -c 'builtin' [BARGV...] "" ARG0 [ARG1...] */
+ const struct built_in_command *x;
+ x = find_builtin(G.global_argv[0]);
+ if (x) { /* paranoia */
+ argv = G.global_argv;
+ G.global_argc -= builtin_argc + 1; /* skip [BARGV...] "" */
+ G.global_argv += builtin_argc + 1;
+ G.global_argv[-1] = NULL; /* replace "" */
+ G.last_exitcode = x->b_function(argv);
+ }
+ goto final_return;
+ }
+#endif
+
+ script = G.global_argv[0];
+ if (!script)
+ bb_error_msg_and_die(bb_msg_requires_arg, "-c");
+ if (!G.global_argv[1]) {
+ /* -c 'script' (no params): prevent empty $0 */
+ G.global_argv[0] = argv[0];
+ } else { /* else -c 'script' ARG0 [ARG1...]: $0 is ARG0 */
+ G.global_argc--;
+ G.global_argv++;
+ }
+ parse_and_run_string(script);
+ goto final_return;
+ }
+
+ /* -s is: hush -s ARGV1 ARGV2 (no SCRIPT) */
+ if (!G.opt_s && G.global_argv[1]) {
+ HFILE *input;
+ /*
+ * "bash <script>" (which is never interactive (unless -i?))
+ * sources $BASH_ENV here (without scanning $PATH).
+ * If called as sh, does the same but with $ENV.
+ * Also NB, per POSIX, $ENV should undergo parameter expansion.
+ */
+ G.global_argc--;
+ G.global_argv++;
+ debug_printf("running script '%s'\n", G.global_argv[0]);
+ xfunc_error_retval = 127; /* for "hush /does/not/exist" case */
+ input = hfopen(G.global_argv[0]);
+ if (!input) {
+ bb_simple_perror_msg_and_die(G.global_argv[0]);
+ }
+ xfunc_error_retval = 1;
+ install_special_sighandlers();
+ parse_and_run_file(input);
+#if ENABLE_FEATURE_CLEAN_UP
+ hfclose(input);
+#endif
+ goto final_return;
+ }
+ /* "implicit" -s: bare interactive hush shows 's' in $- */
+ G.opt_s = 1;
+
+#endif /* __U_BOOT__ */
+ /* Up to here, shell was non-interactive. Now it may become one.
+ * NB: don't forget to (re)run install_special_sighandlers() as needed.
+ */
+
+ /* A shell is interactive if the '-i' flag was given,
+ * or if all of the following conditions are met:
+ * no -c command
+ * no arguments remaining or the -s flag given
+ * standard input is a terminal
+ * standard output is a terminal
+ * Refer to Posix.2, the description of the 'sh' utility.
+ */
+#if ENABLE_HUSH_JOB
+ if (isatty(STDIN_FILENO) && isatty(STDOUT_FILENO)) {
+ G_saved_tty_pgrp = tcgetpgrp(STDIN_FILENO);
+ debug_printf("saved_tty_pgrp:%d\n", G_saved_tty_pgrp);
+ if (G_saved_tty_pgrp < 0)
+ G_saved_tty_pgrp = 0;
+
+ /* try to dup stdin to high fd#, >= 255 */
+ G_interactive_fd = dup_CLOEXEC(STDIN_FILENO, 254);
+ if (G_interactive_fd < 0) {
+ /* try to dup to any fd */
+ G_interactive_fd = dup(STDIN_FILENO);
+ if (G_interactive_fd < 0) {
+ /* give up */
+ G_interactive_fd = 0;
+ G_saved_tty_pgrp = 0;
+ }
+ }
+ }
+ debug_printf("interactive_fd:%d\n", G_interactive_fd);
+ if (G_interactive_fd) {
+ close_on_exec_on(G_interactive_fd);
+
+ if (G_saved_tty_pgrp) {
+ /* If we were run as 'hush &', sleep until we are
+ * in the foreground (tty pgrp == our pgrp).
+ * If we get started under a job aware app (like bash),
+ * make sure we are now in charge so we don't fight over
+ * who gets the foreground */
+ while (1) {
+ pid_t shell_pgrp = getpgrp();
+ G_saved_tty_pgrp = tcgetpgrp(G_interactive_fd);
+ if (G_saved_tty_pgrp == shell_pgrp)
+ break;
+ /* send TTIN to ourself (should stop us) */
+ kill(- shell_pgrp, SIGTTIN);
+ }
+ }
+
+ /* Install more signal handlers */
+ install_special_sighandlers();
+
+ if (G_saved_tty_pgrp) {
+ /* Set other signals to restore saved_tty_pgrp */
+ install_fatal_sighandlers();
+ /* Put ourselves in our own process group
+ * (bash, too, does this only if ctty is available) */
+ bb_setpgrp(); /* is the same as setpgid(our_pid, our_pid); */
+ /* Grab control of the terminal */
+ tcsetpgrp(G_interactive_fd, cached_getpid);
+ }
+ enable_restore_tty_pgrp_on_exit();
+
+# if ENABLE_FEATURE_EDITING
+ G.line_input_state = new_line_input_t(FOR_SHELL);
+# if ENABLE_FEATURE_TAB_COMPLETION
+ G.line_input_state->get_exe_name = hush_command_name;
+# endif
+# if EDITING_HAS_sh_get_var
+ G.line_input_state->sh_get_var = get_local_var_value;
+# endif
+# endif
+# if ENABLE_HUSH_SAVEHISTORY && MAX_HISTORY > 0
+ {
+ const char *hp = get_local_var_value("HISTFILE");
+ if (!hp) {
+ hp = get_local_var_value("HOME");
+ if (hp)
+ hp = concat_path_file(hp, ".hush_history");
+ } else {
+ hp = xstrdup(hp);
+ }
+ if (hp) {
+ G.line_input_state->hist_file = hp;
+ //set_local_var(xasprintf("HISTFILE=%s", ...));
+ }
+# if ENABLE_FEATURE_SH_HISTFILESIZE
+ hp = get_local_var_value("HISTFILESIZE");
+ G.line_input_state->max_history = size_from_HISTFILESIZE(hp);
+# endif
+ }
+# endif
+ } else {
+ install_special_sighandlers();
+ }
+#elif ENABLE_HUSH_INTERACTIVE
+ /* No job control compiled in, only prompt/line editing */
+ if (isatty(STDIN_FILENO) && isatty(STDOUT_FILENO)) {
+ G_interactive_fd = dup_CLOEXEC(STDIN_FILENO, 254);
+ if (G_interactive_fd < 0) {
+ /* try to dup to any fd */
+ G_interactive_fd = dup_CLOEXEC(STDIN_FILENO, -1);
+ if (G_interactive_fd < 0)
+ /* give up */
+ G_interactive_fd = 0;
+ }
+ }
+ if (G_interactive_fd) {
+ close_on_exec_on(G_interactive_fd);
+ }
+ install_special_sighandlers();
+#else
+ /* We have interactiveness code disabled */
+ install_special_sighandlers();
+#endif
+ /* bash:
+ * if interactive but not a login shell, sources ~/.bashrc
+ * (--norc turns this off, --rcfile <file> overrides)
+ */
+
+ if (G_interactive_fd) {
+#if ENABLE_HUSH_INTERACTIVE && ENABLE_FEATURE_EDITING_FANCY_PROMPT
+ /* Set (but not export) PS1/2 unless already set */
+ if (!get_local_var_value("PS1"))
+ set_local_var_from_halves("PS1", "\\w \\$ ");
+ if (!get_local_var_value("PS2"))
+ set_local_var_from_halves("PS2", "> ");
+#endif
+ if (!ENABLE_FEATURE_SH_EXTRA_QUIET) {
+ /* note: ash and hush share this string */
+ printf("\n\n%s %s\n"
+ IF_HUSH_HELP("Enter 'help' for a list of built-in commands.\n")
+ "\n",
+ bb_banner,
+ "hush - the humble shell"
+ );
+ }
+ }
+
+ parse_and_run_file(hfopen(NULL)); /* stdin */
+
+ final_return:
+ hush_exit(G.last_exitcode);
+}
+
+
+
+/*
+ * Built-ins
+ */
+static int FAST_FUNC builtin_true(char **argv UNUSED_PARAM)
+{
+ return 0;
+}
+
+static int FAST_FUNC builtin_false(char **argv UNUSED_PARAM)
+{
+ return 1;
+}
+
+#if ENABLE_HUSH_TEST || ENABLE_HUSH_ECHO || ENABLE_HUSH_PRINTF || ENABLE_HUSH_KILL
+static NOINLINE int run_applet_main(char **argv, int (*applet_main_func)(int argc, char **argv))
+{
+ int argc = string_array_len(argv);
+ return applet_main_func(argc, argv);
+}
+#endif
+#if ENABLE_HUSH_TEST || BASH_TEST2
+static int FAST_FUNC builtin_test(char **argv)
+{
+ return run_applet_main(argv, test_main);
+}
+#endif
+#if ENABLE_HUSH_ECHO
+static int FAST_FUNC builtin_echo(char **argv)
+{
+ return run_applet_main(argv, echo_main);
+}
+#endif
+#if ENABLE_HUSH_PRINTF
+static int FAST_FUNC builtin_printf(char **argv)
+{
+ return run_applet_main(argv, printf_main);
+}
+#endif
+
+#if ENABLE_HUSH_HELP
+static int FAST_FUNC builtin_help(char **argv UNUSED_PARAM)
+{
+ const struct built_in_command *x;
+
+ printf(
+ "Built-in commands:\n"
+ "------------------\n");
+ for (x = bltins1; x != &bltins1[ARRAY_SIZE(bltins1)]; x++) {
+ if (x->b_descr)
+ printf("%-10s%s\n", x->b_cmd, x->b_descr);
+ }
+ return EXIT_SUCCESS;
+}
+#endif
+
+#if MAX_HISTORY && ENABLE_FEATURE_EDITING
+static int FAST_FUNC builtin_history(char **argv UNUSED_PARAM)
+{
+ show_history(G.line_input_state);
+ return EXIT_SUCCESS;
+}
+#endif
+
+static int FAST_FUNC builtin_cd(char **argv)
+{
+ const char *newdir;
+
+ argv = skip_dash_dash(argv);
+ newdir = argv[0];
+ if (newdir == NULL) {
+ /* bash does nothing (exitcode 0) if HOME is ""; if it's unset,
+ * bash says "bash: cd: HOME not set" and does nothing
+ * (exitcode 1)
+ */
+ const char *home = get_local_var_value("HOME");
+ newdir = home ? home : "/";
+ }
+ if (chdir(newdir)) {
+ /* Mimic bash message exactly */
+ bb_perror_msg("cd: %s", newdir);
+ return EXIT_FAILURE;
+ }
+ /* Read current dir (get_cwd(1) is inside) and set PWD.
+ * Note: do not enforce exporting. If PWD was unset or unexported,
+ * set it again, but do not export. bash does the same.
+ */
+ set_pwd_var(/*flag:*/ 0);
+ return EXIT_SUCCESS;
+}
+
+static int FAST_FUNC builtin_pwd(char **argv UNUSED_PARAM)
+{
+ puts(get_cwd(0));
+ return EXIT_SUCCESS;
+}
+
+static int FAST_FUNC builtin_eval(char **argv)
+{
+ argv = skip_dash_dash(argv);
+
+ if (!argv[0])
+ return EXIT_SUCCESS;
+
+ IF_HUSH_MODE_X(G.x_mode_depth++;)
+ //bb_error_msg("%s: ++x_mode_depth=%d", __func__, G.x_mode_depth);
+ if (!argv[1]) {
+ /* bash:
+ * eval "echo Hi; done" ("done" is syntax error):
+ * "echo Hi" will not execute too.
+ */
+ parse_and_run_string(argv[0]);
+ } else {
+ /* "The eval utility shall construct a command by
+ * concatenating arguments together, separating
+ * each with a <space> character."
+ */
+ char *str, *p;
+ unsigned len = 0;
+ char **pp = argv;
+ do
+ len += strlen(*pp) + 1;
+ while (*++pp);
+ str = p = xmalloc(len);
+ pp = argv;
+ for (;;) {
+ p = stpcpy(p, *pp);
+ pp++;
+ if (!*pp)
+ break;
+ *p++ = ' ';
+ }
+ parse_and_run_string(str);
+ free(str);
+ }
+ IF_HUSH_MODE_X(G.x_mode_depth--;)
+ //bb_error_msg("%s: --x_mode_depth=%d", __func__, G.x_mode_depth);
+ return G.last_exitcode;
+}
+
+static int FAST_FUNC builtin_exec(char **argv)
+{
+ argv = skip_dash_dash(argv);
+ if (argv[0] == NULL)
+ return EXIT_SUCCESS; /* bash does this */
+
+ /* Careful: we can end up here after [v]fork. Do not restore
+ * tty pgrp then, only top-level shell process does that */
+ if (G_saved_tty_pgrp && getpid() == G.root_pid)
+ tcsetpgrp(G_interactive_fd, G_saved_tty_pgrp);
+
+ /* Saved-redirect fds, script fds and G_interactive_fd are still
+ * open here. However, they are all CLOEXEC, and execv below
+ * closes them. Try interactive "exec ls -l /proc/self/fd",
+ * it should show no extra open fds in the "ls" process.
+ * If we'd try to run builtins/NOEXECs, this would need improving.
+ */
+ //close_saved_fds_and_FILE_fds();
+
+ /* TODO: if exec fails, bash does NOT exit! We do.
+ * We'll need to undo trap cleanup (it's inside execvp_or_die)
+ * and tcsetpgrp, and this is inherently racy.
+ */
+ execvp_or_die(argv);
+}
+
+static int FAST_FUNC builtin_exit(char **argv)
+{
+ debug_printf_exec("%s()\n", __func__);
+
+ /* interactive bash:
+ * # trap "echo EEE" EXIT
+ * # exit
+ * exit
+ * There are stopped jobs.
+ * (if there are _stopped_ jobs, running ones don't count)
+ * # exit
+ * exit
+ * EEE (then bash exits)
+ *
+ * TODO: we can use G.exiting = -1 as indicator "last cmd was exit"
+ */
+
+ /* note: EXIT trap is run by hush_exit */
+ argv = skip_dash_dash(argv);
+ if (argv[0] == NULL) {
+#if ENABLE_HUSH_TRAP
+ if (G.pre_trap_exitcode >= 0) /* "exit" in trap uses $? from before the trap */
+ hush_exit(G.pre_trap_exitcode);
+#endif
+ hush_exit(G.last_exitcode);
+ }
+ /* mimic bash: exit 123abc == exit 255 + error msg */
+ xfunc_error_retval = 255;
+ /* bash: exit -2 == exit 254, no error msg */
+ hush_exit(xatoi(argv[0]) & 0xff);
+}
+
+#if ENABLE_HUSH_TYPE
+/* http://www.opengroup.org/onlinepubs/9699919799/utilities/type.html */
+static int FAST_FUNC builtin_type(char **argv)
+{
+ int ret = EXIT_SUCCESS;
+
+ while (*++argv) {
+ const char *type;
+ char *path = NULL;
+
+ if (0) {} /* make conditional compile easier below */
+ /*else if (find_alias(*argv))
+ type = "an alias";*/
+# if ENABLE_HUSH_FUNCTIONS
+ else if (find_function(*argv))
+ type = "a function";
+# endif
+ else if (find_builtin(*argv))
+ type = "a shell builtin";
+ else if ((path = find_in_path(*argv)) != NULL)
+ type = path;
+ else {
+ bb_error_msg("type: %s: not found", *argv);
+ ret = EXIT_FAILURE;
+ continue;
+ }
+
+ printf("%s is %s\n", *argv, type);
+ free(path);
+ }
+
+ return ret;
+}
+#endif
+
+#if ENABLE_HUSH_READ
+/* Interruptibility of read builtin in bash
+ * (tested on bash-4.2.8 by sending signals (not by ^C)):
+ *
+ * Empty trap makes read ignore corresponding signal, for any signal.
+ *
+ * SIGINT:
+ * - terminates non-interactive shell;
+ * - interrupts read in interactive shell;
+ * if it has non-empty trap:
+ * - executes trap and returns to command prompt in interactive shell;
+ * - executes trap and returns to read in non-interactive shell;
+ * SIGTERM:
+ * - is ignored (does not interrupt) read in interactive shell;
+ * - terminates non-interactive shell;
+ * if it has non-empty trap:
+ * - executes trap and returns to read;
+ * SIGHUP:
+ * - terminates shell (regardless of interactivity);
+ * if it has non-empty trap:
+ * - executes trap and returns to read;
+ * SIGCHLD from children:
+ * - does not interrupt read regardless of interactivity:
+ * try: sleep 1 & read x; echo $x
+ */
+static int FAST_FUNC builtin_read(char **argv)
+{
+ const char *r;
+ struct builtin_read_params params;
+
+ memset(¶ms, 0, sizeof(params));
+
+ /* "!": do not abort on errors.
+ * Option string must start with "sr" to match BUILTIN_READ_xxx
+ */
+ params.read_flags = getopt32(argv,
+# if BASH_READ_D
+ IF_NOT_HUSH_BASH_COMPAT("^")
+ "!srn:p:t:u:d:" IF_NOT_HUSH_BASH_COMPAT("\0" "-1"/*min 1 arg*/),
+ ¶ms.opt_n, ¶ms.opt_p, ¶ms.opt_t, ¶ms.opt_u, ¶ms.opt_d
+# else
+ IF_NOT_HUSH_BASH_COMPAT("^")
+ "!srn:p:t:u:" IF_NOT_HUSH_BASH_COMPAT("\0" "-1"/*min 1 arg*/),
+ ¶ms.opt_n, ¶ms.opt_p, ¶ms.opt_t, ¶ms.opt_u
+# endif
+//TODO: print "read: need variable name"
+//for the case of !BASH "read" with no args (now it fails silently)
+//(or maybe extend getopt32() to emit a message if "-1" fails)
+ );
+ if ((uint32_t)params.read_flags == (uint32_t)-1)
+ return EXIT_FAILURE;
+ argv += optind;
+ params.argv = argv;
+ params.setvar = set_local_var_from_halves;
+ params.ifs = get_local_var_value("IFS"); /* can be NULL */
+
+ again:
+ r = shell_builtin_read(¶ms);
+
+ if ((uintptr_t)r == 1 && errno == EINTR) {
+ unsigned sig = check_and_run_traps();
+ if (sig != SIGINT)
+ goto again;
+ }
+
+ if ((uintptr_t)r > 1) {
+ bb_simple_error_msg(r);
+ r = (char*)(uintptr_t)1;
+ }
+
+ return (uintptr_t)r;
+}
+#endif
+
+#if ENABLE_HUSH_UMASK
+static int FAST_FUNC builtin_umask(char **argv)
+{
+ int rc;
+ mode_t mask;
+
+ rc = 1;
+ mask = umask(0);
+ argv = skip_dash_dash(argv);
+ if (argv[0]) {
+ mode_t old_mask = mask;
+
+ /* numeric umasks are taken as-is */
+ /* symbolic umasks are inverted: "umask a=rx" calls umask(222) */
+ if (!isdigit(argv[0][0]))
+ mask ^= 0777;
+ mask = bb_parse_mode(argv[0], mask);
+ if (!isdigit(argv[0][0]))
+ mask ^= 0777;
+ if ((unsigned)mask > 0777) {
+ mask = old_mask;
+ /* bash messages:
+ * bash: umask: 'q': invalid symbolic mode operator
+ * bash: umask: 999: octal number out of range
+ */
+ bb_error_msg("%s: invalid mode '%s'", "umask", argv[0]);
+ rc = 0;
+ }
+ } else {
+ /* Mimic bash */
+ printf("%04o\n", (unsigned) mask);
+ /* fall through and restore mask which we set to 0 */
+ }
+ umask(mask);
+
+ return !rc; /* rc != 0 - success */
+}
+#endif
+
+#if ENABLE_HUSH_EXPORT || ENABLE_HUSH_READONLY || ENABLE_HUSH_SET || ENABLE_HUSH_TRAP
+static void print_escaped(const char *s)
+{
+//TODO? bash "set" does not quote variables which contain only alnums and "%+,-./:=@_~",
+// (but "export" quotes all variables, even with only these chars).
+// I think quoting strings with %+,=~ looks better
+// (example: "set" printing var== instead of var='=' looks strange)
+// IOW: do not quote "-./:@_": / is used in pathnames, : in PATH, -._ often in file names, @ in emails
+
+ if (*s == '\'')
+ goto squote;
+ do {
+ const char *p = strchrnul(s, '\'');
+ /* print 'xxxx', possibly just '' */
+ printf("'%.*s'", (int)(p - s), s);
+ if (*p == '\0')
+ break;
+ s = p;
+ squote:
+ /* s points to '; print "'''...'''" */
+ putchar('"');
+ do putchar('\''); while (*++s == '\'');
+ putchar('"');
+ } while (*s);
+}
+#endif
+
+#if ENABLE_HUSH_EXPORT || ENABLE_HUSH_LOCAL || ENABLE_HUSH_READONLY
+static int helper_export_local(char **argv, unsigned flags)
+{
+ do {
+ char *name = *argv;
+ const char *name_end = endofname(name);
+
+ if (*name_end == '\0') {
+ struct variable *var, **vpp;
+
+ vpp = get_ptr_to_local_var(name);
+ var = vpp ? *vpp : NULL;
+
+ if (flags & SETFLAG_UNEXPORT) {
+ /* export -n NAME (without =VALUE) */
+ if (var) {
+ var->flg_export = 0;
+ debug_printf_env("%s: unsetenv '%s'\n", __func__, name);
+ unsetenv(name);
+ } /* else: export -n NOT_EXISTING_VAR: no-op */
+ continue;
+ }
+ if (flags & SETFLAG_EXPORT) {
+ /* export NAME (without =VALUE) */
+ if (var) {
+ var->flg_export = 1;
+ debug_printf_env("%s: putenv '%s'\n", __func__, var->varstr);
+ putenv(var->varstr);
+ continue;
+ }
+ }
+ if (flags & SETFLAG_MAKE_RO) {
+ /* readonly NAME (without =VALUE) */
+ if (var) {
+ var->flg_read_only = 1;
+ continue;
+ }
+ }
+# if ENABLE_HUSH_LOCAL
+ /* Is this "local" bltin? */
+ if (!(flags & (SETFLAG_EXPORT|SETFLAG_UNEXPORT|SETFLAG_MAKE_RO))) {
+ unsigned lvl = flags >> SETFLAG_VARLVL_SHIFT;
+ if (var && var->var_nest_level == lvl) {
+ /* "local x=abc; ...; local x" - ignore second local decl */
+ continue;
+ }
+ }
+# endif
+ /* Exporting non-existing variable.
+ * bash does not put it in environment,
+ * but remembers that it is exported,
+ * and does put it in env when it is set later.
+ * We just set it to "" and export.
+ */
+ /* Or, it's "local NAME" (without =VALUE).
+ * bash sets the value to "".
+ */
+ /* Or, it's "readonly NAME" (without =VALUE).
+ * bash remembers NAME and disallows its creation
+ * in the future.
+ */
+ name = xasprintf("%s=", name);
+ } else {
+ if (*name_end != '=') {
+ bb_error_msg("'%s': bad variable name", name);
+ /* do not parse following argv[]s: */
+ return 1;
+ }
+ /* (Un)exporting/making local NAME=VALUE */
+ name = xstrdup(name);
+ /* Testcase: export PS1='\w \$ ' */
+ unbackslash(name);
+ }
+ debug_printf_env("%s: set_local_var('%s')\n", __func__, name);
+ if (set_local_var(name, flags))
+ return EXIT_FAILURE;
+ } while (*++argv);
+ return EXIT_SUCCESS;
+}
+#endif
+
+#if ENABLE_HUSH_EXPORT
+static int FAST_FUNC builtin_export(char **argv)
+{
+ unsigned opt_unexport;
+
+# if ENABLE_HUSH_EXPORT_N
+ /* "!": do not abort on errors */
+ opt_unexport = getopt32(argv, "!n");
+ if (opt_unexport == (uint32_t)-1)
+ return EXIT_FAILURE;
+ argv += optind;
+# else
+ opt_unexport = 0;
+ argv++;
+# endif
+
+ if (argv[0] == NULL) {
+ char **e = environ;
+ if (e) {
+ while (*e) {
+# if 0
+ puts(*e++);
+# else
+ /* ash emits: export VAR='VAL'
+ * bash: declare -x VAR="VAL"
+ * we follow ash example */
+ const char *s = *e++;
+ const char *p = strchr(s, '=');
+
+ if (!p) /* wtf? take next variable */
+ continue;
+ /* "export VAR=" */
+ printf("%s %.*s", "export", (int)(p - s) + 1, s);
+ print_escaped(p + 1);
+ putchar('\n');
+# endif
+ }
+ /*fflush_all(); - done after each builtin anyway */
+ }
+ return EXIT_SUCCESS;
+ }
+
+ return helper_export_local(argv, opt_unexport ? SETFLAG_UNEXPORT : SETFLAG_EXPORT);
+}
+#endif
+
+#if ENABLE_HUSH_LOCAL
+static int FAST_FUNC builtin_local(char **argv)
+{
+ if (G.func_nest_level == 0) {
+ bb_error_msg("%s: not in a function", argv[0]);
+ return EXIT_FAILURE; /* bash compat */
+ }
+//TODO? ash and bash support "local -" special form,
+//which saves/restores $- around function call (including async returns, such as ^C)
+//(IOW: it makes "set +/-..." effects local)
+ argv++;
+ /* Since all builtins run in a nested variable level,
+ * need to use level - 1 here. Or else the variable will be removed at once
+ * after builtin returns.
+ */
+ return helper_export_local(argv, (G.var_nest_level - 1) << SETFLAG_VARLVL_SHIFT);
+}
+#endif
+
+#if ENABLE_HUSH_READONLY
+static int FAST_FUNC builtin_readonly(char **argv)
+{
+ argv++;
+ if (*argv == NULL) {
+ /* bash: readonly [-p]: list all readonly VARs
+ * (-p has no effect in bash)
+ */
+ struct variable *e;
+ for (e = G.top_var; e; e = e->next) {
+ if (e->flg_read_only) {
+ const char *s = e->varstr;
+ const char *p = strchr(s, '=');
+
+ if (!p) /* wtf? take next variable */
+ continue;
+ /* "readonly VAR=" */
+ printf("%s %.*s", "readonly", (int)(p - s) + 1, s);
+ print_escaped(p + 1);
+ putchar('\n');
+ }
+ }
+ return EXIT_SUCCESS;
+ }
+ return helper_export_local(argv, SETFLAG_MAKE_RO);
+}
+#endif
+
+#if ENABLE_HUSH_UNSET
+/* http://www.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#unset */
+static int FAST_FUNC builtin_unset(char **argv)
+{
+ int ret;
+ unsigned opts;
+
+ /* "!": do not abort on errors */
+ /* "+": stop at 1st non-option */
+ opts = getopt32(argv, "!+vf");
+ if (opts == (unsigned)-1)
+ return EXIT_FAILURE;
+ if (opts == 3) {
+ bb_simple_error_msg("unset: -v and -f are exclusive");
+ return EXIT_FAILURE;
+ }
+ argv += optind;
+
+ ret = EXIT_SUCCESS;
+ while (*argv) {
+ if (!(opts & 2)) { /* not -f */
+ if (unset_local_var(*argv)) {
+ /* unset <nonexistent_var> doesn't fail.
+ * Error is when one tries to unset RO var.
+ * Message was printed by unset_local_var. */
+ ret = EXIT_FAILURE;
+ }
+ }
+# if ENABLE_HUSH_FUNCTIONS
+ else {
+ unset_func(*argv);
+ }
+# endif
+ argv++;
+ }
+ return ret;
+}
+#endif
+
+#if ENABLE_HUSH_SET
+/* http://www.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#set
+ * built-in 'set' handler
+ * SUSv3 says:
+ * set [-abCefhmnuvx] [-o option] [argument...]
+ * set [+abCefhmnuvx] [+o option] [argument...]
+ * set -- [argument...]
+ * set -o
+ * set +o
+ * Implementations shall support the options in both their hyphen and
+ * plus-sign forms. These options can also be specified as options to sh.
+ * Examples:
+ * Write out all variables and their values: set
+ * Set $1, $2, and $3 and set "$#" to 3: set c a b
+ * Turn on the -x and -v options: set -xv
+ * Unset all positional parameters: set --
+ * Set $1 to the value of x, even if it begins with '-' or '+': set -- "$x"
+ * Set the positional parameters to the expansion of x, even if x expands
+ * with a leading '-' or '+': set -- $x
+ *
+ * So far, we only support "set -- [argument...]" and some of the short names.
+ */
+static int FAST_FUNC builtin_set(char **argv)
+{
+ int n;
+ char **pp, **g_argv;
+ char *arg = *++argv;
+
+ if (arg == NULL) {
+ struct variable *e;
+ for (e = G.top_var; e; e = e->next) {
+ const char *s = e->varstr;
+ const char *p = strchr(s, '=');
+
+ if (!p) /* wtf? take next variable */
+ continue;
+ /* var= */
+ printf("%.*s", (int)(p - s) + 1, s);
+ print_escaped(p + 1);
+ putchar('\n');
+ }
+ return EXIT_SUCCESS;
+ }
+
+ do {
+ if (strcmp(arg, "--") == 0) {
+ ++argv;
+ goto set_argv;
+ }
+ if (arg[0] != '+' && arg[0] != '-')
+ break;
+ for (n = 1; arg[n]; ++n) {
+ if (set_mode((arg[0] == '-'), arg[n], argv[1])) {
+ bb_error_msg("%s: %s: invalid option", "set", arg);
+ return EXIT_FAILURE;
+ }
+ if (arg[n] == 'o' && argv[1])
+ argv++;
+ }
+ } while ((arg = *++argv) != NULL);
+ /* Now argv[0] is 1st argument */
+
+ if (arg == NULL)
+ return EXIT_SUCCESS;
+ set_argv:
+
+ /* NB: G.global_argv[0] ($0) is never freed/changed */
+ g_argv = G.global_argv;
+ if (G.global_args_malloced) {
+ pp = g_argv;
+ while (*++pp)
+ free(*pp);
+ g_argv[1] = NULL;
+ } else {
+ G.global_args_malloced = 1;
+ pp = xzalloc(sizeof(pp[0]) * 2);
+ pp[0] = g_argv[0]; /* retain $0 */
+ g_argv = pp;
+ }
+ /* This realloc's G.global_argv */
+ G.global_argv = pp = add_strings_to_strings(g_argv, argv, /*dup:*/ 1);
+
+ G.global_argc = 1 + string_array_len(pp + 1);
+
+ return EXIT_SUCCESS;
+}
+#endif
+
+static int FAST_FUNC builtin_shift(char **argv)
+{
+ int n = 1;
+ argv = skip_dash_dash(argv);
+ if (argv[0]) {
+ n = bb_strtou(argv[0], NULL, 10);
+ if (errno || n < 0) {
+ /* shared string with ash.c */
+ bb_error_msg("Illegal number: %s", argv[0]);
+ /*
+ * ash aborts in this case.
+ * bash prints error message and set $? to 1.
+ * Interestingly, for "shift 99999" bash does not
+ * print error message, but does set $? to 1
+ * (and does no shifting at all).
+ */
+ }
+ }
+ if (n >= 0 && n < G.global_argc) {
+ if (G_global_args_malloced) {
+ int m = 1;
+ while (m <= n)
+ free(G.global_argv[m++]);
+ }
+ G.global_argc -= n;
+ memmove(&G.global_argv[1], &G.global_argv[n+1],
+ G.global_argc * sizeof(G.global_argv[0]));
+ return EXIT_SUCCESS;
+ }
+ return EXIT_FAILURE;
+}
+
+#if ENABLE_HUSH_GETOPTS
+static int FAST_FUNC builtin_getopts(char **argv)
+{
+/* http://pubs.opengroup.org/onlinepubs/9699919799/utilities/getopts.html
+
+TODO:
+If a required argument is not found, and getopts is not silent,
+a question mark (?) is placed in VAR, OPTARG is unset, and a
+diagnostic message is printed. If getopts is silent, then a
+colon (:) is placed in VAR and OPTARG is set to the option
+character found.
+
+Test that VAR is a valid variable name?
+
+"Whenever the shell is invoked, OPTIND shall be initialized to 1"
+*/
+ char cbuf[2];
+ const char *cp, *optstring, *var;
+ int c, n, exitcode, my_opterr;
+ unsigned count;
+
+ optstring = *++argv;
+ if (!optstring || !(var = *++argv)) {
+ bb_simple_error_msg("usage: getopts OPTSTRING VAR [ARGS]");
+ return EXIT_FAILURE;
+ }
+
+ if (argv[1])
+ argv[0] = G.global_argv[0]; /* for error messages in getopt() */
+ else
+ argv = G.global_argv;
+ cbuf[1] = '\0';
+
+ my_opterr = 0;
+ if (optstring[0] != ':') {
+ cp = get_local_var_value("OPTERR");
+ /* 0 if "OPTERR=0", 1 otherwise */
+ my_opterr = (!cp || NOT_LONE_CHAR(cp, '0'));
+ }
+
+ /* getopts stops on first non-option. Add "+" to force that */
+ /*if (optstring[0] != '+')*/ {
+ char *s = alloca(strlen(optstring) + 2);
+ sprintf(s, "+%s", optstring);
+ optstring = s;
+ }
+
+ /* Naively, now we should just
+ * cp = get_local_var_value("OPTIND");
+ * optind = cp ? atoi(cp) : 0;
+ * optarg = NULL;
+ * opterr = my_opterr;
+ * c = getopt(string_array_len(argv), argv, optstring);
+ * and be done? Not so fast...
+ * Unlike normal getopt() usage in C programs, here
+ * each successive call will (usually) have the same argv[] CONTENTS,
+ * but not the ADDRESSES. Worse yet, it's possible that between
+ * invocations of "getopts", there will be calls to shell builtins
+ * which use getopt() internally. Example:
+ * while getopts "abc" RES -a -bc -abc de; do
+ * unset -ff func
+ * done
+ * This would not work correctly: getopt() call inside "unset"
+ * modifies internal libc state which is tracking position in
+ * multi-option strings ("-abc"). At best, it can skip options
+ * or return the same option infinitely. With glibc implementation
+ * of getopt(), it would use outright invalid pointers and return
+ * garbage even _without_ "unset" mangling internal state.
+ *
+ * We resort to resetting getopt() state and calling it N times,
+ * until we get Nth result (or failure).
+ * (N == G.getopt_count is reset to 0 whenever OPTIND is [un]set).
+ */
+ GETOPT_RESET();
+ count = 0;
+ n = string_array_len(argv);
+ do {
+ optarg = NULL;
+ opterr = (count < G.getopt_count) ? 0 : my_opterr;
+ c = getopt(n, argv, optstring);
+ if (c < 0)
+ break;
+ count++;
+ } while (count <= G.getopt_count);
+
+ /* Set OPTIND. Prevent resetting of the magic counter! */
+ set_local_var_from_halves("OPTIND", utoa(optind));
+ G.getopt_count = count; /* "next time, give me N+1'th result" */
+ GETOPT_RESET(); /* just in case */
+
+ /* Set OPTARG */
+ /* Always set or unset, never left as-is, even on exit/error:
+ * "If no option was found, or if the option that was found
+ * does not have an option-argument, OPTARG shall be unset."
+ */
+ cp = optarg;
+ if (c == '?') {
+ /* If ":optstring" and unknown option is seen,
+ * it is stored to OPTARG.
+ */
+ if (optstring[1] == ':') {
+ cbuf[0] = optopt;
+ cp = cbuf;
+ }
+ }
+ if (cp)
+ set_local_var_from_halves("OPTARG", cp);
+ else
+ unset_local_var("OPTARG");
+
+ /* Convert -1 to "?" */
+ exitcode = EXIT_SUCCESS;
+ if (c < 0) { /* -1: end of options */
+ exitcode = EXIT_FAILURE;
+ c = '?';
+ }
+
+ /* Set VAR */
+ cbuf[0] = c;
+ set_local_var_from_halves(var, cbuf);
+
+ return exitcode;
+}
+#endif
+
+static int FAST_FUNC builtin_source(char **argv)
+{
+ char *arg_path, *filename;
+ HFILE *input;
+ save_arg_t sv;
+ char *args_need_save;
+#if ENABLE_HUSH_FUNCTIONS
+ smallint sv_flg;
+#endif
+
+ argv = skip_dash_dash(argv);
+ filename = argv[0];
+ if (!filename) {
+ /* bash says: "bash: .: filename argument required" */
+ return 2; /* bash compat */
+ }
+ arg_path = NULL;
+ if (!strchr(filename, '/')) {
+ arg_path = find_in_path(filename);
+ if (arg_path)
+ filename = arg_path;
+ else if (!ENABLE_HUSH_BASH_SOURCE_CURDIR) {
+ errno = ENOENT;
+ bb_simple_perror_msg(filename);
+ return EXIT_FAILURE;
+ }
+ }
+ input = hfopen(filename);
+ free(arg_path);
+ if (!input) {
+ bb_perror_msg("%s", filename);
+ /* POSIX: non-interactive shell should abort here,
+ * not merely fail. So far no one complained :)
+ */
+ return EXIT_FAILURE;
+ }
+
+#if ENABLE_HUSH_FUNCTIONS
+ sv_flg = G_flag_return_in_progress;
+ /* "we are inside sourced file, ok to use return" */
+ G_flag_return_in_progress = -1;
+#endif
+ args_need_save = argv[1]; /* used as a boolean variable */
+ if (args_need_save)
+ save_and_replace_G_args(&sv, argv);
+
+ /* "false; . ./empty_line; echo Zero:$?" should print 0 */
+ G.last_exitcode = 0;
+ parse_and_run_file(input);
+ hfclose(input);
+
+ if (args_need_save) /* can't use argv[1] instead: "shift" can mangle it */
+ restore_G_args(&sv, argv);
+#if ENABLE_HUSH_FUNCTIONS
+ G_flag_return_in_progress = sv_flg;
+#endif
+
+ return G.last_exitcode;
+}
+
+#if ENABLE_HUSH_TRAP
+static int FAST_FUNC builtin_trap(char **argv)
+{
+ int sig;
+ char *new_cmd;
+
+ if (!G_traps)
+ G_traps = xzalloc(sizeof(G_traps[0]) * NSIG);
+
+ argv++;
+ if (!*argv) {
+ int i;
+ /* No args: print all trapped */
+ for (i = 0; i < NSIG; ++i) {
+ if (G_traps[i]) {
+ printf("trap -- ");
+ print_escaped(G_traps[i]);
+ /* note: bash adds "SIG", but only if invoked
+ * as "bash". If called as "sh", or if set -o posix,
+ * then it prints short signal names.
+ * We are printing short names: */
+ printf(" %s\n", get_signame(i));
+ }
+ }
+ /*fflush_all(); - done after each builtin anyway */
+ return EXIT_SUCCESS;
+ }
+
+ new_cmd = NULL;
+ /* If first arg is a number: reset all specified signals */
+ sig = bb_strtou(*argv, NULL, 10);
+ if (errno == 0) {
+ int ret;
+ process_sig_list:
+ ret = EXIT_SUCCESS;
+ while (*argv) {
+ sighandler_t handler;
+
+ sig = get_signum(*argv++);
+ if (sig < 0) {
+ ret = EXIT_FAILURE;
+ /* Mimic bash message exactly */
+ bb_error_msg("trap: %s: invalid signal specification", argv[-1]);
+ continue;
+ }
+
+ free(G_traps[sig]);
+ G_traps[sig] = xstrdup(new_cmd);
+
+ debug_printf("trap: setting SIG%s (%i) to '%s'\n",
+ get_signame(sig), sig, G_traps[sig]);
+
+ /* There is no signal for 0 (EXIT) */
+ if (sig == 0)
+ continue;
+
+ if (new_cmd)
+ handler = (new_cmd[0] ? record_pending_signo : SIG_IGN);
+ else
+ /* We are removing trap handler */
+ handler = pick_sighandler(sig);
+ install_sighandler(sig, handler);
+ }
+ return ret;
+ }
+
+ if (!argv[1]) { /* no second arg */
+ bb_simple_error_msg("trap: invalid arguments");
+ return EXIT_FAILURE;
+ }
+
+ /* First arg is "-": reset all specified to default */
+ /* First arg is "--": skip it, the rest is "handler SIGs..." */
+ /* Everything else: set arg as signal handler
+ * (includes "" case, which ignores signal) */
+ if (argv[0][0] == '-') {
+ if (argv[0][1] == '\0') { /* "-" */
+ /* new_cmd remains NULL: "reset these sigs" */
+ goto reset_traps;
+ }
+ if (argv[0][1] == '-' && argv[0][2] == '\0') { /* "--" */
+ argv++;
+ }
+ /* else: "-something", no special meaning */
+ }
+ new_cmd = *argv;
+ reset_traps:
+ argv++;
+ goto process_sig_list;
+}
+#endif
+
+#if ENABLE_HUSH_JOB
+static struct pipe *parse_jobspec(const char *str)
+{
+ struct pipe *pi;
+ unsigned jobnum;
+
+ if (sscanf(str, "%%%u", &jobnum) != 1) {
+ if (str[0] != '%'
+ || (str[1] != '%' && str[1] != '+' && str[1] != '\0')
+ ) {
+ bb_error_msg("bad argument '%s'", str);
+ return NULL;
+ }
+ /* It is "%%", "%+" or "%" - current job */
+ jobnum = G.last_jobid;
+ if (jobnum == 0) {
+ bb_simple_error_msg("no current job");
+ return NULL;
+ }
+ }
+ for (pi = G.job_list; pi; pi = pi->next) {
+ if (pi->jobid == jobnum) {
+ return pi;
+ }
+ }
+ bb_error_msg("%u: no such job", jobnum);
+ return NULL;
+}
+
+static int FAST_FUNC builtin_jobs(char **argv UNUSED_PARAM)
+{
+ struct pipe *job;
+ const char *status_string;
+
+ checkjobs(NULL, 0 /*(no pid to wait for)*/);
+ for (job = G.job_list; job; job = job->next) {
+ if (job->alive_cmds == job->stopped_cmds)
+ status_string = "Stopped";
+ else
+ status_string = "Running";
+
+ printf(JOB_STATUS_FORMAT, job->jobid, status_string, job->cmdtext);
+ }
+
+ clean_up_last_dead_job();
+
+ return EXIT_SUCCESS;
+}
+
+/* built-in 'fg' and 'bg' handler */
+static int FAST_FUNC builtin_fg_bg(char **argv)
+{
+ int i;
+ struct pipe *pi;
+
+ if (!G_interactive_fd)
+ return EXIT_FAILURE;
+
+ /* If they gave us no args, assume they want the last backgrounded task */
+ if (!argv[1]) {
+ for (pi = G.job_list; pi; pi = pi->next) {
+ if (pi->jobid == G.last_jobid) {
+ goto found;
+ }
+ }
+ bb_error_msg("%s: no current job", argv[0]);
+ return EXIT_FAILURE;
+ }
+
+ pi = parse_jobspec(argv[1]);
+ if (!pi)
+ return EXIT_FAILURE;
+ found:
+ /* TODO: bash prints a string representation
+ * of job being foregrounded (like "sleep 1 | cat") */
+ if (argv[0][0] == 'f' && G_saved_tty_pgrp) {
+ /* Put the job into the foreground. */
+ tcsetpgrp(G_interactive_fd, pi->pgrp);
+ }
+
+ /* Restart the processes in the job */
+ debug_printf_jobs("reviving %d procs, pgrp %d\n", pi->num_cmds, pi->pgrp);
+ for (i = 0; i < pi->num_cmds; i++) {
+ debug_printf_jobs("reviving pid %d\n", pi->cmds[i].pid);
+ }
+ pi->stopped_cmds = 0;
+
+ i = kill(- pi->pgrp, SIGCONT);
+ if (i < 0) {
+ if (errno == ESRCH) {
+ delete_finished_job(pi);
+ return EXIT_SUCCESS;
+ }
+ bb_simple_perror_msg("kill (SIGCONT)");
+ }
+
+ if (argv[0][0] == 'f') {
+ remove_job_from_table(pi); /* FG job shouldn't be in job table */
+ return checkjobs_and_fg_shell(pi);
+ }
+ return EXIT_SUCCESS;
+}
+#endif
+
+#if ENABLE_HUSH_KILL
+static int FAST_FUNC builtin_kill(char **argv)
+{
+ int ret = 0;
+
+# if ENABLE_HUSH_JOB
+ if (argv[1] && strcmp(argv[1], "-l") != 0) {
+ int i = 1;
+
+ do {
+ struct pipe *pi;
+ char *dst;
+ int j, n;
+
+ if (argv[i][0] != '%')
+ continue;
+ /*
+ * "kill %N" - job kill
+ * Converting to pgrp / pid kill
+ */
+ pi = parse_jobspec(argv[i]);
+ if (!pi) {
+ /* Eat bad jobspec */
+ j = i;
+ do {
+ j++;
+ argv[j - 1] = argv[j];
+ } while (argv[j]);
+ ret = 1;
+ i--;
+ continue;
+ }
+ /*
+ * In jobs started under job control, we signal
+ * entire process group by kill -PGRP_ID.
+ * This happens, f.e., in interactive shell.
+ *
+ * Otherwise, we signal each child via
+ * kill PID1 PID2 PID3.
+ * Testcases:
+ * sh -c 'sleep 1|sleep 1 & kill %1'
+ * sh -c 'true|sleep 2 & sleep 1; kill %1'
+ * sh -c 'true|sleep 1 & sleep 2; kill %1'
+ */
+ n = G_interactive_fd ? 1 : pi->num_cmds;
+ dst = alloca(n * sizeof(int)*4);
+ argv[i] = dst;
+ if (G_interactive_fd)
+ dst += sprintf(dst, " -%u", (int)pi->pgrp);
+ else for (j = 0; j < n; j++) {
+ struct command *cmd = &pi->cmds[j];
+ /* Skip exited members of the job */
+ if (cmd->pid == 0)
+ continue;
+ /*
+ * kill_main has matching code to expect
+ * leading space. Needed to not confuse
+ * negative pids with "kill -SIGNAL_NO" syntax
+ */
+ dst += sprintf(dst, " %u", (int)cmd->pid);
+ }
+ *dst = '\0';
+ } while (argv[++i]);
+ }
+# endif
+
+ if (argv[1] || ret == 0) {
+ ret = run_applet_main(argv, kill_main);
+ }
+ /* else: ret = 1, "kill %bad_jobspec" case */
+ return ret;
+}
+#endif
+
+#if ENABLE_HUSH_WAIT
+/* http://www.opengroup.org/onlinepubs/9699919799/utilities/wait.html */
+# if !ENABLE_HUSH_JOB
+# define wait_for_child_or_signal(pipe,pid) wait_for_child_or_signal(pid)
+# endif
+static int wait_for_child_or_signal(struct pipe *waitfor_pipe, pid_t waitfor_pid)
+{
+ int ret = 0;
+ for (;;) {
+ int sig;
+ sigset_t oldset;
+
+ if (!sigisemptyset(&G.pending_set))
+ goto check_sig;
+
+ /* waitpid is not interruptible by SA_RESTARTed
+ * signals which we use. Thus, this ugly dance:
+ */
+
+ /* Make sure possible SIGCHLD is stored in kernel's
+ * pending signal mask before we call waitpid.
+ * Or else we may race with SIGCHLD, lose it,
+ * and get stuck in sigsuspend...
+ */
+ sigfillset(&oldset); /* block all signals, remember old set */
+ sigprocmask2(SIG_SETMASK, &oldset);
+
+ if (!sigisemptyset(&G.pending_set)) {
+ /* Crap! we raced with some signal! */
+ goto restore;
+ }
+
+ /*errno = 0; - checkjobs does this */
+/* Can't pass waitfor_pipe into checkjobs(): it won't be interruptible */
+ ret = checkjobs(NULL, waitfor_pid); /* waitpid(WNOHANG) inside */
+ debug_printf_exec("checkjobs:%d\n", ret);
+# if ENABLE_HUSH_JOB
+ if (waitfor_pipe) {
+ int rcode = job_exited_or_stopped(waitfor_pipe);
+ debug_printf_exec("job_exited_or_stopped:%d\n", rcode);
+ if (rcode >= 0) {
+ ret = rcode;
+ sigprocmask(SIG_SETMASK, &oldset, NULL);
+ break;
+ }
+ }
+# endif
+ /* if ECHILD, there are no children (ret is -1 or 0) */
+ /* if ret == 0, no children changed state */
+ /* if ret != 0, it's exitcode+1 of exited waitfor_pid child */
+ if (errno == ECHILD || ret) {
+ ret--;
+ if (ret < 0) /* if ECHILD, may need to fix "ret" */
+ ret = 0;
+# if ENABLE_HUSH_BASH_COMPAT
+ if (waitfor_pid == -1 && errno == ECHILD) {
+ /* exitcode of "wait -n" with no children is 127, not 0 */
+ ret = 127;
+ }
+# endif
+ sigprocmask(SIG_SETMASK, &oldset, NULL);
+ break;
+ }
+ /* Wait for SIGCHLD or any other signal */
+ /* It is vitally important for sigsuspend that SIGCHLD has non-DFL handler! */
+ /* Note: sigsuspend invokes signal handler */
+ sigsuspend(&oldset);
+ /* ^^^ add "sigdelset(&oldset, SIGCHLD)" before sigsuspend
+ * to make sure SIGCHLD is not masked off?
+ * It was reported that this:
+ * fn() { : | return; }
+ * shopt -s lastpipe
+ * fn
+ * exec hush SCRIPT
+ * under bash 4.4.23 runs SCRIPT with SIGCHLD masked,
+ * making "wait" commands in SCRIPT block forever.
+ */
+ restore:
+ sigprocmask(SIG_SETMASK, &oldset, NULL);
+ check_sig:
+ /* So, did we get a signal? */
+ sig = check_and_run_traps();
+ if (sig /*&& sig != SIGCHLD - always true */) {
+ /* Do this for any (non-ignored) signal, not only for ^C */
+ ret = 128 | sig;
+ break;
+ }
+ /* SIGCHLD, or no signal, or ignored one, such as SIGQUIT. Repeat */
+ }
+ return ret;
+}
+
+static int FAST_FUNC builtin_wait(char **argv)
+{
+ int ret;
+ int status;
+
+ argv = skip_dash_dash(argv);
+# if ENABLE_HUSH_BASH_COMPAT
+ if (argv[0] && strcmp(argv[0], "-n") == 0) {
+ /* wait -n */
+ /* (bash accepts "wait -n PID" too and ignores PID) */
+ G.dead_job_exitcode = -1;
+ return wait_for_child_or_signal(NULL, -1 /*no job, wait for one job*/);
+ }
+# endif
+ if (argv[0] == NULL) {
+ /* Don't care about wait results */
+ /* Note 1: must wait until there are no more children */
+ /* Note 2: must be interruptible */
+ /* Examples:
+ * $ sleep 3 & sleep 6 & wait
+ * [1] 30934 sleep 3
+ * [2] 30935 sleep 6
+ * [1] Done sleep 3
+ * [2] Done sleep 6
+ * $ sleep 3 & sleep 6 & wait
+ * [1] 30936 sleep 3
+ * [2] 30937 sleep 6
+ * [1] Done sleep 3
+ * ^C <-- after ~4 sec from keyboard
+ * $
+ */
+ return wait_for_child_or_signal(NULL, 0 /*no job and no pid to wait for*/);
+ }
+
+ do {
+ pid_t pid = bb_strtou(*argv, NULL, 10);
+ if (errno || pid <= 0) {
+# if ENABLE_HUSH_JOB
+ if (argv[0][0] == '%') {
+ struct pipe *wait_pipe;
+ ret = 127; /* bash compat for bad jobspecs */
+ wait_pipe = parse_jobspec(*argv);
+ if (wait_pipe) {
+ ret = job_exited_or_stopped(wait_pipe);
+ if (ret < 0) {
+ ret = wait_for_child_or_signal(wait_pipe, 0);
+ } else {
+ /* waiting on "last dead job" removes it */
+ clean_up_last_dead_job();
+ }
+ }
+ /* else: parse_jobspec() already emitted error msg */
+ continue;
+ }
+# endif
+ /* mimic bash message */
+ bb_error_msg("wait: '%s': not a pid or valid job spec", *argv);
+ ret = EXIT_FAILURE;
+ continue; /* bash checks all argv[] */
+ }
+
+ /* Do we have such child? */
+ ret = waitpid(pid, &status, WNOHANG);
+ if (ret < 0) {
+ /* No */
+ ret = 127;
+ if (errno == ECHILD) {
+ if (pid == G.last_bg_pid) {
+ /* "wait $!" but last bg task has already exited. Try:
+ * (sleep 1; exit 3) & sleep 2; echo $?; wait $!; echo $?
+ * In bash it prints exitcode 0, then 3.
+ * In dash, it is 127.
+ */
+ ret = G.last_bg_pid_exitcode;
+ } else {
+ /* Example: "wait 1". mimic bash message */
+ bb_error_msg("wait: pid %u is not a child of this shell", (unsigned)pid);
+ }
+ } else {
+ /* ??? */
+ bb_perror_msg("wait %s", *argv);
+ }
+ continue; /* bash checks all argv[] */
+ }
+ if (ret == 0) {
+ /* Yes, and it still runs */
+ ret = wait_for_child_or_signal(NULL, pid);
+ } else {
+ /* Yes, and it just exited */
+ process_wait_result(NULL, pid, status);
+ ret = WEXITSTATUS(status);
+ if (WIFSIGNALED(status))
+ ret = 128 | WTERMSIG(status);
+ }
+ } while (*++argv);
+
+ return ret;
+}
+#endif
+
+#if ENABLE_HUSH_LOOPS || ENABLE_HUSH_FUNCTIONS
+static unsigned parse_numeric_argv1(char **argv, unsigned def, unsigned def_min)
+{
+ if (argv[1]) {
+ def = bb_strtou(argv[1], NULL, 10);
+ if (errno || def < def_min || argv[2]) {
+ bb_error_msg("%s: bad arguments", argv[0]);
+ def = UINT_MAX;
+ }
+ }
+ return def;
+}
+#endif
+
+#if ENABLE_HUSH_LOOPS
+static int FAST_FUNC builtin_break(char **argv)
+{
+ unsigned depth;
+ if (G.depth_of_loop == 0) {
+ bb_error_msg("%s: only meaningful in a loop", argv[0]);
+ /* if we came from builtin_continue(), need to undo "= 1" */
+ G.flag_break_continue = 0;
+ return EXIT_SUCCESS; /* bash compat */
+ }
+ G.flag_break_continue++; /* BC_BREAK = 1, or BC_CONTINUE = 2 */
+
+ G.depth_break_continue = depth = parse_numeric_argv1(argv, 1, 1);
+ if (depth == UINT_MAX)
+ G.flag_break_continue = BC_BREAK;
+ if (G.depth_of_loop < depth)
+ G.depth_break_continue = G.depth_of_loop;
+
+ return EXIT_SUCCESS;
+}
+
+static int FAST_FUNC builtin_continue(char **argv)
+{
+ G.flag_break_continue = 1; /* BC_CONTINUE = 2 = 1+1 */
+ return builtin_break(argv);
+}
+#endif
+
+#if ENABLE_HUSH_FUNCTIONS
+static int FAST_FUNC builtin_return(char **argv)
+{
+ int rc;
+
+ if (G_flag_return_in_progress != -1) {
+ bb_error_msg("%s: not in a function or sourced script", argv[0]);
+ return EXIT_FAILURE; /* bash compat */
+ }
+
+ G_flag_return_in_progress = 1;
+
+ /* bash:
+ * out of range: wraps around at 256, does not error out
+ * non-numeric param:
+ * f() { false; return qwe; }; f; echo $?
+ * bash: return: qwe: numeric argument required <== we do this
+ * 255 <== we also do this
+ */
+ rc = parse_numeric_argv1(argv, G.last_exitcode, 0);
+# if ENABLE_HUSH_TRAP
+ if (argv[1]) { /* "return ARG" inside a running trap sets $? */
+ debug_printf_exec("G.return_exitcode=%d\n", rc);
+ G.return_exitcode = rc;
+ }
+# endif
+ return rc;
+}
+#endif
+
+#if ENABLE_HUSH_TIMES
+static int FAST_FUNC builtin_times(char **argv UNUSED_PARAM)
+{
+ static const uint8_t times_tbl[] ALIGN1 = {
+ ' ', offsetof(struct tms, tms_utime),
+ '\n', offsetof(struct tms, tms_stime),
+ ' ', offsetof(struct tms, tms_cutime),
+ '\n', offsetof(struct tms, tms_cstime),
+ 0
+ };
+ const uint8_t *p;
+ unsigned clk_tck;
+ struct tms buf;
+
+ clk_tck = bb_clk_tck();
+
+ times(&buf);
+ p = times_tbl;
+ do {
+ unsigned sec, frac;
+ unsigned long t;
+ t = *(clock_t *)(((char *) &buf) + p[1]);
+ sec = t / clk_tck;
+ frac = t % clk_tck;
+ printf("%um%u.%03us%c",
+ sec / 60, sec % 60,
+ (frac * 1000) / clk_tck,
+ p[0]);
+ p += 2;
+ } while (*p);
+
+ return EXIT_SUCCESS;
+}
+#endif
+
+#if ENABLE_HUSH_MEMLEAK
+static int FAST_FUNC builtin_memleak(char **argv UNUSED_PARAM)
+{
+ void *p;
+ unsigned long l;
+
+# ifdef M_TRIM_THRESHOLD
+ /* Optional. Reduces probability of false positives */
+ malloc_trim(0);
+# endif
+ /* Crude attempt to find where "free memory" starts,
+ * sans fragmentation. */
+ p = malloc(240);
+ l = (unsigned long)p;
+ free(p);
+ p = malloc(3400);
+ if (l < (unsigned long)p) l = (unsigned long)p;
+ free(p);
+
+
+# if 0 /* debug */
+ {
+ struct mallinfo mi = mallinfo();
+ printf("top alloc:0x%lx malloced:%d+%d=%d\n", l,
+ mi.arena, mi.hblkhd, mi.arena + mi.hblkhd);
+ }
+# endif
+
+ if (!G.memleak_value)
+ G.memleak_value = l;
+
+ l -= G.memleak_value;
+ if ((long)l < 0)
+ l = 0;
+ l /= 1024;
+ if (l > 127)
+ l = 127;
+
+ /* Exitcode is "how many kilobytes we leaked since 1st call" */
+ return l;
+}
+#endif
+#endif /* !__U_BOOT__ */
#include <bootretry.h>
#include <cli.h>
#include <command.h>
+#include <hang.h>
+#include <malloc.h>
#include <time.h>
#include <watchdog.h>
#include <asm/global_data.h>
static unsigned hist_num;
static char *hist_list[HIST_MAX];
-static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
getcmd_putch(ch);
}
-static void hist_init(void)
+static int hist_init(void)
{
+ unsigned char *hist;
int i;
hist_max = 0;
hist_cur = -1;
hist_num = 0;
- for (i = 0; i < HIST_MAX; i++) {
- hist_list[i] = hist_lines[i];
- hist_list[i][0] = '\0';
- }
+ hist = calloc(HIST_MAX, HIST_SIZE + 1);
+ if (!hist)
+ return -ENOMEM;
+
+ for (i = 0; i < HIST_MAX; i++)
+ hist_list[i] = hist + (i * (HIST_SIZE + 1));
+
+ return 0;
}
static void cread_add_to_hist(char *line)
#else /* !CONFIG_CMDLINE_EDITING */
-static inline void hist_init(void)
+static inline int hist_init(void)
{
+ return 0;
}
static int cread_line(const char *const prompt, char *buf, unsigned int *len,
*/
if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) {
if (!initted) {
- hist_init();
- initted = 1;
+ rc = hist_init();
+ if (rc == 0)
+ initted = 1;
}
if (prompt)
#define debug_parser(fmt, args...) \
debug_cond(DEBUG_PARSER, fmt, ##args)
-
-int cli_simple_parse_line(char *line, char *argv[])
-{
- int nargs = 0;
-
- debug_parser("%s: \"%s\"\n", __func__, line);
- while (nargs < CONFIG_SYS_MAXARGS) {
- /* skip any white space */
- while (isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("%s: nargs=%d\n", __func__, nargs);
- return nargs;
- }
-
- argv[nargs++] = line; /* begin of argument string */
-
- /* find end of string */
- while (*line && !isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("parse_line: nargs=%d\n", nargs);
- return nargs;
- }
-
- *line++ = '\0'; /* terminate current arg */
- }
-
- printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
-
- debug_parser("%s: nargs=%d\n", __func__, nargs);
- return nargs;
-}
-
int cli_simple_process_macros(const char *input, char *output, int max_size)
{
char c, prev;
return ret;
}
+#ifdef CONFIG_CMDLINE
+int cli_simple_parse_line(char *line, char *argv[])
+{
+ int nargs = 0;
+
+ debug_parser("%s: \"%s\"\n", __func__, line);
+ while (nargs < CONFIG_SYS_MAXARGS) {
+ /* skip any white space */
+ while (isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+ }
+
+ argv[nargs++] = line; /* begin of argument string */
+
+ /* find end of string */
+ while (*line && !isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("parse_line: nargs=%d\n", nargs);
+ return nargs;
+ }
+
+ *line++ = '\0'; /* terminate current arg */
+ }
+
+ printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
+
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+}
+
/*
* WARNING:
*
return rcode;
}
+#endif
return len;
}
-static char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */
-
int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
{
+ char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */
int n = *np, col = *colp;
char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
char *cmdv[20];
#include <stdio_dev.h>
#include <exports.h>
#include <env_internal.h>
+#include <video_console.h>
#include <watchdog.h>
#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
+#define CSI "\x1b["
+
static int on_console(const char *name, const char *value, enum env_op op,
int flags)
{
return 0;
}
+int console_clear(void)
+{
+ /*
+ * Send clear screen and home
+ *
+ * FIXME(Heinrich Schuchardt <xypron.glpk@gmx.de>): This should go
+ * through an API and only be written to serial terminals, not video
+ * displays
+ */
+ printf(CSI "2J" CSI "1;1H");
+ if (IS_ENABLED(CONFIG_VIDEO_ANSI))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_VIDEO)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev);
+ if (ret)
+ return ret;
+ ret = vidconsole_clear_and_reset(dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void stdio_print_current_devices(void)
{
char *stdinname, *stdoutname, *stderrname;
#include <common.h>
#include <autoboot.h>
#include <bootstage.h>
+#include <bootstd.h>
#include <cli.h>
#include <command.h>
#include <console.h>
autoboot_command(s);
+ /* if standard boot if enabled, assume that it will be able to boot */
+ if (IS_ENABLED(CONFIG_BOOTSTD_PROG)) {
+ int ret;
+
+ ret = bootstd_prog_boot();
+ printf("Standard boot failed (err=%dE)\n", ret);
+ panic("Failed to boot");
+ }
+
cli_loop();
+
panic("No CLI available");
}
config SPL_SHOW_ERRORS
bool "Show more information when something goes wrong"
+ depends on SPL_LIBCOMMON_SUPPORT
help
This enabled more verbose error messages and checking when something
goes wrong in SPL. For example, it shows the error code when U-Boot
config SPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in SPL"
depends on SPL_BINMAN_SYMBOLS
- default n if ARCH_IMX8M
+ default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in SPL which refer to U-Boot phases,
spl_board_init() from board_init_r(). This function should be
provided by the board.
+config SPL_LOAD_BLOCK
+ bool
+ help
+ Support loading images from block devices. This adds a bl_len member
+ to struct spl_load_info.
+
config SPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM"
+ select SPL_LOAD_BLOCK if MACH_IMX
help
Some platforms (e.g. the Rockchip RK3368) provide support in their
ROM for loading the next boot-stage after performing basic setup
default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x118000 if MACH_SUN50I_H6
- default 0x58000 if MACH_SUN50I_H616
+ default 0x52a00 if MACH_SUN50I_H616
default 0x40000 if MACH_SUN8I_R528
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I
banner ("U-Boot SPL ..."). This function should be provided by
the board.
+config SPL_SYS_MMCSD_RAW_MODE
+ bool
+ help
+ Support booting from an MMC without a filesystem.
+
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
+ select SPL_LOAD_BLOCK if SPL_MMC
+ select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
bool "MMC Raw mode: by partition"
+ select SPL_LOAD_BLOCK if SPL_MMC
+ select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
help
Use a partition for loading U-Boot when using MMC/SD in raw mode.
filesystem from within SPL. Support for the underlying block
device (e.g. MMC or USB) must be enabled separately.
+config SPL_FS_FAT_DMA_ALIGN
+ bool "Use DMA-aligned buffers with FAT"
+ depends on SPL_FS_FAT
+ select SPL_LOAD_BLOCK
+ default y if SPL_LOAD_FIT
+ help
+ The FAT filesystem driver tries to ensure that the reads it issues to
+ the block subsystem use DMA-aligned buffers. If the supplied buffer is
+ not DMA-aligned, the FAT driver will use a bounce-buffer and read
+ block-by-block. This is separate from the bounce-buffer used by the
+ block subsystem (CONFIG_BOUNCE_BUFFER).
+
+ Enable this config to align buffers passed to the FAT filesystem
+ driver. This will speed up reads, but will increase the size of U-Boot
+ by around 60 bytes.
+
config SPL_FS_LOAD_PAYLOAD_NAME
string "File to load for U-Boot from the filesystem"
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING
allows DRAM to be set up before loading U-Boot into that DRAM,
where it can run.
-config SPL_MTD_SUPPORT
+config SPL_MTD
bool "Support MTD drivers"
help
Enable support for MTD (Memory Technology Device) within SPL. MTD
config SPL_NAND_SUPPORT
bool "Support NAND flash"
+ select SPL_LOAD_BLOCK
help
Enable support for NAND (Negative AND) flash in SPL. NAND flash
can be used to allow SPL to load U-Boot from supported devices.
config SPL_FALCON_BOOT_MMCSD
bool "Enable Falcon boot from MMC or SD media"
depends on SPL_OS_BOOT && SPL_MMC
+ select SPL_LOAD_BLOCK
+ select SPL_SYS_MMCSD_RAW_MODE
help
Select this if the Falcon mode OS image mode is on MMC or SD media.
config SPL_NVME
bool "NVM Express device support"
depends on BLK
- select HAVE_BLOCK_DEVICE
select FS_LOADER
select SPL_BLK_FS
help
config TPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in TPL"
depends on TPL_BINMAN_SYMBOLS
- default n if ARCH_IMX8M
+ default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in TPL which refer to U-Boot phases,
config VPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in VPL"
depends on VPL_BINMAN_SYMBOLS
- default n if ARCH_IMX8M
+ default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in VPL which refer to U-Boot phases,
#include <mapmem.h>
#include <serial.h>
#include <spl.h>
+#include <spl_load.h>
#include <system-constants.h>
#include <asm/global_data.h>
#include <asm-generic/gpio.h>
return 0;
}
+#if SPL_LOAD_USERS > 1
+int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev, struct spl_load_info *info,
+ size_t size, size_t offset)
+{
+ return _spl_load(spl_image, bootdev, info, size, offset);
+}
+#endif
+
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
ret = boot_from_devices(&spl_image, spl_boot_list,
ARRAY_SIZE(spl_boot_list));
if (ret) {
- if (CONFIG_IS_ENABLED(SHOW_ERRORS) &&
- CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT))
+ if (CONFIG_IS_ENABLED(SHOW_ERRORS))
printf(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n",
ret);
else
#include <common.h>
#include <spl.h>
+#include <spl_load.h>
#include <image.h>
#include <fs.h>
+#include <asm/cache.h>
#include <asm/io.h>
struct blk_dev {
const char *ifname;
+ const char *filename;
char dev_part_str[8];
};
return ret;
}
- ret = fs_read(load->filename, virt_to_phys(buf), file_offset, size,
+ ret = fs_read(dev->filename, virt_to_phys(buf), file_offset, size,
&actlen);
if (ret < 0) {
printf("spl: error reading image %s. Err - %d\n",
- load->filename, ret);
+ dev->filename, ret);
return ret;
}
enum uclass_id uclass_id, int devnum, int partnum)
{
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
- struct legacy_img_hdr *header;
struct blk_desc *blk_desc;
- loff_t actlen, filesize;
+ loff_t filesize;
struct blk_dev dev;
+ struct spl_load_info load;
int ret;
blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum);
}
blk_show_device(uclass_id, devnum);
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ dev.filename = filename;
dev.ifname = blk_get_uclass_name(uclass_id);
snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x",
devnum, partnum);
if (ret) {
printf("spl: unable to set blk_dev %s %s. Err - %d\n",
dev.ifname, dev.dev_part_str, ret);
- goto out;
- }
-
- ret = fs_read(filename, virt_to_phys(header), 0,
- sizeof(struct legacy_img_hdr), &actlen);
- if (ret) {
- printf("spl: unable to read file %s. Err - %d\n", filename,
- ret);
- goto out;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = spl_fit_read;
- load.bl_len = 1;
- load.filename = (void *)filename;
- load.priv = &dev;
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- }
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret) {
- printf("spl: unable to parse image header. Err - %d\n",
- ret);
- goto out;
- }
-
- ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
- if (ret) {
- printf("spl: unable to set blk_dev %s %s. Err - %d\n",
- dev.ifname, dev.dev_part_str, ret);
- goto out;
+ return ret;
}
ret = fs_size(filename, &filesize);
if (ret) {
printf("spl: unable to get file size: %s. Err - %d\n",
filename, ret);
- goto out;
- }
-
- ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
- if (ret) {
- printf("spl: unable to set blk_dev %s %s. Err - %d\n",
- dev.ifname, dev.dev_part_str, ret);
- goto out;
+ return ret;
}
- ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize,
- &actlen);
- if (ret)
- printf("spl: unable to read file %s. Err - %d\n",
- filename, ret);
-out:
- return ret;
+ load.read = spl_fit_read;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
+ spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
+ else
+ spl_set_bl_len(&load, 1);
+ load.priv = &dev;
+ return spl_load(spl_image, bootdev, &load, filesize, 0);
}
#include <common.h>
#include <env.h>
-#include <mapmem.h>
#include <part.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/u-boot.h>
#include <ext4fs.h>
#include <errno.h>
#include <image.h>
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ int ret;
+ loff_t actlen;
+
+ ret = ext4fs_read(buf, file_offset, size, &actlen);
+ if (ret)
+ return ret;
+ return actlen;
+}
+
int spl_load_image_ext(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct blk_desc *block_dev, int partition,
const char *filename)
{
s32 err;
- struct legacy_img_hdr *header;
- loff_t filelen, actlen;
+ loff_t filelen;
struct disk_partition part_info = {};
-
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ struct spl_load_info load;
if (part_get_info(block_dev, partition, &part_info)) {
printf("spl: no partition table found\n");
ext4fs_set_blk_dev(block_dev, &part_info);
- err = ext4fs_mount(part_info.size);
+ err = ext4fs_mount();
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
puts("spl: ext4fs_open failed\n");
goto end;
}
- err = ext4fs_read((char *)header, 0, sizeof(struct legacy_img_hdr), &actlen);
- if (err < 0) {
- puts("spl: ext4fs_read failed\n");
- goto end;
- }
-
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err < 0) {
- puts("spl: ext: failed to parse image header\n");
- goto end;
- }
- err = ext4fs_read(map_sysmem(spl_image->load_addr, filelen), 0, filelen,
- &actlen);
+ spl_set_bl_len(&load, 1);
+ load.read = spl_fit_read;
+ err = spl_load(spl_image, bootdev, &load, filelen, 0);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
ext4fs_set_blk_dev(block_dev, &part_info);
- err = ext4fs_mount(part_info.size);
+ err = ext4fs_mount();
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
#include <common.h>
#include <env.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/u-boot.h>
#include <fat.h>
#include <errno.h>
{
loff_t actread;
int ret;
- char *filename = (char *)load->filename;
+ char *filename = load->priv;
ret = fat_read_file(filename, buf, file_offset, size, &actread);
if (ret)
const char *filename)
{
int err;
- struct legacy_img_hdr *header;
+ loff_t size;
+ struct spl_load_info load;
err = spl_register_fat_device(block_dev, partition);
if (err)
goto end;
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
-
- err = file_fat_read(filename, header, sizeof(struct legacy_img_hdr));
- if (err <= 0)
- goto end;
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- err = file_fat_read(filename,
- map_sysmem(CONFIG_SYS_LOAD_ADDR, 0), 0);
- if (err <= 0)
- goto end;
- err = spl_parse_image_header(spl_image, bootdev,
- map_sysmem(CONFIG_SYS_LOAD_ADDR,
- err));
- if (err == -EAGAIN)
- return err;
- if (err == 0)
- err = 1;
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = spl_fit_read;
- load.bl_len = 1;
- load.filename = (void *)filename;
- load.priv = NULL;
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
+ /*
+ * Avoid pulling in this function for other image types since we are
+ * very short on space on some boards.
+ */
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+ err = fat_size(filename, &size);
if (err)
goto end;
-
- err = file_fat_read(filename, map_sysmem(spl_image->load_addr,
- spl_image->size), 0);
+ } else {
+ size = 0;
}
+ load.read = spl_fit_read;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
+ spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
+ else
+ spl_set_bl_len(&load, 1);
+ load.priv = (void *)filename;
+ err = spl_load(spl_image, bootdev, &load, size, 0);
+
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (err <= 0)
+ if (err < 0)
printf("%s: error reading image %s, err - %d\n",
__func__, filename, err);
#endif
- return (err <= 0);
+ return err;
}
#if CONFIG_IS_ENABLED(OS_BOOT)
#include <mapmem.h>
#include <spl.h>
#include <sysinfo.h>
-#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/libfdt.h>
static int get_aligned_image_offset(struct spl_load_info *info, int offset)
{
- /*
- * If it is a FS read, get the first address before offset which is
- * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
- * block number to which offset belongs.
- */
- if (info->filename)
- return offset & ~(ARCH_DMA_MINALIGN - 1);
-
- return offset / info->bl_len;
+ return ALIGN_DOWN(offset, spl_get_bl_len(info));
}
static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
{
- /*
- * If it is a FS read, get the difference between the offset and
- * the first address before offset which is aligned to
- * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
- * block.
- */
- if (info->filename)
- return offset & (ARCH_DMA_MINALIGN - 1);
-
- return offset % info->bl_len;
+ return offset & (spl_get_bl_len(info) - 1);
}
static int get_aligned_image_size(struct spl_load_info *info, int data_size,
{
data_size = data_size + get_aligned_image_overhead(info, offset);
- if (info->filename)
- return data_size;
-
- return (data_size + info->bl_len - 1) / info->bl_len;
+ return ALIGN(data_size, spl_get_bl_len(info));
}
/**
*
* Return: 0 on success or a negative error number.
*/
-static int load_simple_fit(struct spl_load_info *info, ulong sector,
+static int load_simple_fit(struct spl_load_info *info, ulong fit_offset,
const struct spl_fit_info *ctx, int node,
struct spl_image_info *image_info)
{
void *load_ptr;
void *src;
ulong overhead;
- int nr_sectors;
uint8_t image_comp = -1, type = -1;
const void *data;
const void *fit = ctx->fit;
length = len;
overhead = get_aligned_image_overhead(info, offset);
- nr_sectors = get_aligned_image_size(info, length, offset);
+ size = get_aligned_image_size(info, length, offset);
if (info->read(info,
- sector + get_aligned_image_offset(info, offset),
- nr_sectors, src_ptr) != nr_sectors)
+ fit_offset +
+ get_aligned_image_offset(info, offset), size,
+ src_ptr) < length)
return -EIO;
debug("External data: dst=%p, offset=%x, size=%lx\n",
}
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector,
+ struct spl_load_info *info, ulong offset,
const struct spl_fit_info *ctx)
{
struct spl_image_info image_info;
spl_image->fdt_addr = map_sysmem(image_info.load_addr, size);
memcpy(spl_image->fdt_addr, gd->fdt_blob, size);
} else {
- ret = load_simple_fit(info, sector, ctx, node, &image_info);
+ ret = load_simple_fit(info, offset, ctx, node, &image_info);
if (ret < 0)
return ret;
__func__);
}
image_info.load_addr = (ulong)tmpbuffer;
- ret = load_simple_fit(info, sector, ctx, node,
+ ret = load_simple_fit(info, offset, ctx, node,
&image_info);
if (ret < 0)
break;
}
static int spl_fit_load_fpga(struct spl_fit_info *ctx,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
int node, ret;
warn_deprecated("'fpga' property in config node. Use 'loadables'");
/* Load the image and set up the fpga_image structure */
- ret = load_simple_fit(info, sector, ctx, node, &fpga_image);
+ ret = load_simple_fit(info, offset, ctx, node, &fpga_image);
if (ret) {
printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
return ret;
}
static int spl_simple_fit_read(struct spl_fit_info *ctx,
- struct spl_load_info *info, ulong sector,
+ struct spl_load_info *info, ulong offset,
const void *fit_header)
{
unsigned long count, size;
- int sectors;
void *buf;
/*
* For FIT with data embedded, data is loaded as part of FIT image.
* For FIT with external data, data is not loaded in this step.
*/
- sectors = get_aligned_image_size(info, size, 0);
- buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
+ size = get_aligned_image_size(info, size, 0);
+ buf = board_spl_fit_buffer_addr(size, size, 1);
- count = info->read(info, sector, sectors, buf);
+ count = info->read(info, offset, size, buf);
ctx->fit = buf;
- debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
- sector, sectors, buf, count, size);
+ debug("fit read offset %lx, size=%lu, dst=%p, count=%lu\n",
+ offset, size, buf, count);
return (count == 0) ? -EIO : 0;
}
}
int spl_load_simple_fit(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector, void *fit)
+ struct spl_load_info *info, ulong offset, void *fit)
{
struct spl_image_info image_info;
struct spl_fit_info ctx;
int index = 0;
int firmware_node;
- ret = spl_simple_fit_read(&ctx, info, sector, fit);
+ ret = spl_simple_fit_read(&ctx, info, offset, fit);
if (ret < 0)
return ret;
return ret;
if (IS_ENABLED(CONFIG_SPL_FPGA))
- spl_fit_load_fpga(&ctx, info, sector);
+ spl_fit_load_fpga(&ctx, info, offset);
/*
* Find the U-Boot image using the following search order:
}
/* Load the image and set up the spl_image structure */
- ret = load_simple_fit(info, sector, &ctx, node, spl_image);
+ ret = load_simple_fit(info, offset, &ctx, node, spl_image);
if (ret)
return ret;
* We allow this to fail, as the U-Boot image might embed its FDT.
*/
if (os_takes_devicetree(spl_image->os)) {
- ret = spl_fit_append_fdt(spl_image, info, sector, &ctx);
+ ret = spl_fit_append_fdt(spl_image, info, offset, &ctx);
if (ret < 0 && spl_image->os != IH_OS_U_BOOT)
return ret;
}
continue;
image_info.load_addr = 0;
- ret = load_simple_fit(info, sector, &ctx, node, &image_info);
+ ret = load_simple_fit(info, offset, &ctx, node, &image_info);
if (ret < 0) {
printf("%s: can't load image loadables index %d (ret = %d)\n",
__func__, index, ret);
debug("Loadable is %s\n", genimg_get_os_name(os_type));
if (os_takes_devicetree(os_type)) {
- spl_fit_append_fdt(&image_info, info, sector, &ctx);
+ spl_fit_append_fdt(&image_info, info, offset, &ctx);
spl_image->fdt_addr = image_info.fdt_addr;
}
struct spl_load_info *info,
struct container_hdr *container,
int image_index,
- u32 container_sector)
+ ulong container_offset)
{
struct boot_img_t *images;
- ulong sector;
- u32 sectors;
+ ulong offset, overhead, size;
if (image_index > container->num_images) {
debug("Invalid image number\n");
images = (struct boot_img_t *)((u8 *)container +
sizeof(struct container_hdr));
- if (images[image_index].offset % info->bl_len) {
+ if (!IS_ALIGNED(images[image_index].offset, spl_get_bl_len(info))) {
printf("%s: image%d offset not aligned to %u\n",
- __func__, image_index, info->bl_len);
+ __func__, image_index, spl_get_bl_len(info));
return NULL;
}
- sectors = roundup(images[image_index].size, info->bl_len) /
- info->bl_len;
- sector = images[image_index].offset / info->bl_len +
- container_sector;
+ size = ALIGN(images[image_index].size, spl_get_bl_len(info));
+ offset = images[image_index].offset + container_offset;
- debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
- container, sector, sectors);
- if (info->read(info, sector, sectors,
- map_sysmem(images[image_index].dst,
- images[image_index].size)) != sectors) {
+ debug("%s: container: %p offset: %lu size: %lu\n", __func__,
+ container, offset, size);
+ if (info->read(info, offset, size,
+ map_sysmem(images[image_index].dst - overhead,
+ images[image_index].size)) <
+ images[image_index].size) {
printf("%s wrong\n", __func__);
return NULL;
}
}
static int read_auth_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
struct container_hdr *container = NULL;
u16 length;
- u32 sectors;
int i, size, ret = 0;
- size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len);
- sectors = size / info->bl_len;
+ size = ALIGN(CONTAINER_HDR_ALIGNMENT, spl_get_bl_len(info));
/*
* It will not override the ATF code, so safe to use it here,
if (!container)
return -ENOMEM;
- debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
- container, sector, sectors);
- if (info->read(info, sector, sectors, container) != sectors) {
+ debug("%s: container: %p offset: %lu size: %u\n", __func__,
+ container, offset, size);
+ if (info->read(info, offset, size, container) <
+ CONTAINER_HDR_ALIGNMENT) {
ret = -EIO;
goto end;
}
debug("Container length %u\n", length);
if (length > CONTAINER_HDR_ALIGNMENT) {
- size = roundup(length, info->bl_len);
- sectors = size / info->bl_len;
+ size = ALIGN(length, spl_get_bl_len(info));
free(container);
container = malloc(size);
if (!container)
return -ENOMEM;
- debug("%s: container: %p sector: %lu sectors: %u\n",
- __func__, container, sector, sectors);
- if (info->read(info, sector, sectors, container) !=
- sectors) {
+ debug("%s: container: %p offset: %lu size: %u\n",
+ __func__, container, offset, size);
+ if (info->read(info, offset, size, container) < length) {
ret = -EIO;
goto end;
}
for (i = 0; i < container->num_images; i++) {
struct boot_img_t *image = read_auth_image(spl_image, info,
container, i,
- sector);
+ offset);
if (!image) {
ret = -EINVAL;
}
int spl_load_imx_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
- return read_auth_container(spl_image, info, sector);
+ return read_auth_container(spl_image, info, offset);
}
return 0;
}
-/*
- * This function is added explicitly to avoid code size increase, when
- * no compression method is enabled. The compiler will optimize the
- * following switch/case statement in spl_load_legacy_img() away due to
- * Dead Code Elimination.
- */
-static inline int spl_image_get_comp(const struct legacy_img_hdr *hdr)
-{
- if (IS_ENABLED(CONFIG_SPL_LZMA))
- return image_get_comp(hdr);
-
- return IH_COMP_NONE;
-}
-
-int spl_load_legacy_img(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct spl_load_info *load, ulong offset,
- struct legacy_img_hdr *hdr)
+int spl_load_legacy_lzma(struct spl_image_info *spl_image,
+ struct spl_load_info *load, ulong offset)
{
- __maybe_unused SizeT lzma_len;
- __maybe_unused void *src;
- ulong dataptr;
+ SizeT lzma_len = LZMA_LEN;
+ void *src;
+ ulong dataptr, overhead, size;
int ret;
- /*
- * If the payload is compressed, the decompressed data should be
- * directly write to its load address.
- */
- if (spl_image_get_comp(hdr) != IH_COMP_NONE)
- spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
+ /* dataptr points to compressed payload */
+ dataptr = ALIGN_DOWN(sizeof(struct legacy_img_hdr),
+ spl_get_bl_len(load));
+ overhead = sizeof(struct legacy_img_hdr) - dataptr;
+ size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load));
+ dataptr += offset;
+
+ debug("LZMA: Decompressing %08lx to %08lx\n",
+ dataptr, spl_image->load_addr);
+ src = malloc(size);
+ if (!src) {
+ printf("Unable to allocate %d bytes for LZMA\n",
+ spl_image->size);
+ return -ENOMEM;
+ }
- ret = spl_parse_image_header(spl_image, bootdev, hdr);
- if (ret)
+ load->read(load, dataptr, size, src);
+ ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr,
+ spl_image->size), &lzma_len,
+ src + overhead, spl_image->size);
+ if (ret) {
+ printf("LZMA decompression error: %d\n", ret);
return ret;
-
- /* Read image */
- switch (spl_image_get_comp(hdr)) {
- case IH_COMP_NONE:
- dataptr = offset;
-
- /*
- * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY
- * is set
- */
- if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
- dataptr += sizeof(*hdr);
-
- load->read(load, dataptr, spl_image->size,
- map_sysmem(spl_image->load_addr, spl_image->size));
- break;
-
- case IH_COMP_LZMA:
- lzma_len = LZMA_LEN;
-
- /* dataptr points to compressed payload */
- dataptr = offset + sizeof(*hdr);
-
- debug("LZMA: Decompressing %08lx to %08lx\n",
- dataptr, spl_image->load_addr);
- src = malloc(spl_image->size);
- if (!src) {
- printf("Unable to allocate %d bytes for LZMA\n",
- spl_image->size);
- return -ENOMEM;
- }
-
- load->read(load, dataptr, spl_image->size, src);
- ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr,
- spl_image->size),
- &lzma_len, src, spl_image->size);
- if (ret) {
- printf("LZMA decompression error: %d\n", ret);
- return ret;
- }
-
- spl_image->size = lzma_len;
- break;
-
- default:
- debug("Compression method %s is not supported\n",
- genimg_get_comp_short_name(image_get_comp(hdr)));
- return -EINVAL;
}
+ spl_image->size = lzma_len;
return 0;
}
#include <common.h>
#include <dm.h>
#include <log.h>
-#include <mapmem.h>
#include <part.h>
#include <spl.h>
+#include <spl_load.h>
#include <linux/compiler.h>
#include <errno.h>
#include <asm/u-boot.h>
#include <image.h>
#include <imx_container.h>
-static int mmc_load_legacy(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct mmc *mmc,
- ulong sector, struct legacy_img_hdr *header)
+static ulong h_spl_load_read(struct spl_load_info *load, ulong off,
+ ulong size, void *buf)
{
- u32 image_offset_sectors;
- u32 image_size_sectors;
- unsigned long count;
- u32 image_offset;
- int ret;
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret)
- return ret;
-
- /* convert offset to sectors - round down */
- image_offset_sectors = spl_image->offset / mmc->read_bl_len;
- /* calculate remaining offset */
- image_offset = spl_image->offset % mmc->read_bl_len;
+ struct blk_desc *bd = load->priv;
+ lbaint_t sector = off >> bd->log2blksz;
+ lbaint_t count = size >> bd->log2blksz;
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) /
- mmc->read_bl_len;
-
- /* Read the header too to avoid extra memcpy */
- count = blk_dread(mmc_get_blk_desc(mmc),
- sector + image_offset_sectors,
- image_size_sectors,
- map_sysmem(spl_image->load_addr,
- image_size_sectors * mmc->read_bl_len));
- debug("read %x sectors to %lx\n", image_size_sectors,
- spl_image->load_addr);
- if (count != image_size_sectors)
- return -EIO;
-
- if (image_offset)
- memmove((void *)(ulong)spl_image->load_addr,
- (void *)(ulong)spl_image->load_addr + image_offset,
- spl_image->size);
-
- return 0;
-}
-
-static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
-{
- struct mmc *mmc = load->dev;
-
- return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
+ return blk_dread(bd, sector, count, buf) << bd->log2blksz;
}
static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part)
struct spl_boot_device *bootdev,
struct mmc *mmc, unsigned long sector)
{
- unsigned long count;
- struct legacy_img_hdr *header;
+ int ret;
struct blk_desc *bd = mmc_get_blk_desc(mmc);
- int ret = 0;
-
- header = spl_get_load_buffer(-sizeof(*header), bd->blksz);
-
- /* read image header to find the image size & load address */
- count = blk_dread(bd, sector, 1, header);
- debug("hdr read sector %lx, count=%lu\n", sector, count);
- if (count == 0) {
- ret = -EIO;
- goto end;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
- ret = spl_load_simple_fit(spl_image, &load, sector, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
-
- ret = spl_load_imx_container(spl_image, &load, sector);
- } else {
- ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header);
- }
+ struct spl_load_info load;
-end:
+ load.priv = bd;
+ spl_set_bl_len(&load, bd->blksz);
+ load.read = h_spl_load_read;
+ ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz);
if (ret) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_sector: mmc block read error\n");
#include <imx_container.h>
#include <log.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/io.h>
+#include <mapmem.h>
#include <nand.h>
#include <linux/libfdt_env.h>
#include <fdt.h>
nand_spl_load_image(spl_nand_get_uboot_raw_page(),
CFG_SYS_NAND_U_BOOT_SIZE,
- (void *)CFG_SYS_NAND_U_BOOT_DST);
+ map_sysmem(CFG_SYS_NAND_U_BOOT_DST,
+ CFG_SYS_NAND_U_BOOT_SIZE));
spl_set_header_raw_uboot(spl_image);
nand_deselect();
}
#else
-static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
- ulong size, void *dst)
+__weak u32 nand_spl_adjust_offset(u32 sector, u32 offs)
{
- int err;
- ulong sector;
-
- sector = *(int *)load->priv;
- offs *= load->bl_len;
- size *= load->bl_len;
- offs = sector + nand_spl_adjust_offset(sector, offs - sector);
- err = nand_spl_load_image(offs, size, dst);
- if (err)
- return 0;
-
- return size / load->bl_len;
+ return offs;
}
-static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs,
- ulong size, void *dst)
+static ulong spl_nand_read(struct spl_load_info *load, ulong offs, ulong size,
+ void *dst)
{
int err;
+ ulong sector;
debug("%s: offs %lx, size %lx, dst %p\n",
__func__, offs, size, dst);
+ sector = *(int *)load->priv;
+ offs = sector + nand_spl_adjust_offset(sector, offs - sector);
err = nand_spl_load_image(offs, size, dst);
+ spl_set_bl_len(load, nand_page_size());
if (err)
return 0;
return size;
}
-struct mtd_info * __weak nand_get_mtd(void)
-{
- return NULL;
-}
-
static int spl_nand_load_element(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- int offset, struct legacy_img_hdr *header)
+ struct spl_boot_device *bootdev, int offset)
{
- struct mtd_info *mtd = nand_get_mtd();
- int bl_len = mtd ? mtd->writesize : 1;
- int err;
+ struct spl_load_info load;
- err = nand_spl_load_image(offset, sizeof(*header), (void *)header);
- if (err)
- return err;
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = NULL;
- load.priv = &offset;
- load.filename = NULL;
- load.bl_len = bl_len;
- load.read = spl_nand_fit_read;
- return spl_load_simple_fit(spl_image, &load, offset / bl_len, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = bl_len;
- load.read = spl_nand_fit_read;
- return spl_load_imx_container(spl_image, &load, offset / bl_len);
- } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) &&
- image_get_magic(header) == IH_MAGIC) {
- struct spl_load_info load;
-
- debug("Found legacy image\n");
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_nand_legacy_read;
-
- return spl_load_legacy_img(spl_image, bootdev, &load, offset, header);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
- return nand_spl_load_image(offset, spl_image->size,
- (void *)(ulong)spl_image->load_addr);
- }
+ load.priv = &offset;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_nand_read;
+ return spl_load(spl_image, bootdev, &load, 0, offset);
}
static int spl_nand_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
int err;
- struct legacy_img_hdr *header;
- int *src __attribute__((unused));
- int *dst __attribute__((unused));
#ifdef CONFIG_SPL_NAND_SOFTECC
debug("spl: nand - using sw ecc\n");
#endif
nand_init();
- header = spl_get_load_buffer(0, sizeof(*header));
-
#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
+ int *src, *dst;
+ struct legacy_img_hdr *header =
+ spl_get_load_buffer(0, sizeof(*header));
+
/*
* load parameter image
* load to temp position since nand_spl_load_image reads
}
#endif
#ifdef CONFIG_NAND_ENV_DST
- spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET, header);
+ spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET);
#ifdef CONFIG_ENV_OFFSET_REDUND
- spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND, header);
+ spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND);
#endif
#endif
/* Load u-boot */
- err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page(),
- header);
+ err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page());
#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
#if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
if (err)
err = spl_nand_load_element(spl_image, bootdev,
- CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
- header);
+ CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND);
#endif
#endif
nand_deselect();
#include <errno.h>
#include <image.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
#include <net.h>
#include <linux/libfdt.h>
static int spl_net_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- struct legacy_img_hdr *header = map_sysmem(image_load_addr,
- sizeof(*header));
+ struct spl_load_info load;
int rv;
env_init();
return rv;
}
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.bl_len = 1;
- load.read = spl_net_load_read;
- rv = spl_load_simple_fit(spl_image, &load, 0, header);
- } else {
- debug("Legacy image\n");
-
- rv = spl_parse_image_header(spl_image, bootdev, header);
- if (rv)
- return rv;
-
- memcpy(map_sysmem(spl_image->load_addr, spl_image->size),
- map_sysmem(image_load_addr, spl_image->size),
- spl_image->size);
- }
-
- return rv;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_net_load_read;
+ return spl_load(spl_image, bootdev, &load, 0, 0);
}
#endif
#include <image.h>
#include <imx_container.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
static int spl_nor_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- struct legacy_img_hdr *header;
- __maybe_unused struct spl_load_info load;
+ struct spl_load_info load;
/*
* Loading of the payload to SDRAM is done with skipping of
* Load Linux from its location in NOR flash to its defined
* location in SDRAM
*/
- header = (void *)CONFIG_SYS_OS_BASE;
+ const struct legacy_img_hdr *header =
+ (const struct legacy_img_hdr *)CONFIG_SYS_OS_BASE;
#ifdef CONFIG_SPL_LOAD_FIT
if (image_get_magic(header) == FDT_MAGIC) {
int ret;
debug("Found FIT\n");
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_nor_load_read;
ret = spl_load_simple_fit(spl_image, &load,
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- header = map_sysmem(spl_nor_get_uboot_base(), sizeof(*header));
-#ifdef CONFIG_SPL_LOAD_FIT
- if (image_get_magic(header) == FDT_MAGIC) {
- debug("Found FIT format U-Boot\n");
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_simple_fit(spl_image, &load,
- spl_nor_get_uboot_base(),
- (void *)header);
- }
-#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_imx_container(spl_image, &load,
- spl_nor_get_uboot_base());
- }
-
- /* Legacy image handling */
- if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_legacy_img(spl_image, bootdev, &load,
- spl_nor_get_uboot_base(),
- header);
- }
-
- return -EINVAL;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_nor_load_read;
+ return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base());
}
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
struct spl_load_info load;
debug("Found FIT\n");
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_ram_load_read;
ret = spl_load_simple_fit(spl_image, &load, 0, header);
} else {
#include <log.h>
#include <semihosting.h>
#include <spl.h>
-
-static int smh_read_full(long fd, void *memp, size_t len)
-{
- long read;
-
- read = smh_read(fd, memp, len);
- if (read < 0)
- return read;
- if (read != len)
- return -EIO;
- return 0;
-}
+#include <spl_load.h>
static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset,
ulong size, void *buf)
{
- long fd;
+ long fd = *(long *)load->priv;
ulong ret;
- fd = smh_open(load->filename, MODE_READ | MODE_BINARY);
- if (fd < 0) {
- log_debug("could not open %s: %ld\n", load->filename, fd);
+ if (smh_seek(fd, file_offset))
return 0;
- }
- ret = smh_read(fd, buf, size);
- smh_close(fd);
- return ret;
+ ret = smh_read(fd, buf, size);
+ return ret < 0 ? 0 : ret;
}
static int spl_smh_load_image(struct spl_image_info *spl_image,
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
int ret;
long fd, len;
- struct legacy_img_hdr *header =
- spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ struct spl_load_info load;
fd = smh_open(filename, MODE_READ | MODE_BINARY);
if (fd < 0) {
}
len = ret;
- ret = smh_read_full(fd, header, sizeof(struct legacy_img_hdr));
- if (ret) {
- log_debug("could not read image header: %d\n", ret);
- goto out;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = smh_fit_read;
- load.bl_len = 1;
- load.filename = filename;
- load.priv = NULL;
- smh_close(fd);
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- }
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret) {
- log_debug("failed to parse image header: %d\n", ret);
- goto out;
- }
-
- ret = smh_seek(fd, 0);
- if (ret) {
- log_debug("could not seek to start of image: %d\n", ret);
- goto out;
- }
-
- ret = smh_read_full(fd, (void *)spl_image->load_addr, len);
+ load.read = smh_fit_read;
+ spl_set_bl_len(&load, 1);
+ load.priv = &fd;
+ ret = spl_load(spl_image, bootdev, &load, len, 0);
if (ret)
log_debug("could not read %s: %d\n", filename, ret);
out:
#include <image.h>
#include <imx_container.h>
#include <log.h>
-#include <mapmem.h>
#include <spi.h>
#include <spi_flash.h>
#include <errno.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/ofnode.h>
-#if CONFIG_IS_ENABLED(OS_BOOT)
-/*
- * Load the kernel, check for a valid header we can parse, and if found load
- * the kernel and then device tree.
- */
-static int spi_load_image_os(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct spi_flash *flash,
- struct legacy_img_hdr *header)
-{
- int err;
-
- /* Read for a header, parse or error out. */
- spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
- (void *)header);
-
- if (image_get_magic(header) != IH_MAGIC)
- return -1;
-
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
-
- spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS,
- spl_image->size, (void *)spl_image->load_addr);
-
- /* Read device tree. */
- spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
- CFG_SYS_SPI_ARGS_SIZE,
- (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
-
- return 0;
-}
-#endif
-
static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
- struct spi_flash *flash = load->dev;
+ struct spi_flash *flash = load->priv;
ulong ret;
ret = spi_flash_read(flash, sector, count, buf);
int err = 0;
unsigned int payload_offs;
struct spi_flash *flash;
- struct legacy_img_hdr *header;
unsigned int sf_bus = spl_spi_boot_bus();
unsigned int sf_cs = spl_spi_boot_cs();
+ struct spl_load_info load;
/*
* Load U-Boot image from SPI flash into RAM
return -ENODEV;
}
- payload_offs = spl_spi_get_uboot_offs(flash);
+ load.priv = flash;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_spi_fit_read;
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+#if CONFIG_IS_ENABLED(OS_BOOT)
+ if (spl_start_uboot()) {
+ int err = spl_load(spl_image, bootdev, &load, 0,
+ CFG_SYS_SPI_KERNEL_OFFS);
+
+ if (!err)
+ /* Read device tree. */
+ return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
+ CFG_SYS_SPI_ARGS_SIZE,
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
+ }
+#endif
+ payload_offs = spl_spi_get_uboot_offs(flash);
if (CONFIG_IS_ENABLED(OF_REAL)) {
payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset",
payload_offs);
}
-#if CONFIG_IS_ENABLED(OS_BOOT)
- if (spl_start_uboot() || spi_load_image_os(spl_image, bootdev, flash, header))
-#endif
- {
- /* Load u-boot, mkimage header is 64 bytes. */
- err = spi_flash_read(flash, payload_offs, sizeof(*header),
- (void *)header);
- if (err) {
- debug("%s: Failed to read from SPI flash (err=%d)\n",
- __func__, err);
- return err;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- u32 size = roundup(fdt_totalsize(header), 4);
-
- err = spi_flash_read(flash, payload_offs,
- size,
- map_sysmem(CONFIG_SYS_LOAD_ADDR,
- size));
- if (err)
- return err;
- err = spl_parse_image_header(spl_image, bootdev,
- phys_to_virt(CONFIG_SYS_LOAD_ADDR));
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
- err = spl_load_simple_fit(spl_image, &load,
- payload_offs,
- header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
-
- err = spl_load_imx_container(spl_image, &load,
- payload_offs);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
- err = spi_flash_read(flash, payload_offs + spl_image->offset,
- spl_image->size,
- map_sysmem(spl_image->load_addr,
- spl_image->size));
- }
- if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) {
- err = spi_nor_remove(flash);
- if (err)
- return err;
- }
- }
-
+ err = spl_load(spl_image, bootdev, &load, 0, payload_offs);
+ if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET))
+ err = spi_nor_remove(flash);
return err;
}
/* Use priorty 1 so that boards can override this */
struct ymodem_fit_info info;
debug("Found FIT\n");
- load.dev = NULL;
load.priv = (void *)&info;
- load.filename = NULL;
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
info.buf = buf;
info.image_read = BUF_SIZE;
load.read = ymodem_read_fit;
panic("Stack smashing detected in function:\n%p relocated from %p",
ra, ra - gd->reloc_off);
}
+
+void __stack_chk_fail_local(void)
+{
+ __stack_chk_fail();
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <timestamp.h>
+#include <version.h>
+#include <version_string.h>
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
+
+const char version_string[] = U_BOOT_VERSION_STRING;
+const unsigned short version_num = U_BOOT_VERSION_NUM;
+const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
CONFIG_SYS_MONITOR_BASE=0xCFF80000
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_MONITOR_BASE=0xD7F80000
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_SCCR_MASK=0x00000000
CONFIG_SYS_DER=0x2002000F
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_IMI is not set
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_IMI is not set
CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_MONITOR_BASE=0x00000400
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y
CONFIG_SYS_MONITOR_BASE=0xFFC00400
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_DEVICE_NULLDEV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_LOOPW=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_MONITOR_BASE=0xFF800400
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=5
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="bootm ffe40000"
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_MONITOR_BASE=0x00000400
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2"
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_MONITOR_BASE=0x00000400
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_MONITOR_BASE=0x00000400
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_MONITOR_BASE=0x00000400
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_SYS_DER=0x2002000F
CONFIG_SYS_MONITOR_BASE=0x04000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_FLUSH_STDIN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
+CONFIG_SYS_PBSIZE=278
# CONFIG_HWCONFIG is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="S3K> "
-CONFIG_SYS_PBSIZE=278
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_LOADB is not set
CONFIG_BOOTDELAY=6
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_LOADS_ECHO=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_TPL_MPC8XXX_INIT_DDR=y
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_TPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_LOAD_ADDR=0x1000000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SYS_LOAD_ADDR=0x1000000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_PBSIZE=1024
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=1024
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_PBSIZE=1024
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=1024
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_PBSIZE=1024
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=1024
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_TARGET_ANDES_AE350=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_ARCH_RV64I=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_TIMESTAMP=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_SPL=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_SPL=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_SPL_ETH=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_MUSB_NEW=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_EXTENSION=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00080000
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_SPL_MMC is not set
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_SPL=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x81000000
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL"
CONFIG_SPL_POWER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL=y
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
# CONFIG_SPL_YMODEM_SUPPORT is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_TIMESTAMP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SERIES=y
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_RESET_TO_RETRY=y
CONFIG_BOOTCOMMAND="if mmc dev 1; mmc rescan; then run emmc_setup; else echo ERROR: eMMC device not detected!; panic; fi; if run loaduimage; then run mmcboot; else echo ERROR Unable to load uImage from eMMC!; echo Performing Rollback!; setenv _active_ ${active_root}; setenv _inactive_ ${inactive_root}; setenv active_root ${_inactive_}; setenv inactive_root ${_active_}; saveenv; reset; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="noautoboot"
CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR: SD/MMC-Card not detected!; panic; fi; run fusecmd; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_RESET_TO_RETRY=y
CONFIG_BOOTCOMMAND="run fusecmd; if run netboot; then echo Booting from network; else echo ERROR: Cannot boot from network!; panic; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_RESET_TO_RETRY=y
CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR: SD/MMC-Card not detected!; panic; fi; if run loaduimage; then echo Bootable SD/MMC-Card inserted, booting from it!; run mmcboot; else echo ERROR: Unable to load uImage from SD/MMC-Card!; panic; fi; "
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
+CONFIG_SYS_PBSIZE=1054
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
# CONFIG_SPL_POWER is not set
CONFIG_SYS_PROMPT="AM3517_EVM # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0xaa0000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
CONFIG_CMD_SPL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_AHCI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LZO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x08000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_BEAGLEPLAY=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_TPS62360=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x7ec00
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
-CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="bootm ffc20000"
+CONFIG_SYS_PBSIZE=282
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="amcore $ "
-CONFIG_SYS_PBSIZE=282
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f650000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SYS_PROMPT="ap121 # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f680000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SYS_PROMPT="ap143 # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f060000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SYS_PROMPT="ap152 # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2068
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Apalis iMX8 # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
+CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd"
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1054
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Apalis TK1 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.10.1"
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1055
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
CONFIG_SYS_MAXARGS=48
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1055
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_LBA48=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x14420000
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1054
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Apalis T30 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_E1000=y
CONFIG_E1000_NO_NVM=y
CONFIG_ARCH_APPLE=y
CONFIG_DEFAULT_DEVICE_TREE="t8103-j274"
CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_NET is not set
CONFIG_APPLE_SPI_KEYB=y
# CONFIG_MMC is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
-# CONFIG_GENERATE_SMBIOS_TABLE is not set
+# CONFIG_SMBIOS is not set
CONFIG_LMB_MAX_REGIONS=64
CONFIG_SYS_MALLOC_LEN=0x240000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_RESET=y
# CONFIG_PSCI_RESET is not set
CONFIG_ARCH_NPCM8XX=y
+CONFIG_SYS_SKIP_UART_INIT=y
CONFIG_TARGET_ARBEL_EVB=y
CONFIG_SYS_LOAD_ADDR=0x06208000
CONFIG_ENV_ADDR=0x803C0000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x1400000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x1400000
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UUID=y
CONFIG_CMD_HASH=y
CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NPCM_SHA=y
CONFIG_NPCM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_NPCM=y
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_NPCM_HOST=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_NPCM=y
-CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_OHCI_NPCM=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Nuvoton"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0416
+CONFIG_USB_GADGET_PRODUCT_NUM=0xffff
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_LIB_HW_RAND=y
CONFIG_TPM=y
CONFIG_SHA_HW_ACCEL=y
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run ari_boot"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run ari_boot"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="ARNDALE # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset"
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="URMEL > "
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_IMLS=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:3; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_DEBUG_UART=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_DEBUG_UART=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:3; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 uImage; bootm"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x71000000 dtb; fatload mmc 0:1 0x72000000 zImage; bootz 0x72000000 - 0x71000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};fatload mmc 0:1 0x21000000 dtb;fatload mmc 0:1 0x22000000 uImage;bootm 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_nand};nand read 0x21000000 0x180000 0x080000;nand read 0x22000000 0x200000 0x400000;bootm 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_nand};sf probe 0; sf read 0x22000000 0x100000 0x300000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x80000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x20000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x22000000 0x100000 0x300000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flash_self"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x3e00
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=278
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AXS# "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=278
-CONFIG_SYS_BOOTM_LEN=0x8000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=278
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AXS# "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=278
-CONFIG_SYS_BOOTM_LEN=0x8000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=536
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=536
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_MTD=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+# CONFIG_RANDOM_UUID is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=536
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=536
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_IDENT_STRING=" Broadcom BCM47622"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM63138"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM63148"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM63178"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM6756"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=545
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="bcm968380gerg # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=545
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_IDENT_STRING=" Broadcom BCM6846"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM6855"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_IDENT_STRING=" Broadcom BCM6878"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x1800000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flash_pending_rfs_imgs;run fastboot_nitro && run bootcmd_mmc_fits || run bootcmd_usb || run bootcmd_pxe"
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1049
# CONFIG_SYS_XTRACE is not set
-CONFIG_SYS_BOOTM_LEN=0x1800000
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2075
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="antminer> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2075
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x3c00000
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_DM is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_PART=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTP_SERVERIP=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_MMC_SDHCI=y
CONFIG_WDT=y
CONFIG_WDT_CDNS=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
-# CONFIG_EFI_LOADER is not set
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_TOOLS_MKEFICAPSULE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run set_gpio122; run set_gpio96; sf probe; run manage_userdata; run bootcmd_nand"
CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=256
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PROMPT="boston # "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_PROMPT="boston # "
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=0
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="mw ${cfgaddr} 0; mw ${dtbaddr} 0; run cfgscr; run brdefaultip"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=0
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
CONFIG_BOOTCOMMAND="mmc dev 1; run b_default"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run cfgscr; run brdefaultip"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_MACH_S900=y
CONFIG_IDENT_STRING="\nBubblegum-96"
CONFIG_SYS_LOAD_ADDR=0x7ffc0
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
+CONFIG_SYS_PBSIZE=1051
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot => "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1051
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CACHE=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2086
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2086
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS_SUBST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tpm init; tpm startup TPM2_SU_CLEAR; bootflow scan -lb"
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LOG=y
CONFIG_LOGF_FUNC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_TPL_POWER=y
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_CPU=y
CONFIG_CMD_PMC=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_PCH=y
CONFIG_SPL_RTC=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_SPI=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_TPL_DM_SPI=y
CONFIG_TPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_ARCH_JZ47XX=y
CONFIG_SYS_MIPS_TIMER_FREQ=1200000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_MMC_TINY=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="echo SD boot attempt ...; run sdbootscript; run sdboot; echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; echo USB boot attempt ...; run usbbootscript; "
+CONFIG_SYS_PBSIZE=543
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=543
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="usb start;sf probe"
+CONFIG_SYS_PBSIZE=538
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="CM-FX6 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=538
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="mmc dev 0; if mmc rescan; then if run loadbootscript; then run bootscript; fi; fi; mmc dev 1; if mmc rescan; then run emmcboot; fi;"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="COBRA > "
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_IMLS=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb"
+CONFIG_SYS_PBSIZE=547
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=547
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81100000
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb"
+CONFIG_SYS_PBSIZE=547
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=547
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81100000
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2068
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Colibri iMX8X # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
+CONFIG_GPIO_HOG=y
CONFIG_FXL6408_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1056
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="Colibri iMX6 # "
CONFIG_SYS_MAXARGS=48
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1056
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x14420000
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb "
+CONFIG_SYS_PBSIZE=544
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=544
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81100000
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb"
+CONFIG_SYS_PBSIZE=544
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=544
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_BUF_ADDR=0x81100000
CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_TARGET_COLIBRI_T20=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1055
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Colibri T20 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1055
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=1536
CONFIG_TFTP_TSIZE=y
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_TARGET_COLIBRI_T30=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1055
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Colibri T30 # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1055
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_TFTP_TSIZE=y
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_BOOTCOMMAND="run ubiboot || run distro_bootcmd;"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
+CONFIG_SYS_PBSIZE=1056
CONFIG_LOGLEVEL=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="Colibri VFxx # "
-CONFIG_SYS_PBSIZE=1056
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AR-5315un # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AR-5387un # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=539
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CT-5361 # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=539
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=540
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VR-3032u # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=540
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="WAP-5813n # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_NET_RETRY_COUNT=50
CONFIG_USE_ROOTPATH=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SYS_SATA_MAX_PORTS=2
CONFIG_SCSI_AHCI=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_SCSI_MAX_SCSI_ID=2
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_PBSIZE=532
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LOG=y
CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_NO_BSS_LIMIT=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
CONFIG_IDENT_STRING=" corstone1000 aarch64 "
CONFIG_SYS_LOAD_ADDR=0x82100000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_CONSOLE_RECORD=y
+CONFIG_SYS_CBSIZE=512
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="corstone1000# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
# CONFIG_CMD_CONSOLE is not set
CONFIG_CMD_FWU_METADATA=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_LOADM=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_USB=y
CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_ISP1760=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_ERRNO_STR=y
CONFIG_EFI_MM_COMM_TEE=y
CONFIG_FFA_SHARED_MM_BUF_SIZE=4096
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_WDT=y
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SYS_PROMPT="G3#"
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0xc00000
CONFIG_CMD_MTD=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
-CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x3000
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=96
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_MACH_S700=y
CONFIG_IDENT_STRING="\ncubieboard7"
CONFIG_SYS_LOAD_ADDR=0x7ffc0
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
+CONFIG_SYS_PBSIZE=1051
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot => "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1051
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_MMC=y
CONFIG_MMC_OWL=y
CONFIG_PHY_REALTEK=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1047
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1047
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
# CONFIG_CMD_BOOTZ is not set
CONFIG_CMD_IMLS=y
CONFIG_CRC32_VERIFY=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_TEGRA_ENABLE_UARTD=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2086
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2086
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2073
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2073
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_LPC32XX_SLC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;run boot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_SPL_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_VERSION_VARIABLE=y
CONFIG_ARP_TIMEOUT=200
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_LBA48=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if run check_em_pad; then run recovery;else if test ${BOOT_FROM} = FACTORY; then run factory_nfs;else run boot_mmc;fi;fi"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2076
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2076
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="echo SDP Display5 recovery"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2084
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 factory > "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2084
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_SPL=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="DockStar> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1051
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
CONFIG_PALMAS_POWER=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_ENV_OFFSET_REDUND=0xB80000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_BOOT_RETRY_TIME=60
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),512k(spl.backup2),512k(spl.backup3),7680k(u-boot),2048k(u-boot.env0),2048k(u-boot.env1),2048k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x80
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_RASTABAN=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_BOOT_RETRY_TIME=60
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),300m(rootfs),512k(mtdoops),-(configuration)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_THUBAN=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_BOOT_RETRY_TIME=60
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
-CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_AM33XX=y
-CONFIG_SYS_MPUCLK=300
-CONFIG_TARGET_DRACO=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2E0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_SYS_LOAD_ADDR=0x81000000
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_BOOT_RETRY=y
-CONFIG_BOOT_RETRY_TIME=60
-CONFIG_RESET_TO_RETRY=y
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-CONFIG_SPL_I2C=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_RANGE=0x80000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/opt/eldk"
-CONFIG_SPL_DM=y
-# CONFIG_SPL_BLK is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_ENV=y
-CONFIG_DFU_NAND=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHY_SMSC=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0908
-CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=548
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="dragonboard410c => "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=548
# CONFIG_CMD_IMI is not set
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyMSM0,115200n8"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=548
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="dragonboard820c => "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=548
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
CONFIG_BOOTDELAY=5
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_CBSIZE=512
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
CONFIG_CMD_GPIO=y
# CONFIG_NET is not set
CONFIG_CLK=y
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYS_PCI_64BIT=y
CONFIG_PCI=y
CONFIG_AHCI=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=280
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="durian#"
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=280
-CONFIG_SYS_BOOTM_LEN=0x3c00000
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_PCI=y
# CONFIG_MMC is not set
CONFIG_PCI_PHYTIUM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1048
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="eDPU>> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1048
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_PROMPT="EA-LPC3250v2=> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=288
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="EA-LPC3250v2=> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="printenv"
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1054
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="\nEB+CPU5282> "
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1054
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="printenv"
+CONFIG_SYS_CBSIZE=1024
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_CBSIZE=1024
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
CONFIG_SYS_MONITOR_BASE=0x01101000
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2068
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=128
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_CPU=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_TIMER=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
-# CONFIG_CMD_NET is not set
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-CONFIG_USE_ROOTPATH=y
+# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_REGEX is not set
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
-# CONFIG_CMD_NET is not set
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-CONFIG_USE_ROOTPATH=y
+# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CONSOLE_SCROLL_LINES=5
-# CONFIG_REGEX is not set
CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
+CONFIG_SYS_PBSIZE=532
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_CMD_GPIO=y
-CONFIG_RANDOM_UUID=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x110a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_RANDOM_UUID=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_CLK_FREQ=40000000
CONFIG_SYS_LOAD_ADDR=0x10000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=280
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="emsdp# "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=280
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
+CONFIG_SYS_PBSIZE=2084
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Endeavoru) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_BUTTON=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS80031=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS80031=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_TPS80031=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_VIDEO_LCD_ENDEAVORU=y
CONFIG_VIDEO_DSI_TEGRA30=y
CONFIG_TEGRA_BACKLIGHT_PWM=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
CONFIG_IDENT_STRING=" for ESPRESSO7420"
CONFIG_SYS_LOAD_ADDR=0x43e00000
+CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="ESPRESSO7420 # "
-CONFIG_SYS_PBSIZE=1024
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0xc6000 0x294000; bootm 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_EV_IMX280_NANO_X_MB=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_IMX_MODULE_FUSE=y
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="bootm 20080000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_PRE_CONSOLE_BUFFER=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run bootspi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_SYS_LOAD_ADDR=0x60800800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_OPTEE_IMAGE=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_RANDOM_UUID=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x110a
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_RANDOM_UUID=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
-CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_TEXT_BASE=0x22900000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_AUTOBOOT_STOP_STR="x"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0x7000
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMINFO=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/mmcblk0p3 rw rootwait console=$consoledev,$baudrate $othbootargs;ext2load mmc 0:2 ${kernel_addr} $bootfile;ext2load mmc 0:2 ${fdt_addr} $fdtfile;bootm ${kernel_addr} - ${fdt_addr}"
+CONFIG_SYS_CBSIZE=1024
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_CPUINFO=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=1024
CONFIG_CMD_CPU=y
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_BINOP=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run tryboot;"
CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_LOG_MAX_LEVEL=8
CONFIG_LOG_DEFAULT_LEVEL=4
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2073
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2073
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1053
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1053
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_SATA=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc0; poweroff;"
+CONFIG_SYS_PBSIZE=2084
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Grouper) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_BUTTON=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_TEGRA20=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="ignore_loglevel"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_USB=y
CONFIG_SYS_LOAD_ADDR=0x23000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=539
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=539
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=539
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=539
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_SPL_NAND_OFS=0x1100000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_UNZIP=y
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MISC=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_GXP_SPI=y
CONFIG_TIMER=y
CONFIG_GXP_TIMER=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_SHA512=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2085
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2085
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_EXPERT is not set
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="HC2910# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=537
CONFIG_CMD_BOOTDEV=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_MISC_INIT_R=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_NVRAM=y
-CONFIG_SYS_SATA_MAX_PORTS=5
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_BOOTCOUNT_LIMIT=y
# CONFIG_MMC is not set
CONFIG_CALXEDA_XGMAC=y
CONFIG_SCSI=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_SCSI_MAX_SCSI_ID=5
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=283
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot => "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=283
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2075
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="hsdk-4xd# "
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2075
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ENV_FLAGS=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2071
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="hsdk# "
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2071
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ENV_FLAGS=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=538
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="HG556a # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=538
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1051
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part rootfs; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; bootm 0x800000"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="iConnect> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1051
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_TIMESTAMP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_PBSIZE=1052
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="MIPSfpga # "
-CONFIG_SYS_PBSIZE=1052
# CONFIG_CMD_SAVEENV is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=532
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x13000000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=8
CONFIG_SPL_SIZE_LIMIT=69632
CONFIG_SPL=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_SLEEP is not set
# CONFIG_CMD_MP is not set
CONFIG_ENV_WRITEABLE_LIST=y
CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_TFTP_BLOCKSIZE=512
+# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
-CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run autoboot"
+CONFIG_SYS_PBSIZE=543
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="i.MX6 Logic # "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=543
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x1500000
CONFIG_CMD_SPL_WRITE_SIZE=0x00100000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=546
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-mipi> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=546
CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=545
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=545
CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=538
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=538
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=538
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=538
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run $modeboot"
+CONFIG_SYS_PBSIZE=541
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=541
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SPL_BSS_START_ADDR=0x84100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run boot${boot-mode}"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_SYS_PBSIZE=532
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_I2C=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_EXTENSION=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_EXTENSION=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="Verdin iMX8MM # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_IMX_WATCHDOG=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run dmo_preboot"
CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
+CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x950000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x950000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_IMX_WATCHDOG=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x950000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2067
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_NAND_IDENT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2067
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_FUSE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2067
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2067
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2067
CONFIG_BOARD_TYPES=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2067
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-icore-mx8mp-edimm2.2.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_MDIO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-debix-model-a.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk2.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gpio clear GPIO1_11 ; sleep 0.1 ; gpio set GPIO1_11 ; sleep 0.1 ; i2c dev 4 && i2c mw 0x70 0 4 && i2c probe 0x2d && i2c mw 0x2d 0xaa55.2 0"
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk3.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=1050
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=1050
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SD_BOOT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_SYS_PBSIZE=1050
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x13e000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x04000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x128000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x04000000
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2068
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2068
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x400000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_TARGET_IMX93_VAR_SOM=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL=y
+CONFIG_CMD_DEKBLOB=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx93-var-som-symphony.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_NET=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=3
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=100
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_CLK_IMX93=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_GPIO_HOG=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ADIN=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_MIPI_DPHY_HELPERS=y
+CONFIG_PHY_IMX93_MIPI_DPHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX93_BLK_CTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_CI_UDC=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_CMD_WDT=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_SYS_I2C_SPEED=100000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_CMD_READ=y
+CONFIG_SERIAL_TAG=y
\ No newline at end of file
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1046
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1046
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_USE_BOOTCOMMAND=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_USE_BOOTCOMMAND=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_USE_BOOTCOMMAND=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
CONFIG_USE_BOOTCOMMAND=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftpboot ; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftpboot ; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftpboot ; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftpboot ; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=289
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=289
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=1
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Boot XG6846 in %d seconds\n"
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; sf read 0x81000000 0x40000 0x500000; bootm 0x81000000"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="XG6846 # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x380000
CONFIG_SYS_PROMPT="IOT2050> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_SYS_LOAD_ADDR=0x30000000
CONFIG_LOCALVERSION="-iotdk-1.0"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SYS_PROMPT="IoTDK# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=280
+CONFIG_SYS_PROMPT="IoTDK# "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-beagleboneai64"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD_UBI=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_SPL_DFU=y
+CONFIG_LZO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x70000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J721E=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_TARGET_J721E_R5_BEAGLEBONEAI64=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-beagleboneai64"
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0xf59f0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0xf59f0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
+CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-j721e-r5-common-proc-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721e-r5-beagleboneai64"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_ADC=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
-CONFIG_RANDOM_UUID=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_RANDOM_UUID=y
CONFIG_CMD_ADC=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
-CONFIG_RANDOM_UUID=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_RANDOM_UUID=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2089
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2089
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
+CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
-CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
+CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
-CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
+CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
-CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_LOADS_ECHO=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_FIXUP_PARTITIONS=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_LZMADEC is not set
CONFIG_CMD_CLK=y
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_BOARD_LATE_INIT=y
# CONFIG_HWCONFIG is not set
CONFIG_PCI_INIT_R=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMDLINE_PS_SUPPORT=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_RV8803=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_AUTOBOOT_STOP_STR="."
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run usbupd; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_SILENT_CONSOLE=y
# CONFIG_SILENT_CONSOLE_UPDATE_ON_SET is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="."
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_TLV_EEPROM=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_QSPI_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SD_BOOT_QSPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0xf40000
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_LPUART=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_LPUART=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_TSEC_ENET=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_MEMINFO=y
CONFIG_TSEC_ENET=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd;env exists secureboot && esbc_halt;"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FW_ADDR=0x60940000
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_LPUART=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_TSEC_ENET=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_TSEC_ENET=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_TSEC_ENET=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_PBSIZE=532
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_SYS_PBSIZE=532
CONFIG_ID_EEPROM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_DM_PCI_COMPAT=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_I2C=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_I2C=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
+CONFIG_SYS_PBSIZE=532
CONFIG_RESET_PHY_R=y
CONFIG_SPL_MAX_SIZE=0x16000
CONFIG_SPL_PAD_TO=0x20000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load"
+CONFIG_SYS_PBSIZE=532
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SPL_MAX_SIZE=0x16000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_USB=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_SYS_PBSIZE=532
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_DM_RTC=y
CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS3231=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_MISC_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_BOOTCOMMAND="run mmc_mmc"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run try_bootscript"
+CONFIG_SYS_CBSIZE=1024
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_PAD_TO=0x8000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_TARGET="u-boot-with-nand-spl.imx"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_NAND_MXC=y
CONFIG_MXC_NAND_HWECC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_TARGET_MALTA=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_CPU_MIPS64_R2=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=283
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=283
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_ENV_ADDR=0xBE3E0000
CONFIG_TARGET_MALTA=y
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_MIPS_TIMER_FREQ=250000000
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=283
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=283
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x18000000
CONFIG_SYS_OS_BASE=0x8180000
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NOR_OFS=0x09600000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NOR_OFS=0x09600000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2089
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2089
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_TEGRA_NAND=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_LOADS is not set
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_LOADS is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=romfs"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_SYS_MAXARGS=15
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=544
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=282
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM_MTD=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SD_BOOT=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
CONFIG_TPL_NEEDS_SEPARATE_STACK=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0098FC00
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=279
CONFIG_LOGLEVEL=7
CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="jr2 # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=279
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_LOGLEVEL=7
CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="luton # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=282
CONFIG_LOGLEVEL=7
CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="ocelot # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=282
CONFIG_LOGLEVEL=7
CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="serval # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_SYS_MEMTEST_END=0x9fc00000
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=283
CONFIG_LOGLEVEL=7
CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="servalt # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=283
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0x30000
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0x30000
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7622> "
CONFIG_SYS_MAXARGS=8
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="mt7623a-unielec-u7623-02-emmc.dtb"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_MAXARGS=8
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2.dtb"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_MAXARGS=8
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
CONFIG_MIPS_BOOT_FDT=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_BSS_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="mt7629-rfb"
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SYS_MAXARGS=8
-CONFIG_SYS_PBSIZE=1049
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7981> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7981-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7981> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7981> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7986a-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7986> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-emmc"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="BPI-R3> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-sd"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="BPI-R3> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7988> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7988> "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="mt8183-pumpkin"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_MEMORY is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_USB_ETHER=y
CONFIG_WDT=y
CONFIG_WDT_MTK=y
+# CONFIG_RANDOM_UUID is not set
# CONFIG_REGEX is not set
# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="mt8365_evk"
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x4c000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="mt8365-evk"
+CONFIG_TARGET_MT8365=y
+CONFIG_IDENT_STRING=" mt8365-evk"
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEFAULT_FDT_FILE="mt8365-evk"
+CONFIG_CLK=y
+CONFIG_MMC_MTK=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb"
-CONFIG_SYS_PROMPT="MT8512> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+CONFIG_SYS_PROMPT="MT8512> "
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_MEMORY is not set
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
CONFIG_WDT=y
CONFIG_WDT_MTK=y
+# CONFIG_RANDOM_UUID is not set
# CONFIG_SHA256 is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb"
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SYS_PROMPT="MT8518> "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=281
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="MT8518> "
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
CONFIG_EFI_PARTITION=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Marvell>> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1051
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Marvell>> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1051
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run doquiet; run tryboot"
+CONFIG_SYS_CBSIZE=1024
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=48
-CONFIG_SYS_CBSIZE=1024
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYS_PBSIZE=528
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=528
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_VIDEO_LOGO_MAX_SIZE=0x600000
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_BOOT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=785408
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=256
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x9e000000
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=256
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
-CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_NAND=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1048
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=539
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CG3100D # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=539
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=542
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="DGND3700v2 # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=542
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1046
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1046
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1046
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1046
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1046
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1046
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="dhcp && run netconsole; if run usbload || run diskload; then bootm; fi"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1046
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1046
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_SYS_LOAD_ADDR=0xe00800
CONFIG_DEBUG_UART=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc1,115200 "
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="NSA310s> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1050
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_SATA=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_SYS_PROMPT="nsim# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=279
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_SYS_PROMPT="nsim# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=279
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SYS_PROMPT="nsim# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=279
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SYS_PROMPT="nsim# "
CONFIG_CMD_DM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_SYS_PROMPT="nsim# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=279
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2087
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2087
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MT41K256M16HA_125E=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_IMX_MODULE_FUSE=y
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_CYCLIC=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_RAM=y
CONFIG_RAM_OCTEON=y
CONFIG_RAM_OCTEON_DDR4=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=3
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_MEMTEST_END=0x040f0000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_PL01X_SERIAL=y
CONFIG_SYS_MEMTEST_END=0x28f0000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=4 rootwait rw root=/dev/sda2 coherent_pool=16M"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_PL01X_SERIAL=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_BOOTM_LEN=0x10000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/sda2 coherent_pool=16M"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Marvell> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_PL01X_SERIAL=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="ODROID-XU3 # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run distro_bootcmd ; run autoboot"
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="Odroid # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
+CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
+CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
# CONFIG_SPL_POWER is not set
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
+CONFIG_SYS_PBSIZE=1055
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SYS_PROMPT="BeagleBoard # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1055
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x280000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then setenv boot mmc; setenv addr_fit 0x8b000000; run update_to_fit; run mmcboot; fi; run envboot; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
+CONFIG_SYS_PBSIZE=1053
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1053
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x280000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
+CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
+CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
# CONFIG_SPL_POWER is not set
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1054
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; "
-CONFIG_SYS_PROMPT="openpiton$ "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=284
+CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MD5=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; "
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=284
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x82000000
# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="boot/fw_payload.bin"
CONFIG_SPL_RTC=y
CONFIG_SYS_PROMPT="openpiton$ "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=284
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x10000000
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run check_env"
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
+CONFIG_SYS_PBSIZE=535
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="BIOS> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=535
CONFIG_CMD_CONFIG=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
+CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
+CONFIG_AXP305_POWER=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3"
+CONFIG_SPL=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
+CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee
+CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000
+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
+CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624
+CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f
+CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_LPDDR4=y
+CONFIG_DRAM_CLK=792
+CONFIG_USB1_VBUS_PIN="PC16"
+CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_SPI_SUNXI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_AXP313_POWER=y
+CONFIG_SPI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="ORIGEN # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_MMC_DW=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_TEGRA210=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2089
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2089
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_PCI=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2089
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2089
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_TARGET_P2571=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_TEGRA186=y
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_PCI=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2093
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2093
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_TEGRA186=y
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_PCI=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2093
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2093
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_PCI=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2089
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2089
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_TARGET_PAZ00=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PBSIZE=2087
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2087
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run bootcmd_nand"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmcboot;run nandboot"
+CONFIG_SYS_PBSIZE=532
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x7800
CONFIG_SYS_PROMPT="Peach-Pi # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x7800
CONFIG_SYS_PROMPT="Peach-Pit # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_SILENT_CONSOLE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm"
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_DEBUG_UART=y
CONFIG_LTO=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_LZO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd"
+CONFIG_SYS_PBSIZE=1048
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SYS_BOOTPARAMS_LEN=0x1000
CONFIG_SYS_PROMPT="dask # "
-CONFIG_SYS_PBSIZE=1048
# CONFIG_CMD_SAVEENV is not set
CONFIG_LOOPW=y
CONFIG_CMD_MEMINFO=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run default_boot"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x8000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_MAX_SIZE=0xe000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_TEGRA_NAND=y
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="pm9261> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 "
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=288
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="u-boot-pm9263> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=288
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:128k(bootstrap)ro,640k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),8M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x70000000 0x180000 0x880000; nand read 0x70080000 0x200000 0x800000; bootz 0x70080000 - 0x70000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs $(bootargs_console); run bootcmd_usb; bootm 0x00800000 0x01100000"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1050
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1050
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="Pogo_V4> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1050
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_FIT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
-CONFIG_SYS_PROMPT="U-Boot>"
-CONFIG_SYS_MAXARGS=32
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=280
+CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_SYS_MAXARGS=32
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo"
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_SYS_PCI_64BIT=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=280
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="pomelo#"
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=280
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_IDENT_STRING="poplar"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="poplar# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=537
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x20000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_BOOT_RETRY_TIME=60
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_CBSIZE=512
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
# CONFIG_CMD_MII is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_PL011=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_PCI_INIT_R=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_PL011=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum"
-CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=256
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
CONFIG_CMD_IDE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77970-eagle.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77980-condor.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77990-ebisu.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a779a0-falcon.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb"
+CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1843200
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779g0-white-hawk.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779g0-white-hawk.dtb"
+CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-salvator-x.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe633f000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-ulcb.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb"
+CONFIG_SYS_PBSIZE=2068
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe633f000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x13000000
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
+CONFIG_SYS_PBSIZE=1052
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="rock960 => "
-CONFIG_SYS_PBSIZE=1052
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_RANDOM_UUID=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_USB=y
CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_RANDOM_UUID=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="pci enum; usb start;"
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_SIMPLEFB=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_BOOT_RETRY_TIME=60
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_ASKENV=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=1
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PBSIZE=1050
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nanopi2# "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_RTEMS is not set
CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=384
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Goni # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=384
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run mmcboot"
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="Universal # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=540
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="F@ST1704 # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=540
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x21000000 at91-sam9x60_curiosity.dtb; fatload mmc 1:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x60_curiosity.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;fatload mmc 0:1 0x22000000 zImage;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x600000; nand read 0x21000000 0x180000 0x20000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x180000 0x80000; sf read 0x22000000 0x200000 0x600000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_giantboard.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 1 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_STRINGS=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_LSBLK=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_STRINGS=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_LSBLK=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_STRINGS=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_LSBLK=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DM=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 0:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 1:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 1:0; sf read 0x22000000 0x180000 0x80000; sf read 0x23000000 0x200000 0x600000; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; ext4load mmc 0:1 0x23000000 /boot/zImage; bootz 0x23000000 - 0x22000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_IMLS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_IMLS=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_BASE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000"
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_END=0x70000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000"
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMTEST=y
CONFIG_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x6000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_SANDBOX=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SMEM=y
CONFIG_SANDBOX_SMEM=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
-CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
+CONFIG_GETOPT=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x6000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_MEASURED_BOOT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTM_PRE_LOAD=y
CONFIG_CMD_BOOTZ=y
+CONFIG_BOOTM_OPENRTOS=y
+CONFIG_BOOTM_OSE=y
CONFIG_CMD_BOOTEFI_HELLO=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_ABOOTIMG=y
-# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPIO_READ=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_MUX=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_AES=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_SCMI=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_CBFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_MMC_SANDBOX=y
CONFIG_MMC_SDHCI=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_RTC_RV8803=y
CONFIG_RTC_HT1380=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SM=y
CONFIG_SMEM=y
CONFIG_ECDSA_VERIFY=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
+CONFIG_GETOPT=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTEFI_HELLO=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_BMP_24BPP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
-CONFIG_LZ4=y
CONFIG_ZSTD=y
CONFIG_ERRNO_STR=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_SOFTECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_IDENT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_SPL_PWRSEQ=y
CONFIG_FS_LOADER=y
CONFIG_MMC_SANDBOX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x2000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_DM_RTC=y
CONFIG_SPL_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_RSA_VERIFY_WITH_PKEY=y
CONFIG_TPM=y
-CONFIG_LZ4=y
CONFIG_ZSTD=y
CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_DM_RTC=y
CONFIG_SPL_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_RSA_VERIFY_WITH_PKEY=y
CONFIG_TPM=y
CONFIG_SPL_CRC8=y
-CONFIG_LZ4=y
CONFIG_ZSTD=y
CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_SPL_DM_RTC=y
CONFIG_TPL_DM_RTC=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_RSA_VERIFY_WITH_PKEY=y
CONFIG_TPM=y
-CONFIG_LZ4=y
CONFIG_ZSTD=y
# CONFIG_VPL_LZMA is not set
CONFIG_ERRNO_STR=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2086
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2086
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_TEGRA_KEYBOARD=y
CONFIG_MTD=y
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
+# CONFIG_RANDOM_UUID is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_REMAKE_ELF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=539
CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="NB4-SER # "
CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=539
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_PWM=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774c0-ek874.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb"
+CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
# CONFIG_NET is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
# CONFIG_NET is not set
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if test ${bootdev} = 'usb'; then ${bootdev} start; fi; if test ${bootdev} = 'scsi'; then ${bootdev} scan; fi; ${bootdev} info; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${loadaddr} ${bootfile}; ${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} ${ramdiskaddr} ${ramdiskfile}; zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
-CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x1000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=537
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
# CONFIG_CMD_LOADS is not set
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="SMDK5250 # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x7800
CONFIG_SYS_PROMPT="SMDK5420 # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run ubifsboot"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=384
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="SMDKC100 # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=384
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_ONENAND=y
CONFIG_USE_ONENAND_BOARD_INIT=y
CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000"
+CONFIG_SYS_PBSIZE=1024
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="SMDKV310 # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run setup_boot_menu;"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=538
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_BSS_START_ADDR=0x80000000
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_PROMPT="sniper # "
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=538
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTMETH_CROS=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
CONFIG_BLOBLIST=y
# CONFIG_SPL_BLOBLIST is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="snow # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_UNIT_TEST=y
-# CONFIG_UT_LIB_ASN1 is not set
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SYS_PBSIZE=2082
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2082
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
+CONFIG_SYS_PBSIZE=2082
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2082
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SYS_PBSIZE=2082
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2082
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_FS_FAT=y
CONFIG_FIT=y
CONFIG_SPL_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FPGA=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_DW=y
CONFIG_MISC=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SYS_PBSIZE=2079
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2079
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_FS_FAT=y
# CONFIG_PSCI_RESET is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
+CONFIG_SYS_PBSIZE=2079
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2079
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SYS_PBSIZE=2079
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2079
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=45
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SYS_PBSIZE=2085
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2085
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_OPTIMIZE_INLINING=y
CONFIG_SPL_OPTIMIZE_INLINING=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
+CONFIG_SYS_PBSIZE=2085
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x3ff00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2085
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_TIMESTAMP=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMDLINE_PS_SUPPORT=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=1
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password to abort autoboot in %d seconds!\n"
CONFIG_BOOTCOMMAND="run boot_usb;run boot_nor"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
+CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_REGINFO=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_IMLS=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run setfdtfile; run checkbootdev; run loadfdt;if run loadbootscript; then run bootscript; else if run loadimage; then run setbootargs; bootz ${loadaddr} - ${fdt_addr}; fi; fi"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PROMPT="spring # "
-CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_OF_BOARD_FIXUP is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_QSPI_BOOT=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="StarFive # "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
CONFIG_RNG_JH7110=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
CONFIG_TIMER_EARLY=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
CONFIG_USB_KEYBOARD=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_STARFIVE=y
CONFIG_BOOTDELAY=0
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_BMP=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy"
CONFIG_SYS_LOAD_ADDR=0x100000
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fastbootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_CONFIG=y
CONFIG_CMD_LICENSE=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m"
+CONFIG_SYS_PBSIZE=1058
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="stih410-b2260 => "
-CONFIG_SYS_PBSIZE=1058
-CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIMER=y
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_STM32_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=12
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_RANDOM_UUID is not set
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
# CONFIG_ISO_PARTITION is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_PINCTRL_FULL is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x9000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x81c0000
CONFIG_SPL_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco"
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval"
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram loglevel=8"
CONFIG_BOOTCOMMAND="bootm 90080000"
CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=282
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3db00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_FDT_SIMPLEFB=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_SPL_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_FDT_SIMPLEFB=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
-CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EEPROM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_EEPROM=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_FDT_SIMPLEFB=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
-CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_SYS_PBSIZE=1050
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x400000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1"
+CONFIG_STM32MP25X=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_TARGET_ST_STM32MP25X=y
+CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_SYS_MEMTEST_START=0x84000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_BOOTDELAY=1
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ADTIMG=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADB is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+# CONFIG_MMC is not set
+CONFIG_PINCONF=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+# CONFIG_STM32MP1_DDR is not set
+CONFIG_DM_RNG=y
+CONFIG_SERIAL_RX_BUFFER=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+CONFIG_WDT_ARM_SMC=y
+CONFIG_ERRNO_STR=y
+# CONFIG_LMB_USE_MAX_REGIONS is not set
+CONFIG_LMB_MEMORY_REGIONS=2
+CONFIG_LMB_RESERVED_REGIONS=32
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe 0:1 50000000; sf read ${loadaddr} 0x100000 ${kern_size}; bootm ${loadaddr}"
+CONFIG_SYS_PBSIZE=283
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SYS_PROMPT="stmark2 $ "
-CONFIG_SYS_PBSIZE=283
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="go 0x40040000"
+CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="STV0991> "
-CONFIG_SYS_PBSIZE=1050
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_FWU_NUM_IMAGES_PER_BANK=1
CONFIG_AHCI=y
CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTSTAGE_STASH_SIZE=4096
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=128
CONFIG_CMD_FWU_METADATA=y
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2071
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2071
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_MAX_SIZE=0x3e00
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_SYS_XTRACE is not set
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_SYS_PROMPT="[tb100]:~# "
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=284
-CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_PROMPT="[tb100]:~# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start"
CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb"
+CONFIG_SYS_PBSIZE=544
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Matrix U-Boot> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=544
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2081
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2081
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_TEGRA_NAND=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
+CONFIG_SYS_PBSIZE=532
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_PCI_INIT_R=y
CONFIG_RESET_PHY_R=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_RX8025=y
-CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
# CONFIG_FIT_PRINT is not set
# CONFIG_BOOTSTD is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTARGS_SUBST=y
CONFIG_BOOTCOMMAND=""
CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a.dtb"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOG=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="LPI4A=> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CONFIG=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_CPU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_SYS_LOAD_ADDR=0x500000
CONFIG_DEBUG_UART=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug maxcpus=48 rootwait rw root=/dev/sda2 coherent_pool=16M"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="ThunderX_88XX> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=544
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXTENSION is not set
# CONFIG_CMD_DATE is not set
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2077
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2077
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
CONFIG_CMD_MEMTEST=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2077
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2077
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
CONFIG_CMD_MEMTEST=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot"
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2077
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2077
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
CONFIG_CMD_MEMTEST=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
CONFIG_BOOTCOMMAND="if part number mmc 0 vbmeta is_avb; then echo MMC with vbmeta partition detected.; echo starting Android Verified boot.; avb init 0; if avb verify; then set bootargs $bootargs $avb_bootargs; part start mmc 0 boot boot_start; part size mmc 0 boot boot_size; mmc read ${load_addr} ${boot_start} ${boot_size}; bootm ${load_addr} ${load_addr} ${fdt_addr_r}; else; echo AVB verification failed.; exit; fi; elif part number mmc 0 system is_non_avb_android; then booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r};else; echo Booting FIT image.; bootm ${load_addr} ${load_addr} ${fdt_addr_r}; fi;"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AVB_VERIFY=y
CONFIG_AVB_BUF_SIZE=0x10000000
CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=544
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=256
+# CONFIG_RANDOM_UUID is not set
CONFIG_LIBAVB=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
+CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="setenv skip_boot 0; setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; if test ${skip_boot} -eq 1; then; else run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff; fi"
+CONFIG_SYS_PBSIZE=2084
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (Transformer) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_BUTTON=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x91000000
CONFIG_I2C_MUX_GPIO=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_TPS65910=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_TEGRA20=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run autoboot"
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="Trats2 # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run autoboot"
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="Trats # "
-CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_PCI=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2087
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2087
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=48000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
-CONFIG_SCSI=y
CONFIG_SERIAL_PROBE_ALL=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
# CONFIG_PCI is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_HWCONFIG is not set
CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_OLD_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
-CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1048
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="uDPU>> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1048
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_CMD_CONFIG=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_CMD_CONFIG=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_TIMESTAMP=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
CONFIG_CMD_CONFIG=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_XIMG is not set
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_GPIO=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock1 mtdparts=mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2) rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nboot 21000000 0"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=281
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADB is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
+CONFIG_SYS_PBSIZE=532
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_LZO=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2086
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2086
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2085
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2085
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-wifi-dev"
CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x40000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="Verdin AM62 # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_BOOTM_LEN=0x40000000
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="Verdin iMX8MM # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="Verdin iMX8MP # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
CONFIG_CMD_PCI=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
CONFIG_CMD_ABOOTIMG=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ARMFLASH=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda2 rw rootwait"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=541
# CONFIG_MMC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=532
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_LOGLEVEL=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev 0 0;mmc read ${loadaddr} ${k_offset} ${k_blksize};mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};bootz ${loadaddr} - ${oftaddr}"
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=282
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="vinco => "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPT=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=532
CONFIG_LOGLEVEL=8
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_LICENSE=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x8800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x8000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
-CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_SYS_PBSIZE=532
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=532
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
-CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MDIO_MUX_MESON_GXL=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_MAX313XX=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_SYS_PBSIZE=2084
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra30 (x3) # "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2084
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_SPL_DM=y
CONFIG_BUTTON=y
CONFIG_EXTCON=y
CONFIG_EXTCON_MAX14526=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX77663=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_MAX77663=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_BACKLIGHT_LM3533=y
CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
CONFIG_VIDEO_TEGRA20=y
-# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_AXP305_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=10
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=1051
CONFIG_SYS_PROMPT="xenguest# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1051
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_IMI is not set
CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_SYS_PCI_64BIT=y
CONFIG_PCI=y
+CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTDELAY=10
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=1051
CONFIG_PCI_INIT_R=y
CONFIG_SYS_PROMPT="xenguest# "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=1051
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_IMI is not set
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x21200000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_DEBUG_UART=y
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TIMER=y
+CONFIG_PANIC_HANG=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x21200000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_UARTLITE=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+# CONFIG_RISCV_TIMER is not set
+CONFIG_XILINX_TIMER=y
+CONFIG_PANIC_HANG=y
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="Versal> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="Versal> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="Versal> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2073
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="Versal NET> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2073
-CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2073
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="Versal> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2073
-CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2071
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=2071
# CONFIG_BOOTM_NETBSD is not set
-CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_CMD_IMLS=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_LEN=0x4040000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ENV_SOURCE_FILE="zynqmp_kria"
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x2200000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_STACK_R_ADDR=0x18000000
+CONFIG_SPL_STACK=0xfffffffc
+CONFIG_SPL_SIZE_LIMIT=0x2a000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x2220000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_CMD_FRU=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_ENV_ADDR=0x2200000
+CONFIG_AHCI=y
+CONFIG_SYS_MEMTEST_START=0x00000000
+CONFIG_SYS_MEMTEST_END=0x00001000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x6400000
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2073
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FS_LOAD_KERNEL_NAME=""
+CONFIG_SPL_FS_LOAD_ARGS_NAME=""
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_BOARD=y
+CONFIG_OF_LIST=""
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART=":auto"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SATA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
+CONFIG_DMA=y
+CONFIG_XILINX_DPDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_GPIO_HOG=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SLG7XL45106_I2C_GPO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ADIN=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_XILINX_GMII2RGMII=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_XILINX_AXIEMAC=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_PHY=y
+CONFIG_PHY_XILINX_ZYNQMP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_ZYNQMP_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_CADENCE_TTC=y
+CONFIG_RESET_ZYNQMP=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_RTC_ZYNQMP=y
+CONFIG_SCSI=y
+CONFIG_ARM_DCC=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SOC_XILINX_ZYNQMP=y
+CONFIG_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_COPY=y
+CONFIG_I2C_EDID=y
+CONFIG_VIDEO_ZYNQMP_DPSUB=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_PANIC_HANG=y
+CONFIG_TPM=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_REMAKE_ELF=y
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_NO_DDR=y
# CONFIG_PSCI_RESET is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=0
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1049
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_ARM_DCC=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
-# CONFIG_FAT_WRITE is not set
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
CONFIG_CPU_FREQ_HZ=500000000
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_DEBUG_UART=y
+CONFIG_SYS_BOOTM_LEN=0x3c00000
CONFIG_BOOTSTAGE=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=284
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=284
-CONFIG_SYS_BOOTM_LEN=0x3c00000
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_EMBED=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
+CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run scsi_init;usb start"
+CONFIG_SYS_PBSIZE=2073
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=2073
-CONFIG_SYS_BOOTM_LEN=0x6400000
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
CONFIG_RTC_EMULATION=y
CONFIG_RTC_ZYNQMP=y
CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_ARM_DCC=y
CONFIG_XILINX_UARTLITE=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press <SPACE> to stop\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_PBSIZE=1049
CONFIG_MISC_INIT_R=y
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_PBSIZE=1049
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL_STACK=0xfffffe00
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1047
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1047
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL_STACK=0xfffffe00
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1047
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1047
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_ZYNQ_DDRC_INIT is not set
# CONFIG_CMD_ZYNQ is not set
CONFIG_SYS_LOAD_ADDR=0x0
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1047
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_PBSIZE=1047
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
#ifndef _DISK_PART_AMIGA_H
#define _DISK_PART_AMIGA_H
-#include <common.h>
#if CONFIG_IS_ENABLED(ISO_PARTITION)
/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS
+++ /dev/null
-SHA1 usage:
------------
-
-In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated.
-This SHA1 sum is used, to check, if the U-Boot Image in Flash is not
-corrupted.
-
-The following command is available:
-
-=> help sha1
-sha1 address len [addr] calculate the SHA1 sum [save at addr]
- -p calculate the SHA1 sum from the U-Boot image in flash and print
- -c check the U-Boot image in flash
-
-"sha1 -p"
- calculates and prints the SHA1 sum, from the Image stored in Flash
-
-"sha1 -c"
- check, if the SHA1 sum from the Image stored in Flash is correct
-
-
-It is possible to calculate a SHA1 checksum from a memoryrange with:
-
-"sha1 address len"
-
-If you want to store a new Image in Flash for the pcs440ep board,
-which has no SHA1 sum, you can do the following:
-
-a) cp the new Image on a position in RAM (here 0x300000)
- (for this example we use the Image from Flash, stored at 0xfffa0000 and
- 0x60000 Bytes long)
-
-"cp.b fffa0000 300000 60000"
-
-b) Initialize the SHA1 sum in the Image with 0x00
- The SHA1 sum is stored in Flash at:
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS
- for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
- = 0xffffffe0
- for the example in RAM: 0x300000 + 0x60000 + -0x20
- = 0x35ffe0
-
- note: a SHA1 checksum is 20 bytes long.
-
-"mw.b 35ffe0 0 14"
-
-c) now calculate the SHA1 sum from the memoryrange and write
- the calculated checksum at the right place:
-
-"sha1 300000 60000 35ffe0"
-
-Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum.
-
-If you do a "buildman -k pcs440ep" or a "make all" to get the U-Boot image,
-which will be found in ../current/ipam390/ - the correct SHA1 sum will be
-automagically included in the U-Boot image.
-
-Heiko Schocher, 11 Jul 2007
bcb - Load/set/clear/test/dump/store Android BCB fields
Usage:
- bcb load <dev> <part> - load BCB from mmc <dev>:<part>
- bcb set <field> <val> - set BCB <field> to <val>
- bcb clear [<field>] - clear BCB <field> or all fields
- bcb test <field> <op> <val> - test BCB <field> against <val>
- bcb dump <field> - dump BCB <field>
- bcb store - store BCB back to mmc
+ bcb load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>
+ load <dev> <part> - load BCB from mmc <dev>:<part>
+ bcb set <field> <val> - set BCB <field> to <val>
+ bcb clear [<field>] - clear BCB <field> or all fields
+ bcb test <field> <op> <val> - test BCB <field> against <val>
+ bcb dump <field> - dump BCB <field>
+ bcb store - store BCB back to <interface>
Legend:
- <dev> - MMC device index containing the BCB partition
- <part> - MMC partition index or name containing the BCB
- <field> - one of {command,status,recovery,stage,reserved}
- <op> - the binary operator used in 'bcb test':
- '=' returns true if <val> matches the string stored in <field>
- '~' returns true if <val> matches a subset of <field>'s string
- <val> - string/text provided as input to bcb {set,test}
- NOTE: any ':' character in <val> will be replaced by line feed
- during 'bcb set' and used as separator by upper layers
+ <interface> - storage device interface (virtio, mmc, etc)
+ <dev> - storage device index containing the BCB partition
+ <part> - partition index or name containing the BCB
+ <field> - one of {command,status,recovery,stage,reserved}
+ <op> - the binary operator used in 'bcb test':
+ '=' returns true if <val> matches the string stored in <field>
+ '~' returns true if <val> matches a subset of <field>'s string
+ <val> - string/text provided as input to bcb {set,test}
+ NOTE: any ':' character in <val> will be replaced by line feed
+ during 'bcb set' and used as separator by upper layers
'bcb'. Example of getting reboot reason
CONFIG_PARTITIONS=y
CONFIG_MMC=y
- CONFIG_BCB=y
+ CONFIG_CMD_BCB=y
.. [1] https://android.googlesource.com/platform/bootable/recovery
.. [2] https://source.android.com/devices/bootloader
VPL (Verifying Program Loader)
------------------------------
-Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run
-using::
+Sandbox provides an example build of vpl called `sandbox_vpl`. To build it:
- /path/to/sandbox_vpl/tpl/u-boot-tpl -D
+.. code-block:: bash
+
+ make sandbox_vpl_defconfig all
+
+This can be run using:
+
+.. code-block:: bash
+
+ ./tpl/u-boot-tpl -d u-boot.dtb
It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot
proper, following the normal flow for a verified boot. At present, no
verification is actually implemented.
+Here is an example trace::
+
+ U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+ U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from vbe_simple
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+ U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+ Trying to boot from vbe_simple
+ Trying to boot from sandbox_image
+ Trying to boot from sandbox_file
+
+
+ U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
+
+ Reset Status: COLD
+ Model: sandbox
+ DRAM: 256 MiB
+ using memory 0x1b576000-0x1f578000 for malloc()
+
+ Warning: host_lo MAC addresses don't match:
+ Address in ROM is 96:cd:ef:82:78:51
+ Address in environment is 02:00:11:22:33:44
+ Core: 103 devices, 51 uclasses, devicetree: board
+ MMC:
+ Loading Environment from nowhere... OK
+ In: serial,cros-ec-keyb,usbkbd
+ Out: serial,vidconsole
+ Err: serial,vidconsole
+ Model: sandbox
+ Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000
+ Hit any key to stop autoboot: 1
+
Debugging the init sequence
---------------------------
# apt-get install mtd-utils
# mtdinfo
- # mtd_debug erase /dev/mtdX 0 0xf0000
- # mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin
+ # flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX
``/dev/mtdX`` needs to be replaced with the respective device name, as listed
in the output of ``mtdinfo``.
U-Boot for the ASUS/Google Nexus 7 (2012)
=========================================
-``DISCLAMER!`` Moving your ASUS/Google Nexus 7 (2012) to use
-U-Boot assumes replacement of the vendor ASUS bootloader. Vendor
-android firmwares will no longer be able to run on the device.
-This replacement IS reversible.
+``DISCLAMER!`` Moving your ASUS/Google Nexus 7 (2012) to use U-Boot assumes
+replacement of the vendor ASUS bootloader. Vendor android firmwares will no
+longer be able to run on the device. This replacement IS reversible.
Quick Start
-----------
- Build U-Boot
-- Pack U-Boot into repart-block
-- Flash repart-block into the eMMC
+- Process U-Boot
+- Flashing U-Boot into the eMMC
- Boot
- Self Upgrading
Build U-Boot
------------
-Device support is implemented by applying config fragment to a generic
-board defconfig. Valid fragments are ``grouper_E1565.config``,
-``grouper_PM269.config`` and ``tilapia.config``.
+Device support is implemented by applying config fragment to a generic board
+defconfig. Valid fragments are ``tilapia.config``, ``grouper_E1565.config``
+and ``grouper_PM269.config``.
.. code-block:: bash
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
-image, ready for flashing (but check the next section for additional
-adjustments).
+image, ready for further processing.
-Pack U-Boot into repar-block
-----------------------------
+Process U-Boot
+--------------
-``DISCLAMER!`` All questions related to re-crypt work should be asked
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
in re-crypt repo issues. NOT HERE!
-re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
-form usable by device. This process is required only on the first
-installation or to recover the device in case of a failed update.
-You need to know your tablet's individual SBK to continue.
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update. You need to know your
+tablet's individual SBK to continue.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
.. code-block:: bash
- $ git clone https://github.com/clamor-s/re-crypt.git
- $ cd re-crypt # place your u-boot-dtb-regra.bin here
- $ ./re-crypt.sh -d grouper -k deadbeefdeadc0dedeadd00dfee1dead
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev grouper --sbk <your sbk>
+
+where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX``
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
-Script will produce you a ``repart-block.bin`` ready to flash.
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
-Flash repart-block into the eMMC
---------------------------------
+Flashing with the NV3P protocol
+*******************************
-``DISCLAMER!`` All questions related to NvFlash should be asked
-in the proper place. NOT HERE! Flashing repart-block will erase
-all your eMMC, so make a backup before!
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
-``repart-block.bin`` contains BCT and bootloader in encrypted state
-in form which can just be written RAW at the start of eMMC.
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
$ wheelie --blob blob.bin
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
Boot
----
-After flashing ``repart-block.bin`` the device should reboot and turn
-itself off. This is normal behavior if no boot configuration is
-found.
-
-To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration
-on eMMC. Additionally if Volume Down button is pressed while booting
-device will enter bootmenu. Bootmenu contains entries to mount eMMC as
-mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot
-console and update bootloader (check next chapter).
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+if the Volume Down button is pressed while booting, the device will enter
+bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot,
+reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
-Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
-and allows the user to use/partition it in any way the user desires.
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
Self Upgrading
--------------
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
-eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
-update bootloader option with Power button and U-Boot should update
-itself. Once the process is completed, U-Boot will ask to press any
-button to reboot.
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using
+ability of u-boot to mount it). Enter bootmenu, choose update bootloader option
+with Power button and U-Boot should update itself. Once the process is
+completed, U-Boot will ask to press any button to reboot.
U-Boot for the ASUS Transformer device family
=============================================
-``DISCLAMER!`` Moving your ASUS Transformer to use U-Boot
-assumes replacement of the vendor ASUS bootloader. Vendor
-android firmwares will no longer be able to run on the device.
-This replacement IS reversible.
+``DISCLAMER!`` Moving your ASUS Transformer to use U-Boot assumes replacement
+of the vendor ASUS bootloader. Vendor Android firmwares will no longer be
+able to run on the device. This replacement IS reversible.
Quick Start
-----------
- Build U-Boot
-- Pack U-Boot into repart-block
-- Flash repart-block into the eMMC
-- Flash repart-block into TF600T SPI flash
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Flashing U-Boot into the SPI flash
- Boot
- Self Upgrading
Build U-Boot
------------
-Device support is implemented by applying config fragment
-to a generic board defconfig. Valid fragments are ``tf201.config``,
-``tf300t.config``, ``tf300tg.config``, ``tf300tl.config``,
-``tf700t.config``, ``tf600t.config`` and ``p1801-t.config``.
+Device support is implemented by applying a config fragment to a generic board
+defconfig. Valid fragments are ``tf201.config``, ``tf300t.config``,
+``tf300tg.config``, ``tf300tl.config``, ``tf700t.config``, ``tf600t.config`` and
+``p1801-t.config``.
.. code-block:: bash
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
-image, ready for flashing (but check the next section for additional
-adjustments).
+image, ready for further processing.
-Pack U-Boot into repar-block
-----------------------------
+Process U-Boot
+--------------
-``DISCLAMER!`` All questions related to re-crypt work should be asked
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
in re-crypt repo issues. NOT HERE!
-re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
-form usable by device. This process is required only on the first
-installation or to recover the device in case of a failed update.
-You need to know your tablet's individual SBK to continue.
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update. You need to know your
+tablet's individual SBK to continue.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
.. code-block:: bash
- $ git clone https://github.com/clamor-s/re-crypt.git
- $ cd re-crypt # place your u-boot-dtb-regra.bin here
- $ ./re-crypt.sh -d tf201 -k deadbeefdeadc0dedeadd00dfee1dead
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev tf201 --sbk <your sbk>
+
+where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX``
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
-Script will produce you a `repart-block.bin` ready to flash.
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
-Flash repart-block into the eMMC
---------------------------------
+Flashing U-Boot into the eMMC
+-----------------------------
-``DISCLAMER!`` All questions related to NvFlash should be asked
-in the proper place. NOT HERE! Flashing repart-block will erase
-all your eMMC, so make a backup before!
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
-``repart-block.bin`` contains BCT and bootloader in encrypted state
-in form which can just be written RAW at the start of eMMC.
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
$ wheelie --blob blob.bin
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
-Flash repart-block into TF600T SPI flash
-----------------------------------------
-
-Unlike other transformers TF600T uses separate 4 MB SPI flash which
-contains all data required for boot. It is flashed from within u-boot
-itself preloaded into RAM using fusee gelee. After creating your
-``repart-block.bin`` you have to place it on a 1st partition of microSD
-card formated in fat. Then insert this microSD card into your tablet
-and boot it using fusee gelee and u-boot which was included into
-repart-block.bin, while booting you must hold volume down button.
-Process should take less then a minute, if everything goes correct,
-on microSD will appear ``spi-flash-backup.bin`` file, which is dump of
-your spi flash content and can be used to restore UEFI, do not loose it,
-tablet will power itself off.
-
-Self-updating of u-boot is performed by placing ``u-boot-dtb-tegra.bin``
-on 1st partition of microSD, inserting it into tablet and booting with
-pressed volume down button.
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Flashing U-Boot into the SPI Flash
+----------------------------------
+
+Some of Transformers use a separate 4 MB SPI flash, which contains all data
+required for boot. It is flashed from within U-Boot itself, preloaded into RAM
+using Fusée Gelée.
+
+After creating your ``repart-block.bin`` you have to place it on a 1st partition
+of microSD card formated in fat. Then insert this microSD card into your tablet
+and boot it using Fusée Gelée and U-Boot, which was included into
+``repart-block.bin``, while booting you must hold the ``volume down`` button.
+
+The process should take less than a minute, if everything goes correctly,
+on microSD will appear ``spi-flash-backup.bin`` file, which is the dump of your
+SPI Flash content and can be used to restore UEFI, do not lose it, tablet will
+power itself off.
+
+Self-updating of U-Boot is performed by placing ``u-boot-dtb-tegra.bin`` on 1st
+partition of microSD, inserting it into the tablet and booting with a pressed
+``volume down`` button.
Boot
----
-After flashing ``repart-block.bin`` the device should reboot and turn
-itself off. This is normal behavior if no boot configuration is
-found.
-
-To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD
-and then on eMMC. Additionally if Volume Down button is pressed
-while booting device will enter bootmenu. Bootmenu contains entries
-to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot
-RCM, poweroff, enter U-Boot console and update bootloader (check next
-chapter).
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
-Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
-and allows the user to use/partition it in any way the user desires.
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
Self Upgrading
--------------
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
-MicroSD card and insert it into the tablet. Enter bootmenu, choose
-update bootloader option with Power button and U-Boot should update
-itself. Once the process is completed, U-Boot will ask to press any
-button to reboot.
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the tablet. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
----------
Below is the pictorial representation of boot flow:
-.. image:: img/boot_diagram_k3_current.svg
+.. image:: ../ti/img/boot_diagram_k3_current.svg
:alt: Boot flow diagram
- On this platform, 'TI Foundational Security' (TIFS) functions as the
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. prompt:: bash $
- export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config"
- export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config"
+ export UBOOT_CFG_CORTEXR=am62x_beagleplay_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62x_beagleplay_a53_defconfig
export TFA_BOARD=lite
# we dont use any extra TFA parameters
unset TFA_EXTRA_ARGS
export OPTEE_PLATFORM=k3-am62x
export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
-.. include:: am62x_sk.rst
+.. include:: ../ti/am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_build_steps
:end-before: .. am62x_evm_rst_include_end_build_steps
- tiboot3.bin
-.. image:: img/multi_cert_tiboot3.bin.svg
+.. image:: ../ti/img/multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin image format
- tispl.bin
-.. image:: img/dm_tispl.bin.svg
+.. image:: ../ti/img/dm_tispl.bin.svg
:alt: tispl.bin image format
Additional hardware for U-Boot development
A53 SPL DDR Memory Layout
-------------------------
-.. include:: am62x_sk.rst
+.. include:: ../ti/am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_ddr_mem_layout
:end-before: .. am62x_evm_rst_include_end_ddr_mem_layout
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_tag_connect
:end-before: .. k3_rst_include_end_openocd_connect_tag_connect
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_cfg_external_intro
:end-before: .. k3_rst_include_end_openocd_cfg_external_intro
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+BeagleBoard.org
+###############
+
+
+ARM based boards
+----------------
+
+.. toctree::
+ :maxdepth: 2
+
+ am62x_beagleplay
+ j721e_beagleboneai64
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+J721E/TDA4VM Beagleboard.org BeagleBone AI-64
+=============================================
+
+Introduction:
+-------------
+
+BeagleBoard.org BeagleBone AI-64 is an open source hardware single
+board computer based on the Texas Instruments TDA4VM SoC featuring
+dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
+floating-point VLIW DSPs, 3x dual ARM Cortex-R5 co-processors,
+2x 6-core Programmable Real-Time Unit and Industrial Communication
+SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
+DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
+CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
+BeagleBone expansion headers.
+
+Further information can be found at:
+
+* Product Page: https://beagleboard.org/ai-64
+* Hardware documentation: https://git.beagleboard.org/beagleboard/beaglebone-ai-64
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: ../ti/img/boot_diagram_j721e.svg
+ :alt: Boot flow diagram
+
+- On this platform, DMSC runs 'TI Foundational Security' (TIFS) which
+ functions as the security enclave master. The 'Device Manager' (DM),
+ also known as the 'TISCI server' in "TI terminology", running on boot
+ R5F, offers all the essential services required for device management.
+ The A72, C7x, C6x or R5F (Aux cores) sends requests to TIFS/DM to
+ accomplish the needed services, as illustrated in the diagram above.
+
+Sources:
+--------
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR=j721e_beagleboneai64_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721e_beagleboneai64_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j721e
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
+
+.. include:: ../ti/j721e_evm.rst
+ :start-after: .. j721e_evm_rst_include_start_build_steps
+ :end-before: .. j721e_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+Copy the below images to an SD card and boot:
+
+* tiboot3-j721e-gp-evm.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Image formats
+-------------
+
+- tiboot3.bin
+
+.. image:: ../ti/img/no_multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: ../ti/img/dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+- sysfw.itb
+
+.. image:: ../ti/img/sysfw.itb.svg
+ :alt: sysfw.itb image format
+
+Additional hardware for U-Boot development
+------------------------------------------
+
+* Serial Console is critical for U-Boot development on BeagleBone AI-64. See
+ `BeagleBone AI-64 connector documentation
+ <https://docs.beagleboard.org/latest/boards/beaglebone/ai-64/ch07.html>`_.
+* uSD is preferred option over eMMC, and a SD/MMC reader will be needed.
+* (optionally) JTAG is useful when working with very early stages of boot.
+
+Default storage options
+-----------------------
+
+There are multiple storage media options on BeagleBone AI-64, but primarily:
+
+* Onboard eMMC (default) - reliable, fast and meant for deployment use.
+* SD/MMC card interface (hold 'BOOT' switch and power on) - Entirely
+ depends on the SD card quality.
+
+Flash to uSD card or how to deal with "bricked" Board
+--------------------------------------------------------
+
+When deploying or working on Linux, it's common to use the onboard
+eMMC. However, avoiding the eMMC and using the uSD card is safer when
+working with U-Boot.
+
+If you choose to hand format your own bootable uSD card, be
+aware that it can be difficult. The following information
+may be helpful, but remember that it is only sometimes
+reliable, and partition options can cause issues. These
+can potentially help:
+
+* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh
+* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD
+
+The simplest option is to start with a standard distribution
+image like those in `BeagleBoard.org Distros Page
+<https://www.beagleboard.org/distros>`_ and download a disk image for
+BeagleBone AI-64. Pick a 16GB+ uSD card to be on the safer side.
+
+With an SD/MMC Card reader and `Balena Etcher
+<https://etcher.balena.io/>`_, having a functional setup in minutes is
+a trivial matter, and it works on almost all Host Operating Systems.
+Yes Windows users, Windows Subsystem for Linux(WSL) based development
+with U-Boot and update uSD card is practical.
+
+Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and
+u-boot.img to the "BOOT" partition of the uSD card. Remember to sync
+and unmount (or Eject - depending on the Operating System) the uSD
+card prior to physically removing from SD card reader.
+
+Also see following section on switch setting used for booting using
+uSD card.
+
+.. note::
+ Great news! If the board has not been damaged physically, there's no
+ need to worry about it being "bricked" on this platform. You only have
+ to flash an uSD card, plug it in, and reinstall the image on eMMC. This
+ means that even if you make a mistake, you can quickly fix it and rest
+ easy.
+
+ If you are frequently working with uSD cards, you might find the
+ following useful:
+
+ * `USB-SD-Mux <https://www.linux-automation.com/en/products/usb-sd-mux.html>`_
+ * `SD-Wire <https://wiki.tizen.org/SDWire>`_
+
+Flash to eMMC
+-------------
+
+The eMMC layout selected is user-friendly for developers. The
+boot hardware partition of the eMMC only contains the fixed-size
+tiboot3.bin image. This is because the contents of the boot partitions
+need to run from the SoC's internal SRAM, which remains a fixed size
+constant. The other components of the boot sequence, such as tispl.bin
+and u-boot.img, are located in the /BOOT partition in the User Defined
+Area (UDA) hardware partition of the eMMC. These components can vary
+significantly in size. The choice of keeping tiboot3.bin in boot0 or
+boot1 partition depends on A/B update requirements.
+
+.. image:: img/beagleplay_emmc.svg
+ :alt: eMMC partitions and boot file organization for BeagleBone AI-64
+
+The following are the steps from Linux shell to program eMMC:
+
+.. prompt:: bash #
+
+ # Enable Boot0 boot
+ mmc bootpart enable 1 2 /dev/mmcblk0
+ mmc bootbus set single_backward x1 x8 /dev/mmcblk0
+ mmc hwreset enable /dev/mmcblk0
+
+ # Clear eMMC boot0
+ echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
+ dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
+ # Write tiboot3.bin
+ dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
+
+ # Copy the rest of the boot binaries
+ mount /dev/mmcblk0p1 /boot/firmware
+ cp tispl.bin /boot/firmware
+ cp u-boot.img /boot/firmware
+ sync
+
+.. warning ::
+
+ U-Boot is configured to prioritize booting from an SD card if it
+ detects a valid boot partition and boot files on it, even if the
+ system initially booted from eMMC. The boot order is set as follows:
+
+ * SD/MMC
+ * eMMC
+ * USB
+ * PXE
+
+LED patterns during boot
+------------------------
+
+.. list-table:: USR LED status indication
+ :widths: 16 16
+ :header-rows: 1
+
+ * - USR LEDs (012345)
+ - Indicates
+
+ * - 00000
+ - Boot failure or R5 image not started up
+
+ * - 11111
+ - A53 SPL/U-boot has started up
+
+ * - 10101
+ - OS boot process has been initiated
+
+ * - 01010
+ - OS boot process failed and drops to U-Boot shell
+
+.. note ::
+
+ In the table above, 0 indicates LED switched off and 1 indicates LED
+ switched ON.
+
+.. warning ::
+
+ The green LED very next to the serial connector labelled "WKUP UART0"
+ is the power LED (LED6). This is the same color as the rest of the USR
+ LEDs. If the "green" LED6 power LED is not glowing, the system power
+ supply is not functional. Please refer to `BeagleBone AI-64 documentation
+ <https://beagleboard.org/ai-64/>`_ for further information.
+
+Switch Setting for Boot Mode
+----------------------------
+
+The boot time option is configured via "BOOT" button on the board.
+See `BeagleBone AI-64 Schematics <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/-/blob/main/BeagleBone_AI-64_SCH.pdf>`_
+for details.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - BOOT Switch Position
+ - Primary Boot
+ - Secondary Boot
+
+ * - Not Pressed
+ - eMMC
+ - SD Card
+
+ * - Pressed
+ - SD Card
+ - SD Card
+
+To switch to SD card boot mode, hold the BOOT button while powering on
+with Type-C power supply, then release when power LED lights up.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup and debugging information.
+
+.. warning::
+
+ **OpenOCD support since**: v0.12.0
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_tag_connect
+ :end-before: .. k3_rst_include_end_openocd_connect_tag_connect
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_openocd_cfg_external_intro
+ :end-before: .. k3_rst_include_end_openocd_cfg_external_intro
+
+For example, with BeagleBone AI-64 (J721e platform), the openocd_connect.cfg:
+
+.. code-block:: tcl
+
+ # TUMPA example:
+ # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+ source [find interface/ftdi/tumpa.cfg]
+
+ transport select jtag
+
+ # default JTAG configuration has only SRST and no TRST
+ reset_config srst_only srst_push_pull
+
+ # delay after SRST goes inactive
+ adapter srst delay 20
+
+ if { ![info exists SOC] } {
+ # Set the SoC of interest
+ set SOC j721e
+ }
+
+ source [find target/ti_k3.cfg]
+
+ ftdi tdo_sample_edge falling
+
+ # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+ # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+ adapter speed 16000
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+ACPI on QEMU
+============
+
+QEMU can provide ACPI tables on ARM, RISC-V (since QEMU v8.0.0), and x86.
+
+The following U-Boot settings are needed for ACPI support::
+
+ CONFIG_CMD_QFW=y
+ CONFIG_ACPI=y
+ CONFIG_GENERATE_ACPI_TABLE=y
+
+On x86 these settings are already included in the defconfig files. ARM and
+RISC-V default to use device-trees.
+
+Instead of updating the configuration manually you can add the configuration
+fragment `acpi.config` to the make command for initializing the configuration.
+E.g.
+
+.. code-block:: bash
+
+ make qemu-riscv64_smode_defconfig acpi.config
.. toctree::
:maxdepth: 1
+ acpi
blkdev
../../usage/semihosting
qemu-arm
-drive if=none,file=riscv64.img,format=raw,id=mydisk \
-device ide-hd,drive=mydisk,bus=ahci.0
-You will have to run 'scsi scan' to use it.
+or alternatively attach an emulated UFS::
+
+ -device ufs,id=ufs0 \
+ -drive if=none,file=test.img,format=raw,id=lun0 \
+ -device ufs-lu,drive=lun0,bus=ufs0
+
+You will have to run 'scsi scan' to use them.
A video console can be emulated in RISC-V virt machine by removing "-nographic"
and adding::
U-Boot for the HTC One X (endeavoru)
====================================
-``DISCLAMER!`` Moving your HTC ONe X to use U-Boot assumes
-replacement of the vendor hboot. Vendor android firmwares
-will no longer be able to run on the device.
-This replacement IS reversible.
+``DISCLAMER!`` Moving your HTC ONe X to use U-Boot assumes replacement of the
+vendor hboot. Vendor android firmwares will no longer be able to run on the
+device. This replacement IS reversible.
Quick Start
-----------
- Build U-Boot
-- Pack U-Boot into repart-block
-- Flash repart-block into the eMMC
+- Process U-Boot
+- Flashing U-Boot into the eMMC
- Boot
- Self Upgrading
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
-image, ready for flashing (but check the next section for additional
-adjustments).
+image, ready for further processing.
-Pack U-Boot into repar-block
-----------------------------
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
-``DISCLAMER!`` All questions related to re-crypt work should be
-asked in re-crypt repo issues. NOT HERE!
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
-re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
-form usable by device. This process is required only on the first
-installation or to recover the device in case of a failed update.
+Processing for the NV3P protocol
+********************************
.. code-block:: bash
- $ git clone https://github.com/clamor-s/re-crypt.git
- $ cd re-crypt # place your u-boot-dtb-regra.bin here
- $ ./re-crypt.sh -d endeavoru
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev endeavoru
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
-Script will produce you a ``repart-block.bin`` ready to flash.
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
-Flash repart-block into the eMMC
---------------------------------
+Flashing U-Boot into the eMMC
+-----------------------------
-``DISCLAMER!`` All questions related to NvFlash should be asked
-in the proper place. NOT HERE! Flashing repart-block will erase
-all your eMMC, so make a backup before!
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
-``repart-block.bin`` contains BCT and bootloader in encrypted state
-in form which can just be written RAW at the start of eMMC.
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
$ wheelie --blob blob.bin
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
Boot
----
-After flashing ``repart-block.bin`` the device should reboot and turn
-itself off. This is normal behavior if no boot configuration is
-found.
-
-To boot Linux, U-Boot will look for an ``extlinux.conf`` configuration
-on eMMC. Additionally if Volume Down button is pressed while booting
-device will enter bootmenu. Bootmenu contains entries to mount eMMC as
-mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot
-console and update bootloader (check next chapter).
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+if the Volume Down button is pressed while booting, the device will enter
+bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot,
+reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
-Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
-and allows the user to use/partition it in any way the user desires.
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
Self Upgrading
--------------
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
-eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
-update bootloader option with Power button and U-Boot should update
-itself. Once the process is completed, U-Boot will ask to press any
-button to reboot.
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using
+ability of u-boot to mount it). Enter bootmenu, choose update bootloader option
+with Power button and U-Boot should update itself. Once the process is
+completed, U-Boot will ask to press any button to reboot.
asus/index
atmel/index
beacon/index
+ beagle/index
broadcom/index
bsh/index
cloos/index
U-Boot for the LG X3 T30 device family
======================================
-``DISCLAMER!`` Moving your LG P880 or P895 to use U-Boot
-assumes replacement of the vendor LG bootloader. Vendor
-android firmwares will no longer be able to run on the
-device. This replacement IS reversible.
+``DISCLAMER!`` Moving your LG P880 or P895 to use U-Boot assumes replacement
+of the vendor LG bootloader. Vendor android firmwares will no longer be able
+to run on the device. This replacement IS reversible.
Quick Start
-----------
- Build U-Boot
-- Pack U-Boot into repart-block
-- Flash repart-block into the eMMC
+- Process U-Boot
+- Flashing U-Boot into the eMMC
- Boot
- Self Upgrading
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
-image, ready for flashing (but check the next section for additional
-adjustments).
+image, ready for further processing.
-Pack U-Boot into repar-block
-----------------------------
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
-``DISCLAMER!`` All questions related to re-crypt work should be
-asked in re-crypt repo issues. NOT HERE!
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
-re-crypt is a small script which packs ``u-boot-dtb-tegra.bin`` in
-form usable by device. This process is required only on the first
-installation or to recover the device in case of a failed update.
+Processing for the NV3P protocol
+********************************
.. code-block:: bash
- $ git clone https://github.com/clamor-s/re-crypt.git
- $ cd re-crypt # place your u-boot-dtb-regra.bin here
- $ ./re-crypt.sh -d p895
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev p895
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
-Script will produce you a ``repart-block.bin`` ready to flash.
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
-Flash repart-block into the eMMC
---------------------------------
+Flashing U-Boot into the eMMC
+-----------------------------
-``DISCLAMER!`` All questions related to NvFlash should be asked
-in the proper place. NOT HERE! Flashing repart-block will erase
-all your eMMC, so make a backup before!
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
-``repart-block.bin`` contains BCT and bootloader in encrypted state
-in form which can just be written RAW at the start of eMMC.
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
$ wheelie --blob blob.bin
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
Boot
----
-After flashing ``repart-block.bin`` the device should reboot and turn
-itself off. This is normal behavior if no boot configuration is
-found.
-
-To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD
-and then on eMMC. Additionally if Volume Down button is pressed
-while booting device will enter bootmenu. Bootmenu contains entries
-to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot
-RCM, poweroff, enter U-Boot console and update bootloader (check next
-chapter).
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+if the Volume Down button is pressed while booting, the device will enter
+bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot,
+reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
-Flashing ``repart-block.bin`` eliminates vendor restriction on eMMC
-and allows the user to use/partition it in any way the user desires.
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
Self Upgrading
--------------
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the
-eMMC (using ability of u-boot to mount it). Enter bootmenu, choose
-update bootloader option with Power button and U-Boot should update
-itself. Once the process is completed, U-Boot will ask to press any
-button to reboot.
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using
+ability of u-boot to mount it). Enter bootmenu, choose update bootloader option
+with Power button and U-Boot should update itself. Once the process is
+completed, U-Boot will ask to press any button to reboot.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx93_11x11_evk
+=======================
+
+U-Boot for the NXP i.MX93 EVK on the 11x11mm board
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.8
+
+.. code-block:: bash
+
+ $ unset LDFLAGS
+ $ make PLAT=imx93 bl31
+ $ cp build/imx93/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+ $ chmod +x firmware-imx-8.21.bin
+ $ ./firmware-imx-8.21.bin
+ $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin
+ $ chmod +x firmware-sentinel-0.10.bin
+ $ ./firmware-sentinel-0.10.bin
+ $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx93_11x11_evk_defconfig
+ $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
imx8mp_evk
imx8mq_evk
imx8qxp_mek
+ imx93_11x11_evk
imxrt1020-evk
imxrt1050-evk
ls1046ardb
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jai Luthra <j-luthra@ti.com>
+
+AM62A Platforms
+===============
+
+Introduction:
+-------------
+The AM62A SoC family is built on the K3 Multicore SoC architecture platform,
+providing a deep learning accelerator, multi-camera support with ISP, video
+transcoder and other BOM-saving integrations.
+The AM62A SoC enables cost-sensitive automotive applications including driver
+and in-cabin monitoring systems, next generation of eMirror system, as well as
+a broad set of industrial applications in Factory Automation, Building
+Automation, Robotics and more.
+
+Some highlights of this SoC are:
+
+* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
+* Cortex-R5F for general-purpose or safety usage.
+* Deep Learning Accelerator with Single-core C7x Vector DSP with MMA (up to
+ 1.0GHz).
+* Vision Processing Accelerator (VPAC) with a 315MPixel/s ISP (up to 5MP @
+ 60fps) supporting 16-bit RAW input with RGB-IR separation.
+* 4K Video encoder and decoder for HEVC (Level 5.1 High-tier) and H.264 (Level
+ 5.2) supporting upto 240MPixels/s and MJPEG encoder at 416MPixels/s
+* Single display with 24-bit RGB parallel (DPI) interface supporting upto
+ 165Mhz pixel clock for 2K resolution.
+* Integrated Giga-bit Ethernet switch supporting up to a total of two
+ external ports (TSN capable).
+* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
+ NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
+ 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
+* Dedicated Centralized System Controller for Security, Power, and
+ Resource Management.
+* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
+ enabling battery powered system design.
+
+More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj16
+
+Platform information:
+
+* https://www.ti.com/tool/SK-AM62A-LP
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+ :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62ax
+ $ # we dont use any extra OPTEE parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+1. Trusted Firmware-A:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+2. OP-TEE:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-am62ax-gp-evm.bin from step 3.1
+ * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+ * tiboot3-am62ax-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-am62ax-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM62 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj16 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD
+ - 01000000
+ - 11000010
+
+ * - OSPI
+ - 00000000
+ - 11001110
+
+ * - EMMC
+ - 00000000
+ - 11010010
+
+ * - UART
+ - 00000000
+ - 11011100
+
+ * - USB DFU
+ - 00000000
+ - 11001010
+
+For SW2 and SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: August 2023 (git master)
+
+ Until the next stable release of OpenOCD is available in your development
+ environment's distribution, it might be necessary to build OpenOCD `from the
+ source <https://github.com/openocd-org/openocd>`_.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_am62a7evm.cfg
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. prompt:: bash $
1. Trusted Firmware-A:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
* 3.1 R5:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 3.2 A72:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
.. j721e_evm_rst_include_end_build_steps
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_XDS110
:end-before: .. k3_rst_include_end_openocd_connect_XDS110
.. toctree::
:maxdepth: 1
- am62x_beagleplay
+ am62ax_sk
am62x_sk
+ ../beagle/am62x_beagleplay
../toradex/verdin-am62
am64x_evm
am65x_evm
j7200_evm
+ ../beagle/j721e_beagleboneai64
j721e_evm
j721s2_evm
For more information on the bootup process of your SoC, consult the
device specific boot flow documentation.
+Secure Boot
+-----------
+
+K3 HS-SE (High Security - Security Enforced) devices enforce an
+authenticated boot flow for secure boot. HS-FS (High Security - Field
+Securable) is the state of a K3 device before it has been eFused with
+customer security keys. In the HS-FS state the authentication still can
+function as in HS-SE but as there are no customer keys to verify the
+signatures against the authentication will pass for certificates signed
+with any key.
+
+Chain of trust
+^^^^^^^^^^^^^^
+
+1) Public ROM loads the tiboot3.bin (R5 SPL, TIFS)
+2) R5 SPL loads tispl.bin (ATF, OP-TEE, DM, SPL)
+3) SPL loads u-boot.img (U-Boot)
+4) U-Boot loads fitImage (Linux and DTBs)
+
+Steps 1-3 are all authenticated by either the Secure ROM or TIFS as the
+authenticating entity and step 4 uses U-boot standard mechanism for
+authenticating.
+
+All the authentication that are done for ROM/TIFS are done through x509
+certificates that are signed.
+
+Firewalls
+^^^^^^^^^
+
+1) Secure ROM comes up and sets up firewalls that are needed by itself
+2) TIFS will setup it's own firewalls to protect core system resources
+3) R5 SPL will remove any firewalls that are leftover from the Secure ROM stage
+ that are no longer required.
+4) Each stage beyond this: such as tispl.bin containing TFA/OPTEE uses OIDs to
+ set up firewalls to protect themselves (enforced by TIFS)
+5) TFA/OP-TEE can configure other firewalls at runtime if required as they
+ are already authenticated and firewalled off from illegal access.
+6) All later stages can setup or remove firewalls that have not been already
+ configured by previous stages, such as those created by TIFS, TFA, and OP-TEE.
+
+Futhur, firewalls have a lockdown bit in hardware that enforces the setting
+(and cannot be over-ridden) until the full system is reset.
+
Software Sources
----------------
the final `tiboot3.bin` binary. (or the `sysfw.itb` if your device
uses the split binary flow)
+.. _k3_rst_include_start_build_steps_spl_r5:
+
.. k3_rst_include_start_build_steps_spl_r5
.. prompt:: bash $
finished, we can jump back into U-Boot again, this time running on a
64bit core in the main domain.
+.. _k3_rst_include_start_build_steps_uboot:
+
.. k3_rst_include_start_build_steps_uboot
.. prompt:: bash $
make CROSS_COMPILE=$CC64 BINMAN_INDIRS=$LNX_FW_PATH \
BL31=$TFA_PATH/build/k3/$TFA_BOARD/release/bl31.bin \
TEE=$OPTEE_PATH/out/arm-plat-k3/core/tee-raw.bin
+
+.. note::
+ It is also possible to pick up a custom DM binary by adding TI_DM argument
+ pointing to the file. If not provided, it defaults to picking up the DM
+ binary from BINMAN_INDIRS. This is only applicable to devices that utilize
+ split firmware.
+
.. k3_rst_include_end_build_steps_uboot
At this point you should have every binary needed initialize both the
| `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices
| `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices
-Fit Signature Signing
+FIT signature signing
---------------------
-K3 Platforms have fit signature signing enabled by default on their primary
-platforms. Here we'll take an example for creating fit image for J721e platform
+K3 platforms have FIT signature signing enabled by default on their primary
+platforms. Here we'll take an example for creating FIT Image for J721E platform
and the same can be extended to other platforms
-1. Describing FIT source
+Pre-requisites:
+
+* U-boot build (:ref:`U-boot build <k3_rst_include_start_build_steps_spl_r5>`)
+* Linux Image and Linux DTB prebuilt
+
+Describing FIT source
+^^^^^^^^^^^^^^^^^^^^^
- .. code-block:: bash
+FIT Image is a packed structure containing binary blobs and configurations.
+The Kernel FIT Image that we have has Kernel Image, DTB and the DTBOs. It
+supports packing multiple images and configurations that allow you to
+choose any configuration at runtime to boot from.
+
+.. code-block::
/dts-v1/;
/ {
- description = "Kernel fitImage for j721e-hs-evm";
- #address-cells = <1>;
-
- images {
- kernel-1 {
- description = "Linux kernel";
- data = /incbin/("Image");
- type = "kernel";
- arch = "arm64";
- os = "linux";
- compression = "none";
- load = <0x80080000>;
- entry = <0x80080000>;
- hash-1 {
- algo = "sha512";
- };
-
- };
- fdt-ti_k3-j721e-common-proc-board.dtb {
- description = "Flattened Device Tree blob";
- data = /incbin/("k3-j721e-common-proc-board.dtb");
- type = "flat_dt";
- arch = "arm64";
- compression = "none";
- load = <0x83000000>;
- hash-1 {
- algo = "sha512";
- };
-
- };
+ description = "FIT Image description";
+ #address-cells = <1>;
+
+ images {
+ [image-1]
+ [image-2]
+ [fdt-1]
+ [fdt-2]
+ }
+
+ configurations {
+ default = <conf-1>
+ [conf-1: image-1,fdt-1]
+ [conf-2: image-2,fdt-1]
+ }
+ }
+
+* Sample Images
+
+.. code-block::
+
+ kernel-1 {
+ description = "Linux kernel";
+ data = /incbin/("linux.bin");
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "gzip";
+ load = <0x81000000>;
+ entry = <0x81000000>;
+ hash-1 {
+ algo = "sha512";
};
-
- configurations {
- default = "conf-ti_k3-j721e-common-proc-board.dtb";
- conf-ti_k3-j721e-common-proc-board.dtb {
- description = "Linux kernel, FDT blob";
- fdt = "fdt-ti_k3-j721e-common-proc-board.dtb";
- kernel = "kernel-1";
- signature-1 {
- algo = "sha512,rsa4096";
- key-name-hint = "custMpk";
- sign-images = "kernel", "fdt";
- };
- };
+ };
+ fdt-ti_k3-j721e-common-proc-board.dtb {
+ description = "Flattened Device Tree blob";
+ data = /incbin/("arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dtb");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x83000000>;
+ hash-1 {
+ algo = "sha512";
};
};
+ # Optional images
+ fdt-ti_k3-j721e-evm-virt-mac-client.dtbo {
+ description = "Flattened Device Tree blob";
+ data = /incbin/("arch/arm64/boot/dts/ti/k3-j721e-evm-virt-mac-client.dtbo");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x83080000>;
+ hash-1 {
+ algo = "sha512";
+ };
+ };
+
+.. note::
- You would require to change the '/incbin/' lines to point to the respective
- files in your local machine and the key-name-hint also needs to be changed
- if you are using some other key other than the TI dummy key that we are
- using for this example.
+ Change the path in data variables to point to the respective files in your
+ local machine. For e.g change "linux.bin" to "<path-to-kernel-image>".
-2. Compile U-boot for the respective board
+For enabling usage of FIT signature, add the signature node to the
+corresponding configuration node as follows.
-.. include:: k3.rst
- :start-after: .. k3_rst_include_start_build_steps_uboot
- :end-before: .. k3_rst_include_end_build_steps_uboot
+* Sample Configurations
+
+.. code-block::
+
+ conf-ti_k3-j721e-common-proc-board.dtb {
+ description = "Linux kernel, FDT blob";
+ fdt = "fdt-ti_k3-j721e-common-proc-board.dtb";
+ kernel = "kernel-1";
+ signature-1 {
+ algo = "sha512,rsa4096";
+ key-name-hint = "custMpk";
+ sign-images = "kernel", "fdt";
+ };
+ };
+ # Optional configurations
+ conf-ti_k3-j721e-evm-virt-mac-client.dtbo {
+ description = "FDTO blob";
+ fdt = "fdt-ti_k3-j721e-evm-virt-mac-client.dtbo";
+
+ signature-1 {
+ algo = "sha512,rsa4096";
+ key-name-hint = "custMpk";
+ sign-images = "fdt";
+ };
+ };
+
+Specify all images you need the signature to authenticate as a part of
+sign-images. The key-name-hint needs to be changed if you are using some
+other key other than the TI dummy key that we are using for this example.
+It should be the name of the file containing the keys.
.. note::
- The changes only affect a72 binaries so the example just builds that
+ Generating new set of keys:
-3. Sign the fit image and embed the dtb in uboot
+ .. prompt:: bash $
- Now once the build is done, you'll have a dtb for your board that you'll
- be passing to mkimage for signing the fitImage and embedding the key in
- the u-boot dtb.
+ mkdir keys
+ openssl genpkey -algorithm RSA -out keys/dev.key \
+ -pkeyopt rsa_keygen_bits:4096 -pkeyopt rsa_keygen_pubexp:65537
+ openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
- .. prompt:: bash $
+Generating the fitImage
+^^^^^^^^^^^^^^^^^^^^^^^
- mkimage -r -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
- $UBOOT_PATH/build/a72/dts/dt.dtb
+.. note::
+
+ For signing a secondary platform like SK boards, you'll require
+ additional steps
- For signing a secondary platform, pass the -K parameter to that DTB
+ - Change the CONFIG_DEFAULT_DEVICE_TREE
- .. prompt:: bash $
+ For e.g
- mkimage -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
- $UBOOT_PATH/build/a72/arch/arm/dts/k3-j721e-sk.dtb
+ .. code-block::
- .. note::
+ diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
+ index a5c1df7e0054..6d0126d955ef 100644
+ --- a/configs/j721e_evm_a72_defconfig
+ +++ b/configs/j721e_evm_a72_defconfig
+ @@ -13,7 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+ CONFIG_ENV_SIZE=0x20000
+ CONFIG_DM_GPIO=y
+ CONFIG_SPL_DM_SPI=y
+ -CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
+ +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-sk"
+ CONFIG_SPL_TEXT_BASE=0x80080000
+ CONFIG_DM_RESET=y
+ CONFIG_SPL_MMC=y
- If changing `CONFIG_DEFAULT_DEVICE_TREE` to the secondary platform,
- binman changes would also be required so that correct dtb gets packaged.
+ - Change the binman nodes to package u-boot.dtb for the correct set of platform
- .. code-block:: bash
+ For e.g
- diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
- index 673be646b1e3..752fa805fe8d 100644
- --- a/arch/arm/dts/k3-j721e-binman.dtsi
- +++ b/arch/arm/dts/k3-j721e-binman.dtsi
- @@ -299,8 +299,8 @@
- #define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
+ .. code-block::
- #define UBOOT_NODTB "u-boot-nodtb.bin"
- -#define J721E_EVM_DTB "u-boot.dtb"
- -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
- +#define J721E_EVM_DTB "arch/arm/dts/k3-j721e-common-proc-board.dtb"
- +#define J721E_SK_DTB "u-boot.dtb"
+ diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
+ index 673be646b1e3..752fa805fe8d 100644
+ --- a/arch/arm/dts/k3-j721e-binman.dtsi
+ +++ b/arch/arm/dts/k3-j721e-binman.dtsi
+ @@ -299,8 +299,8 @@
+ #define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
-5. Rebuilt u-boot
+ #define UBOOT_NODTB "u-boot-nodtb.bin"
+ -#define J721E_EVM_DTB "u-boot.dtb"
+ -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
+ +#define J721E_EVM_DTB "arch/arm/dts/k3-j721e-common-proc-board.dtb"
+ +#define J721E_SK_DTB "u-boot.dtb"
- This is required so that the modified dtb gets updated in u-boot.img
+This step will embed the public key in the u-boot.dtb file that was already
+built during the initial u-boot build.
-.. include:: k3.rst
- :start-after: .. k3_rst_include_start_build_steps_uboot
- :end-before: .. k3_rst_include_end_build_steps_uboot
+.. prompt:: bash $
-6. (Optional) Enabled FIT_SIGNATURE_ENFORCED
+ mkimage -r -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K $UBOOT_PATH/build/$ARMV8/dts/dt.dtb fitImage
- By default u-boot will boot up the fit image without any authentication as
- such if the public key is not embedded properly, to check if the public key
- nodes are proper you can enable FIT_SIGNATURE_ENFORCED that would not rely
- on the dtb for anything else then the signature node for checking the fit
- image, rest other things will be enforced such as the property of
- required-keys. This is not an extensive check so do manual checks also
+.. note::
+
+ If you have another set of keys then change the -k argument to point to
+ the folder where your keys are present, the build requires the presence
+ of both .key and .crt file.
+
+Build u-boot again
+^^^^^^^^^^^^^^^^^^
- This is by default enabled for devices with TI_SECURE_DEVICE enabled.
+The updated u-boot.dtb needs to be packed in u-boot.img for authentication
+so rebuild U-boot ARMV8 without changing any parameters.
+Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`)
.. note::
- The devices now also have distroboot enabled so if the fit image doesn't
- work then the fallback to normal distroboot will be there on hs devices,
- this will need to be explicitly disabled by changing the boot_targets.
+ The devices now also have distroboot enabled so if the FIT image doesn't
+ work then the fallback to normal distroboot will be there on HS devices.
+ This will need to be explicitly disabled by changing the boot_targets to
+ disallow fallback during testing.
Saving environment
------------------
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx93_var_som
+=======================
+
+U-Boot for the Variscite VAR-SOM-MX93 Symphony evaluation board
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.8
+
+.. code-block:: bash
+
+ $ unset LDFLAGS
+ $ make PLAT=imx93 bl31
+ $ cp build/imx93/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+ $ chmod +x firmware-imx-8.21.bin
+ $ ./firmware-imx-8.21.bin
+ $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin
+ $ chmod +x firmware-sentinel-0.10.bin
+ $ ./firmware-sentinel-0.10.bin
+ $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx93_var_som_defconfig
+ $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
:maxdepth: 2
imx8mn_var_som
+ imx93_var_som
supported inline assembly is needed to get and set the r9 or x18 value. This
leads to larger code then strictly necessary, but at least works.
-**NOTE:** target compilation only work for _some_ ARM boards at the moment.
-Also AArch64 is not supported currently due to a lack of private libgcc
-support. Boards which reassign gd in c will also fail to compile, but there is
-in no strict reason to do so in the ARM world, since crt0.S takes care of this.
-These assignments can be avoided by changing the init calls but this is not in
-mainline yet.
-
-
Debian based
------------
sudo apt-get install clang
-Note that we still use binutils for some tools so we must continue to set
-CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g.
+We make use of the CROSS_COMPILE variable to derive the build target which is
+passed as the --target parameter to clang.
+
+The CROSS_COMPILE variable further determines the paths to other build
+tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as'
+instead of the LLVM integrated assembler (IAS).
+
+Here is an example demonstrating building U-Boot for the Raspberry Pi 2
+using clang:
.. code-block:: bash
make HOSTCC=clang rpi_2_defconfig
- make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \
- CC="clang -target arm-linux-gnueabi" -j8
+ make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8
It can also be used to compile sandbox:
# Display the documentation in a graphical web browser
x-www-browser doc/output/index.html
-The HTML documentation is published at https://u-boot.readthedocs.io. The build
+The HTML documentation is published at https://docs.u-boot.org. The build
process for that site is controlled by the file *.readthedocs.yml*.
Infodoc documentation
load = <0>;
entry = <0>;
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
arch = "arm";
compression = "none";
hash-1{
- algo = "sha1";
+ algo = "sha256";
};
};
};
load = <0>;
entry = <0>;
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
arch = "arm";
compression = "none";
hash-1{
- algo = "sha1";
+ algo = "sha256";
};
};
};
For the design goals of bloblist, please see the comments at the top of the
`bloblist.h` header file.
+Bloblist is an implementation with the `Firmware Handoff`_ protocol.
+
Passing state through the boot process
--------------------------------------
-----------------
.. kernel-doc:: include/bloblist.h
-
+.. _`Firmware Handoff`: https://github.com/FirmwareHandoff/firmware_handoff
Simon Glass
sjg@chromium.org
devicetree at runtime, for example if an earlier bootloader stage creates
it and passes it to U-Boot.
+If CONFIG_BLOBLIST is defined, the devicetree may come from a bloblist passed
+from a previous stage, if present.
+
If CONFIG_SANDBOX is defined, then it will be read from a file on
startup. Use the -d flag to U-Boot to specify the file to read, -D for the
default and -T for the test devicetree, used to run sandbox unit tests.
Current Status
--------------
-* U-Boot v2023.10 was released on Mon 02 October 2023.
+* U-Boot v2024.01 was released on Mon 08 January 2024.
-* The Merge Window for the next release (v2024.01) is **closed**.
+* The Merge Window for the next release (v2024.04) is **open** until the -rc1
+ release on Mon 29 January 2024.
* The next branch is now **closed**.
-* Release "v2024.01" is scheduled for 08 January 2024.
+* Release "v2024.04" is scheduled for 02 April 2024.
Future Releases
---------------
.. The following commented out dates are for when release candidates are
planned to be tagged.
-For the next scheduled release, release candidates were made on::
+.. For the next scheduled release, release candidates were made on::
-* U-Boot v2024.01-rc1 was released on Mon 23 October 2023.
+.. * U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
-* U-Boot v2024.01-rc2 was released on Mon 06 November 2023.
+.. * U-Boot v2024.01-rc2 was released on Mon 12 February 2024.
-* U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
+.. * U-Boot v2024.01-rc3 was released on Mon 26 February 2024.
-* U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
+.. * U-Boot v2024.01-rc4 was released on Mon 11 March 2024.
-.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
-
-.. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024.
+.. * U-Boot v2024.01-rc5 was released on Mon 25 March 2024.
Please note that the following dates are planned only and may be deviated from
as needed.
-* "v2024.01": end of MW = Mon, Oct 23, 2023; release = Mon, Jan 08, 2024
-
* "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024
* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024
* "v2024.10": end of MW = Mon, Jul 22, 2024; release = Mon, Oct 07, 2024
+* "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025
+
Previous Releases
-----------------
<https://source.denx.de/u-boot/gitdm>`_, which was originally created by
Jonathan Corbet.
+* :doc:`statistics/u-boot-stats-v2024.01` which was released on 08 January 2024.
+
* :doc:`statistics/u-boot-stats-v2023.10` which was released on 02 October 2023.
* :doc:`statistics/u-boot-stats-v2023.07` which was released on 10 July 2023.
* Awaiting Upstream
- * Superseeded
+ * Superseded
* Deferred
and has not merged yet to master, or has queued the patch up to be submitted
to be merged, but has not yet.
-* Superseeded: Patches are marked as 'superseeded' when the poster submits a
+* Superseded: Patches are marked as 'superseded' when the poster submits a
new version of these patches.
* Deferred: Deferred usually means the patch depends on something else that
--- /dev/null
+:orphan:
+
+Release Statistics for U-Boot v2024.01
+======================================
+
+* Processed 1564 changesets from 191 developers
+
+* 25 employers found
+
+* A total of 100266 lines added, 38766 removed (delta 61500)
+
+.. table:: Developers with the most changesets
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 273 (17.5%)
+ Marek Vasut 194 (12.4%)
+ Michal Simek 64 (4.1%)
+ Heinrich Schuchardt 51 (3.3%)
+ Tom Rini 50 (3.2%)
+ Jonas Karlman 46 (2.9%)
+ Sean Anderson 38 (2.4%)
+ Svyatoslav Ryhel 36 (2.3%)
+ Nishanth Menon 35 (2.2%)
+ Andre Przywara 33 (2.1%)
+ Paul Barker 32 (2.0%)
+ Venkatesh Yadav Abbarapu 28 (1.8%)
+ Bryan Brattlof 26 (1.7%)
+ Sughosh Ganu 21 (1.3%)
+ AKASHI Takahiro 20 (1.3%)
+ Bin Meng 19 (1.2%)
+ Alexey Romanov 19 (1.2%)
+ Chanho Park 18 (1.2%)
+ Dario Binacchi 16 (1.0%)
+ Sam Protsenko 15 (1.0%)
+ Dan Carpenter 15 (1.0%)
+ Tim Harvey 14 (0.9%)
+ Fabio Estevam 14 (0.9%)
+ Roger Quadros 13 (0.8%)
+ Rasmus Villemoes 13 (0.8%)
+ Randolph 11 (0.7%)
+ Tony Dinh 11 (0.7%)
+ Alexander Dahl 11 (0.7%)
+ Igor Prusov 9 (0.6%)
+ Ilias Apalodimas 9 (0.6%)
+ Hector Martin 9 (0.6%)
+ Samuel Holland 9 (0.6%)
+ Johan Jonker 9 (0.6%)
+ Matthias Schiffer 9 (0.6%)
+ Neha Malcom Francis 8 (0.5%)
+ Chris Packham 8 (0.5%)
+ Joao Marcos Costa 8 (0.5%)
+ Jan Kiszka 7 (0.4%)
+ Jim Liu 7 (0.4%)
+ Yang Xiwen 7 (0.4%)
+ Marcel Ziswiler 7 (0.4%)
+ Siddharth Vadapalli 7 (0.4%)
+ Gatien Chevallier 7 (0.4%)
+ Neil Armstrong 6 (0.4%)
+ Masahisa Kojima 6 (0.4%)
+ Udit Kumar 6 (0.4%)
+ Eddie James 6 (0.4%)
+ Sam Edwards 6 (0.4%)
+ Teresa Remmet 6 (0.4%)
+ Manorit Chawdhry 6 (0.4%)
+ Laurentiu Tudor 6 (0.4%)
+ Joshua Watt 6 (0.4%)
+ Mattijs Korpershoek 5 (0.3%)
+ Shantur Rathore 5 (0.3%)
+ Patrick Delaunay 5 (0.3%)
+ Artur Rojek 5 (0.3%)
+ Mikhail Kshevetskiy 5 (0.3%)
+ FUKAUMI Naoki 5 (0.3%)
+ Ashok Reddy Soma 5 (0.3%)
+ Mark Kettenis 4 (0.3%)
+ John Clark 4 (0.3%)
+ Philip Oberfichtner 4 (0.3%)
+ Milan P. Stanić 4 (0.3%)
+ Tom Fitzhenry 4 (0.3%)
+ Josua Mayer 4 (0.3%)
+ Elaine Zhang 4 (0.3%)
+ Sébastien Szymanski 4 (0.3%)
+ Andrew Davis 4 (0.3%)
+ Manoj Sai 4 (0.3%)
+ Alper Nebi Yasak 4 (0.3%)
+ Emanuele Ghidoli 3 (0.2%)
+ Alexander Gendin 3 (0.2%)
+ Hiago De Franco 3 (0.2%)
+ Andrejs Cainikovs 3 (0.2%)
+ Yu Chien Peter Lin 3 (0.2%)
+ Quentin Schulz 3 (0.2%)
+ Tim Lunn 3 (0.2%)
+ Patrice Chotard 3 (0.2%)
+ Algapally Santosh Sagar 3 (0.2%)
+ Abdellatif El Khlifi 3 (0.2%)
+ Fedor Ross 3 (0.2%)
+ Reid Tonking 3 (0.2%)
+ Massimo Pegorer 3 (0.2%)
+ Frank Wunderlich 3 (0.2%)
+ Fabrice Gasnier 3 (0.2%)
+ Thomas Mittelstaedt 3 (0.2%)
+ Baruch Siach 2 (0.1%)
+ Peter Robinson 2 (0.1%)
+ Hugo Villeneuve 2 (0.1%)
+ Janne Grunau 2 (0.1%)
+ Simon Holesch 2 (0.1%)
+ Dylan Corrales 2 (0.1%)
+ Oleksandr Suvorov 2 (0.1%)
+ Tejas Bhumkar 2 (0.1%)
+ Amit Kumar Mahapatra 2 (0.1%)
+ Robert Marko 2 (0.1%)
+ Sean Edmond 2 (0.1%)
+ Maksim Kiselev 2 (0.1%)
+ Wei Chen 2 (0.1%)
+ Francois Berder 2 (0.1%)
+ Lukas Funke 2 (0.1%)
+ Lars Feyaerts 2 (0.1%)
+ Love Kumar 2 (0.1%)
+ Suman Anna 2 (0.1%)
+ Laurent Pinchart 2 (0.1%)
+ Harald Seiler 2 (0.1%)
+ Neal Frager 2 (0.1%)
+ Shiji Yang 2 (0.1%)
+ Anthony Loiseau 1 (0.1%)
+ Moritz Fischer 1 (0.1%)
+ Miquel Raynal 1 (0.1%)
+ Mikhail Kalashnikov 1 (0.1%)
+ Stephen Graf 1 (0.1%)
+ Chukun Pan 1 (0.1%)
+ Weizhao Ouyang 1 (0.1%)
+ Stefan Roese 1 (0.1%)
+ Cong Dang 1 (0.1%)
+ Jonathan Corbet 1 (0.1%)
+ Nikita Yushchenko 1 (0.1%)
+ John Keeping 1 (0.1%)
+ Ludwig Kormann 1 (0.1%)
+ Igor Opaniuk 1 (0.1%)
+ Bhupesh Sharma 1 (0.1%)
+ Ibai Erkiaga 1 (0.1%)
+ Piyush Mehta 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Dmitry Rokosov 1 (0.1%)
+ Frank de Brabander 1 (0.1%)
+ Dylan Hung 1 (0.1%)
+ Ley Foon Tan 1 (0.1%)
+ Caleb Connolly 1 (0.1%)
+ Maxim Cournoyer 1 (0.1%)
+ Yong-Xuan Wang 1 (0.1%)
+ Eugen Hristev 1 (0.1%)
+ Nathan Barrett-Morrison 1 (0.1%)
+ Emekcan Aras 1 (0.1%)
+ Vishal Mahaveer 1 (0.1%)
+ Wojciech Nizinski 1 (0.1%)
+ Michel Alex 1 (0.1%)
+ Martin Fäcknitz 1 (0.1%)
+ Marek Behún 1 (0.1%)
+ Andrey Skvortsov 1 (0.1%)
+ Yurii Monakov 1 (0.1%)
+ Ricardo Pardini 1 (0.1%)
+ Matwey V. Kornilov 1 (0.1%)
+ Guochun Huang 1 (0.1%)
+ Okhunjon Sobirjonov 1 (0.1%)
+ Mayuresh Chitale 1 (0.1%)
+ Guillaume La Roque 1 (0.1%)
+ Ye Li 1 (0.1%)
+ Alice Guo 1 (0.1%)
+ Joao Paulo Goncalves 1 (0.1%)
+ Eduard Strehlau 1 (0.1%)
+ Andrej Rosano 1 (0.1%)
+ Ricardo Salveti 1 (0.1%)
+ Michael Scott 1 (0.1%)
+ Dominik Haller 1 (0.1%)
+ Nikhil M Jain 1 (0.1%)
+ Roman Azarenko 1 (0.1%)
+ Nicolò Veronese 1 (0.1%)
+ Andrii Chepurnyi 1 (0.1%)
+ Han Xu 1 (0.1%)
+ Patryk Biel 1 (0.1%)
+ Polak, Leszek 1 (0.1%)
+ Tanmay Shah 1 (0.1%)
+ shengfei Xu 1 (0.1%)
+ Joseph Chen 1 (0.1%)
+ Anatolij Gustschin 1 (0.1%)
+ Kuan Lim Lee 1 (0.1%)
+ Roger Knecht 1 (0.1%)
+ Jesse Taube 1 (0.1%)
+ Rong Tao 1 (0.1%)
+ Andy Shevchenko 1 (0.1%)
+ Troy Kisky 1 (0.1%)
+ Thippeswamy Havalige 1 (0.1%)
+ Srinivas Neeli 1 (0.1%)
+ Saeed Nowshadi 1 (0.1%)
+ Maxim Kochetkov 1 (0.1%)
+ Christian Taedcke 1 (0.1%)
+ Trevor Woerner 1 (0.1%)
+ Nicolas Frattaroli 1 (0.1%)
+ Li Hua Qian 1 (0.1%)
+ Robert Nelson 1 (0.1%)
+ Łukasz Stelmach 1 (0.1%)
+ Elena Popa 1 (0.1%)
+ Naveen Kumar Chaudhary 1 (0.1%)
+ Kevin Chen 1 (0.1%)
+ Sergei Antonov 1 (0.1%)
+ Jason Kacines 1 (0.1%)
+ Ilya Lukin 1 (0.1%)
+ Mihai Sain 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most changed lines
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 11496 (9.8%)
+ Marek Vasut 8067 (6.8%)
+ Michal Simek 7518 (6.4%)
+ Laurentiu Tudor 6213 (5.3%)
+ Paul Barker 5361 (4.5%)
+ Andre Przywara 4529 (3.8%)
+ Tim Harvey 4234 (3.6%)
+ Nishanth Menon 3762 (3.2%)
+ Jonas Karlman 3755 (3.2%)
+ Dario Binacchi 3615 (3.1%)
+ AKASHI Takahiro 3492 (3.0%)
+ Robert Nelson 3243 (2.8%)
+ FUKAUMI Naoki 2908 (2.5%)
+ Roger Quadros 2836 (2.4%)
+ Neha Malcom Francis 2822 (2.4%)
+ Svyatoslav Ryhel 2768 (2.3%)
+ Manorit Chawdhry 2699 (2.3%)
+ Tom Rini 2320 (2.0%)
+ Sean Anderson 2224 (1.9%)
+ Johan Jonker 1984 (1.7%)
+ Heinrich Schuchardt 1886 (1.6%)
+ Sughosh Ganu 1824 (1.5%)
+ Igor Prusov 1710 (1.5%)
+ Eddie James 1481 (1.3%)
+ Bryan Brattlof 1357 (1.2%)
+ Tom Fitzhenry 1323 (1.1%)
+ Reid Tonking 1209 (1.0%)
+ John Clark 1202 (1.0%)
+ Tony Dinh 1163 (1.0%)
+ Alexey Romanov 1159 (1.0%)
+ Sébastien Szymanski 1129 (1.0%)
+ Frank Wunderlich 1035 (0.9%)
+ Mikhail Kshevetskiy 926 (0.8%)
+ Chanho Park 880 (0.7%)
+ Teresa Remmet 781 (0.7%)
+ Mihai Sain 781 (0.7%)
+ Yang Xiwen 652 (0.6%)
+ Patrice Chotard 605 (0.5%)
+ Artur Rojek 595 (0.5%)
+ Alexander Gendin 516 (0.4%)
+ Yu Chien Peter Lin 421 (0.4%)
+ Randolph 379 (0.3%)
+ Andrew Davis 354 (0.3%)
+ Joshua Watt 343 (0.3%)
+ Joao Marcos Costa 334 (0.3%)
+ Alexander Dahl 305 (0.3%)
+ Mikhail Kalashnikov 294 (0.2%)
+ Sam Edwards 288 (0.2%)
+ Neil Armstrong 282 (0.2%)
+ Venkatesh Yadav Abbarapu 277 (0.2%)
+ Samuel Holland 266 (0.2%)
+ Philip Oberfichtner 266 (0.2%)
+ Gatien Chevallier 264 (0.2%)
+ Janne Grunau 231 (0.2%)
+ Matthias Schiffer 230 (0.2%)
+ Bin Meng 201 (0.2%)
+ Andrii Chepurnyi 181 (0.2%)
+ Marek Behún 180 (0.2%)
+ Jan Kiszka 179 (0.2%)
+ Algapally Santosh Sagar 174 (0.1%)
+ Linus Walleij 170 (0.1%)
+ Udit Kumar 165 (0.1%)
+ Patrick Delaunay 142 (0.1%)
+ Rasmus Villemoes 128 (0.1%)
+ Fabio Estevam 126 (0.1%)
+ Shiji Yang 123 (0.1%)
+ Elaine Zhang 111 (0.1%)
+ Oleksandr Suvorov 108 (0.1%)
+ Siddharth Vadapalli 107 (0.1%)
+ Fabrice Gasnier 103 (0.1%)
+ Sergei Antonov 103 (0.1%)
+ Kuan Lim Lee 102 (0.1%)
+ Alper Nebi Yasak 99 (0.1%)
+ Marcel Ziswiler 97 (0.1%)
+ Christian Taedcke 95 (0.1%)
+ Tim Lunn 93 (0.1%)
+ Hector Martin 90 (0.1%)
+ Emanuele Ghidoli 89 (0.1%)
+ Nicolas Frattaroli 89 (0.1%)
+ Mark Kettenis 88 (0.1%)
+ Fedor Ross 86 (0.1%)
+ Chris Packham 84 (0.1%)
+ Love Kumar 84 (0.1%)
+ Robert Marko 80 (0.1%)
+ Sam Protsenko 78 (0.1%)
+ Vishal Mahaveer 75 (0.1%)
+ Ilias Apalodimas 70 (0.1%)
+ Ashok Reddy Soma 64 (0.1%)
+ Andrejs Cainikovs 59 (0.1%)
+ Peter Robinson 58 (0.0%)
+ Jesse Taube 57 (0.0%)
+ Quentin Schulz 55 (0.0%)
+ Tejas Bhumkar 54 (0.0%)
+ Suman Anna 51 (0.0%)
+ Ibai Erkiaga 49 (0.0%)
+ Masahisa Kojima 45 (0.0%)
+ Sean Edmond 45 (0.0%)
+ Maxim Cournoyer 45 (0.0%)
+ Laurent Pinchart 44 (0.0%)
+ Jim Liu 43 (0.0%)
+ Lars Feyaerts 42 (0.0%)
+ Massimo Pegorer 41 (0.0%)
+ Manoj Sai 40 (0.0%)
+ Joseph Chen 40 (0.0%)
+ Simon Holesch 39 (0.0%)
+ Josua Mayer 35 (0.0%)
+ Hiago De Franco 35 (0.0%)
+ Tanmay Shah 33 (0.0%)
+ Frank de Brabander 32 (0.0%)
+ Shantur Rathore 31 (0.0%)
+ Igor Opaniuk 30 (0.0%)
+ Dan Carpenter 28 (0.0%)
+ Ludwig Kormann 27 (0.0%)
+ Maxim Kochetkov 26 (0.0%)
+ Neal Frager 23 (0.0%)
+ Mattijs Korpershoek 22 (0.0%)
+ Baruch Siach 22 (0.0%)
+ Ley Foon Tan 20 (0.0%)
+ Andy Shevchenko 20 (0.0%)
+ shengfei Xu 19 (0.0%)
+ Eduard Strehlau 16 (0.0%)
+ Yurii Monakov 14 (0.0%)
+ Ye Li 13 (0.0%)
+ Dylan Hung 12 (0.0%)
+ Michel Alex 12 (0.0%)
+ Matwey V. Kornilov 12 (0.0%)
+ Milan P. Stanić 11 (0.0%)
+ Li Hua Qian 11 (0.0%)
+ Wei Chen 10 (0.0%)
+ Mayuresh Chitale 10 (0.0%)
+ Polak, Leszek 9 (0.0%)
+ Dylan Corrales 8 (0.0%)
+ Andrey Skvortsov 8 (0.0%)
+ Troy Kisky 8 (0.0%)
+ Naveen Kumar Chaudhary 8 (0.0%)
+ Okhunjon Sobirjonov 7 (0.0%)
+ Roman Azarenko 7 (0.0%)
+ Han Xu 7 (0.0%)
+ Anatolij Gustschin 7 (0.0%)
+ Thomas Mittelstaedt 6 (0.0%)
+ Amit Kumar Mahapatra 6 (0.0%)
+ Eugen Hristev 6 (0.0%)
+ Abdellatif El Khlifi 5 (0.0%)
+ Harald Seiler 5 (0.0%)
+ Anthony Loiseau 5 (0.0%)
+ Chukun Pan 5 (0.0%)
+ Weizhao Ouyang 5 (0.0%)
+ Roger Knecht 5 (0.0%)
+ Trevor Woerner 5 (0.0%)
+ Ilya Lukin 5 (0.0%)
+ Hugo Villeneuve 4 (0.0%)
+ Lukas Funke 4 (0.0%)
+ Jonathan Corbet 4 (0.0%)
+ Ricardo Salveti 4 (0.0%)
+ Nicolò Veronese 4 (0.0%)
+ Saeed Nowshadi 4 (0.0%)
+ Maksim Kiselev 3 (0.0%)
+ Caleb Connolly 3 (0.0%)
+ Guillaume La Roque 3 (0.0%)
+ Jason Kacines 3 (0.0%)
+ Francois Berder 2 (0.0%)
+ Stephen Graf 2 (0.0%)
+ Nikita Yushchenko 2 (0.0%)
+ Bhupesh Sharma 2 (0.0%)
+ Piyush Mehta 2 (0.0%)
+ Wojciech Nizinski 2 (0.0%)
+ Alice Guo 2 (0.0%)
+ Joao Paulo Goncalves 2 (0.0%)
+ Andrej Rosano 2 (0.0%)
+ Srinivas Neeli 2 (0.0%)
+ Łukasz Stelmach 2 (0.0%)
+ Moritz Fischer 1 (0.0%)
+ Miquel Raynal 1 (0.0%)
+ Stefan Roese 1 (0.0%)
+ Cong Dang 1 (0.0%)
+ John Keeping 1 (0.0%)
+ Dmitry Rokosov 1 (0.0%)
+ Yong-Xuan Wang 1 (0.0%)
+ Nathan Barrett-Morrison 1 (0.0%)
+ Emekcan Aras 1 (0.0%)
+ Martin Fäcknitz 1 (0.0%)
+ Ricardo Pardini 1 (0.0%)
+ Guochun Huang 1 (0.0%)
+ Michael Scott 1 (0.0%)
+ Dominik Haller 1 (0.0%)
+ Nikhil M Jain 1 (0.0%)
+ Patryk Biel 1 (0.0%)
+ Rong Tao 1 (0.0%)
+ Thippeswamy Havalige 1 (0.0%)
+ Elena Popa 1 (0.0%)
+ Kevin Chen 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most lines removed
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Laurentiu Tudor 5975 (15.4%)
+ Dario Binacchi 3012 (7.8%)
+ Tom Rini 1059 (2.7%)
+ Andrew Davis 346 (0.9%)
+ Tim Harvey 83 (0.2%)
+ Chris Packham 58 (0.1%)
+ Peter Robinson 58 (0.1%)
+ Ilias Apalodimas 21 (0.1%)
+ Jesse Taube 21 (0.1%)
+ Ibai Erkiaga 16 (0.0%)
+ Eduard Strehlau 16 (0.0%)
+ Bin Meng 12 (0.0%)
+ Matwey V. Kornilov 10 (0.0%)
+ Andy Shevchenko 9 (0.0%)
+ Ilya Lukin 5 (0.0%)
+ Trevor Woerner 4 (0.0%)
+ Maxim Kochetkov 2 (0.0%)
+ Piyush Mehta 2 (0.0%)
+ Joao Paulo Goncalves 2 (0.0%)
+ Abdellatif El Khlifi 1 (0.0%)
+ Stephen Graf 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most signoffs (total 215)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Michal Simek 55 (25.6%)
+ Neil Armstrong 29 (13.5%)
+ Minkyu Kang 13 (6.0%)
+ Heinrich Schuchardt 9 (4.2%)
+ Peng Fan 7 (3.3%)
+ Ilias Apalodimas 6 (2.8%)
+ Dario Binacchi 5 (2.3%)
+ Bin Meng 5 (2.3%)
+ Frieder Schrempf 5 (2.3%)
+ Marc Kleine-Budde 5 (2.3%)
+ Alexandre Torgue 5 (2.3%)
+ Mattijs Korpershoek 4 (1.9%)
+ Ashok Reddy Soma 4 (1.9%)
+ Patrice Chotard 4 (1.9%)
+ Marek Vasut 4 (1.9%)
+ Simon Glass 4 (1.9%)
+ Tom Rini 3 (1.4%)
+ Oleksandr Suvorov 3 (1.4%)
+ Venkatesh Yadav Abbarapu 3 (1.4%)
+ Jonas Karlman 3 (1.4%)
+ Andre Przywara 3 (1.4%)
+ Miquel Raynal 2 (0.9%)
+ Francesco Dolcini 2 (0.9%)
+ Rui Miguel Silva 2 (0.9%)
+ Qi Feng 2 (0.9%)
+ Suniel Mahesh 2 (0.9%)
+ Siddharth Vadapalli 2 (0.9%)
+ Neha Malcom Francis 2 (0.9%)
+ Alexey Romanov 2 (0.9%)
+ Sébastien Szymanski 2 (0.9%)
+ Roger Quadros 2 (0.9%)
+ Nishanth Menon 2 (0.9%)
+ Andy Shevchenko 1 (0.5%)
+ Abdellatif El Khlifi 1 (0.5%)
+ Jon Mason 1 (0.5%)
+ Martin Kurbanov 1 (0.5%)
+ Jakub Klama 1 (0.5%)
+ Marcin Jabrzyk 1 (0.5%)
+ Valerio 'ftp21' Mancini 1 (0.5%)
+ Lee Jones 1 (0.5%)
+ Geert Uytterhoeven 1 (0.5%)
+ Hiago De Franco 1 (0.5%)
+ Patrick Delaunay 1 (0.5%)
+ Elaine Zhang 1 (0.5%)
+ Fabio Estevam 1 (0.5%)
+ Manorit Chawdhry 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Developers with the most reviews (total 990)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 251 (25.4%)
+ Kever Yang 67 (6.8%)
+ Tom Rini 66 (6.7%)
+ Nishanth Menon 55 (5.6%)
+ Marek Vasut 50 (5.1%)
+ Mattijs Korpershoek 47 (4.7%)
+ Bin Meng 38 (3.8%)
+ Patrice Chotard 33 (3.3%)
+ Fabio Estevam 33 (3.3%)
+ Leo Yu-Chi Liang 33 (3.3%)
+ Heinrich Schuchardt 24 (2.4%)
+ Stefan Roese 23 (2.3%)
+ Patrick Delaunay 20 (2.0%)
+ Biju Das 17 (1.7%)
+ Neil Armstrong 16 (1.6%)
+ Lad Prabhakar 16 (1.6%)
+ Sean Anderson 16 (1.6%)
+ Ilias Apalodimas 15 (1.5%)
+ Etienne Carriere 14 (1.4%)
+ Jaehoon Chung 12 (1.2%)
+ Andre Przywara 11 (1.1%)
+ Neha Malcom Francis 9 (0.9%)
+ Ramon Fried 9 (0.9%)
+ Bhupesh Sharma 7 (0.7%)
+ Jernej Skrabec 6 (0.6%)
+ Yannic Moog 6 (0.6%)
+ Samuel Holland 6 (0.6%)
+ Heiko Schocher 5 (0.5%)
+ Sam Edwards 5 (0.5%)
+ Manorit Chawdhry 4 (0.4%)
+ Mark Kettenis 4 (0.4%)
+ Peng Fan 3 (0.3%)
+ Roger Quadros 3 (0.3%)
+ Yoshihiro Shimoda 3 (0.3%)
+ Heiko Stuebner 3 (0.3%)
+ Michael Trimarchi 3 (0.3%)
+ Marcel Ziswiler 3 (0.3%)
+ Paul Barker 3 (0.3%)
+ Frieder Schrempf 2 (0.2%)
+ Weizhao Ouyang 2 (0.2%)
+ Xavier Drudis Ferran 2 (0.2%)
+ Angelo Dureghello 2 (0.2%)
+ Christopher Obbard 2 (0.2%)
+ Mike Frysinger 2 (0.2%)
+ Dhruva Gole 2 (0.2%)
+ Qu Wenruo 2 (0.2%)
+ Linus Walleij 2 (0.2%)
+ Svyatoslav Ryhel 2 (0.2%)
+ Jonas Karlman 1 (0.1%)
+ Andrew Davis 1 (0.1%)
+ Nikhil M Jain 1 (0.1%)
+ Eric Curtin 1 (0.1%)
+ Neal Gompa 1 (0.1%)
+ Dragan Simic 1 (0.1%)
+ Daniel Schwierzeck 1 (0.1%)
+ Ryan Chen 1 (0.1%)
+ Lukasz Majewski 1 (0.1%)
+ Rick Chen 1 (0.1%)
+ Anup Patel 1 (0.1%)
+ Kristian Amlie 1 (0.1%)
+ Sebastian Reichel 1 (0.1%)
+ Martyn Welch 1 (0.1%)
+ Grzegorz Szymaszek 1 (0.1%)
+ Raphaël Gallais-Pou 1 (0.1%)
+ Wei Liang Lim 1 (0.1%)
+ Adam Ford 1 (0.1%)
+ Alexander Graf 1 (0.1%)
+ Devarsh Thakkar 1 (0.1%)
+ Michal Suchánek 1 (0.1%)
+ Rafał Miłecki 1 (0.1%)
+ Weijie Gao 1 (0.1%)
+ Jan Kiszka 1 (0.1%)
+ Sam Protsenko 1 (0.1%)
+ Ye Li 1 (0.1%)
+ Marek Behún 1 (0.1%)
+ Bryan Brattlof 1 (0.1%)
+ Mikhail Kalashnikov 1 (0.1%)
+ Randolph 1 (0.1%)
+ Tony Dinh 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most test credits (total 131)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Tom Rini 29 (22.1%)
+ Mattijs Korpershoek 22 (16.8%)
+ Joao Paulo Goncalves 8 (6.1%)
+ Bhupesh Sharma 6 (4.6%)
+ Yannic Moog 6 (4.6%)
+ Samuel Holland 5 (3.8%)
+ Svyatoslav Ryhel 5 (3.8%)
+ Simon Glass 4 (3.1%)
+ Nishanth Menon 4 (3.1%)
+ Ivan T.Ivanov 4 (3.1%)
+ Milan P. Stanić 4 (3.1%)
+ Thuan Nguyen Hong 3 (2.3%)
+ Marek Vasut 2 (1.5%)
+ Ilias Apalodimas 2 (1.5%)
+ Sam Edwards 2 (1.5%)
+ Michal Simek 2 (1.5%)
+ Andreas Westman Dorcsak 2 (1.5%)
+ Sean Anderson 1 (0.8%)
+ Jaehoon Chung 1 (0.8%)
+ Neha Malcom Francis 1 (0.8%)
+ Marcel Ziswiler 1 (0.8%)
+ Paul Barker 1 (0.8%)
+ Christopher Obbard 1 (0.8%)
+ Mikhail Kalashnikov 1 (0.8%)
+ Andy Shevchenko 1 (0.8%)
+ Stephen Graf 1 (0.8%)
+ Bob McChesney 1 (0.8%)
+ Piotr Oniszczuk 1 (0.8%)
+ Maksim Kurnosenko 1 (0.8%)
+ Henrik Grimler 1 (0.8%)
+ Bao Cheng Su 1 (0.8%)
+ Kevin Amadiva 1 (0.8%)
+ Chris Paterson 1 (0.8%)
+ Masahisa Kojima 1 (0.8%)
+ Maksim Kiselev 1 (0.8%)
+ Shantur Rathore 1 (0.8%)
+ Chanho Park 1 (0.8%)
+ FUKAUMI Naoki 1 (0.8%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 131)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Bryan Brattlof 26 (19.8%)
+ Nishanth Menon 18 (13.7%)
+ Marek Vasut 17 (13.0%)
+ Andre Przywara 10 (7.6%)
+ Joao Marcos Costa 8 (6.1%)
+ Svyatoslav Ryhel 7 (5.3%)
+ Simon Glass 6 (4.6%)
+ Teresa Remmet 6 (4.6%)
+ Roger Quadros 5 (3.8%)
+ Jonas Karlman 5 (3.8%)
+ Heinrich Schuchardt 4 (3.1%)
+ Paul Barker 3 (2.3%)
+ Tom Rini 2 (1.5%)
+ Sam Edwards 2 (1.5%)
+ Andrew Davis 2 (1.5%)
+ Ilias Apalodimas 1 (0.8%)
+ Sean Anderson 1 (0.8%)
+ Mikhail Kalashnikov 1 (0.8%)
+ Jan Kiszka 1 (0.8%)
+ Lukas Funke 1 (0.8%)
+ Guillaume La Roque 1 (0.8%)
+ Wojciech Nizinski 1 (0.8%)
+ Massimo Pegorer 1 (0.8%)
+ Eddie James 1 (0.8%)
+ Robert Nelson 1 (0.8%)
+ ==================================== =====
+
+
+.. table:: Developers with the most report credits (total 25)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Nishanth Menon 3 (12.0%)
+ Tom Rini 2 (8.0%)
+ Sean Anderson 2 (8.0%)
+ Date Huang 2 (8.0%)
+ Vincent Stehlé 2 (8.0%)
+ Andre Przywara 1 (4.0%)
+ Roger Quadros 1 (4.0%)
+ Jonas Karlman 1 (4.0%)
+ Heinrich Schuchardt 1 (4.0%)
+ Mikhail Kalashnikov 1 (4.0%)
+ Bao Cheng Su 1 (4.0%)
+ Fabio Estevam 1 (4.0%)
+ Weizhao Ouyang 1 (4.0%)
+ Martin Liška 1 (4.0%)
+ Peter Hoyes 1 (4.0%)
+ Madushan Nishantha 1 (4.0%)
+ Ivan Ivanov 1 (4.0%)
+ Jayantajit Gogoi 1 (4.0%)
+ Suman Anna 1 (4.0%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most report credits (total 25)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 6 (24.0%)
+ Nishanth Menon 3 (12.0%)
+ Marek Vasut 3 (12.0%)
+ Andre Przywara 2 (8.0%)
+ Heinrich Schuchardt 2 (8.0%)
+ Siddharth Vadapalli 2 (8.0%)
+ Roger Quadros 1 (4.0%)
+ Jan Kiszka 1 (4.0%)
+ Massimo Pegorer 1 (4.0%)
+ Samuel Holland 1 (4.0%)
+ Jonathan Corbet 1 (4.0%)
+ Rasmus Villemoes 1 (4.0%)
+ Udit Kumar 1 (4.0%)
+ ==================================== =====
+
+
+.. table:: Top changeset contributors by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 515 (32.9%)
+ Google LLC 274 (17.5%)
+ Renesas Electronics 177 (11.3%)
+ AMD 114 (7.3%)
+ Texas Instruments 100 (6.4%)
+ Linaro 95 (6.1%)
+ DENX Software Engineering 72 (4.6%)
+ Konsulko Group 50 (3.2%)
+ ARM 39 (2.5%)
+ Amarula Solutions 20 (1.3%)
+ Samsung 19 (1.2%)
+ ST Microelectronics 18 (1.2%)
+ Toradex 17 (1.1%)
+ NXP 10 (0.6%)
+ Siemens 8 (0.5%)
+ Phytec 7 (0.4%)
+ Rockchip 7 (0.4%)
+ BayLibre SAS 6 (0.4%)
+ IBM 6 (0.4%)
+ Bosch 3 (0.2%)
+ Weidmüller Interface GmbH & Co. KG 3 (0.2%)
+ Bootlin 1 (0.1%)
+ Collabora Ltd. 1 (0.1%)
+ Intel 1 (0.1%)
+ LWN.net 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Top lines changed by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 43854 (37.2%)
+ Texas Instruments 12605 (10.7%)
+ Renesas Electronics 11595 (9.8%)
+ Google LLC 11497 (9.8%)
+ AMD 8291 (7.0%)
+ NXP 6236 (5.3%)
+ Linaro 5994 (5.1%)
+ ARM 4545 (3.9%)
+ Amarula Solutions 3655 (3.1%)
+ Konsulko Group 2320 (2.0%)
+ DENX Software Engineering 2239 (1.9%)
+ IBM 1481 (1.3%)
+ ST Microelectronics 1114 (0.9%)
+ Samsung 882 (0.7%)
+ Phytec 782 (0.7%)
+ Toradex 282 (0.2%)
+ Siemens 190 (0.2%)
+ Rockchip 171 (0.1%)
+ Weidmüller Interface GmbH & Co. KG 99 (0.1%)
+ BayLibre SAS 25 (0.0%)
+ Intel 20 (0.0%)
+ Bosch 6 (0.0%)
+ Collabora Ltd. 6 (0.0%)
+ LWN.net 4 (0.0%)
+ Bootlin 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Employers with the most signoffs (total 215)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ AMD 62 (28.8%)
+ Linaro 37 (17.2%)
+ (Unknown) 28 (13.0%)
+ Samsung 13 (6.0%)
+ ST Microelectronics 10 (4.7%)
+ Canonical 9 (4.2%)
+ Texas Instruments 7 (3.3%)
+ NXP 7 (3.3%)
+ ARM 7 (3.3%)
+ Amarula Solutions 7 (3.3%)
+ Pengutronix 5 (2.3%)
+ Google LLC 4 (1.9%)
+ DENX Software Engineering 4 (1.9%)
+ BayLibre SAS 4 (1.9%)
+ Konsulko Group 3 (1.4%)
+ Toradex 3 (1.4%)
+ Bootlin 2 (0.9%)
+ Renesas Electronics 1 (0.5%)
+ Rockchip 1 (0.5%)
+ Intel 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Employers with the most hackers (total 192)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 104 (54.2%)
+ AMD 14 (7.3%)
+ Texas Instruments 12 (6.2%)
+ Linaro 10 (5.2%)
+ DENX Software Engineering 6 (3.1%)
+ NXP 5 (2.6%)
+ Toradex 5 (2.6%)
+ ST Microelectronics 4 (2.1%)
+ ARM 4 (2.1%)
+ Rockchip 4 (2.1%)
+ Renesas Electronics 3 (1.6%)
+ Samsung 2 (1.0%)
+ Amarula Solutions 2 (1.0%)
+ Google LLC 2 (1.0%)
+ BayLibre SAS 2 (1.0%)
+ Phytec 2 (1.0%)
+ Siemens 2 (1.0%)
+ Weidmüller Interface GmbH & Co. KG 2 (1.0%)
+ Konsulko Group 1 (0.5%)
+ Bootlin 1 (0.5%)
+ Intel 1 (0.5%)
+ IBM 1 (0.5%)
+ Bosch 1 (0.5%)
+ Collabora Ltd. 1 (0.5%)
+ LWN.net 1 (0.5%)
+ ==================================== =====
As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot
command 'efidebug' can be used to set the variables.
+UEFI HTTP Boot
+~~~~~~~~~~~~~~
+
+HTTP Boot provides the capability for system deployment and configuration
+over the network. HTTP Boot can be activated by specifying::
+
+ CONFIG_EFI_HTTP_BOOT
+
+Enabling that will automatically select::
+
+ CONFIG_CMD_DNS
+ CONFIG_CMD_WGET
+ CONFIG_BLKMAP
+
+Set up the load option specifying the target URI::
+
+ efidebug boot add -u 1 netinst http://foo/bar
+
+When this load option is selected as boot selection, resolve the
+host ip address by dns, then download the file with wget.
+If the downloaded file extension is .iso or .img file, efibootmgr tries to
+mount the image and boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
+If the downloaded file is PE-COFF image, load the downloaded file and
+start it.
+
+The current implementation tries to resolve the IP address as a host name.
+If the uri is like "http://192.168.1.1/foobar",
+the dns process tries to resolve the host "192.168.1.1" and it will
+end up with "host not found".
+
+We need to preset the "httpserverip" environment variable to proceed the wget::
+
+ setenv httpserverip 192.168.1.1
+
Executing the built in hello world application
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--- /dev/null
+LEDs connected to TI LP5562 controller
+
+This driver works with a TI LP5562 4-channel LED controller.
+CONFIG_LED_BLINK is supported using the controller engines. However
+there are only 3 engines available for the 4 channels. This means
+that the blue and white channels share the same engine. When both
+blue and white LEDs are set to blink, they will share the same blink
+rate. Changing the blink rate of the blue LED will affect the white
+LED and vice-versa. Manual on/off is handled independently for all 4
+channels.
+
+Required properties:
+ - compatible : should be "ti,lp5562".
+ - #address-cells : must be 1.
+ - #size-cells : must be 0.
+ - reg : LP5562 LED controller I2C address.
+
+Optional properties:
+ - enable-gpios : Enable GPIO
+ - clock-mode : u8, configures the clock mode:
+ - 0 # automode
+ - 1 # internal
+ - 2 # external
+
+Each LED is represented as a sub-node of the ti,lp5562 device.
+
+LED sub-node required properties:
+ - reg : Zero-based channel identifier:
+ - 0 red
+ - 1 green
+ - 2 blue
+ - 3 white
+
+LED sub-node optional properties:
+ - chan-name : name of LED
+ - max-cur : LED current at max brightness in 100uA steps (0x00 - 0xFF)
+ Default : 100 (10 mA)
+
+Example:
+ leds0: lp5562@30 {
+ compatible = "ti,lp5562";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ reg = <0x30>;
+ clock-mode = /bits/8 <1>;
+
+ led@0 {
+ reg = <0>;
+ chan-name = "red";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ led@1 {
+ reg = <1>;
+ chan-name = "green";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ led@2 {
+ reg = <2>;
+ chan-name = "blue";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ };
+++ /dev/null
-Texas Instruments K3 ESM Binding
-======================
-
-ESM (Error Signaling Module) is an IP block on TI K3 devices that allows
-handling of safety events somewhat similar to what interrupt controller
-would do. The safety signals have their separate paths within the SoC,
-and they are handled by the ESM, which routes them to the proper
-destination, which can be system reset, interrupt controller, etc. In
-the simplest configuration the signals are just routed to reset the
-SoC.
-
-Required properties :
-- compatible : "ti,j721e-esm"
-- ti,esm-pins : integer array of esm events IDs to route to external event
- pin which can be used to reset the SoC. The array can
- have arbitrary amount of event IDs listed on it.
-
-Example
-=======
-
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <344>, <345>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 ESM
+
+maintainers:
+ - Neha Malcom Francis <n-francis@ti.com>
+
+description:
+ The ESM (Error Signaling Module) is an IP block on TI K3 devices
+ that allows handling of safety events somewhat similar to what interrupt
+ controller would do. The safety signals have their separate paths within
+ the SoC, and they are handled by the ESM, which routes them to the proper
+ destination, which can be system reset, interrupt controller, etc. In the
+ simplest configuration the signals are just routed to reset the SoC.
+
+properties:
+ compatible:
+ const: ti,j721e-esm
+
+ reg:
+ maxItems: 1
+
+ ti,esm-pins:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ integer array of ESM interrupt pins to route to external event pin
+ which can be used to reset the SoC.
+ minItems: 1
+ maxItems: 255
+
+required:
+ - compatible
+ - reg
+ - ti,esm-pins
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x700000 0x0 0x1000>;
+ ti,esm-pins = <344>, <345>;
+ };
+ };
--- /dev/null
+Sandbox NAND
+============
+
+The sandbox NAND controller emulates a NAND controller and attached devices.
+
+Required properties:
+- compatible: "sandbox,nand"
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Any number of child nodes may be present, each representing a NAND device:
+
+Required Properties:
+- reg: The chip-select(s) to use. Only single-die devices are supported for now.
+- sandbox,id: An array of bytes to be reported by the READID (0x90) command
+- sandbox,erasesize: The block size (erase size) of the device, in bytes. Must
+ be a power-of-two multiple of the page size.
+- sandbox,oobsize: The size of the OOB area per page, in bytes.
+- sandbox,pagesize: The page size (write size) of the device, in bytes. Must be
+ a power of two.
+- sandbox,pages: The total number of pages in the device.
+- sandbox,err-count: Number of bit errors to inject per step.
+- sandbox,err-step-size: Size of the step to use when injecting errors, in
+ bytes. Must evenly divide the page size.
+
+Optional properties:
+- sandbox,onfi: The complete ONFI parameter page, including the CRC. Should be
+ exactly 256 bytes.
+- Any common NAND chip properties as documented by Linux's
+ Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml
+
+To match U-Boot's error correction capabilities, errors are only injected into
+the data area and the ECC codes. Other data in the OOB area is never corrupted.
+Generally, sandbox,err-step-size should be the same as the ECC step size, and
+sandbox,err-count should be less than the number of correctable bit errors (the
+ECC strength).
+
+Example
+-------
+
+nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sandbox,nand";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ sandbox,id = [00 e3];
+ sandbox,erasesize = <(8 * 1024)>;
+ sandbox,oobsize = <16>;
+ sandbox,pagesize = <512>;
+ sandbox,pages = <0x2000>;
+ sandbox,err-count = <1>;
+ sandbox,err-step-size = <512>;
+ };
+};
matters, since by then the system boots in the OS and U-Boot is no-longer
running. `bootflow scan -b` is a quick way to boot the first available OS.
A valid bootflow is one that made it all the way to the `loaded` state.
+ Note that if `-m` is provided as well, booting is delayed until the user
+ selects a bootflow.
-e
Used with -l to also show errors for each bootflow. The shows detailed error
priority or label is tried, to see if more bootdevs can be discovered, but
this flag disables that process.
+-m
+ Show a menu of available bootflows for the user to select. When used with
+ -b it then boots the one that was selected, if any.
The optional argument specifies a particular bootdev to scan. This can either be
the name of a bootdev or its sequence number (both shown with `bootdev list`).
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+cli command
+===========
+
+Synopis
+-------
+
+::
+
+ cli get
+ cli set cli_flavor
+
+Description
+-----------
+
+The cli command permits getting and changing the current parser at runtime.
+
+cli get
+~~~~~~~
+
+It shows the current value of the parser used by the CLI.
+
+cli set
+~~~~~~~
+
+It permits setting the value of the parser used by the CLI.
+
+Possible values are old and modern.
+Note that, to use a specific parser its code should have been compiled, that
+is to say you need to enable the corresponding CONFIG_HUSH*.
+Otherwise, an error message is printed.
+
+Examples
+--------
+
+Get the current parser::
+
+ => cli get
+ old
+
+Change the current parser::
+
+ => cli get
+ old
+ => cli set modern
+ => cli get
+ modern
+ => cli set old
+ => cli get
+ old
+
+Trying to set the current parser to an unknown value::
+
+ => cli set foo
+ Bad value for parser name: foo
+ cli - cli
+
+ Usage:
+ cli get - print current cli
+ set - set the current cli, possible values are: old, modern
+
+Trying to set the current parser to a correct value but its code was not
+compiled::
+
+ => cli get
+ modern
+ => cli set old
+ Want to set current parser to old, but its code was not compiled!
+
+Return value
+------------
+
+The return value $? indicates whether the command succeeded.
With verify=no incorrect hashes, signatures, or check sums don't stop the
extraction. But correct hashes are still indicated in the output
-(here: md5, sha1).
+(here: sha256, sha512).
.. code-block:: console
=> setenv verify no
=> imxtract $loadaddr kernel-1 $kernel_addr_r
## Copying 'kernel-1' subimage from FIT image at 40200000 ...
- md5+ sha1+ Loading part 0 ... OK
+ sha256+ sha512+ Loading part 0 ... OK
=>
With verify=yes incorrect hashes, signatures, or check sums stop the extraction.
=> setenv verify yes
=> imxtract $loadaddr kernel-1 $kernel_addr_r
## Copying 'kernel-1' subimage from FIT image at 40200000 ...
- md5 error!
+ sha256 error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
=>
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+:
+
+scmi command
+============
+
+Synopsis
+--------
+
+::
+
+ scmi info
+ scmi perm_dev <agent id> <device id> <flags>
+ scmi perm_proto <agent id> <device id> <protocol id> <flags>
+ scmi reset <agent id> <flags>
+
+Description
+-----------
+
+Arm System Control and Management Interface (SCMI hereafter) is a set of
+standardised interfaces to manage system resources, like clocks, power
+domains, pin controls, reset and so on, in a system-wide manner.
+
+An entity which provides those services is called a SCMI firmware (or
+SCMI server if you like) may be placed/implemented by EL3 software or
+by a dedicated system control processor (SCP) or else.
+
+A user of SCMI interfaces, including U-Boot, is called a SCMI agent and
+may issues commands, which are defined in each protocol for specific system
+resources, to SCMI server via a communication channel, called a transport.
+Those interfaces are independent from the server's implementation thanks to
+a transport layer.
+
+For more details, see the `SCMI specification`_.
+
+While most of system resources managed under SCMI protocols are implemented
+and handled as standard U-Boot devices, for example clk_scmi, scmi command
+provides additional management functionality against SCMI server.
+
+scmi info
+~~~~~~~~~
+ Show base information about SCMI server and supported protocols
+
+scmi perm_dev
+~~~~~~~~~~~~~
+ Allow or deny access permission to the device
+
+scmi perm_proto
+~~~~~~~~~~~~~~~
+ Allow or deny access to the protocol on the device
+
+scmi reset
+~~~~~~~~~~
+ Reset the already-configured permissions against the device
+
+Parameters are used as follows:
+
+<agent id>
+ SCMI Agent ID, hex value
+
+<device id>
+ SCMI Device ID, hex value
+
+ Please note that what a device means is not defined
+ in the specification.
+
+<protocol id>
+ SCMI Protocol ID, hex value
+
+ It must not be 0x10 (base protocol)
+
+<flags>
+ Flags to control the action, hex value
+
+ 0 to deny, 1 to allow. The other values are reserved and allowed
+ values may depend on the implemented version of SCMI server in
+ the future. See SCMI specification for more details.
+
+Example
+-------
+
+Obtain basic information about SCMI server:
+
+::
+
+ => scmi info
+ SCMI device: scmi
+ protocol version: 0x20000
+ # of agents: 3
+ 0: platform
+ > 1: OSPM
+ 2: PSCI
+ # of protocols: 4
+ Power domain management
+ Performance domain management
+ Clock management
+ Sensor management
+ vendor: Linaro
+ sub vendor: PMWG
+ impl version: 0x20b0000
+
+Ask for access permission to device#0:
+
+::
+
+ => scmi perm_dev 1 0 1
+
+Reset configurations with all access permission settings retained:
+
+::
+
+ => scmi reset 1 0
+
+Configuration
+-------------
+
+The scmi command is only available if CONFIG_CMD_SCMI=y.
+Default n because this command is mainly for debug purpose.
+
+Return value
+------------
+
+The return value ($?) is set to 0 if the operation succeeded,
+1 if the operation failed or -1 if the operation failed due to
+a syntax error.
+
+.. _`SCMI specification`: https://developer.arm.com/documentation/den0056/e/?lang=en
The wget command is used to download a file from an HTTP server.
wget command will use HTTP over TCP to download files from an HTTP server.
-Currently it can only download image from an HTTP server hosted on port 80.
+By default the destination port is 80 and the source port is pseudo-random.
+The environment variable *httpdstp* can be used to set the destination port.
address
memory address for the data downloaded
anything other than "no", U-Boot does go through all
available network interfaces.
+httpdstp
+ If this is set, the value is used for HTTP's TCP
+ destination port instead of the default port 80.
+
netretry
When set to "no" each network operation will
either succeed or fail without retrying.
load = <0x80008000>;
entry = <0x80008000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
fdt-1 {
arch = "arm";
compression = "none";
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
kernel = "kernel";
fdt = "fdt-1";
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
};
OS: Linux
Load Address: 0x80008000
Entry Point: 0x80008000
- Hash algo: sha1
- Hash value: c94364646427e10f423837e559898ef02c97b988
+ Hash algo: sha256
+ Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1
Image 1 (fdt-1)
Description: beaglebone-black
Created: Sun Jun 1 12:50:30 2014
Compression: uncompressed
Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
Architecture: ARM
- Hash algo: sha1
- Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Hash algo: sha256
+ Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd
Default Configuration: 'conf-1'
Configuration 0 (conf-1)
Description: unavailable
which results in::
- Verifying Hash Integrity ... sha1,rsa2048:dev+
+ Verifying Hash Integrity ... sha256,rsa2048:dev+
## Loading kernel from FIT Image at 7fc6ee469000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ...
- sha1,rsa2048:dev+
+ sha256,rsa2048:dev+
OK
Trying 'kernel' kernel subimage
OS: Linux
Load Address: 0x80008000
Entry Point: 0x80008000
- Hash algo: sha1
- Hash value: c94364646427e10f423837e559898ef02c97b988
+ Hash algo: sha256
+ Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1
Verifying Hash Integrity ...
- sha1+
+ sha256+
OK
Unimplemented compression type 4
Compression: uncompressed
Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
Architecture: ARM
- Hash algo: sha1
- Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Hash algo: sha256
+ Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd
Verifying Hash Integrity ...
- sha1+
+ sha256+
OK
Loading Flat Device Tree ... OK
Signature check OK
-At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key
-of size 2048 bits using SHA1 as the hash algorithm. The key name checked was
+At the top, you see "sha256,rsa2048:dev+". This means that it checked an RSA key
+of size 2048 bits using SHA256 as the hash algorithm. The key name checked was
'dev' and the '+' means that it verified. If it showed '-' that would be bad.
Once the configuration is verified it is then possible to rely on the hashes
in each image referenced by that configuration. So fit_check_sign goes on to
load each of the images. We have a kernel and an FDT but no ramkdisk. In each
-case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1
+case fit_check_sign checks the hash and prints sha256+ meaning that the SHA256
hash verified. This means that none of the images has been tampered with.
There is a test in test/vboot which uses U-Boot's sandbox build to verify that
and extends for about 7MB. Try changing a byte at 0x2000 (say) and run
fit_check_sign again. You should see something like::
- Verifying Hash Integrity ... sha1,rsa2048:dev+
+ Verifying Hash Integrity ... sha256,rsa2048:dev+
## Loading kernel from FIT Image at 7f5a39571000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ...
- sha1,rsa2048:dev+
+ sha256,rsa2048:dev+
OK
Trying 'kernel' kernel subimage
OS: Linux
Load Address: 0x80008000
Entry Point: 0x80008000
- Hash algo: sha1
- Hash value: c94364646427e10f423837e559898ef02c97b988
+ Hash algo: sha256
+ Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1
Verifying Hash Integrity ...
- sha1 error
+ sha256 error
Bad hash value for 'hash-1' hash node in 'kernel' image node
Bad Data Hash
Compression: uncompressed
Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
Architecture: ARM
- Hash algo: sha1
- Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Hash algo: sha256
+ Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd
Verifying Hash Integrity ...
- sha1+
+ sha256+
OK
Loading Flat Device Tree ... OK
the hash::
fdtget -tx image.fit /images/kernel/hash-1 value
- c9436464 6427e10f 423837e5 59898ef0 2c97b988
- fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
+ 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c1
+ fdtput -tx image.fit /images/kernel/hash-1 value 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c8
Now check it again::
$UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
- Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+ Verifying Hash Integrity ... sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
rsa_verify_with_keynode: RSA failed to verify: -13
-
Failed to verify required signature 'key-dev'
fdtput -p image.fit /configurations/conf-1/signature-1 value fred
$UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
Verifying Hash Integrity ... -
- sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+ sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
rsa_verify_with_keynode: RSA failed to verify: -13
-
Failed to verify required signature 'key-dev'
U-Boot# bootm 82000000
## Loading kernel from FIT Image at 82000000 ...
Using 'conf-1' configuration
- Verifying Hash Integrity ... sha1,rsa2048:dev+ OK
+ Verifying Hash Integrity ... sha256,rsa2048:dev+ OK
Trying 'kernel' kernel subimage
Description: unavailable
Created: 2014-06-01 19:32:54 UTC
OS: Linux
Load Address: 0x80008000
Entry Point: 0x80008000
- Hash algo: sha1
- Hash value: c94364646427e10f423837e559898ef02c97b988
- Verifying Hash Integrity ... sha1+ OK
+ Hash algo: sha256
+ Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1
+ Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 82000000 ...
Using 'conf-1' configuration
Trying 'fdt-1' fdt subimage
Data Start: 0x8276e2ec
Data Size: 31547 Bytes = 30.8 KiB
Architecture: ARM
- Hash algo: sha1
- Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
- Verifying Hash Integrity ... sha1+ OK
+ Hash algo: sha256
+ Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd
+ Verifying Hash Integrity ... sha256+ OK
Booting using the fdt blob at 0x8276e2ec
Uncompressing Kernel Image ... OK
Loading Device Tree to 8fff5000, end 8ffffb3a ... OK
The new uImage format allows more flexibility in handling images of various
types (kernel, ramdisk, etc.), it also enhances integrity protection of images
-with sha1 and md5 checksums.
+with cryptographic checksums.
Two auxiliary tools are needed on the development host system in order to
create an uImage in the new format: mkimage and dtc, although only one
load = <0x8 0x8000000>;
entry = <0x8 0x8000000>;
hash {
- algo = "md5";
+ algo = "sha256";
};
};
atf {
load = <0xfffea000>;
entry = <0xfffea000>;
hash {
- algo = "md5";
+ algo = "sha256";
};
};
fdt_1 {
compression = "none";
load = <0x100000>;
hash {
- algo = "md5";
+ algo = "sha256";
};
};
};
Entry Point: 0x00000000
Hash algo: crc32
Hash value: 2ae2bb40
- Hash algo: sha1
- Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4
+ Hash algo: sha256
+ Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f
Default Configuration: 'config-1'
Configuration 0 (config-1)
Description: Boot Linux kernel
Entry Point: 0x00000000
Hash algo: crc32
Hash value: 2ae2bb40
- Hash algo: sha1
- Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4
+ Hash algo: sha256
+ Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f
Default Configuration: 'config-1'
Configuration 0 (config-1)
Description: Boot Linux kernel
Entry Point: 0x00000000
Hash algo: crc32
Hash value: 2ae2bb40
- Hash algo: sha1
- Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4
+ Hash algo: sha256
+ Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f
Verifying Hash Integrity ... crc32+ sha1+ OK
Uncompressing Kernel Image ... OK
Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
Entry Point: 0x00000000
Hash algo: crc32
Hash value: 2c0cc807
- Hash algo: sha1
- Hash value: 264b59935470e42c418744f83935d44cdf59a3bb
+ Hash algo: sha256
+ Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c
Image 1 (fdt-1)
Description: Flattened Device Tree blob
Type: Flat Device Tree
Architecture: PowerPC
Hash algo: crc32
Hash value: 0d655d71
- Hash algo: sha1
- Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def
+ Hash algo: sha256
+ Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214
Default Configuration: 'conf-1'
Configuration 0 (conf-1)
Description: Boot Linux kernel with FDT blob
Entry Point: 0x00000000
Hash algo: crc32
Hash value: 2c0cc807
- Hash algo: sha1
- Hash value: 264b59935470e42c418744f83935d44cdf59a3bb
+ Hash algo: sha256
+ Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c
Image 1 (fdt-1)
Description: Flattened Device Tree blob
Type: Flat Device Tree
Architecture: PowerPC
Hash algo: crc32
Hash value: 0d655d71
- Hash algo: sha1
- Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def
+ Hash algo: sha256
+ Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214
Default Configuration: 'conf-1'
Configuration 0 (conf-1)
Description: Boot Linux kernel with FDT blob
Hash algo: crc32
Hash value: 2c0cc807
Hash algo: sha1
- Hash value: 264b59935470e42c418744f83935d44cdf59a3bb
+ Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c
Verifying Hash Integrity ... crc32+ sha1+ OK
Uncompressing Kernel Image ... OK
## Flattened Device Tree from FIT Image at 00900000
Hash algo: crc32
Hash value: 0d655d71
Hash algo: sha1
- Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def
+ Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214
Verifying Hash Integrity ... crc32+ sha1+ OK
Booting using the fdt blob at 0xa0abdc
Loading Device Tree to 007fc000, end 007fffff ... OK
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
load = <0x01000000>;
entry = <0x00000000>;
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
load = <0x00090000>;
entry = <0x00090000>;
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
fdt-1 {
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
fdt@1 {
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
fdt@2 {
algo = "crc32";
};
hash-2 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
compression = "none";
load = <0x10000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
load = <0x30000000>;
compatible = "u-boot,fpga-legacy"
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
load = <0x8000>;
entry = <0x8000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
};
load = <0xa0000000>;
entry = <0xa0000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
compression = "none";
load = <0xb0000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
compression = "none";
load = <0xb0400000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
load = <0xa0000000>;
entry = <0xa0000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
};
load = <00000000>;
entry = <00000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
hash-2 {
- algo = "sha1";
+ algo = "sha512";
};
};
load = <00000000>;
entry = <00000000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
load = <00000000>;
entry = <00000000>;
hash-1 {
- algo = "md5";
+ algo = "sha256";
};
};
load = <00000000>;
entry = <00000000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
compression = "none";
load = <00700000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
entry = <0x8>;
kernel-version = <1>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
fdt-1 {
compression = "none";
fdt-version = <1>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
kernel = "kernel";
fdt = "fdt-1";
signature {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
};
entry = <0x8>;
kernel-version = <1>;
signature {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
key-name-hint = "dev";
};
};
compression = "none";
fdt-version = <1>;
signature {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
key-name-hint = "dev";
};
};
properties are:
algo
- Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256")
+ Algorithm name (e.g. "sha256,rsa2048" or "sha512,ecdsa256")
Optional properties are:
kernel-1 {
data = <data for kernel1>
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...kernel signature 1...>
};
};
kernel-2 {
data = <data for kernel2>
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...kernel signature 2...>
};
};
fdt-1 {
data = <data for fdt1>;
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...fdt signature 1...>
};
};
fdt-2 {
data = <data for fdt2>;
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...fdt signature 2...>
};
};
kernel-1 {
data = <data for kernel1>
hash-1 {
- algo = "sha1";
+ algo = "sha256";
value = <...kernel hash 1...>
};
};
kernel-2 {
data = <data for kernel2>
hash-1 {
- algo = "sha1";
+ algo = "sha256";
value = <...kernel hash 2...>
};
};
fdt-1 {
data = <data for fdt1>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
value = <...fdt hash 1...>
};
};
fdt-2 {
data = <data for fdt2>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
value = <...fdt hash 2...>
};
};
kernel = "kernel-1";
fdt = "fdt-1";
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...conf 1 signature...>;
};
};
kernel = "kernel-2";
fdt = "fdt-2";
signature-1 {
- algo = "sha1,rsa2048";
+ algo = "sha256,rsa2048";
value = <...conf 1 signature...>;
};
};
Sign the fitImage with the hardware key::
$ ./tools/mkimage -F -k \
- "model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \
+ "pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \
-K u-boot.dtb -N pkcs11 -r fitImage
type = "firmware";
load = <FF700000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
update-2 {
type = "firmware";
load = <FF8E0000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
type = "firmware";
load = <FFAC0000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
type = "firmware";
load = <0xFFFC0000>;
hash-1 {
- algo = "sha1";
+ algo = "sha256";
};
};
};
OS: Linux
Load Address: 0x01000000
Entry Point: 0x00000000
- Hash algo: sha1
- Hash value: 446b5163ebfe0fb6ee20cbb7a8501b263cd92392
+ Hash algo: sha256
+ Hash value: 4bbf49981ade163ed089f8525236fedfe44508e9b02a21a48294a96a1518107b
Image 1 (setup)
Description: Linux setup.bin
Created: Tue Oct 7 10:57:24 2014
Type: x86 setup.bin
Compression: uncompressed
Data Size: 12912 Bytes = 12.61 kB = 0.01 MB
- Hash algo: sha1
- Hash value: a1f2099cf47ff9816236cd534c77af86e713faad
+ Hash algo: sha256
+ Hash value: 6aa50c2e0392cb119cdf0971dce8339f100608ed3757c8200b0e39e889e432d2
Default Configuration: 'config-1'
Configuration 0 (config-1)
Description: Boot Linux kernel
cmd/cat
cmd/cbsysinfo
cmd/cedit
+ cmd/cli
cmd/cls
cmd/cmp
cmd/coninfo
cmd/rng
cmd/saves
cmd/sbi
+ cmd/scmi
cmd/scp03
cmd/seama
cmd/setexpr
See also CMD_SATA which provides command-line support.
-config SYS_SATA_MAX_PORTS
- int "Maximum supported SATA ports"
- depends on SCSI_AHCI && !DM_SCSI
- default 1
- help
- Sets the maximum number of ports to scan when looking for devices.
- Ports from 0 to (this value - 1) are scanned.
-
config LIBATA
bool
help
config AHCI_PCI
bool "Support for PCI-based AHCI controller"
depends on PCI
- depends on DM_SCSI
+ depends on SCSI
depends on SCSI_AHCI
help
Enables support for the PCI-based AHCI controller.
bool "Support for PCI-based AHCI controller for SPL"
depends on SPL
depends on SPL_PCI
- depends on SPL_SATA && DM_SCSI
+ depends on SPL_SATA && SCSI
config DWC_AHCI
bool "Enable Synopsys DWC AHCI driver support"
select SCSI_AHCI
select PHY
- depends on DM_SCSI
+ depends on SCSI
help
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
bool "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU || ARCH_OCTEON
select SCSI_AHCI
- select DM_SCSI
+ select SCSI
help
This option enables support for the Marvell EBU SoC's
onboard AHCI SATA.
config SATA_CEVA
bool "Ceva Sata controller"
depends on AHCI
- depends on DM_SCSI
+ depends on SCSI
help
This option enables Ceva Sata controller hard IP available on Xilinx
ZynqMP. Support up to 2 external devices. Compliant with SATA 3.1 and
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
-obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
-#ifndef CONFIG_DM_SCSI
-struct ahci_uc_priv *probe_ent = NULL;
-#endif
-
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
/*
static int ahci_host_init(struct ahci_uc_priv *uc_priv)
{
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- struct udevice *dev = uc_priv->dev;
- struct pci_child_plat *pplat = dev_get_parent_plat(dev);
- u16 tmp16;
-#endif
void __iomem *mmio = uc_priv->mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
- u16 tmp16;
-
- dm_pci_read_config16(dev, 0x92, &tmp16);
- dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
- }
-#endif
uc_priv->cap = readl(mmio + HOST_CAP);
uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
port_map = uc_priv->port_map;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
-#if !defined(CONFIG_DM_SCSI)
- if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS)
- uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS;
-#endif
-
for (i = 0; i < uc_priv->n_ports; i++) {
if (!(port_map & (1 << i)))
continue;
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
-#if !defined(CONFIG_DM_SCSI)
-#ifndef CONFIG_SCSI_AHCI_PLAT
- dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
- tmp |= PCI_COMMAND_MASTER;
- dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
-#endif
-#endif
return 0;
}
static void ahci_print_info(struct ahci_uc_priv *uc_priv)
{
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- struct udevice *dev = uc_priv->dev;
- u16 cc;
-#endif
void __iomem *mmio = uc_priv->mmio_base;
u32 vers, cap, cap2, impl, speed;
const char *speed_s;
else
speed_s = "?";
-#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
scc_s = "SATA";
-#else
- dm_pci_read_config16(dev, 0x0a, &cc);
- if (cc == 0x0101)
- scc_s = "IDE";
- else if (cc == 0x0106)
- scc_s = "SATA";
- else if (cc == 0x0104)
- scc_s = "RAID";
- else
- scc_s = "unknown";
-#endif
printf("AHCI %02x%02x.%02x%02x "
"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
(vers >> 24) & 0xff,
cap2 & (1 << 0) ? "boh " : "");
}
-#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
{
-#if !defined(CONFIG_DM_SCSI)
- u16 vendor;
-#endif
int rc;
uc_priv->dev = dev;
uc_priv->pio_mask = 0x1f;
uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
-#if !defined(CONFIG_DM_SCSI)
- uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0,
- PCI_REGION_TYPE, PCI_REGION_MEM);
-
- /* Take from kernel:
- * JMicron-specific fixup:
- * make sure we're in AHCI mode
- */
- dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
- if (vendor == 0x197b)
- dm_pci_write_config8(dev, 0x41, 0xa1);
-#else
struct scsi_plat *plat = dev_get_uclass_plat(dev);
uc_priv->mmio_base = (void *)plat->base;
-#endif
debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
/* initialize adapter */
err_out:
return rc;
}
-#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
{
- struct ahci_uc_priv *uc_priv;
-#ifdef CONFIG_DM_SCSI
- uc_priv = dev_get_uclass_priv(dev->parent);
-#else
- uc_priv = probe_ent;
-#endif
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
int ret;
switch (pccb->cmd[0]) {
return 0;
}
-#ifndef CONFIG_DM_SCSI
-void scsi_low_level_init(int busdevfunc)
-{
- struct ahci_uc_priv *uc_priv;
-
-#ifndef CONFIG_SCSI_AHCI_PLAT
- probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
- if (!probe_ent) {
- printf("%s: No memory for uc_priv\n", __func__);
- return;
- }
- uc_priv = probe_ent;
- struct udevice *dev;
- int ret;
-
- ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
- if (ret)
- return;
- ahci_init_one(uc_priv, dev);
-#else
- uc_priv = probe_ent;
-#endif
-
- ahci_start_ports(uc_priv);
-}
-#endif
-
-#ifndef CONFIG_SCSI_AHCI_PLAT
int ahci_init_one_dm(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
return ahci_init_one(uc_priv, dev);
}
-#endif
int ahci_start_ports_dm(struct udevice *dev)
{
return ahci_start_ports(uc_priv);
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
-{
- int rc;
-
- uc_priv->host_flags = ATA_FLAG_SATA
- | ATA_FLAG_NO_LEGACY
- | ATA_FLAG_MMIO
- | ATA_FLAG_PIO_DMA
- | ATA_FLAG_NO_ATAPI;
- uc_priv->pio_mask = 0x1f;
- uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
-
- uc_priv->mmio_base = base;
-
- /* initialize adapter */
- rc = ahci_host_init(uc_priv);
- if (rc)
- goto err_out;
-
- ahci_print_info(uc_priv);
-
- rc = ahci_start_ports(uc_priv);
-
-err_out:
- return rc;
-}
-
-#ifndef CONFIG_DM_SCSI
-int ahci_init(void __iomem *base)
-{
- struct ahci_uc_priv *uc_priv;
-
- probe_ent = malloc(sizeof(struct ahci_uc_priv));
- if (!probe_ent) {
- printf("%s: No memory for uc_priv\n", __func__);
- return -ENOMEM;
- }
-
- uc_priv = probe_ent;
- memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
-
- return ahci_init_common(uc_priv, base);
-}
-#endif
-
-int ahci_init_dm(struct udevice *dev, void __iomem *base)
-{
- struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
-
- return ahci_init_common(uc_priv, base);
-}
-
-void __weak scsi_init(void)
-{
-}
-
-#endif /* CONFIG_SCSI_AHCI_PLAT */
-
/*
* In the general case of generic rotating media it makes sense to have a
* flush capability. It probably even makes sense in the case of SSDs because
return 0;
}
-#ifdef CONFIG_DM_SCSI
int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
{
struct udevice *dev;
.id = UCLASS_SCSI,
.ops = &scsi_ops,
};
-#else
-int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
-{
- return ahci_scsi_exec(dev, pccb);
-}
-
-__weak int scsi_bus_reset(struct udevice *dev)
-{
- return ahci_scsi_bus_reset(dev);
-
- return 0;
-}
-#endif
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
-#ifndef CONFIG_AHCI
-struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-#endif
-
int sata_reset(struct udevice *dev)
{
struct ahci_ops *ops = ahci_get_ops(dev);
return ret;
}
-#ifndef CONFIG_AHCI
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *sata_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-#endif
-#endif
-
static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, void *dst)
{
return -ENOSYS;
}
-#ifndef CONFIG_AHCI
-int __sata_initialize(void)
-{
- int rc, ret = -1;
- int i;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
- memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
- sata_dev_desc[i].uclass_id = UCLASS_AHCI;
- sata_dev_desc[i].devnum = i;
- sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[i].lba = 0;
- sata_dev_desc[i].blksz = 512;
- sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- rc = init_sata(i);
- if (!rc) {
- rc = scan_sata(i);
- if (!rc && sata_dev_desc[i].lba > 0 &&
- sata_dev_desc[i].blksz > 0) {
- part_init(&sata_dev_desc[i]);
- ret = i;
- }
- }
- }
-
- return ret;
-}
-int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
-
-__weak int __sata_stop(void)
-{
- int i, err = 0;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
- err |= reset_sata(i);
-
- if (err)
- printf("Could not reset some SATA devices\n");
-
- return err;
-}
-int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
-#endif
-
static const struct blk_ops sata_blk_ops = {
.read = sata_bread,
.write = sata_bwrite,
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- */
-
-#include <common.h>
-#include <blk.h>
-
-int init_sata(int dev)
-{
- return 0;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-int scan_sata(int dev)
-{
- return 0;
-}
-
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- return 0;
-}
-
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
- return 0;
-}
#define __X86EMU_X86EMU_H
#include <asm/types.h>
-#include <common.h>
#include <pci.h>
#include <asm/io.h>
#define X86API
config SPL_LEGACY_BLOCK
bool # "Enable Legacy Block Device"
- depends on SPL && !DM_SPL
+ depends on SPL
default y if SPL_MMC || SPL_USB_STORAGE || SCSI || NVME || IDE
default y if SPL_AHCI_PCI
help
config RKMTD
bool "Rockchip rkmtd virtual block device"
+ select RANDOM_UUID
help
Enable "rkmtd" class and driver to create a virtual block device
to transfer Rockchip boot block data to and from NAND with block
endif
obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
-obj-$(CONFIG_BLKMAP) += blkmap.o
+obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap.o
+obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap_helper.o
obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o
void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms);
};
-/**
- * struct blkmap - Block map
- *
- * Data associated with a blkmap.
- *
- * @label: Human readable name of this blkmap
- * @blk: Underlying block device
- * @slices: List of slices associated with this blkmap
- */
-struct blkmap {
- char *label;
- struct udevice *blk;
- struct list_head slices;
-};
-
static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr)
{
return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt));
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * blkmap helper function
+ *
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <blk.h>
+#include <blkmap.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+
+int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
+ struct udevice **devp)
+{
+ int ret;
+ lbaint_t blknum;
+ struct blkmap *bm;
+ struct blk_desc *desc;
+ struct udevice *bm_dev;
+
+ ret = blkmap_create(label, &bm_dev);
+ if (ret) {
+ log_err("failed to create blkmap\n");
+ return ret;
+ }
+
+ bm = dev_get_plat(bm_dev);
+ desc = dev_get_uclass_plat(bm->blk);
+ blknum = image_size >> desc->log2blksz;
+ ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+ if (ret) {
+ log_err("Unable to map %#llx at block %d : %d\n",
+ (unsigned long long)image_addr, 0, ret);
+ goto err;
+ }
+ log_info("Block %d+0x" LBAF " mapped to %#llx\n", 0, blknum,
+ (unsigned long long)image_addr);
+
+ ret = device_probe(bm->blk);
+ if (ret)
+ goto err;
+
+ if (devp)
+ *devp = bm_dev;
+
+ return 0;
+
+err:
+ blkmap_destroy(bm_dev);
+
+ return ret;
+}
This driver is for SiFive Composable L2/L3 cache. It enables cache
ways of composable cache.
+config SIFIVE_PL2
+ bool "SiFive private L2 cache"
+ select CACHE
+ help
+ This driver is for SiFive Private L2 cache. It configures registers
+ to enable the clock gating feature.
+
endmenu
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
+obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 SiFive
+ */
+
+#include <cache.h>
+#include <dm.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+
+#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000
+#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3)
+
+static int sifive_pl2_probe(struct udevice *dev)
+{
+ fdt_addr_t base;
+ u32 val;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Enable regionClockDisable bit */
+ val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+ writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
+ (void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+
+ return 0;
+}
+
+static const struct udevice_id sifive_pl2_ids[] = {
+ { .compatible = "sifive,pl2cache0" },
+ { .compatible = "sifive,pl2cache1" },
+ {}
+};
+
+U_BOOT_DRIVER(sifive_pl2) = {
+ .name = "sifive_pl2",
+ .id = UCLASS_CACHE,
+ .of_match = sifive_pl2_ids,
+ .probe = sifive_pl2_probe,
+};
return 0;
}
-struct clk_ops ast2600_clk_ops = {
- .get_rate = ast2600_clk_get_rate,
- .set_rate = ast2600_clk_set_rate,
- .enable = ast2600_clk_enable,
-};
-
-static int ast2600_clk_probe(struct udevice *dev)
-{
- struct ast2600_clk_priv *priv = dev_get_priv(dev);
-
- priv->scu = devfdt_get_addr_ptr(dev);
- if (IS_ERR(priv->scu))
- return PTR_ERR(priv->scu);
-
- ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig);
- ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig);
- ast2600_configure_mac12_clk(priv->scu);
- ast2600_configure_mac34_clk(priv->scu);
- ast2600_configure_rsa_ecc_clk(priv->scu);
-
- return 0;
-}
-
-static int ast2600_clk_bind(struct udevice *dev)
-{
- int ret;
-
- /* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
- if (ret)
- debug("Warning: No reset driver: ret=%d\n", ret);
-
- return 0;
-}
-
struct aspeed_clks {
ulong id;
const char *name;
};
+#if IS_ENABLED(CONFIG_CMD_CLK)
static struct aspeed_clks aspeed_clk_names[] = {
{ ASPEED_CLK_HPLL, "hpll" },
{ ASPEED_CLK_MPLL, "mpll" },
{ ASPEED_CLK_HUARTX, "huxclk" },
};
-int soc_clk_dump(void)
+static void ast2600_clk_dump(struct udevice *dev)
{
- struct udevice *dev;
struct clk clk;
unsigned long rate;
int i, ret;
- ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu),
- &dev);
- if (ret)
- return ret;
-
printf("Clk\t\tHz\n");
for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
return 0;
}
+#endif
+
+struct clk_ops ast2600_clk_ops = {
+ .get_rate = ast2600_clk_get_rate,
+ .set_rate = ast2600_clk_set_rate,
+ .enable = ast2600_clk_enable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = ast2600_clk_dump,
+#endif
+};
+
+static int ast2600_clk_probe(struct udevice *dev)
+{
+ struct ast2600_clk_priv *priv = dev_get_priv(dev);
+
+ priv->scu = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig);
+ ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig);
+ ast2600_configure_mac12_clk(priv->scu);
+ ast2600_configure_mac34_clk(priv->scu);
+ ast2600_configure_rsa_ecc_clk(priv->scu);
+
+ return 0;
+}
+
+static int ast2600_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No reset driver: ret=%d\n", ret);
+
+ return 0;
+}
static const struct udevice_id ast2600_clk_ids[] = {
{ .compatible = "aspeed,ast2600-scu", },
#include <linux/clk/at91_pmc.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/time.h>
#include "pmc.h"
#define UBOOT_DM_CLK_AT91_MAIN_RC "at91-main-rc-clk"
#define UBOOT_DM_CLK_AT91_SAM9X5_MAIN "at91-sam9x5-main-clk"
#define MOR_KEY_MASK GENMASK(23, 16)
-#define USEC_PER_SEC 1000000UL
#define SLOW_CLOCK_FREQ 32768
#define clk_main_parent_select(s) (((s) & \
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
- if (rate && rate_ops)
+ if (rate && rate_ops && rate_ops->set_rate)
return rate_ops->set_rate(clk_rate, rate);
else
return clk_get_rate(clk);
if (CONFIG_IS_ENABLED(CLK_CCF)) {
/* Take id 0 as a non-valid clk, such as dummy */
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ ops = clk_dev_ops(clkp->dev);
if (clkp->enable_count) {
clkp->enable_count++;
return 0;
if (CONFIG_IS_ENABLED(CLK_CCF)) {
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ ops = clk_dev_ops(clkp->dev);
if (clkp->flags & CLK_IS_CRITICAL)
return 0;
int clk_register(struct clk *clk, const char *drv_name,
const char *name, const char *parent_name)
{
- struct udevice *parent;
+ struct udevice *parent = NULL;
struct driver *drv;
int ret;
- ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
- if (ret) {
- log_err("%s: failed to get %s device (parent of %s)\n",
- __func__, parent_name, name);
- } else {
- log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
- parent->name, parent);
+ if (parent_name) {
+ ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
+ if (ret) {
+ log_err("%s: failed to get %s device (parent of %s)\n",
+ __func__, parent_name, name);
+ } else {
+ log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
+ parent->name, parent);
+ }
}
drv = lists_driver_lookup_name(drv_name);
#include <dt-bindings/mfd/k210-sysctl.h>
#include <k210/pll.h>
#include <linux/bitfield.h>
+#include <asm/barrier.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-static const struct clk_ops k210_clk_ops = {
- .request = k210_clk_request,
- .set_rate = k210_clk_set_rate,
- .get_rate = k210_clk_get_rate,
- .set_parent = k210_clk_set_parent,
- .enable = k210_clk_enable,
- .disable = k210_clk_disable,
-};
-
-static int k210_clk_probe(struct udevice *dev)
-{
- int ret;
- struct k210_clk_priv *priv = dev_get_priv(dev);
-
- priv->base = dev_read_addr_ptr(dev_get_parent(dev));
- if (!priv->base)
- return -EINVAL;
-
- ret = clk_get_by_index(dev, 0, &priv->in0);
- if (ret)
- return ret;
-
- /*
- * Force setting defaults, even before relocation. This is so we can
- * set the clock rate for PLL1 before we relocate into aisram.
- */
- if (!(gd->flags & GD_FLG_RELOC))
- clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
-
- return 0;
-}
-
-static const struct udevice_id k210_clk_ids[] = {
- { .compatible = "canaan,k210-clk" },
- { },
-};
-
-U_BOOT_DRIVER(k210_clk) = {
- .name = "k210_clk",
- .id = UCLASS_CLK,
- .of_match = k210_clk_ids,
- .ops = &k210_clk_ops,
- .probe = k210_clk_probe,
- .priv_auto = sizeof(struct k210_clk_priv),
-};
-
#if IS_ENABLED(CONFIG_CMD_CLK)
static char show_enabled(struct k210_clk_priv *priv, int id)
{
}
}
-int soc_clk_dump(void)
+static void k210_clk_dump(struct udevice *dev)
{
- int ret;
- struct udevice *dev;
struct k210_clk_priv *priv;
- ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
- &dev);
- if (ret)
- return ret;
priv = dev_get_priv(dev);
puts(" Rate Enabled Name\n");
printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "",
priv->in0.dev->name);
show_clks(priv, K210_CLK_IN0, 1);
- return 0;
}
#endif
+
+static const struct clk_ops k210_clk_ops = {
+ .request = k210_clk_request,
+ .set_rate = k210_clk_set_rate,
+ .get_rate = k210_clk_get_rate,
+ .set_parent = k210_clk_set_parent,
+ .enable = k210_clk_enable,
+ .disable = k210_clk_disable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = k210_clk_dump,
+#endif
+};
+
+static int k210_clk_probe(struct udevice *dev)
+{
+ int ret;
+ struct k210_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev_get_parent(dev));
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->in0);
+ if (ret)
+ return ret;
+
+ /*
+ * Force setting defaults, even before relocation. This is so we can
+ * set the clock rate for PLL1 before we relocate into aisram.
+ */
+ if (!(gd->flags & GD_FLG_RELOC))
+ clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
+
+ return 0;
+}
+
+static const struct udevice_id k210_clk_ids[] = {
+ { .compatible = "canaan,k210-clk" },
+ { },
+};
+
+U_BOOT_DRIVER(k210_clk) = {
+ .name = "k210_clk",
+ .id = UCLASS_CLK,
+ .of_match = k210_clk_ids,
+ .ops = &k210_clk_ops,
+ .probe = k210_clk_probe,
+ .priv_auto = sizeof(struct k210_clk_priv),
+};
DECLARE_GLOBAL_DATA_PTR;
+#define CLK_MHZ(x) ((x) / 1000000)
+
/* Primary oscillator */
#define SYS_POSC_CLK_HZ 24000000
return rate;
}
+#if IS_ENABLED(CONFIG_CMD_CLK)
+static void pic32_dump(struct udevice *dev)
+{
+ int i;
+ struct clk clk;
+
+ clk.dev = dev;
+
+ clk.id = PLLCLK;
+ printf("PLL Speed: %lu MHz\n",
+ CLK_MHZ(pic32_get_rate(&clk)));
+
+ clk.id = PB7CLK;
+ printf("CPU Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk)));
+
+ clk.id = MPLL;
+ printf("MPLL Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk)));
+
+ for (i = PB1CLK; i <= PB7CLK; i++) {
+ clk.id = i;
+ printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
+ CLK_MHZ(pic32_get_rate(&clk)));
+ }
+
+ for (i = REF1CLK; i <= REF5CLK; i++) {
+ clk.id = i;
+ printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
+ CLK_MHZ(pic32_get_rate(&clk)));
+ }
+}
+#endif
+
static struct clk_ops pic32_pic32_clk_ops = {
.set_rate = pic32_set_rate,
.get_rate = pic32_get_rate,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = pic32_dump,
+#endif
};
static int pic32_clk_probe(struct udevice *dev)
U_BOOT_DRIVER(sandbox_clk_ccf) = {
.name = "sandbox_clk_ccf",
.id = UCLASS_CLK,
+ .ops = &ccf_clk_ops,
.probe = sandbox_clk_ccf_probe,
.of_match = sandbox_clk_ccf_test_ids,
};
[SANDBOX_CLK_TEST_ID_FIXED] = "fixed",
[SANDBOX_CLK_TEST_ID_SPI] = "spi",
[SANDBOX_CLK_TEST_ID_I2C] = "i2c",
+ [SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root",
};
int sandbox_clk_test_get(struct udevice *dev)
return 0;
}
-int soc_clk_dump(void)
+#if IS_ENABLED(CONFIG_CMD_CLK)
+static void versal_clk_dump(struct udevice __always_unused *dev)
{
u64 clk_rate = 0;
u32 type, ret, i = 0;
printf("clk: %s freq:%lld\n",
clock[i].clk_name, clk_rate);
}
-
- return 0;
}
+#endif
static void versal_get_clock_info(void)
{
.set_rate = versal_clk_set_rate,
.get_rate = versal_clk_get_rate,
.enable = versal_clk_enable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = versal_clk_dump,
+#endif
};
static const struct udevice_id versal_clk_ids[] = {
return 0;
}
+#if IS_ENABLED(CONFIG_CMD_CLK)
+static const char * const clk_names[clk_max] = {
+ "armpll", "ddrpll", "iopll",
+ "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
+ "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
+ "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
+ "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
+ "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
+ "smc_aper", "swdt", "dbg_trc", "dbg_apb"
+};
+
+static void zynq_clk_dump(struct udevice *dev)
+{
+ int i, ret;
+
+ printf("clk\t\tfrequency\n");
+ for (i = 0; i < clk_max; i++) {
+ const char *name = clk_names[i];
+
+ if (name) {
+ struct clk clk;
+ unsigned long rate;
+
+ clk.id = i;
+ ret = clk_request(dev, &clk);
+ if (ret < 0) {
+ printf("%s clk_request() failed: %d\n",
+ __func__, ret);
+ break;
+ }
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO))
+ printf("%10s%20s\n", name, "unknown");
+ else
+ printf("%10s%20lu\n", name, rate);
+ }
+ }
+}
+#endif
+
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
.enable = dummy_enable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = zynq_clk_dump,
+#endif
};
static int zynq_clk_probe(struct udevice *dev)
}
}
-int soc_clk_dump(void)
+#if IS_ENABLED(CONFIG_CMD_CLK)
+static void zynqmp_clk_dump(struct udevice *dev)
{
- struct udevice *dev;
int i, ret;
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(zynqmp_clk), &dev);
- if (ret)
- return ret;
-
printf("clk\t\tfrequency\n");
for (i = 0; i < clk_max; i++) {
const char *name = clk_names[i];
clk.id = i;
ret = clk_request(dev, &clk);
- if (ret < 0)
- return ret;
+ if (ret < 0) {
+ printf("%s clk_request() failed: %d\n",
+ __func__, ret);
+ break;
+ }
rate = clk_get_rate(&clk);
printf("%10s%20lu\n", name, rate);
}
}
-
- return 0;
}
+#endif
static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
{
break;
case qspi_ref ... can1_ref:
case lpd_lsbus:
+ case topsw_lsbus:
clkact_shift = 24;
mask = 0x1;
break;
.set_rate = zynqmp_clk_set_rate,
.get_rate = zynqmp_clk_get_rate,
.enable = zynqmp_clk_enable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = zynqmp_clk_dump,
+#endif
};
static const struct udevice_id zynqmp_clk_ids[] = {
}
#if IS_ENABLED(CONFIG_CMD_CLK)
-int soc_clk_dump(void)
+static void imx8_clk_dump(struct udevice *dev)
{
- struct udevice *dev;
struct clk clk;
unsigned long rate;
int i, ret;
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(imx8_clk), &dev);
- if (ret)
- return ret;
-
printf("Clk\t\tHz\n");
for (i = 0; i < num_clks; i++) {
printf("%s(%3lu):\t%lu\n",
imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
}
-
- return 0;
}
#endif
.get_rate = imx8_clk_get_rate,
.enable = imx8_clk_enable,
.disable = imx8_clk_disable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = imx8_clk_dump,
+#endif
};
static int imx8_clk_probe(struct udevice *dev)
static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
+
+static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
+
+static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
+
+static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
+#endif
+
static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
clk_dm(IMX8MN_CLK_ENET1_ROOT,
imx_clk_gate4("enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
+ clk_dm(IMX8MN_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MN_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MN_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MN_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+ clk_dm(IMX8MN_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MN_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MN_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MN_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif
#if CONFIG_IS_ENABLED(DM_SPI)
obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
+obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8365 SoC
+ *
+ * Copyright (C) 2023 BayLibre, SAS
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Julien Masson <jmasson@baylibre.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <dm.h>
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include "clk-mtk.h"
+
+/* apmixedsys */
+#define MT8365_PLL_FMAX (3800UL * MHZ)
+#define MT8365_PLL_FMIN (1500UL * MHZ)
+#define CON0_MT8365_RST_BAR BIT(23)
+#define PLL_AO BIT(1)
+
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift, _rst_bar_mask, _pcw_chg_reg) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8365_PLL_FMAX, \
+ .fmin = MT8365_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310,
+ 24, 0x0310, 0, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
+ PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
+ 0x021C, 0, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
+ 0x0354, 0, 0, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
+ 0x0334, 0, 0, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
+ 0x0324, 0, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
+ 0x0368, 0, 0, 0x0364),
+ PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
+ 0x0378, 0, 0, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
+ 0x0394, 0, 0, 0),
+ PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24,
+ 0x03A4, 0, 0, 0),
+};
+
+/* topckgen */
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
+ FIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
+};
+
+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+static const struct mtk_fixed_factor top_divs[] = {
+ PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2),
+ PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", CLK_APMIXED_MAINPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", CLK_APMIXED_MAINPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", CLK_APMIXED_MAINPLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", CLK_APMIXED_MAINPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", CLK_APMIXED_MAINPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", CLK_APMIXED_MAINPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", CLK_APMIXED_MAINPLL, 1, 24),
+ PLL_FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", CLK_APMIXED_MAINPLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", CLK_APMIXED_MAINPLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", CLK_APMIXED_MAINPLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7),
+ PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14),
+ PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28),
+ PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIV_EN, 1, 2),
+ PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", CLK_APMIXED_UNIVPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", CLK_APMIXED_UNIVPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", CLK_APMIXED_UNIVPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", CLK_APMIXED_UNIVPLL, 1, 24),
+ PLL_FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", CLK_APMIXED_UNIVPLL, 1, 96),
+ PLL_FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", CLK_APMIXED_UNIVPLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", CLK_APMIXED_UNIVPLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", CLK_APMIXED_UNIVPLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_MMPLL, "mmpll_ck", CLK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", CLK_APMIXED_LVDSPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", CLK_APMIXED_USB20_EN, 1, 13),
+ PLL_FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", CLK_TOP_USB20_192M, 1, 4),
+ PLL_FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", CLK_TOP_USB20_192M, 1, 8),
+ PLL_FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", CLK_TOP_USB20_192M, 1, 16),
+ PLL_FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", CLK_TOP_USB20_192M, 1, 32),
+ PLL_FACTOR(CLK_TOP_APLL1, "apll1_ck", CLK_APMIXED_APLL1, 1, 1),
+ PLL_FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", CLK_APMIXED_APLL1, 1, 2),
+ PLL_FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", CLK_APMIXED_APLL1, 1, 4),
+ PLL_FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", CLK_APMIXED_APLL1, 1, 8),
+ PLL_FACTOR(CLK_TOP_APLL2, "apll2_ck", CLK_APMIXED_APLL2, 1, 1),
+ PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8),
+ PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", CLK_APMIXED_DSPPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52),
+};
+
+static const int axi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL3_D2
+};
+
+static const int mem_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int scp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MFGPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int atb_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int camtg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_USB20_192M_D8,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_USB20_192M_D4,
+ CLK_TOP_UNIVPLL2_D32,
+ CLK_TOP_USB20_192M_D16,
+ CLK_TOP_USB20_192M_D32,
+};
+
+static const int uart_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_0_hc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int msdc30_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int audio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D16
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int aud_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_D2,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL1_D8
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D8,
+};
+
+static const int aud_spdif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int disp_pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int dxcc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int ssusb_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL2_D8
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int senif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2
+};
+
+static const int aes_fde_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int dpi0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_LVDSPLL_D2,
+ CLK_TOP_LVDSPLL_D4,
+ CLK_TOP_LVDSPLL_D8,
+ CLK_TOP_LVDSPLL_D16
+};
+
+static const int dsp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_DSPPLL_D8
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int ecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int apu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_APMIXED_APUPLL,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7),
+ MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15),
+ MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23),
+ MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31),
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7),
+ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15),
+ MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23),
+ MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31),
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7),
+ MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15),
+ MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23),
+ MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31),
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31),
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15),
+ MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23),
+ MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31),
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15),
+ MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23),
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31),
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23),
+ MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15),
+ MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31),
+ /* CLK_CFG_9 */
+ MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15),
+ MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31),
+ /* CLK_CFG_10 */
+ MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7),
+ MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23),
+ MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31),
+};
+
+static const struct mtk_clk_tree mt8365_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_SYSPLL_D2,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_divs,
+ .muxes = top_muxes,
+};
+
+/* topckgen cg */
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0,
+ .clr_ofs = 0,
+ .sta_ofs = 0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x320,
+ .clr_ofs = 0x320,
+ .sta_ofs = 0x320,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clk_gates[] = {
+ GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+ GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
+ GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
+ GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
+ GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+ GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1),
+ GATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2),
+ GATE_TOP2(CLK_TOP_AUD_I2S3_M, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, CLK_TOP_APLL12_CK_DIV4B, 5),
+ GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6),
+ GATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7),
+ GATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs ifr2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifr3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifr4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs ifr5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs ifr6_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_IFRX(_id, _parent, _shift, _regs) \
+ { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = _regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_IFR2(_id, _parent, _shift) \
+ GATE_IFRX(_id, _parent, _shift, &ifr2_cg_regs)
+
+#define GATE_IFR3(_id, _parent, _shift) \
+ GATE_IFRX(_id, _parent, _shift, &ifr3_cg_regs)
+
+#define GATE_IFR4(_id, _parent, _shift) \
+ GATE_IFRX(_id, _parent, _shift, &ifr4_cg_regs)
+
+#define GATE_IFR5(_id, _parent, _shift) \
+ GATE_IFRX(_id, _parent, _shift, &ifr5_cg_regs)
+
+#define GATE_IFR6(_id, _parent, _shift) \
+ GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs)
+
+static const struct mtk_gate ifr_clks[] = {
+ /* IFR2 */
+ GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0),
+ GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1),
+ GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2),
+ GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3),
+ GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
+ GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
+ GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
+ GATE_IFR2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+ GATE_IFR2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16),
+ GATE_IFR2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17),
+ GATE_IFR2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18),
+ GATE_IFR2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19),
+ GATE_IFR2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),
+ GATE_IFR2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21),
+ GATE_IFR2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
+ GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
+ GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
+ GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
+ GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27),
+ GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
+ GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
+ /* IFR3 */
+ GATE_IFR3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),
+ GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),
+ GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
+ GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
+ GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),
+ GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
+ GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
+ GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
+ GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
+ GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
+ GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+ GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
+ /* IFR4 */
+ GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0),
+ GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2),
+ GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4),
+ GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+ /* IFR5 */
+ GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0),
+ GATE_IFR5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1),
+ GATE_IFR5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2),
+ GATE_IFR5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+ GATE_IFR5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+ GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+ GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+ GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11),
+ GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
+ GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
+ GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
+ GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
+ GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
+ GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+ GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+ GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+ GATE_IFR5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27),
+ GATE_IFR5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
+ GATE_IFR5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
+ GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
+ /* IFR6 */
+ GATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
+ GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
+ GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
+ GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
+ GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
+ GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
+ GATE_IFR6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
+ GATE_IFR6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
+ GATE_IFR6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),
+ GATE_IFR6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+ GATE_IFR6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10),
+ GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static int mt8365_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8365_clk_tree);
+}
+
+static int mt8365_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8365_clk_tree);
+}
+
+static int mt8365_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates);
+}
+
+static int mt8365_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks);
+}
+
+static const struct udevice_id mt8365_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8365-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8365_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8365-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8365_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8365-topckgen-cg", },
+ { }
+};
+
+static const struct udevice_id mt8365_infracfg_compat[] = {
+ { .compatible = "mediatek,mt8365-infracfg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8365-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8365_apmixed_compat,
+ .probe = mt8365_apmixedsys_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8365-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8365_topckgen_compat,
+ .probe = mt8365_topckgen_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8365-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8365_topckgen_cg_compat,
+ .probe = mt8365_topckgen_cg_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt8365-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt8365_infracfg_compat,
+ .probe = mt8365_infracfg_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
return meson_mux_set_parent_by_id(clk, parent_clk->id);
}
-static struct clk_ops meson_clk_ops = {
- .disable = meson_clk_disable,
- .enable = meson_clk_enable,
- .get_rate = meson_clk_get_rate,
- .set_rate = meson_clk_set_rate,
- .set_parent = meson_clk_set_parent,
-};
-
static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
{ }
};
-U_BOOT_DRIVER(meson_clk) = {
- .name = "meson-clk-a1",
- .id = UCLASS_CLK,
- .of_match = meson_clk_ids,
- .priv_auto = sizeof(struct meson_clk),
- .ops = &meson_clk_ops,
- .probe = meson_clk_probe,
-};
-
+#if IS_ENABLED(CONFIG_CMD_CLK)
static const char *meson_clk_get_name(struct clk *clk, int id)
{
const struct meson_clk_info *info;
return IS_ERR(info) ? "unknown" : info->name;
}
-static int meson_clk_dump(struct clk *clk)
+static int meson_clk_dump_single(struct clk *clk)
{
const struct meson_clk_info *info;
struct meson_clk *priv;
return 0;
}
-static int meson_clk_dump_dev(struct udevice *dev)
+static void meson_clk_dump(struct udevice *dev)
{
int i;
struct meson_clk_data *data;
data = (struct meson_clk_data *)dev_get_driver_data(dev);
for (i = 0; i < data->num_clocks; i++) {
- meson_clk_dump(&(struct clk){
+ meson_clk_dump_single(&(struct clk){
.dev = dev,
.id = i
});
}
-
- return 0;
}
+#endif
-int soc_clk_dump(void)
-{
- struct udevice *dev;
- int i = 0;
-
- while (!uclass_get_device(UCLASS_CLK, i++, &dev)) {
- if (dev->driver == DM_DRIVER_GET(meson_clk)) {
- meson_clk_dump_dev(dev);
- printf("\n");
- }
- }
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = meson_clk_dump,
+#endif
+};
- return 0;
-}
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-a1",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
static int clk_dump(const char *name, int (*func)(struct udevice *))
{
struct udevice *dev;
+ int ret;
if (uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
printf("Cannot find device %s\n", name);
return -ENODEV;
}
- return func(dev);
+ ret = func(dev);
+ if (ret)
+ printf("Dump failed for %s: %d\n", name, ret);
+
+ return ret;
}
int armada_37xx_tbg_clk_dump(struct udevice *);
-int soc_clk_dump(void)
+static void armada37xx_clk_dump(struct udevice __always_unused *dev)
{
printf(" xtal at %u000000 Hz\n\n", get_ref_clk());
if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump))
- return 1;
+ return;
if (clk_dump("nb-periph-clk@13000",
armada_37xx_periph_clk_dump))
- return 1;
+ return;
if (clk_dump("sb-periph-clk@18000",
armada_37xx_periph_clk_dump))
- return 1;
-
- return 0;
+ return;
}
#endif
.set_parent = armada_37xx_periph_clk_set_parent,
.enable = armada_37xx_periph_clk_enable,
.disable = armada_37xx_periph_clk_disable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = armada37xx_clk_dump,
+#endif
};
static const struct udevice_id armada_37xx_periph_clk_ids[] = {
return div;
}
-static u32 npcm_clk_set_div(struct clk *clk, u32 div)
+static int npcm_clk_set_div(struct clk *clk, u32 div)
{
struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
struct npcm_clk_div *divider;
if (!divider)
return -EINVAL;
+ if (divider->flags & DIV_RO)
+ return 0;
+
if (divider->flags & PRE_DIV2)
div = div >> 1;
else
clkdiv = ilog2(div);
+ if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {
+ printf("clkdiv(%d) for clk(%ld) is over limit\n",
+ clkdiv, clk->id);
+ return -EINVAL;
+ }
+
val = readl(priv->base + divider->reg);
val &= ~divider->mask;
val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
if (ret)
return ret;
- debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div);
- return (parent_rate / div);
+ debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk));
+ return npcm_clk_get_rate(clk);
}
static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
#define POST_DIV2 BIT(3) /* Post divisor = 2 */
#define FIXED_PARENT BIT(4) /* clock source is fixed */
+#define DIV_RO BIT(5) /* divider is read-only */
/* Parameters of PLL configuration */
struct npcm_clk_pll {
};
static struct npcm_clk_div npcm8xx_clk_dividers[] = {
- {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
- {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
- {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
- {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
- {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1},
- {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
+ {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
+ {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
+ {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
+ {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
+ {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
+ {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
{NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
{NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
{NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},
starfive_clk_gate(priv->reg,
"i2c5_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C5_APB)));
+ /* Watchdog clocks */
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
+ starfive_clk_gate(priv->reg,
+ "wdt_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_WDT_APB)));
+ clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
+ starfive_clk_gate(priv->reg,
+ "wdt_core", "oscillator",
+ OFFSET(JH7110_SYSCLK_WDT_CORE)));
/* enable noc_bus_stg_axi clock */
if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
/* get the current PLLSAIR output freq */
pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
- best_div = pllsair_rate / rate;
-
- /* look into pllsaidivr_table if this divider is available*/
- for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
- if (best_div == pllsaidivr_table[i]) {
- /* set pll_saidivr with found value */
- clrsetbits_le32(®s->dckcfgr,
- RCC_DCKCFGR_PLLSAIDIVR_MASK,
- pllsaidivr_table[i]);
- return rate;
- }
+ if ((pllsair_rate % rate) == 0) {
+ best_div = pllsair_rate / rate;
+
+ /* look into pllsaidivr_table if this divider is available */
+ for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
+ if (best_div == pllsaidivr_table[i]) {
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(®s->dckcfgr,
+ RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ pllsaidivr_table[i] <<
+ RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+ return rate;
+ }
+ }
/*
* As no pllsaidivr value is suitable to obtain requested freq,
}
}
-static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
+static void __maybe_unused stm32mp1_clk_dump(struct udevice *dev)
{
char buf[32];
int i, s, p;
+ struct stm32mp1_clk_priv *priv;
+
+ priv = dev_get_priv(dev);
printf("Clocks:\n");
for (i = 0; i < _PARENT_NB; i++) {
}
}
-#ifdef CONFIG_CMD_CLK
-int soc_clk_dump(void)
-{
- struct udevice *dev;
- struct stm32mp1_clk_priv *priv;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(stm32mp1_clock),
- &dev);
- if (ret)
- return ret;
-
- priv = dev_get_priv(dev);
-
- stm32mp1_clk_dump(priv);
-
- return 0;
-}
-#endif
-
static int stm32mp1_clk_probe(struct udevice *dev)
{
int result = 0;
#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
- stm32mp1_clk_dump(priv);
+ stm32mp1_clk_dump(dev);
#endif
gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
.set_rate = stm32mp1_clk_set_rate,
+#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD)
+ .dump = stm32mp1_clk_dump,
+#endif
};
U_BOOT_DRIVER(stm32mp1_clock) = {
config SPL_DM_STATS
bool "Collect and show driver model stats in SPL"
- depends on DM_SPL
+ depends on SPL_DM
help
Enable this to collect and display memory statistics about driver
model. This can help to figure out where all the memory is going and
if (check_tree_count())
return oftree_null();
+ if (fdt_check_header(fdt)) {
+ log_err("Invalid device tree blob header\n");
+ return oftree_null();
+ }
+
/* register the new tree */
i = oftree_count++;
oftree_list[i] = fdt;
#ifndef __JOBDESC_H
#define __JOBDESC_H
-#include <common.h>
#include <asm/io.h>
#include "rsa_caam.h"
#ifndef __RSA_CAAM_H
#define __RSA_CAAM_H
-#include <common.h>
-
/**
* struct pk_in_params - holder for input to PKHA block in CAAM
* These parameters are required to perform Modular Exponentiation
#ifndef _SDRAM_SOC64_H_
#define _SDRAM_SOC64_H_
-#include <common.h>
#include <linux/sizes.h>
struct altera_sdram_priv {
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3734:
case 3733:
case 3732:
dram_pll_init(MHZ(933));
dram_disable_bypass();
break;
+ case 3600:
+ dram_pll_init(MHZ(900));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
unsigned long imem_start = (unsigned long)_end + fw_offset;
unsigned long dmem_start;
unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
+ static enum fw_type last_type = -1;
+
+ /* If FW doesn't change, we can save the loading. */
+ if (last_type == type)
+ return;
+
+ last_type = type;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
#ifndef _DDR_ML_WRAPPER_H
#define _DDR_ML_WRAPPER_H
-#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#ifndef __DDR3_AXP_H
#define __DDR3_AXP_H
+#include <config.h>
+
#define MV_78XX0_Z1_REV 0x0
#define MV_78XX0_A0_REV 0x1
#define MV_78XX0_B0_REV 0x2
config DFU_TFTP
bool "DFU via TFTP"
+ depends on NETDEVICES
select UPDATE_COMMON
select DFU_OVER_TFTP
help
the buffer once we've been given the whole file. Define
this to the maximum filesize (in bytes) for the buffer.
If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE.
+
+config DFU_NAME_MAX_SIZE
+ int "Size of the name to be added in dfu entity"
+ default 32
+ depends on DFU
+ help
+ This value is used to maximum size. If name is longer than default size,
+ we need to change the proper maximum size.
+
endif
endmenu
config DMA_LEGACY
bool "Legacy DMA support"
- default y if FSLDMAFEC
help
Enable legacy DMA support. This does not use driver model and should
be migrated to the new API.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-/*Main C file for multi-channel DMA API. */
-
-#include <common.h>
-
-#include <MCD_dma.h>
-#include <MCD_tasksInit.h>
-#include <MCD_progCheck.h>
-
-/********************************************************************/
-/* This is an API-internal pointer to the DMA's registers */
-dmaRegs *MCD_dmaBar;
-
-/*
- * These are the real and model task tables as generated by the
- * build process
- */
-extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
-extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
-
-/*
- * However, this (usually) gets relocated to on-chip SRAM, at which
- * point we access them as these tables
- */
-volatile TaskTableEntry *MCD_taskTable;
-TaskTableEntry *MCD_modelTaskTable;
-
-/*
- * MCD_chStatus[] is an array of status indicators for remembering
- * whether a DMA has ever been attempted on each channel, pausing
- * status, etc.
- */
-static int MCD_chStatus[NCHANNELS] = {
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
-};
-
-/* Prototypes for local functions */
-static void MCD_memcpy(int *dest, int *src, u32 size);
-static void MCD_resmActions(int channel);
-
-/*
- * Buffer descriptors used for storage of progress info for single Dmas
- * Also used as storage for the DMA for CRCs for single DMAs
- * Otherwise, the DMA does not parse these buffer descriptors
- */
-#ifdef MCD_INCLUDE_EU
-extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#else
-MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#endif
-MCD_bufDesc *MCD_relocBuffDesc;
-
-/* Defines for the debug control register's functions */
-#define DBG_CTL_COMP1_TASK (0x00002000)
-#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
- DBG_CTL_BREAK | \
- DBG_CTL_INT_BREAK | \
- DBG_CTL_COMP1_TASK)
-#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
- DBG_CTL_INT_BREAK | \
- DBG_CTL_COMP1_TASK)
-#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
-
-/* Offset to context save area where progress info is stored */
-#define CSAVE_OFFSET 10
-
-/* Defines for Byte Swapping */
-#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
-#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
-
-/* Execution Unit Identifiers */
-#define MAC 0 /* legacy - not used */
-#define LUAC 1 /* legacy - not used */
-#define CRC 2 /* legacy - not used */
-#define LURC 3 /* Logic Unit with CRC */
-
-/* Task Identifiers */
-#define TASK_CHAINNOEU 0
-#define TASK_SINGLENOEU 1
-#ifdef MCD_INCLUDE_EU
-#define TASK_CHAINEU 2
-#define TASK_SINGLEEU 3
-#define TASK_FECRX 4
-#define TASK_FECTX 5
-#else
-#define TASK_CHAINEU 0
-#define TASK_SINGLEEU 1
-#define TASK_FECRX 2
-#define TASK_FECTX 3
-#endif
-
-/*
- * Structure to remember which variant is on which channel
- * TBD- need this?
- */
-typedef struct MCD_remVariants_struct MCD_remVariant;
-struct MCD_remVariants_struct {
- int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
- int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
- s16 remDestIncr[NCHANNELS]; /* DestIncr */
- s16 remSrcIncr[NCHANNELS]; /* srcIncr */
- u32 remXferSize[NCHANNELS]; /* xferSize */
-};
-
-/* Structure to remember the startDma parameters for each channel */
-MCD_remVariant MCD_remVariants;
-/********************************************************************/
-/* Function: MCD_initDma
- * Purpose: Initializes the DMA API by setting up a pointer to the DMA
- * registers, relocating and creating the appropriate task
- * structures, and setting up some global settings
- * Arguments:
- * dmaBarAddr - pointer to the multichannel DMA registers
- * taskTableDest - location to move DMA task code and structs to
- * flags - operational parameters
- * Return Value:
- * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
- * MCD_OK otherwise
- */
-extern u32 MCD_funcDescTab0[];
-
-int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags)
-{
- int i;
- TaskTableEntry *entryPtr;
-
- /* setup the local pointer to register set */
- MCD_dmaBar = dmaBarAddr;
-
- /* do we need to move/create a task table */
- if ((flags & MCD_RELOC_TASKS) != 0) {
- int fixedSize;
- u32 *fixedPtr;
- /*int *tablePtr = taskTableDest;TBD */
- int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
- int taskDescTabsOffset;
- int taskTableSize, varTabsSize, funcDescTabsSize,
- contextSavesSize;
- int taskDescTabSize;
-
- int i;
-
- /* check if physical address is aligned on 512 byte boundary */
- if (((u32) taskTableDest & 0x000001ff) != 0)
- return (MCD_TABLE_UNALIGNED);
-
- /* set up local pointer to task Table */
- MCD_taskTable = taskTableDest;
-
- /*
- * Create a task table:
- * - compute aligned base offsets for variable tables and
- * function descriptor tables, then
- * - loop through the task table and setup the pointers
- * - copy over model task table with the the actual task
- * descriptor tables
- */
-
- taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
- /* align variable tables to size */
- varTabsOffset = taskTableSize + (u32) taskTableDest;
- if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
- varTabsOffset =
- (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
- /* align function descriptor tables */
- varTabsSize = NCHANNELS * VAR_TAB_SIZE;
- funcDescTabsOffset = varTabsOffset + varTabsSize;
-
- if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
- funcDescTabsOffset =
- (funcDescTabsOffset +
- FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE);
-
- funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
- contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
- contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
- fixedSize =
- taskTableSize + varTabsSize + funcDescTabsSize +
- contextSavesSize;
-
- /* zero the thing out */
- fixedPtr = (u32 *) taskTableDest;
- for (i = 0; i < (fixedSize / 4); i++)
- fixedPtr[i] = 0;
-
- entryPtr = (TaskTableEntry *) MCD_taskTable;
- /* set up fixed pointers */
- for (i = 0; i < NCHANNELS; i++) {
- /* update ptr to local value */
- entryPtr[i].varTab = (u32) varTabsOffset;
- entryPtr[i].FDTandFlags =
- (u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF;
- entryPtr[i].contextSaveSpace = (u32) contextSavesOffset;
- varTabsOffset += VAR_TAB_SIZE;
-#ifdef MCD_INCLUDE_EU
- /* if not there is only one, just point to the
- same one */
- funcDescTabsOffset += FUNCDESC_TAB_SIZE;
-#endif
- contextSavesOffset += CONTEXT_SAVE_SIZE;
- }
- /* copy over the function descriptor table */
- for (i = 0; i < FUNCDESC_TAB_NUM; i++) {
- MCD_memcpy((void *)(entryPtr[i].
- FDTandFlags & ~MCD_TT_FLAGS_MASK),
- (void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
- }
-
- /* copy model task table to where the context saves stuff
- leaves off */
- MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset;
-
- MCD_memcpy((void *)MCD_modelTaskTable,
- (void *)MCD_modelTaskTableSrc,
- NUMOFVARIANTS * sizeof(TaskTableEntry));
-
- /* point to local version of model task table */
- entryPtr = MCD_modelTaskTable;
- taskDescTabsOffset = (u32) MCD_modelTaskTable +
- (NUMOFVARIANTS * sizeof(TaskTableEntry));
-
- /* copy actual task code and update TDT ptrs in local
- model task table */
- for (i = 0; i < NUMOFVARIANTS; i++) {
- taskDescTabSize =
- entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
- MCD_memcpy((void *)taskDescTabsOffset,
- (void *)entryPtr[i].TDTstart,
- taskDescTabSize);
- entryPtr[i].TDTstart = (u32) taskDescTabsOffset;
- taskDescTabsOffset += taskDescTabSize;
- entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4;
- }
-#ifdef MCD_INCLUDE_EU
- /* Tack single DMA BDs onto end of code so API controls
- where they are since DMA might write to them */
- MCD_relocBuffDesc =
- (MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
-#else
- /* DMA does not touch them so they can be wherever and we
- don't need to waste SRAM on them */
- MCD_relocBuffDesc = MCD_singleBufDescs;
-#endif
- } else {
- /* point the would-be relocated task tables and the
- buffer descriptors to the ones the linker generated */
-
- if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0)
- return (MCD_TABLE_UNALIGNED);
-
- /* need to add code to make sure that every thing else is
- aligned properly TBD. this is problematic if we init
- more than once or after running tasks, need to add
- variable to see if we have aleady init'd */
- entryPtr = MCD_realTaskTableSrc;
- for (i = 0; i < NCHANNELS; i++) {
- if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
- ((entryPtr[i].
- FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
- return (MCD_TABLE_UNALIGNED);
- }
-
- MCD_taskTable = MCD_realTaskTableSrc;
- MCD_modelTaskTable = MCD_modelTaskTableSrc;
- MCD_relocBuffDesc = MCD_singleBufDescs;
- }
-
- /* Make all channels as totally inactive, and remember them as such: */
-
- MCD_dmaBar->taskbar = (u32) MCD_taskTable;
- for (i = 0; i < NCHANNELS; i++) {
- MCD_dmaBar->taskControl[i] = 0x0;
- MCD_chStatus[i] = MCD_NO_DMA;
- }
-
- /* Set up pausing mechanism to inactive state: */
- /* no particular values yet for either comparator registers */
- MCD_dmaBar->debugComp1 = 0;
- MCD_dmaBar->debugComp2 = 0;
- MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
- MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
-
- /* enable or disable commbus prefetch, really need an ifdef or
- something to keep from trying to set this in the 8220 */
- if ((flags & MCD_COMM_PREFETCH_EN) != 0)
- MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
- else
- MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
-
- return (MCD_OK);
-}
-
-/*********************** End of MCD_initDma() ***********************/
-
-/********************************************************************/
-/* Function: MCD_dmaStatus
- * Purpose: Returns the status of the DMA on the requested channel
- * Arguments: channel - channel number
- * Returns: Predefined status indicators
- */
-int MCD_dmaStatus(int channel)
-{
- u16 tcrValue;
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- tcrValue = MCD_dmaBar->taskControl[channel];
- if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */
- /* if last reported with task enabled */
- if (MCD_chStatus[channel] == MCD_RUNNING
- || MCD_chStatus[channel] == MCD_IDLE)
- MCD_chStatus[channel] = MCD_DONE;
- } else { /* something is running */
-
- /* There are three possibilities: paused, running or idle. */
- if (MCD_chStatus[channel] == MCD_RUNNING
- || MCD_chStatus[channel] == MCD_IDLE) {
- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
- /* This register is selected to know which initiator is
- actually asserted. */
- if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
- MCD_chStatus[channel] = MCD_RUNNING;
- else
- MCD_chStatus[channel] = MCD_IDLE;
- /* do not change the status if it is already paused. */
- }
- }
- return MCD_chStatus[channel];
-}
-
-/******************** End of MCD_dmaStatus() ************************/
-
-/********************************************************************/
-/* Function: MCD_startDma
- * Ppurpose: Starts a particular kind of DMA
- * Arguments:
- * srcAddr - the channel on which to run the DMA
- * srcIncr - the address to move data from, or buffer-descriptor address
- * destAddr - the amount to increment the source address per transfer
- * destIncr - the address to move data to
- * dmaSize - the amount to increment the destination address per transfer
- * xferSize - the number bytes in of each data movement (1, 2, or 4)
- * initiator - what device initiates the DMA
- * priority - priority of the DMA
- * flags - flags describing the DMA
- * funcDesc - description of byte swapping, bit swapping, and CRC actions
- * srcAddrVirt - virtual buffer descriptor address TBD
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-
-int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
- s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
- int priority, u32 flags, u32 funcDesc
-#ifdef MCD_NEED_ADDR_TRANS
- s8 * srcAddrVirt
-#endif
- )
-{
- int srcRsdIncr, destRsdIncr;
- int *cSave;
- short xferSizeIncr;
- int tcrCount = 0;
-#ifdef MCD_INCLUDE_EU
- u32 *realFuncArray;
-#endif
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- /* tbd - need to determine the proper response to a bad funcDesc when
- not including EU functions, for now, assign a benign funcDesc, but
- maybe should return an error */
-#ifndef MCD_INCLUDE_EU
- funcDesc = MCD_FUNC_NOEU1;
-#endif
-
-#ifdef MCD_DEBUG
- printf("startDma:Setting up params\n");
-#endif
- /* Set us up for task-wise priority. We don't technically need to do
- this on every start, but since the register involved is in the same
- longword as other registers that users are in control of, setting
- it more than once is probably preferable. That since the
- documentation doesn't seem to be completely consistent about the
- nature of the PTD control register. */
- MCD_dmaBar->ptdControl |= (u16) 0x8000;
-
- /* Not sure what we need to keep here rtm TBD */
-#if 1
- /* Calculate additional parameters to the regular DMA calls. */
- srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
- destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
-
- xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
-
- /* Remember for each channel which variant is running. */
- MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
- MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
- MCD_remVariants.remDestIncr[channel] = destIncr;
- MCD_remVariants.remSrcIncr[channel] = srcIncr;
- MCD_remVariants.remXferSize[channel] = xferSize;
-#endif
-
- cSave =
- (int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET +
- CURRBD;
-
-#ifdef MCD_INCLUDE_EU
- /* may move this to EU specific calls */
- realFuncArray =
- (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
- /* Modify the LURC's normal and byte-residue-loop functions according
- to parameter. */
- realFuncArray[(LURC * 16)] = xferSize == 4 ?
- funcDesc : xferSize == 2 ?
- funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
- realFuncArray[(LURC * 16 + 1)] =
- (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
-#endif
- /* Write the initiator field in the TCR, and also set the
- initiator-hold bit. Note that,due to a hardware quirk, this could
- collide with an MDE access to the initiator-register file, so we
- have to verify that the write reads back correctly. */
-
- MCD_dmaBar->taskControl[channel] =
- (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
-
- while (((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
- ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
- && (tcrCount < 1000)) {
- tcrCount++;
- /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */
- MCD_dmaBar->taskControl[channel] =
- (initiator << 8) | TASK_CTL_HIPRITSKEN |
- TASK_CTL_HLDINITNUM;
- }
-
- MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK;
- /* should be albe to handle this stuff with only one write to ts reg
- - tbd */
- if (channel < 8 && channel >= 0) {
- MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
- MCD_dmaBar->taskSize0 |=
- (xferSize & 3) << (((7 - channel) * 4) + 2);
- MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
- } else {
- MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
- MCD_dmaBar->taskSize1 |=
- (xferSize & 3) << (((15 - channel) * 4) + 2);
- MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
- }
-
- /* setup task table flags/options which mostly control the line
- buffers */
- MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
- MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
-
- if (flags & MCD_FECTX_DMA) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_FECTX].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_FECTX].TDTend;
- MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr,
- (char *)destAddr, MCD_taskTable,
- channel);
- } else if (flags & MCD_FECRX_DMA) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_FECRX].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_FECRX].TDTend;
- MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr,
- (char *)destAddr, MCD_taskTable,
- channel);
- } else if (flags & MCD_SINGLE_DMA) {
- /* this buffer descriptor is used for storing off initial
- parameters for later progress query calculation and for the
- DMA to write the resulting checksum. The DMA does not use
- this to determine how to operate, that info is passed with
- the init routine */
- MCD_relocBuffDesc[channel].srcAddr = srcAddr;
- MCD_relocBuffDesc[channel].destAddr = destAddr;
-
- /* definitely not its final value */
- MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
-
- MCD_relocBuffDesc[channel].dmaSize = dmaSize;
- MCD_relocBuffDesc[channel].flags = 0; /* not used */
- MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
- MCD_relocBuffDesc[channel].next = 0; /* not used */
-
- /* Initialize the progress-querying stuff to show no
- progress: */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
-(u32) & (MCD_relocBuffDesc[channel]);
- /* tbd - need to keep the user from trying to call the EU
- routine when MCD_INCLUDE_EU is not defined */
- if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
- MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr,
- (char *)destAddr, destIncr,
- (int)dmaSize, xferSizeIncr,
- flags, (int *)
- &(MCD_relocBuffDesc[channel]),
- cSave, MCD_taskTable, channel);
- } else {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
- MCD_startDmaSingleEu((char *)srcAddr, srcIncr,
- (char *)destAddr, destIncr,
- (int)dmaSize, xferSizeIncr,
- flags, (int *)
- &(MCD_relocBuffDesc[channel]),
- cSave, MCD_taskTable, channel);
- }
- } else { /* chained DMAS */
- /* Initialize the progress-querying stuff to show no
- progress: */
-#if 1
- /* (!defined(MCD_NEED_ADDR_TRANS)) */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddr)->srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddr)->destAddr;
-#else
- /* if using address translation, need the virtual addr of the
- first buffdesc */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr;
-#endif
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
-
- if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
- /*TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
- MCD_startDmaChainNoEu((int *)srcAddr, srcIncr,
- destIncr, xferSize,
- xferSizeIncr, cSave,
- MCD_taskTable, channel);
- } else {
- /*TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_CHAINEU].TDTend;
- MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr,
- xferSize, xferSizeIncr, cSave,
- MCD_taskTable, channel);
- }
- }
- MCD_chStatus[channel] = MCD_IDLE;
- return (MCD_OK);
-}
-
-/************************ End of MCD_startDma() *********************/
-
-/********************************************************************/
-/* Function: MCD_XferProgrQuery
- * Purpose: Returns progress of DMA on requested channel
- * Arguments: channel - channel to retrieve progress for
- * progRep - pointer to user supplied MCD_XferProg struct
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * MCD_XferProgrQuery() upon completing or after aborting a DMA, or
- * while the DMA is in progress, this function returns the first
- * DMA-destination address not (or not yet) used in the DMA. When
- * encountering a non-ready buffer descriptor, the information for
- * the last completed descriptor is returned.
- *
- * MCD_XferProgQuery() has to avoid the possibility of getting
- * partially-updated information in the event that we should happen
- * to query DMA progress just as the DMA is updating it. It does that
- * by taking advantage of the fact context is not saved frequently for
- * the most part. We therefore read it at least twice until we get the
- * same information twice in a row.
- *
- * Because a small, but not insignificant, amount of time is required
- * to write out the progress-query information, especially upon
- * completion of the DMA, it would be wise to guarantee some time lag
- * between successive readings of the progress-query information.
- */
-
-/* How many iterations of the loop below to execute to stabilize values */
-#define STABTIME 0
-
-int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep)
-{
- MCD_XferProg prevRep;
- int again; /* true if we are to try again to ge
- consistent results */
- int i; /* used as a time-waste counter */
- int destDiffBytes; /* Total no of bytes that we think actually
- got xfered. */
- int numIterations; /* number of iterations */
- int bytesNotXfered; /* bytes that did not get xfered. */
- s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
- int subModVal, addModVal; /* Mode values to added and subtracted
- from the final destAddr */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- /* Read a trial value for the progress-reporting values */
- prevRep.lastSrcAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
- prevRep.lastDestAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
- prevRep.dmaSize =
- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT +
- CSAVE_OFFSET];
- prevRep.currBufDesc =
- (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET];
- /* Repeatedly reread those values until they match previous values: */
- do {
- /* Waste a little bit of time to ensure stability: */
- for (i = 0; i < STABTIME; i++) {
- /* make sure this loop does something so that it
- doesn't get optimized out */
- i += i >> 2;
- }
- /* Check them again: */
- progRep->lastSrcAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
- progRep->lastDestAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
- progRep->dmaSize =
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
- progRep->currBufDesc =
- (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET];
- /* See if they match: */
- if (prevRep.lastSrcAddr != progRep->lastSrcAddr
- || prevRep.lastDestAddr != progRep->lastDestAddr
- || prevRep.dmaSize != progRep->dmaSize
- || prevRep.currBufDesc != progRep->currBufDesc) {
- /* If they don't match, remember previous values and
- try again: */
- prevRep.lastSrcAddr = progRep->lastSrcAddr;
- prevRep.lastDestAddr = progRep->lastDestAddr;
- prevRep.dmaSize = progRep->dmaSize;
- prevRep.currBufDesc = progRep->currBufDesc;
- again = MCD_TRUE;
- } else
- again = MCD_FALSE;
- } while (again == MCD_TRUE);
-
- /* Update the dCount, srcAddr and destAddr */
- /* To calculate dmaCount, we consider destination address. C
- overs M1,P1,Z for destination */
- switch (MCD_remVariants.remDestRsdIncr[channel]) {
- case MINUS1:
- subModVal =
- ((int)progRep->
- lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
- 1);
- addModVal =
- ((int)progRep->currBufDesc->
- destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
- LWAlignedInitDestAddr =
- (progRep->currBufDesc->destAddr) - addModVal;
- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
- destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
- bytesNotXfered =
- (destDiffBytes / MCD_remVariants.remDestIncr[channel]) *
- (MCD_remVariants.remDestIncr[channel]
- + MCD_remVariants.remXferSize[channel]);
- progRep->dmaSize =
- destDiffBytes - bytesNotXfered + addModVal - subModVal;
- break;
- case ZERO:
- progRep->lastDestAddr = progRep->currBufDesc->destAddr;
- break;
- case PLUS1:
- /* This value has to be subtracted from the final
- calculated dCount. */
- subModVal =
- ((int)progRep->currBufDesc->
- destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
- /* These bytes are already in lastDestAddr. */
- addModVal =
- ((int)progRep->
- lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
- 1);
- LWAlignedInitDestAddr =
- (progRep->currBufDesc->destAddr) - subModVal;
- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
- destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
- numIterations =
- (LWAlignedCurrDestAddr -
- LWAlignedInitDestAddr) /
- MCD_remVariants.remDestIncr[channel];
- bytesNotXfered =
- numIterations * (MCD_remVariants.remDestIncr[channel]
- - MCD_remVariants.remXferSize[channel]);
- progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
- break;
- default:
- break;
- }
-
- /* This covers M1,P1,Z for source */
- switch (MCD_remVariants.remSrcRsdIncr[channel]) {
- case MINUS1:
- progRep->lastSrcAddr =
- progRep->currBufDesc->srcAddr +
- (MCD_remVariants.remSrcIncr[channel] *
- (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
- break;
- case ZERO:
- progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
- break;
- case PLUS1:
- progRep->lastSrcAddr =
- progRep->currBufDesc->srcAddr +
- (MCD_remVariants.remSrcIncr[channel] *
- (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
- break;
- default:
- break;
- }
-
- return (MCD_OK);
-}
-
-/******************* End of MCD_XferProgrQuery() ********************/
-
-/********************************************************************/
-/* MCD_resmActions() does the majority of the actions of a DMA resume.
- * It is called from MCD_killDma() and MCD_resumeDma(). It has to be
- * a separate function because the kill function has to negate the task
- * enable before resuming it, but the resume function has to do nothing
- * if there is no DMA on that channel (i.e., if the enable bit is 0).
- */
-static void MCD_resmActions(int channel)
-{
- MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
- MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
- /* This register is selected to know which initiator is
- actually asserted. */
- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
-
- if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
- MCD_chStatus[channel] = MCD_RUNNING;
- else
- MCD_chStatus[channel] = MCD_IDLE;
-}
-
-/********************* End of MCD_resmActions() *********************/
-
-/********************************************************************/
-/* Function: MCD_killDma
- * Purpose: Halt the DMA on the requested channel, without any
- * intention of resuming the DMA.
- * Arguments: channel - requested channel
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * A DMA may be killed from any state, including paused state, and it
- * always goes to the MCD_HALTED state even if it is killed while in
- * the MCD_NO_DMA or MCD_IDLE states.
- */
-int MCD_killDma(int channel)
-{
- /* MCD_XferProg progRep; */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- MCD_dmaBar->taskControl[channel] = 0x0;
- MCD_resumeDma(channel);
- /*
- * This must be after the write to the TCR so that the task doesn't
- * start up again momentarily, and before the status assignment so
- * as to override whatever MCD_resumeDma() may do to the channel
- * status.
- */
- MCD_chStatus[channel] = MCD_HALTED;
-
- /*
- * Update the current buffer descriptor's lastDestAddr field
- *
- * MCD_XferProgrQuery (channel, &progRep);
- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
- */
- return (MCD_OK);
-}
-
-/************************ End of MCD_killDma() **********************/
-
-/********************************************************************/
-/* Function: MCD_continDma
- * Purpose: Continue a DMA which as stopped due to encountering an
- * unready buffer descriptor.
- * Arguments: channel - channel to continue the DMA on
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * This routine does not check to see if there is a task which can
- * be continued. Also this routine should not be used with single DMAs.
- */
-int MCD_continDma(int channel)
-{
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
- MCD_chStatus[channel] = MCD_RUNNING;
-
- return (MCD_OK);
-}
-
-/********************** End of MCD_continDma() **********************/
-
-/*********************************************************************
- * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
- * to freeze a task and resume it. We freeze a task by breakpointing
- * on the stated task. That is, not any specific place in the task,
- * but any time that task executes. In particular, when that task
- * executes, we want to freeze that task and only that task.
- *
- * The bits of the debug control register influence interrupts vs.
- * breakpoints as follows:
- * - Bits 14 and 0 enable or disable debug functions. If enabled, you
- * will get the interrupt but you may or may not get a breakpoint.
- * - Bits 2 and 1 decide whether you also get a breakpoint in addition
- * to an interrupt.
- *
- * The debug unit can do these actions in response to either internally
- * detected breakpoint conditions from the comparators, or in response
- * to the external breakpoint pin, or both.
- * - Bits 14 and 1 perform the above-described functions for
- * internally-generated conditions, i.e., the debug comparators.
- * - Bits 0 and 2 perform the above-described functions for external
- * conditions, i.e., the breakpoint external pin.
- *
- * Note that, although you "always" get the interrupt when you turn
- * the debug functions, the interrupt can nevertheless, if desired, be
- * masked by the corresponding bit in the PTD's IMR. Note also that
- * this means that bits 14 and 0 must enable debug functions before
- * bits 1 and 2, respectively, have any effect.
- *
- * NOTE: It's extremely important to not pause more than one DMA channel
- * at a time.
- ********************************************************************/
-
-/********************************************************************/
-/* Function: MCD_pauseDma
- * Purpose: Pauses the DMA on a given channel (if any DMA is running
- * on that channel).
- * Arguments: channel
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-int MCD_pauseDma(int channel)
-{
- /* MCD_XferProg progRep; */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) {
- MCD_dmaBar->debugComp1 = channel;
- MCD_dmaBar->debugControl =
- DBG_CTL_ENABLE | (1 << (channel + 16));
- MCD_chStatus[channel] = MCD_PAUSED;
-
- /*
- * Update the current buffer descriptor's lastDestAddr field
- *
- * MCD_XferProgrQuery (channel, &progRep);
- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
- */
- }
- return (MCD_OK);
-}
-
-/************************* End of MCD_pauseDma() ********************/
-
-/********************************************************************/
-/* Function: MCD_resumeDma
- * Purpose: Resumes the DMA on a given channel (if any DMA is
- * running on that channel).
- * Arguments: channel - channel on which to resume DMA
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-int MCD_resumeDma(int channel)
-{
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
- MCD_resmActions(channel);
-
- return (MCD_OK);
-}
-
-/************************ End of MCD_resumeDma() ********************/
-
-/********************************************************************/
-/* Function: MCD_csumQuery
- * Purpose: Provide the checksum after performing a non-chained DMA
- * Arguments: channel - channel to report on
- * csum - pointer to where to write the checksum/CRC
- * Returns: MCD_ERROR if the channel is invalid, else MCD_OK
- *
- * Notes:
- *
- */
-int MCD_csumQuery(int channel, u32 * csum)
-{
-#ifdef MCD_INCLUDE_EU
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- *csum = MCD_relocBuffDesc[channel].csumResult;
- return (MCD_OK);
-#else
- return (MCD_ERROR);
-#endif
-}
-
-/*********************** End of MCD_resumeDma() *********************/
-
-/********************************************************************/
-/* Function: MCD_getCodeSize
- * Purpose: Provide the size requirements of the microcoded tasks
- * Returns: Size in bytes
- */
-int MCD_getCodeSize(void)
-{
-#ifdef MCD_INCLUDE_EU
- return (0x2b5c);
-#else
- return (0x173c);
-#endif
-}
-
-/********************** End of MCD_getCodeSize() ********************/
-
-/********************************************************************/
-/* Function: MCD_getVersion
- * Purpose: Provide the version string and number
- * Arguments: longVersion - user supplied pointer to a pointer to a char
- * which points to the version string
- * Returns: Version number and version string (by reference)
- */
-char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
-#define MCD_REV_MAJOR 0x00
-#define MCD_REV_MINOR 0x03
-
-int MCD_getVersion(char **longVersion)
-{
- *longVersion = MCD_versionString;
- return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
-}
-
-/********************** End of MCD_getVersion() *********************/
-
-/********************************************************************/
-/* Private version of memcpy()
- * Note that everything this is used for is longword-aligned.
- */
-static void MCD_memcpy(int *dest, int *src, u32 size)
-{
- u32 i;
-
- for (i = 0; i < size; i += sizeof(int), dest++, src++)
- *dest = *src;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-/* Contains task code and structures for Multi-channel DMA */
-
-#include <common.h>
-
-#include <MCD_dma.h>
-
-u32 MCD_varTab0[];
-u32 MCD_varTab1[];
-u32 MCD_varTab2[];
-u32 MCD_varTab3[];
-u32 MCD_varTab4[];
-u32 MCD_varTab5[];
-u32 MCD_varTab6[];
-u32 MCD_varTab7[];
-u32 MCD_varTab8[];
-u32 MCD_varTab9[];
-u32 MCD_varTab10[];
-u32 MCD_varTab11[];
-u32 MCD_varTab12[];
-u32 MCD_varTab13[];
-u32 MCD_varTab14[];
-u32 MCD_varTab15[];
-
-u32 MCD_funcDescTab0[];
-#ifdef MCD_INCLUDE_EU
-u32 MCD_funcDescTab1[];
-u32 MCD_funcDescTab2[];
-u32 MCD_funcDescTab3[];
-u32 MCD_funcDescTab4[];
-u32 MCD_funcDescTab5[];
-u32 MCD_funcDescTab6[];
-u32 MCD_funcDescTab7[];
-u32 MCD_funcDescTab8[];
-u32 MCD_funcDescTab9[];
-u32 MCD_funcDescTab10[];
-u32 MCD_funcDescTab11[];
-u32 MCD_funcDescTab12[];
-u32 MCD_funcDescTab13[];
-u32 MCD_funcDescTab14[];
-u32 MCD_funcDescTab15[];
-#endif
-
-u32 MCD_contextSave0[];
-u32 MCD_contextSave1[];
-u32 MCD_contextSave2[];
-u32 MCD_contextSave3[];
-u32 MCD_contextSave4[];
-u32 MCD_contextSave5[];
-u32 MCD_contextSave6[];
-u32 MCD_contextSave7[];
-u32 MCD_contextSave8[];
-u32 MCD_contextSave9[];
-u32 MCD_contextSave10[];
-u32 MCD_contextSave11[];
-u32 MCD_contextSave12[];
-u32 MCD_contextSave13[];
-u32 MCD_contextSave14[];
-u32 MCD_contextSave15[];
-
-u32 MCD_realTaskTableSrc[] = {
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab0, /* Task 0 Variable Table */
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave0, /* Task 0 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab1, /* Task 1 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave1, /* Task 1 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab2, /* Task 2 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave2, /* Task 2 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab3, /* Task 3 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave3, /* Task 3 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab4, /* Task 4 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave4, /* Task 4 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab5, /* Task 5 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave5, /* Task 5 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab6, /* Task 6 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave6, /* Task 6 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab7, /* Task 7 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave7, /* Task 7 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab8, /* Task 8 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave8, /* Task 8 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab9, /* Task 9 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave9, /* Task 9 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab10, /* Task 10 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave10, /* Task 10 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab11, /* Task 11 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave11, /* Task 11 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab12, /* Task 12 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave12, /* Task 12 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab13, /* Task 13 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave13, /* Task 13 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab14, /* Task 14 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave14, /* Task 14 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab15, /* Task 15 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave15, /* Task 15 context save space */
- 0x00000000,
-};
-
-u32 MCD_varTab0[] = { /* Task 0 Variable Table */
- 0x00000000, /* var[0] */
- 0x00000000, /* var[1] */
- 0x00000000, /* var[2] */
- 0x00000000, /* var[3] */
- 0x00000000, /* var[4] */
- 0x00000000, /* var[5] */
- 0x00000000, /* var[6] */
- 0x00000000, /* var[7] */
- 0x00000000, /* var[8] */
- 0x00000000, /* var[9] */
- 0x00000000, /* var[10] */
- 0x00000000, /* var[11] */
- 0x00000000, /* var[12] */
- 0x00000000, /* var[13] */
- 0x00000000, /* var[14] */
- 0x00000000, /* var[15] */
- 0x00000000, /* var[16] */
- 0x00000000, /* var[17] */
- 0x00000000, /* var[18] */
- 0x00000000, /* var[19] */
- 0x00000000, /* var[20] */
- 0x00000000, /* var[21] */
- 0x00000000, /* var[22] */
- 0x00000000, /* var[23] */
- 0xe0000000, /* inc[0] */
- 0x20000000, /* inc[1] */
- 0x2000ffff, /* inc[2] */
- 0x00000000, /* inc[3] */
- 0x00000000, /* inc[4] */
- 0x00000000, /* inc[5] */
- 0x00000000, /* inc[6] */
- 0x00000000, /* inc[7] */
-};
-
-u32 MCD_varTab1[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab2[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab3[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab4[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab5[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab6[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab7[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab8[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab9[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab10[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab11[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab12[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab13[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab14[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab15[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_funcDescTab0[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-#ifdef MCD_INCLUDE_EU
-u32 MCD_funcDescTab1[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab2[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab3[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab4[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab5[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab6[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab7[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab8[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab9[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab10[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab11[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab12[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab13[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab14[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab15[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-#endif /*MCD_INCLUDE_EU */
-
-u32 MCD_contextSave0[128]; /* Task 0 context save space */
-u32 MCD_contextSave1[128]; /* Task 1 context save space */
-u32 MCD_contextSave2[128]; /* Task 2 context save space */
-u32 MCD_contextSave3[128]; /* Task 3 context save space */
-u32 MCD_contextSave4[128]; /* Task 4 context save space */
-u32 MCD_contextSave5[128]; /* Task 5 context save space */
-u32 MCD_contextSave6[128]; /* Task 6 context save space */
-u32 MCD_contextSave7[128]; /* Task 7 context save space */
-u32 MCD_contextSave8[128]; /* Task 8 context save space */
-u32 MCD_contextSave9[128]; /* Task 9 context save space */
-u32 MCD_contextSave10[128]; /* Task 10 context save space */
-u32 MCD_contextSave11[128]; /* Task 11 context save space */
-u32 MCD_contextSave12[128]; /* Task 12 context save space */
-u32 MCD_contextSave13[128]; /* Task 13 context save space */
-u32 MCD_contextSave14[128]; /* Task 14 context save space */
-u32 MCD_contextSave15[128]; /* Task 15 context save space */
-
-u32 MCD_ChainNoEu_TDT[];
-u32 MCD_SingleNoEu_TDT[];
-#ifdef MCD_INCLUDE_EU
-u32 MCD_ChainEu_TDT[];
-u32 MCD_SingleEu_TDT[];
-#endif
-u32 MCD_ENetRcv_TDT[];
-u32 MCD_ENetXmit_TDT[];
-
-u32 MCD_modelTaskTableSrc[] = {
- (u32) MCD_ChainNoEu_TDT,
- (u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_SingleNoEu_TDT,
- (u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_ChainEu_TDT,
- (u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_SingleEu_TDT,
- (u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-#endif
- (u32) MCD_ENetRcv_TDT,
- (u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_ENetXmit_TDT,
- (u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_ChainNoEu_TDT[] = {
- 0x80004000,
- 0x8118801b,
- 0xb8c60018,
- 0x10002b10,
- 0x7000000d,
- 0x018cf89f,
- 0x6000000a,
- 0x080cf89f,
- 0x000001f8,
- 0x98180364,
- 0x8118801b,
- 0xf8c6001a,
- 0xb8c6601b,
- 0x10002710,
- 0x00000f18,
- 0xb8c6001d,
- 0x10001310,
- 0x60000007,
- 0x014cf88b,
- 0x98c6001c,
- 0x00000710,
- 0x98c70018,
- 0x10001f10,
- 0x0000c818,
- 0x000001f8,
- 0xc1476018,
- 0xc003231d,
- 0x811a601b,
- 0xc1862102,
- 0x849be009,
- 0x03fed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x1000cb20,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0xc1476018,
- 0xc003241d,
- 0x811a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc1862102,
- 0x849be009,
- 0x0bfed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x1000cb20,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0x8118801b,
- 0xd8c60018,
- 0x98c6601c,
- 0x6000000b,
- 0x0c8cfc9f,
- 0x000001f8,
- 0xa146001e,
- 0x10000b08,
- 0x10002050,
- 0xb8c60018,
- 0x10002b10,
- 0x7000000a,
- 0x080cf89f,
- 0x6000000d,
- 0x018cf89f,
- 0x000001f8,
- 0x8618801b,
- 0x7000000e,
- 0x084cf21f,
- 0xd8990336,
- 0x8019801b,
- 0x040001f8,
- 0x000001f8,
- 0x000001f8,
-};
-
-u32 MCD_SingleNoEu_TDT[] = {
- 0x8198001b,
- 0x7000000d,
- 0x080cf81f,
- 0x8198801b,
- 0x6000000e,
- 0x084cf85f,
- 0x000001f8,
- 0x8298001b,
- 0x7000000d,
- 0x010cf81f,
- 0x6000000e,
- 0x018cf81f,
- 0xc202601b,
- 0xc002221c,
- 0x809a601b,
- 0xc10420c2,
- 0x839be009,
- 0x03fed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000006,
- 0x088cf889,
- 0x1000cb28,
- 0x70000006,
- 0x088cf889,
- 0x1000cb30,
- 0x70000006,
- 0x088cf889,
- 0x0000cb38,
- 0x000001f8,
- 0xc202601b,
- 0xc002229c,
- 0x809a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc10420c2,
- 0x839be009,
- 0x0bfed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000006,
- 0x088cf889,
- 0x1000cb28,
- 0x70000006,
- 0x088cf889,
- 0x1000cb30,
- 0x70000006,
- 0x088cf889,
- 0x0000cb38,
- 0x000001f8,
- 0xc318022d,
- 0x8018801b,
- 0x040001f8,
-};
-
-#ifdef MCD_INCLUDE_EU
-u32 MCD_ChainEu_TDT[] = {
- 0x80004000,
- 0x8198801b,
- 0xb8c68018,
- 0x10002f10,
- 0x7000000d,
- 0x01ccf89f,
- 0x6000000a,
- 0x080cf89f,
- 0x000001f8,
- 0x981803a4,
- 0x8198801b,
- 0xf8c6801a,
- 0xb8c6e01b,
- 0x10002b10,
- 0x00001318,
- 0xb8c6801d,
- 0x10001710,
- 0x60000007,
- 0x018cf88c,
- 0x98c6801c,
- 0x00000b10,
- 0x98c78018,
- 0x10002310,
- 0x0000c820,
- 0x000001f8,
- 0x8698801b,
- 0x7000000f,
- 0x084cf2df,
- 0xd899042d,
- 0x8019801b,
- 0x60000003,
- 0x2cd7c7df,
- 0xd8990364,
- 0x8019801b,
- 0x60000003,
- 0x2c17c7df,
- 0x000001f8,
- 0xc1c7e018,
- 0xc003a35e,
- 0x819a601b,
- 0xc206a142,
- 0x851be009,
- 0x63fe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf81f,
- 0x1000cb20,
- 0x70000006,
- 0x088cf891,
- 0x1000cb28,
- 0x70000006,
- 0x088cf891,
- 0x1000cb30,
- 0x70000006,
- 0x088cf891,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0xc1c7e018,
- 0xc003a49e,
- 0x819a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc206a142,
- 0x851be009,
- 0x6bfe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf81f,
- 0x1000cb20,
- 0x70000006,
- 0x088cf891,
- 0x1000cb28,
- 0x70000006,
- 0x088cf891,
- 0x1000cb30,
- 0x70000006,
- 0x088cf891,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0x8198801b,
- 0xd8c68018,
- 0x98c6e01c,
- 0x6000000b,
- 0x0c8cfc9f,
- 0x0000cc08,
- 0xa1c6801e,
- 0x10000f08,
- 0x10002458,
- 0xb8c68018,
- 0x10002f10,
- 0x7000000a,
- 0x080cf89f,
- 0x6000000d,
- 0x01ccf89f,
- 0x000001f8,
- 0x8698801b,
- 0x7000000e,
- 0x084cf25f,
- 0xd899037f,
- 0x8019801b,
- 0x040001f8,
- 0x000001f8,
- 0x000001f8,
-};
-
-u32 MCD_SingleEu_TDT[] = {
- 0x8218001b,
- 0x7000000d,
- 0x080cf81f,
- 0x8218801b,
- 0x6000000e,
- 0x084cf85f,
- 0x000001f8,
- 0x8318001b,
- 0x7000000d,
- 0x014cf81f,
- 0x6000000e,
- 0x01ccf81f,
- 0x8498001b,
- 0x7000000f,
- 0x080cf19f,
- 0xd81882a4,
- 0x8019001b,
- 0x60000003,
- 0x2c97c7df,
- 0xd818826d,
- 0x8019001b,
- 0x60000003,
- 0x2c17c7df,
- 0x000001f8,
- 0xc282e01b,
- 0xc002a25e,
- 0x811a601b,
- 0xc184a102,
- 0x841be009,
- 0x63fe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf99f,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88b,
- 0x0000cb38,
- 0x000001f8,
- 0xc282e01b,
- 0xc002a31e,
- 0x811a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc184a102,
- 0x841be009,
- 0x6bfe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf99f,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88b,
- 0x0000cb38,
- 0x000001f8,
- 0x8144801c,
- 0x0000c008,
- 0xc398027f,
- 0x8018801b,
- 0x040001f8,
-};
-#endif
-u32 MCD_ENetRcv_TDT[] = {
- 0x80004000,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0x98180209,
- 0x81c40004,
- 0x7000000e,
- 0x010cf05f,
- 0x7000000c,
- 0x01ccf05f,
- 0x70000004,
- 0x014cf049,
- 0x70000004,
- 0x004cf04a,
- 0x00000b88,
- 0xc4030150,
- 0x8119e012,
- 0x03e0cf90,
- 0x81188000,
- 0x000ac788,
- 0xc4030000,
- 0x8199e000,
- 0x70000004,
- 0x084cfc8b,
- 0x60000005,
- 0x0cccf841,
- 0x81c60000,
- 0xc399021b,
- 0x80198000,
- 0x00008400,
- 0x00000f08,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0xc2188209,
- 0x80190000,
- 0x040001f8,
- 0x000001f8,
-};
-
-u32 MCD_ENetXmit_TDT[] = {
- 0x80004000,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0x98180309,
- 0x80004003,
- 0x81c60004,
- 0x7000000e,
- 0x014cf05f,
- 0x7000000c,
- 0x028cf05f,
- 0x7000000d,
- 0x018cf05f,
- 0x70000004,
- 0x01ccf04d,
- 0x10000b90,
- 0x60000004,
- 0x020cf0a1,
- 0xc3188312,
- 0x83c70000,
- 0x00001f10,
- 0xc583a3c3,
- 0x81042325,
- 0x03e0c798,
- 0xd8990000,
- 0x9999e000,
- 0x000acf98,
- 0xd8992306,
- 0x9999e03f,
- 0x03eac798,
- 0xd8990000,
- 0x9999e000,
- 0x000acf98,
- 0xd8990000,
- 0x99832302,
- 0x0beac798,
- 0x81988000,
- 0x6000000b,
- 0x0c4cfc5f,
- 0x81c80000,
- 0xc5190312,
- 0x80198000,
- 0x00008400,
- 0x00000f08,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0xc2988309,
- 0x80190000,
- 0x040001f8,
- 0x000001f8,
-};
-
-#ifdef MCD_INCLUDE_EU
-MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-/* Functions for initializing variable tables of different types of tasks. */
-
-/*
- * Do not edit!
- */
-
-#include <MCD_dma.h>
-
-extern dmaRegs *MCD_dmaBar;
-
-/* Task 0 */
-
-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 1 */
-
-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */
- MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 2 */
-
-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */
- MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */
- MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 3 */
-
-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */
- MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 4 */
-
-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */
- MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
- MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
- MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 5 */
-
-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */
- MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
- MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
- MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */
- MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
obj-$(CONFIG_DMA) += dma-uclass.o
-obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
+k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .default_flow_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ }, \
+ }
+
+#define PSIL_CSI2RX(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62a_src_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
+ PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
+ PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
+ PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4302),
+ PSIL_PDMA_XY_PKT(0x4303),
+ PSIL_PDMA_XY_PKT(0x4304),
+ PSIL_PDMA_XY_PKT(0x4305),
+ PSIL_PDMA_XY_PKT(0x4306),
+ PSIL_PDMA_XY_PKT(0x4307),
+ PSIL_PDMA_XY_PKT(0x4308),
+ PSIL_PDMA_XY_PKT(0x4309),
+ PSIL_PDMA_XY_PKT(0x430a),
+ PSIL_PDMA_XY_PKT(0x430b),
+ PSIL_PDMA_XY_PKT(0x430c),
+ PSIL_PDMA_XY_PKT(0x430d),
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0x4400),
+ PSIL_PDMA_XY_PKT(0x4401),
+ PSIL_PDMA_XY_PKT(0x4402),
+ PSIL_PDMA_XY_PKT(0x4403),
+ PSIL_PDMA_XY_PKT(0x4404),
+ PSIL_PDMA_XY_PKT(0x4405),
+ PSIL_PDMA_XY_PKT(0x4406),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0x4500),
+ PSIL_PDMA_MCASP(0x4501),
+ PSIL_PDMA_MCASP(0x4502),
+ /* CPSW3G */
+ PSIL_ETHERNET(0x4600, 19, 19, 16),
+ /* CSI2RX */
+ PSIL_CSI2RX(0x5000),
+ PSIL_CSI2RX(0x5001),
+ PSIL_CSI2RX(0x5002),
+ PSIL_CSI2RX(0x5003),
+ PSIL_CSI2RX(0x5004),
+ PSIL_CSI2RX(0x5005),
+ PSIL_CSI2RX(0x5006),
+ PSIL_CSI2RX(0x5007),
+ PSIL_CSI2RX(0x5008),
+ PSIL_CSI2RX(0x5009),
+ PSIL_CSI2RX(0x500a),
+ PSIL_CSI2RX(0x500b),
+ PSIL_CSI2RX(0x500c),
+ PSIL_CSI2RX(0x500d),
+ PSIL_CSI2RX(0x500e),
+ PSIL_CSI2RX(0x500f),
+ PSIL_CSI2RX(0x5010),
+ PSIL_CSI2RX(0x5011),
+ PSIL_CSI2RX(0x5012),
+ PSIL_CSI2RX(0x5013),
+ PSIL_CSI2RX(0x5014),
+ PSIL_CSI2RX(0x5015),
+ PSIL_CSI2RX(0x5016),
+ PSIL_CSI2RX(0x5017),
+ PSIL_CSI2RX(0x5018),
+ PSIL_CSI2RX(0x5019),
+ PSIL_CSI2RX(0x501a),
+ PSIL_CSI2RX(0x501b),
+ PSIL_CSI2RX(0x501c),
+ PSIL_CSI2RX(0x501d),
+ PSIL_CSI2RX(0x501e),
+ PSIL_CSI2RX(0x501f),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62a_dst_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
+ PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0xc302),
+ PSIL_PDMA_XY_PKT(0xc303),
+ PSIL_PDMA_XY_PKT(0xc304),
+ PSIL_PDMA_XY_PKT(0xc305),
+ PSIL_PDMA_XY_PKT(0xc306),
+ PSIL_PDMA_XY_PKT(0xc307),
+ PSIL_PDMA_XY_PKT(0xc308),
+ PSIL_PDMA_XY_PKT(0xc309),
+ PSIL_PDMA_XY_PKT(0xc30a),
+ PSIL_PDMA_XY_PKT(0xc30b),
+ PSIL_PDMA_XY_PKT(0xc30c),
+ PSIL_PDMA_XY_PKT(0xc30d),
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0xc400),
+ PSIL_PDMA_XY_PKT(0xc401),
+ PSIL_PDMA_XY_PKT(0xc402),
+ PSIL_PDMA_XY_PKT(0xc403),
+ PSIL_PDMA_XY_PKT(0xc404),
+ PSIL_PDMA_XY_PKT(0xc405),
+ PSIL_PDMA_XY_PKT(0xc406),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0xc500),
+ PSIL_PDMA_MCASP(0xc501),
+ PSIL_PDMA_MCASP(0xc502),
+ /* CPSW3G */
+ PSIL_ETHERNET(0xc600, 19, 19, 8),
+ PSIL_ETHERNET(0xc601, 20, 27, 8),
+ PSIL_ETHERNET(0xc602, 21, 35, 8),
+ PSIL_ETHERNET(0xc603, 22, 43, 8),
+ PSIL_ETHERNET(0xc604, 23, 51, 8),
+ PSIL_ETHERNET(0xc605, 24, 59, 8),
+ PSIL_ETHERNET(0xc606, 25, 67, 8),
+ PSIL_ETHERNET(0xc607, 26, 75, 8),
+};
+
+struct psil_ep_map am62a_ep_map = {
+ .name = "am62a",
+ .src = am62a_src_ep_map,
+ .src_count = ARRAY_SIZE(am62a_src_ep_map),
+ .dst = am62a_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am62a_dst_ep_map),
+};
extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am64_ep_map;
extern struct psil_ep_map am62_ep_map;
+extern struct psil_ep_map am62a_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
soc_ep_map = &am64_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM625))
soc_ep_map = &am62_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_AM62A7))
+ soc_ep_map = &am62a_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
menu "Fastboot support"
+ depends on CMDLINE
config FASTBOOT
bool
*/
int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
+ int ret;
static const char * const boot_cmds[] = {
[FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader",
[FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot",
if (reason >= FASTBOOT_REBOOT_REASONS_COUNT)
return -EINVAL;
- return bcb_write_reboot_reason(mmc_dev, "misc", boot_cmds[reason]);
+ ret = bcb_find_partition_and_load("mmc", mmc_dev, "misc");
+ if (ret)
+ goto out;
+
+ ret = bcb_set(BCB_FIELD_COMMAND, boot_cmds[reason]);
+ if (ret)
+ goto out;
+
+ ret = bcb_store();
+out:
+ bcb_reset();
+ return ret;
}
/**
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/lists.h>
#include <log.h>
#include <zynqmp_firmware.h>
static int zynqmp_power_probe(struct udevice *dev)
{
+ struct udevice *ipi_dev;
+ ofnode ipi_node;
int ret;
debug("%s, (dev=%p)\n", __func__, dev);
+ /*
+ * Probe all IPI parent node driver. It is important to have IPI
+ * devices available when requested by mbox_get_by* API.
+ * If IPI device isn't available, then mailbox request fails and
+ * that causes system boot failure.
+ * To avoid this make sure all IPI parent drivers are probed here,
+ * and IPI parent driver binds each child node to mailbox driver.
+ * This way mbox_get_by_* API will have correct mailbox device
+ * driver probed.
+ */
+ ofnode_for_each_compatible_node(ipi_node, "xlnx,zynqmp-ipi-mailbox") {
+ ret = uclass_get_device_by_ofnode(UCLASS_NOP, ipi_node, &ipi_dev);
+ if (ret) {
+ dev_err(dev, "failed to get IPI device from node %s\n",
+ ofnode_get_name(ipi_node));
+ return ret;
+ }
+ }
+
ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
if (ret) {
debug("%s: Cannot find tx mailbox\n", __func__);
};
static u8 protocols[] = {
- SCMI_PROTOCOL_ID_POWER_DOMAIN,
- SCMI_PROTOCOL_ID_CLOCK,
- SCMI_PROTOCOL_ID_RESET_DOMAIN,
- SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,
+ CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN, (SCMI_PROTOCOL_ID_POWER_DOMAIN,))
+ CONFIG_IS_ENABLED(CLK_SCMI, (SCMI_PROTOCOL_ID_CLOCK,))
+ CONFIG_IS_ENABLED(RESET_SCMI, (SCMI_PROTOCOL_ID_RESET_DOMAIN,))
+ CONFIG_IS_ENABLED(DM_REGULATOR_SCMI, (SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,))
};
#define NUM_PROTOCOLS ARRAY_SIZE(protocols)
return chan->channel_id;
}
+static int sandbox_proto_not_supported(struct scmi_msg *msg)
+{
+ *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED;
+
+ return 0;
+}
+
static int sandbox_scmi_test_process_msg(struct udevice *dev,
struct scmi_channel *channel,
struct scmi_msg *msg)
}
break;
case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_PROTOCOL_VERSION:
return sandbox_scmi_pwd_protocol_version(dev, msg);
}
break;
case SCMI_PROTOCOL_ID_CLOCK:
+ if (!CONFIG_IS_ENABLED(CLK_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_PROTOCOL_ATTRIBUTES:
return sandbox_scmi_clock_protocol_attribs(dev, msg);
}
break;
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+ if (!CONFIG_IS_ENABLED(RESET_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_RESET_DOMAIN_ATTRIBUTES:
return sandbox_scmi_rd_attribs(dev, msg);
}
break;
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
+ if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_VOLTAGE_DOMAIN_ATTRIBUTES:
return sandbox_scmi_voltd_attribs(dev, msg);
case SCMI_PROTOCOL_ID_SYSTEM:
case SCMI_PROTOCOL_ID_PERF:
case SCMI_PROTOCOL_ID_SENSOR:
- *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED;
- return 0;
+ return sandbox_proto_not_supported(msg);
default:
break;
}
if (!devices)
return 0;
- for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
- int ret2 = reset_free(devices->reset + n);
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+ int ret2 = reset_free(devices->reset + n);
- if (ret2 && !ret)
- ret = ret2;
- }
+ if (ret2 && !ret)
+ ret = ret2;
+ }
return ret;
}
.regul_count = SCMI_TEST_DEVICES_VOLTD_COUNT,
};
- ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0);
- if (ret) {
- dev_err(dev, "%s: Failed on power domain\n", __func__);
- return ret;
- }
-
- for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
- ret = clk_get_by_index(dev, n, priv->devices.clk + n);
+ if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) {
+ ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0);
if (ret) {
- dev_err(dev, "%s: Failed on clk %zu\n", __func__, n);
+ dev_err(dev, "%s: Failed on power domain\n", __func__);
return ret;
}
}
- for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
- ret = reset_get_by_index(dev, n, priv->devices.reset + n);
- if (ret) {
- dev_err(dev, "%s: Failed on reset %zu\n", __func__, n);
- goto err_reset;
+ if (CONFIG_IS_ENABLED(CLK_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
+ ret = clk_get_by_index(dev, n, priv->devices.clk + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on clk %zu\n",
+ __func__, n);
+ return ret;
+ }
}
}
- for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) {
- char name[32];
-
- ret = snprintf(name, sizeof(name), "regul%zu-supply", n);
- assert(ret >= 0 && ret < sizeof(name));
+ if (CONFIG_IS_ENABLED(RESET_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+ ret = reset_get_by_index(dev, n,
+ priv->devices.reset + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on reset %zu\n",
+ __func__, n);
+ goto err_reset;
+ }
+ }
+ }
- ret = device_get_supply_regulator(dev, name,
- priv->devices.regul + n);
- if (ret) {
- dev_err(dev, "%s: Failed on voltd %zu\n", __func__, n);
- goto err_regul;
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) {
+ char name[32];
+
+ ret = snprintf(name, sizeof(name), "regul%zu-supply",
+ n);
+ assert(ret >= 0 && ret < sizeof(name));
+
+ ret = device_get_supply_regulator(dev, name,
+ priv->devices.regul
+ + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on voltd %zu\n",
+ __func__, n);
+ goto err_regul;
+ }
}
}
err_regul:
n = SCMI_TEST_DEVICES_RD_COUNT;
err_reset:
- for (; n > 0; n--)
- reset_free(priv->devices.reset + n - 1);
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ for (; n > 0; n--)
+ reset_free(priv->devices.reset + n - 1);
return ret;
}
original maxim device has 8 push/pull outputs,
some clones offers 16bit.
+config MAX77663_GPIO
+ bool "MAX77663 GPIO cell of PMIC driver"
+ depends on DM_GPIO && DM_PMIC_MAX77663
+ help
+ GPIO driver for MAX77663 PMIC from Maxim Semiconductor.
+ MAX77663 PMIC has 8 pins that can be configured as GPIOs
+ and 3 GPIO-like pins dedicated for power/reset buttons
+ and LID sensor.
+
config MCP230XX_GPIO
bool "MCP230XX GPIO driver"
depends on DM
help
Say yes here to support Vybrid vf610 GPIOs.
+config PALMAS_GPIO
+ bool "TI PALMAS series PMICs GPIO"
+ depends on DM_GPIO && PMIC_PALMAS
+ help
+ Select this option to enable GPIO driver for the TI PALMAS
+ series chip family.
+
config PIC32_GPIO
bool "Microchip PIC32 GPIO driver"
depends on DM_GPIO && MACH_PIC32
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
+obj-$(CONFIG_$(SPL_)PALMAS_GPIO) += palmas_gpio.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
+obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o
obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
* DesignWare APB GPIO driver
*/
-#include <common.h>
-#include <log.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <dm.h>
+#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
-#include <dm/lists.h>
-#include <dm/root.h>
+#include <dm/read.h>
#include <errno.h>
#include <reset.h>
-#include <linux/bitops.h>
#define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc)
#define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc)
#include <asm/gpio.h>
#include <config.h>
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/io.h>
ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
&desc->dev);
if (ret) {
+#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO)
+ struct udevice *pmic;
+ ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node,
+ &pmic);
+ if (ret) {
+ log_debug("%s: PMIC device get failed, err %d\n",
+ __func__, ret);
+ goto err;
+ }
+
+ device_foreach_child(desc->dev, pmic) {
+ if (device_get_uclass_id(desc->dev) == UCLASS_GPIO)
+ break;
+ }
+
+ /* if loop exits without GPIO device return error */
+ if (device_get_uclass_id(desc->dev) != UCLASS_GPIO)
+ goto err;
+#else
debug("%s: uclass_get_device_by_ofnode failed\n",
__func__);
goto err;
+#endif
}
}
ret = gpio_find_and_xlate(desc, args);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <asm/gpio.h>
+#include <power/max77663.h>
+#include <power/pmic.h>
+
+#define NUM_ENTRIES 11 /* 8 GPIOs + 3 KEYs */
+#define NUM_GPIOS 8
+
+#define MAX77663_CNFG1_GPIO 0x36
+#define GPIO_REG_ADDR(offset) (MAX77663_CNFG1_GPIO + (offset))
+
+#define MAX77663_CNFG_GPIO_DIR_MASK BIT(1)
+#define MAX77663_CNFG_GPIO_DIR_INPUT BIT(1)
+#define MAX77663_CNFG_GPIO_DIR_OUTPUT 0
+#define MAX77663_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
+#define MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
+#define MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
+#define MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW 0
+#define MAX77663_CNFG_IRQ GENMASK(5, 4)
+
+#define MAX77663_ONOFFSTAT_REG 0x15
+#define EN0 BIT(2) /* KEY 2 */
+#define ACOK BIT(1) /* KEY 1 */
+#define LID BIT(0) /* KEY 0 */
+
+static int max77663_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ int ret;
+
+ if (offset >= NUM_GPIOS)
+ return 0;
+
+ ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
+ MAX77663_CNFG_GPIO_DIR_MASK,
+ MAX77663_CNFG_GPIO_DIR_INPUT);
+ if (ret < 0)
+ log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int max77663_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ u8 val;
+ int ret;
+
+ if (offset >= NUM_GPIOS)
+ return -EINVAL;
+
+ val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
+ MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0) {
+ log_debug("%s: CNFG_GPIOx val update failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
+ MAX77663_CNFG_GPIO_DIR_MASK,
+ MAX77663_CNFG_GPIO_DIR_OUTPUT);
+ if (ret < 0)
+ log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int max77663_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ int ret;
+
+ if (offset >= NUM_GPIOS) {
+ ret = pmic_reg_read(dev->parent, MAX77663_ONOFFSTAT_REG);
+ if (ret < 0) {
+ log_debug("%s: ONOFFSTAT_REG read failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return !!(ret & BIT(offset - NUM_GPIOS));
+ }
+
+ ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset));
+ if (ret < 0) {
+ log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (ret & MAX77663_CNFG_GPIO_DIR_MASK)
+ return !!(ret & MAX77663_CNFG_GPIO_INPUT_VAL_MASK);
+ else
+ return !!(ret & MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK);
+}
+
+static int max77663_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ u8 val;
+ int ret;
+
+ if (offset >= NUM_GPIOS)
+ return -EINVAL;
+
+ val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset),
+ MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0)
+ log_debug("%s: CNFG_GPIO_OUT update failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int max77663_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ int ret;
+
+ if (offset >= NUM_GPIOS)
+ return GPIOF_INPUT;
+
+ ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset));
+ if (ret < 0) {
+ log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (ret & MAX77663_CNFG_GPIO_DIR_MASK)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops max77663_gpio_ops = {
+ .direction_input = max77663_gpio_direction_input,
+ .direction_output = max77663_gpio_direction_output,
+ .get_value = max77663_gpio_get_value,
+ .set_value = max77663_gpio_set_value,
+ .get_function = max77663_gpio_get_function,
+};
+
+static int max77663_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int i, ret;
+
+ uc_priv->gpio_count = NUM_ENTRIES;
+ uc_priv->bank_name = "GPIO";
+
+ /*
+ * GPIO interrupts may be left ON after bootloader, hence let's
+ * pre-initialize hardware to the expected state by disabling all
+ * the interrupts.
+ */
+ for (i = 0; i < NUM_GPIOS; i++) {
+ ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(i),
+ MAX77663_CNFG_IRQ, 0);
+ if (ret < 0) {
+ log_debug("%s: failed to disable interrupt: %d\n", __func__, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(max77663_gpio) = {
+ .name = MAX77663_GPIO_DRIVER,
+ .id = UCLASS_GPIO,
+ .probe = max77663_gpio_probe,
+ .ops = &max77663_gpio_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on mainline Linux palmas GPIO driver
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <power/palmas.h>
+
+#define NUM_GPIOS 8
+
+static int palmas_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ u32 reg;
+ int ret;
+
+ reg = (value) ? PALMAS_GPIO_SET_DATA_OUT : PALMAS_GPIO_CLEAR_DATA_OUT;
+
+ ret = dm_i2c_reg_write(priv->chip2, reg, BIT(offset));
+ if (ret < 0)
+ log_debug("%s: Reg 0x%02x write failed, %d\n", __func__, reg, ret);
+
+ return ret;
+}
+
+static int palmas_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ u32 reg;
+ int ret;
+
+ ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR);
+ if (ret < 0) {
+ log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (ret & BIT(offset))
+ reg = PALMAS_GPIO_DATA_OUT;
+ else
+ reg = PALMAS_GPIO_DATA_IN;
+
+ ret = dm_i2c_reg_read(priv->chip2, reg);
+ if (ret < 0) {
+ log_debug("%s: Reg 0x%02x read failed, %d\n", __func__, reg, ret);
+ return ret;
+ }
+
+ return !!(ret & BIT(offset));
+}
+
+static int palmas_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ int ret;
+
+ ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR,
+ BIT(offset), 0);
+ if (ret < 0)
+ log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int palmas_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ int ret;
+
+ /* Set the initial value */
+ palmas_gpio_set_value(dev, offset, value);
+
+ ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR,
+ BIT(offset), BIT(offset));
+ if (ret < 0)
+ log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int palmas_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct palmas_priv *priv = dev_get_priv(dev->parent);
+ int ret;
+
+ ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR);
+ if (ret < 0) {
+ log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (ret & BIT(offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops palmas_gpio_ops = {
+ .direction_input = palmas_gpio_direction_input,
+ .direction_output = palmas_gpio_direction_output,
+ .get_value = palmas_gpio_get_value,
+ .set_value = palmas_gpio_set_value,
+ .get_function = palmas_gpio_get_function,
+};
+
+static int palmas_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = NUM_GPIOS;
+ uc_priv->bank_name = "GPIO";
+
+ return 0;
+}
+
+static const struct udevice_id palmas_ids[] = {
+ { .compatible = "ti,palmas-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(palmas_gpio) = {
+ .name = PALMAS_GPIO_DRIVER,
+ .id = UCLASS_GPIO,
+ .of_match = palmas_ids,
+ .probe = palmas_gpio_probe,
+ .ops = &palmas_gpio_ops,
+};
#include <linux/err.h>
#include <linux/io.h>
#include <linux/printk.h>
+#include <linux/time.h>
/* STM32 I2C registers */
struct stm32_i2c_regs {
#define STM32_SCLH_MAX BIT(8)
#define STM32_SCLL_MAX BIT(8)
-#define STM32_NSEC_PER_SEC 1000000000L
-
/**
* struct stm32_i2c_spec - private i2c specification timing
* @rate: I2C bus speed (Hz)
struct stm32_i2c_timings *s)
{
struct stm32_i2c_timings *v;
- u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+ u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
setup->speed_freq);
u32 clk_error_prev = i2cbus;
u32 clk_min, clk_max;
dnf_delay = setup->dnf * i2cclk;
tsync = af_delay_min + dnf_delay + (2 * i2cclk);
- clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
- clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
+ clk_max = NSEC_PER_SEC / specs->rate_min;
+ clk_min = NSEC_PER_SEC / specs->rate_max;
/*
* Among Prescaler possibilities discovered above figures out SCL Low
const struct stm32_i2c_spec *specs;
struct stm32_i2c_timings *v, *_v;
struct list_head solutions;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
+ u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->clock_src);
int ret;
specs = get_specs(setup->speed_freq);
configuration to put the DART into bypass mode such that it can
be used transparently by U-Boot.
+config QCOM_HYP_SMMU
+ bool "Qualcomm quirky SMMU support"
+ depends on IOMMU && ARCH_SNAPDRAGON
+ help
+ Enable support for the Qualcomm variant of the Arm System MMU-500.
+ Qualcomm boards have a non-standard SMMU where some registers are
+ emulated by the hypervisor. It is initialised early in the boot
+ process and can't be turned off.
+
+ The main caveat with this hardware is that it doesn't support BYPASS
+ streams, attempting to configure once will instead wind up with a
+ FAULT stream, and the device will crash when DMA is attempted.
+
+ Say Y here to enable support for non-boot peripherals like USB by
+ configuring identity mapped streams for them.
+
endmenu
obj-$(CONFIG_APPLE_DART) += apple_dart.o
obj-$(CONFIG_SANDBOX) += sandbox_iommu.o
+obj-$(CONFIG_QCOM_HYP_SMMU) += qcom-hyp-smmu.o
{
struct ofnode_phandle_args args;
struct udevice *dev_iommu;
+ const struct iommu_ops *ops;
int i, count, ret = 0;
count = dev_count_phandle_with_args(dev, "iommus",
return ret;
}
dev->iommu = dev_iommu;
+
+ if (dev->parent && dev->parent->iommu == dev_iommu)
+ continue;
+
+ ops = device_get_ops(dev->iommu);
+ if (ops && ops->connect) {
+ ret = ops->connect(dev);
+ if (ret)
+ return ret;
+ }
}
- if (CONFIG_IS_ENABLED(PCI) && count < 0 &&
- device_is_on_pci_bus(dev))
+#if CONFIG_IS_ENABLED(PCI)
+ if (count < 0 && device_is_on_pci_bus(dev))
return dev_pci_iommu_enable(dev);
+#endif
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Basic ARM SMMU-500 driver, assuming a pre-initialised SMMU and only IDENTITY domains
+ * this driver only implements the bare minimum to configure stream mappings for periphals
+ * used by u-boot on platforms where the SMMU can't be disabled.
+ */
+
+#include <log.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <iommu.h>
+#include <linux/bitfield.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <lmb.h>
+#include <memalign.h>
+#include <asm/io.h>
+
+#define ARM_SMMU_GR0 0
+#define ARM_SMMU_GR1 1
+
+#define ARM_SMMU_GR0_ID0 0x20
+#define ARM_SMMU_ID0_NUMSMRG GENMASK(7, 0) /* Number of stream mapping groups */
+#define ARM_SMMU_GR0_ID1 0x24
+#define ARM_SMMU_ID1_PAGESIZE \
+ BIT(31) /* Page shift is 16 bits when set, otherwise 23 */
+#define ARM_SMMU_ID1_NUMPAGENDXB \
+ GENMASK(30, 28) /* Number of pages before context banks */
+#define ARM_SMMU_ID1_NUMCB GENMASK(7, 0) /* Number of context banks supported */
+
+#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
+#define ARM_SMMU_CBAR_TYPE GENMASK(17, 16)
+#define ARM_SMMU_CBAR_VMID GENMASK(7, 0)
+enum arm_smmu_cbar_type {
+ CBAR_TYPE_S2_TRANS,
+ CBAR_TYPE_S1_TRANS_S2_BYPASS,
+ CBAR_TYPE_S1_TRANS_S2_FAULT,
+ CBAR_TYPE_S1_TRANS_S2_TRANS,
+};
+
+#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
+#define ARM_SMMU_CBA2R_VA64 BIT(0)
+
+/* Per-CB system control register */
+#define ARM_SMMU_CB_SCTLR 0x0
+#define ARM_SMMU_SCTLR_CFCFG BIT(7) /* Stall on context fault */
+#define ARM_SMMU_SCTLR_CFIE BIT(6) /* Context fault interrupt enable */
+#define ARM_SMMU_SCTLR_CFRE BIT(5) /* Abort on context fault */
+
+/* Translation Table Base, holds address of translation table in memory to be used
+ * for this context bank. Or 0 for bypass
+ */
+#define ARM_SMMU_CB_TTBR0 0x20
+#define ARM_SMMU_CB_TTBR1 0x28
+/* Translation Control Register, configured TTBR/TLB behaviour (0 for bypass) */
+#define ARM_SMMU_CB_TCR 0x30
+/* Memory Attribute Indirection, also 0 for bypass */
+#define ARM_SMMU_CB_S1_MAIR0 0x38
+#define ARM_SMMU_CB_S1_MAIR1 0x3c
+
+#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
+#define ARM_SMMU_SMR_VALID BIT(31)
+#define ARM_SMMU_SMR_MASK GENMASK(31, 16) // Always 0 for now??
+#define ARM_SMMU_SMR_ID GENMASK(15, 0)
+
+#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
+#define ARM_SMMU_S2CR_PRIVCFG GENMASK(25, 24)
+
+enum arm_smmu_s2cr_privcfg {
+ S2CR_PRIVCFG_DEFAULT,
+ S2CR_PRIVCFG_DIPAN,
+ S2CR_PRIVCFG_UNPRIV,
+ S2CR_PRIVCFG_PRIV,
+};
+
+#define ARM_SMMU_S2CR_TYPE GENMASK(17, 16)
+
+enum arm_smmu_s2cr_type {
+ S2CR_TYPE_TRANS,
+ S2CR_TYPE_BYPASS,
+ S2CR_TYPE_FAULT,
+};
+
+#define ARM_SMMU_S2CR_EXIDVALID BIT(10)
+#define ARM_SMMU_S2CR_CBNDX GENMASK(7, 0)
+
+#define VMID_UNUSED 0xff
+
+struct qcom_smmu_priv {
+ phys_addr_t base;
+ struct list_head devices;
+ struct udevice *dev;
+
+ /* Read-once config */
+ int num_cb;
+ int num_smr;
+ u32 pgshift;
+ u32 cb_pg_offset;
+};
+
+struct mmu_dev {
+ struct list_head li;
+ struct udevice *dev;
+ u16 sid;
+ u16 cbx;
+ u16 smr;
+};
+
+#define page_addr(priv, page) ((priv)->base + ((page) << (priv)->pgshift))
+
+#define smmu_readl(priv, page, offset) readl(page_addr(priv, page) + offset)
+#define gr0_readl(priv, offset) smmu_readl(priv, ARM_SMMU_GR0, offset)
+#define gr1_readl(priv, offset) smmu_readl(priv, ARM_SMMU_GR1, offset)
+#define cbx_readl(priv, cbx, offset) \
+ smmu_readl(priv, (priv->cb_pg_offset) + cbx, offset)
+
+#define smmu_writel(priv, page, offset, value) \
+ writel((value), page_addr(priv, page) + offset)
+#define gr0_writel(priv, offset, value) \
+ smmu_writel(priv, ARM_SMMU_GR0, offset, (value))
+#define gr1_writel(priv, offset, value) \
+ smmu_writel(priv, ARM_SMMU_GR1, offset, (value))
+#define cbx_writel(priv, cbx, offset, value) \
+ smmu_writel(priv, (priv->cb_pg_offset) + cbx, offset, value)
+
+#define gr1_setbits(priv, offset, value) \
+ gr1_writel(priv, offset, gr1_readl(priv, offset) | (value))
+
+static int get_stream_id(struct udevice *dev)
+{
+ ofnode node = dev_ofnode(dev);
+ struct ofnode_phandle_args args;
+ int count = ofnode_parse_phandle_with_args(node, "iommus",
+ "#iommu-cells", 0, 0, &args);
+
+ if (count < 0 || args.args[0] == 0) {
+ printf("Error: %s: iommus property not found or wrong number of cells\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return args.args[0]; // Some mask from bit 16 onward?
+}
+
+static struct mmu_dev *alloc_dev(struct udevice *dev)
+{
+ struct qcom_smmu_priv *priv = dev_get_priv(dev->iommu);
+ struct mmu_dev *mmu_dev;
+ int sid;
+
+ sid = get_stream_id(dev);
+ debug("%s %s has SID %#x\n", dev->iommu->name, dev->name, sid);
+ if (sid < 0 || sid > 0xffff) {
+ printf("\tSMMU: Invalid stream ID for %s\n", dev->name);
+ return ERR_PTR(-EINVAL);
+ }
+
+ /* We only support a single SID per device for now */
+ list_for_each_entry(mmu_dev, &priv->devices, li) {
+ if (mmu_dev->sid == sid)
+ return ERR_PTR(-EEXIST);
+ }
+
+ mmu_dev = calloc(sizeof(*mmu_dev), 1);
+ if (!mmu_dev)
+ return ERR_PTR(-ENOMEM);
+
+ mmu_dev->dev = dev;
+ mmu_dev->sid = sid;
+
+ list_add_tail(&mmu_dev->li, &priv->devices);
+
+ return mmu_dev;
+}
+
+/* Find and init the first free context bank */
+static int alloc_cb(struct qcom_smmu_priv *priv)
+{
+ u32 cbar, type, vmid, val;
+
+ for (int i = 0; i < priv->num_cb; i++) {
+ cbar = gr1_readl(priv, ARM_SMMU_GR1_CBAR(i));
+ type = FIELD_GET(ARM_SMMU_CBAR_TYPE, cbar);
+ vmid = FIELD_GET(ARM_SMMU_CBAR_VMID, cbar);
+
+ /* Check that the context bank is available. We haven't reset the SMMU so
+ * we just make a best guess.
+ */
+ if (type != CBAR_TYPE_S2_TRANS &&
+ (type != CBAR_TYPE_S1_TRANS_S2_BYPASS ||
+ vmid != VMID_UNUSED))
+ continue;
+
+ debug("%s: Found free context bank %d (cbar %#x)\n",
+ priv->dev->name, i, cbar);
+ type = CBAR_TYPE_S1_TRANS_S2_BYPASS;
+ vmid = 0;
+ cbar &= ~ARM_SMMU_CBAR_TYPE & ~ARM_SMMU_CBAR_VMID;
+ cbar |= FIELD_PREP(ARM_SMMU_CBAR_TYPE, type) |
+ FIELD_PREP(ARM_SMMU_CBAR_VMID, vmid);
+ gr1_writel(priv, ARM_SMMU_GR1_CBAR(i), cbar);
+
+ val = IS_ENABLED(CONFIG_ARM64) == 1 ? ARM_SMMU_CBA2R_VA64 : 0;
+ gr1_setbits(priv, ARM_SMMU_GR1_CBA2R(i), val);
+ return i;
+ }
+
+ return -1;
+}
+
+/* Search for a context bank that is already configured for this stream
+ * returns the context bank index or -ENOENT
+ */
+static int find_smr(struct qcom_smmu_priv *priv, u16 stream_id)
+{
+ u32 val;
+ int i;
+
+ for (i = 0; i < priv->num_smr; i++) {
+ val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i));
+ if (!(val & ARM_SMMU_SMR_VALID) ||
+ FIELD_GET(ARM_SMMU_SMR_ID, val) != stream_id)
+ continue;
+
+ return i;
+ }
+
+ return -ENOENT;
+}
+
+static int configure_smr_s2cr(struct qcom_smmu_priv *priv, struct mmu_dev *mdev)
+{
+ u32 val;
+ int i;
+
+ for (i = 0; i < priv->num_smr; i++) {
+ /* Configure SMR */
+ val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i));
+ if (val & ARM_SMMU_SMR_VALID)
+ continue;
+
+ val = mdev->sid | ARM_SMMU_SMR_VALID;
+ gr0_writel(priv, ARM_SMMU_GR0_SMR(i), val);
+
+ /*
+ * WARNING: Don't change this to use S2CR_TYPE_BYPASS!
+ * Some Qualcomm boards have angry hypervisor firmware
+ * that converts S2CR type BYPASS to type FAULT on write.
+ * We don't use virtual addressing for these boards in
+ * u-boot so we can get away with using S2CR_TYPE_TRANS
+ * instead
+ */
+ val = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_TRANS) |
+ FIELD_PREP(ARM_SMMU_S2CR_CBNDX, mdev->cbx);
+ gr0_writel(priv, ARM_SMMU_GR0_S2CR(i), val);
+
+ mdev->smr = i;
+ break;
+ }
+
+ /* Make sure our writes went through */
+ mb();
+
+ return 0;
+}
+
+static int qcom_smmu_connect(struct udevice *dev)
+{
+ struct mmu_dev *mdev;
+ struct qcom_smmu_priv *priv;
+ int ret;
+
+ debug("%s: %s -> %s\n", __func__, dev->name, dev->iommu->name);
+
+ priv = dev_get_priv(dev->iommu);
+ if (WARN_ON(!priv))
+ return -EINVAL;
+
+ mdev = alloc_dev(dev);
+ if (IS_ERR(mdev) && PTR_ERR(mdev) != -EEXIST) {
+ printf("%s: %s Couldn't create mmu context\n", __func__,
+ dev->name);
+ return PTR_ERR(mdev);
+ } else if (IS_ERR(mdev)) { // -EEXIST
+ return 0;
+ }
+
+ if (find_smr(priv, mdev->sid) >= 0) {
+ debug("Found existing context bank for %s, skipping init\n",
+ dev->name);
+ return 0;
+ }
+
+ ret = alloc_cb(priv);
+ if (ret < 0 || ret > 0xff) {
+ printf("Error: %s: failed to allocate context bank for %s\n",
+ __func__, dev->name);
+ return 0;
+ }
+ mdev->cbx = ret;
+
+ /* Configure context bank registers */
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TTBR0, 0x0);
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TTBR1, 0x0);
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_S1_MAIR0, 0x0);
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_S1_MAIR1, 0x0);
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_SCTLR,
+ ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
+ ARM_SMMU_SCTLR_CFCFG);
+ cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TCR, 0x0);
+
+ /* Ensure that our writes went through */
+ mb();
+
+ configure_smr_s2cr(priv, mdev);
+
+ return 0;
+}
+
+#ifdef DEBUG
+static inline void dump_boot_mappings(struct arm_smmu_priv *priv)
+{
+ u32 val;
+ int i;
+
+ debug(" SMMU dump boot mappings:\n");
+ for (i = 0; i < priv->num_smr; i++) {
+ val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i));
+ if (val & ARM_SMMU_SMR_VALID)
+ debug("\tSMR %3d: SID: %#lx\n", i,
+ FIELD_GET(ARM_SMMU_SMR_ID, val));
+ }
+}
+#else
+#define dump_boot_mappings(priv) \
+ do { \
+ } while (0)
+#endif
+
+static int qcom_smmu_probe(struct udevice *dev)
+{
+ struct qcom_smmu_priv *priv;
+ u32 val;
+
+ priv = dev_get_priv(dev);
+ priv->dev = dev;
+ priv->base = dev_read_addr(dev);
+ INIT_LIST_HEAD(&priv->devices);
+
+ /* Read SMMU config */
+ val = gr0_readl(priv, ARM_SMMU_GR0_ID0);
+ priv->num_smr = FIELD_GET(ARM_SMMU_ID0_NUMSMRG, val);
+
+ val = gr0_readl(priv, ARM_SMMU_GR0_ID1);
+ priv->num_cb = FIELD_GET(ARM_SMMU_ID1_NUMCB, val);
+ priv->pgshift = FIELD_GET(ARM_SMMU_ID1_PAGESIZE, val) ? 16 : 12;
+ priv->cb_pg_offset = 1
+ << (FIELD_GET(ARM_SMMU_ID1_NUMPAGENDXB, val) + 1);
+
+ dump_boot_mappings(priv);
+
+ return 0;
+}
+
+static int qcom_smmu_remove(struct udevice *dev)
+{
+ (void)dev;
+ /*
+ * We should probably try and de-configure things here,
+ * however I'm yet to find a way to do it without crashing
+ * and it seems like Linux doesn't care at all anyway.
+ */
+
+ return 0;
+}
+
+static struct iommu_ops qcom_smmu_ops = {
+ .connect = qcom_smmu_connect,
+};
+
+static const struct udevice_id qcom_smmu500_ids[] = {
+ { .compatible = "qcom,sdm845-smmu-500" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(qcom_smmu500) = {
+ .name = "qcom_smmu500",
+ .id = UCLASS_IOMMU,
+ .of_match = qcom_smmu500_ids,
+ .priv_auto = sizeof(struct qcom_smmu_priv),
+ .ops = &qcom_smmu_ops,
+ .probe = qcom_smmu_probe,
+ .remove = qcom_smmu_remove,
+ .flags = DM_FLAG_OS_PREPARE,
+};
This option enables support for LEDs connected to the Cortina
Access CAxxxx SOCs.
+config LED_LP5562
+ bool "LED Support for LP5562"
+ depends on LED && DM_I2C
+ help
+ This option enables support for LEDs connected to the TI LP5562
+ 4 channel I2C LED controller. Driver fully supports blink on the
+ B/G/R LEDs. White LED can blink, but re-uses the period from blue.
+
config LED_PWM
bool "LED PWM"
depends on LED && DM_PWM
obj-$(CONFIG_LED_PWM) += led_pwm.o
obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
obj-$(CONFIG_LED_CORTINA) += led_cortina.o
+obj-$(CONFIG_LED_LP5562) += led_lp5562.o
#include <errno.h>
#include <led.h>
#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
+int led_bind_generic(struct udevice *parent, const char *driver_name)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ ret = device_bind_driver_to_node(parent, driver_name,
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int led_get_by_label(const char *label, struct udevice **devp)
{
struct udevice *dev;
struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
- uc_plat->label = dev_read_string(dev, "label");
if (!uc_plat->label)
+ uc_plat->label = dev_read_string(dev, "label");
+
+ if (!uc_plat->label && !dev_read_string(dev, "compatible"))
uc_plat->label = ofnode_get_name(dev_ofnode(dev));
uc_plat->default_state = LEDST_COUNT;
#include <log.h>
#include <malloc.h>
#include <asm/gpio.h>
-#include <dm/lists.h>
struct led_gpio_priv {
struct gpio_desc gpio;
static int led_gpio_bind(struct udevice *parent)
{
- struct udevice *dev;
- ofnode node;
- int ret;
-
- dev_for_each_subnode(node, parent) {
- ret = device_bind_driver_to_node(parent, "gpio_led",
- ofnode_get_name(node),
- node, &dev);
- if (ret)
- return ret;
- }
-
- return 0;
+ return led_bind_generic(parent, "gpio_led");
}
static const struct led_ops gpio_led_ops = {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Doug Zobel <douglas.zobel@climate.com>
+ *
+ * Driver for TI lp5562 4 channel LED driver. There are only 3
+ * engines available for the 4 LEDs, so white and blue LEDs share
+ * the same engine. This means that the blink period is shared
+ * between them. Changing the period of blue blink will affect
+ * the white period (and vice-versa). Blue and white On/Off
+ * states remain independent (as would PWM brightness if that's
+ * ever added to the LED core).
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+#define DEFAULT_CURRENT 100 /* 10 mA */
+#define MIN_BLINK_PERIOD 32 /* ms */
+#define MAX_BLINK_PERIOD 2248 /* ms */
+
+/* Register Map */
+#define REG_ENABLE 0x00
+#define REG_OP_MODE 0x01
+#define REG_B_PWM 0x02
+#define REG_G_PWM 0x03
+#define REG_R_PWM 0x04
+#define REG_B_CUR 0x05
+#define REG_G_CUR 0x06
+#define REG_R_CUR 0x07
+#define REG_CONFIG 0x08
+#define REG_ENG1_PC 0x09
+#define REG_ENG2_PC 0x0A
+#define REG_ENG3_PC 0x0B
+#define REG_STATUS 0x0C
+#define REG_RESET 0x0D
+#define REG_W_PWM 0x0E
+#define REG_W_CUR 0x0F
+#define REG_ENG1_MEM_BEGIN 0x10
+#define REG_ENG2_MEM_BEGIN 0x30
+#define REG_ENG3_MEM_BEGIN 0x50
+#define REG_LED_MAP 0x70
+
+/* LED Register Values */
+/* 0x00 ENABLE */
+#define REG_ENABLE_CHIP_ENABLE (0x1 << 6)
+#define REG_ENABLE_ENG_EXEC_HOLD 0x0
+#define REG_ENABLE_ENG_EXEC_RUN 0x2
+#define REG_ENABLE_ENG_EXEC_MASK 0x3
+
+/* 0x01 OP MODE */
+#define REG_OP_MODE_DISABLED 0x0
+#define REG_OP_MODE_LOAD_SRAM 0x1
+#define REG_OP_MODE_RUN 0x2
+#define REG_OP_MODE_MASK 0x3
+
+/* 0x02, 0x03, 0x04, 0x0E PWM */
+#define REG_PWM_MIN_VALUE 0
+#define REG_PWM_MAX_VALUE 0xFF
+
+/* 0x08 CONFIG */
+#define REG_CONFIG_EXT_CLK 0x0
+#define REG_CONFIG_INT_CLK 0x1
+#define REG_CONFIG_AUTO_CLK 0x2
+#define REG_CONFIG_CLK_MASK 0x3
+
+/* 0x0D RESET */
+#define REG_RESET_RESET 0xFF
+
+/* 0x70 LED MAP */
+#define REG_LED_MAP_ENG_MASK 0x03
+#define REG_LED_MAP_W_ENG_SHIFT 6
+#define REG_LED_MAP_R_ENG_SHIFT 4
+#define REG_LED_MAP_G_ENG_SHIFT 2
+#define REG_LED_MAP_B_ENG_SHIFT 0
+
+/* Engine program related */
+#define REG_ENGINE_MEM_SIZE 0x20
+#define LED_PGRM_RAMP_INCREMENT_SHIFT 0
+#define LED_PGRM_RAMP_SIGN_SHIFT 7
+#define LED_PGRM_RAMP_STEP_SHIFT 8
+#define LED_PGRM_RAMP_PRESCALE_SHIFT 14
+
+struct lp5562_led_wrap_priv {
+ struct gpio_desc enable_gpio;
+};
+
+struct lp5562_led_priv {
+ u8 reg_pwm;
+ u8 reg_current;
+ u8 map_shift;
+ u8 enginenum;
+};
+
+/* enum values map to LED_MAP (0x70) values */
+enum lp5562_led_ctl_mode {
+ I2C = 0x0,
+#ifdef CONFIG_LED_BLINK
+ ENGINE1 = 0x1,
+ ENGINE2 = 0x2,
+ ENGINE3 = 0x3
+#endif
+};
+
+/*
+ * Update a register value
+ * dev - I2C udevice (parent of led)
+ * regnum - register number to update
+ * value - value to write to register
+ * mask - mask of bits that should be changed
+ */
+static int lp5562_led_reg_update(struct udevice *dev, int regnum,
+ u8 value, u8 mask)
+{
+ int ret;
+
+ if (mask == 0xFF)
+ ret = dm_i2c_reg_write(dev, regnum, value);
+ else
+ ret = dm_i2c_reg_clrset(dev, regnum, mask, value);
+
+
+ /*
+ * Data sheet says "Delay between consecutive I2C writes to
+ * ENABLE register (00h) need to be longer than 488 μs
+ * (typical)." and "Delay between consecutive I2C writes to
+ * OP_MODE register need to be longer than 153 μs (typ)."
+ *
+ * The linux driver does usleep_range(500, 600) and
+ * usleep_range(200, 300), respectively.
+ */
+ switch (regnum) {
+ case REG_ENABLE:
+ udelay(600);
+ break;
+ case REG_OP_MODE:
+ udelay(300);
+ break;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_LED_BLINK
+/*
+ * Program the lp5562 engine
+ * dev - I2C udevice (parent of led)
+ * program - array of commands
+ * size - number of commands in program array (1-16)
+ * engine - engine number (1-3)
+ */
+static int lp5562_led_program_engine(struct udevice *dev, u16 *program,
+ u8 size, u8 engine)
+{
+ int ret, cmd;
+ u8 engine_reg = REG_ENG1_MEM_BEGIN +
+ ((engine - 1) * REG_ENGINE_MEM_SIZE);
+ u8 shift = (3 - engine) * 2;
+ __be16 prog_be[16];
+
+ if (size < 1 || size > 16 || engine < 1 || engine > 3)
+ return -EINVAL;
+
+ for (cmd = 0; cmd < size; cmd++)
+ prog_be[cmd] = cpu_to_be16(program[cmd]);
+
+ /* set engine mode to 'disabled' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_DISABLED << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set exec mode to 'hold' */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE,
+ REG_ENABLE_ENG_EXEC_HOLD << shift,
+ REG_ENABLE_ENG_EXEC_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set engine mode to 'load SRAM' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_LOAD_SRAM << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* send the re-ordered program sequence */
+ ret = dm_i2c_write(dev, engine_reg, (uchar *)prog_be, sizeof(u16) * size);
+ if (ret != 0)
+ goto done;
+
+ /* set engine mode to 'run' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_RUN << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set engine exec to 'run' */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE,
+ REG_ENABLE_ENG_EXEC_RUN << shift,
+ REG_ENABLE_ENG_EXEC_MASK << shift);
+
+done:
+ return ret;
+}
+
+/*
+ * Get the LED's current control mode (I2C or ENGINE[1-3])
+ * dev - led udevice (child udevice)
+ */
+static enum lp5562_led_ctl_mode lp5562_led_get_control_mode(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 data;
+ enum lp5562_led_ctl_mode mode = I2C;
+
+ if (dm_i2c_read(dev_get_parent(dev), REG_LED_MAP, &data, 1) == 0)
+ mode = (data & (REG_LED_MAP_ENG_MASK << priv->map_shift))
+ >> priv->map_shift;
+
+ return mode;
+}
+#endif
+
+/*
+ * Set the LED's control mode to I2C or ENGINE[1-3]
+ * dev - led udevice (child udevice)
+ * mode - mode to change to
+ */
+static int lp5562_led_set_control_mode(struct udevice *dev,
+ enum lp5562_led_ctl_mode mode)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+
+ return (lp5562_led_reg_update(dev_get_parent(dev), REG_LED_MAP,
+ mode << priv->map_shift,
+ REG_LED_MAP_ENG_MASK << priv->map_shift));
+}
+
+/*
+ * Return the LED's PWM value; If LED is in BLINK state, then it is
+ * under engine control mode which doesn't use this PWM value.
+ * dev - led udevice (child udevice)
+ */
+static int lp5562_led_get_pwm(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 data;
+
+ if (dm_i2c_read(dev_get_parent(dev), priv->reg_pwm, &data, 1) != 0)
+ return -EINVAL;
+
+ return data;
+}
+
+/*
+ * Set the LED's PWM value and configure it to use this (I2C mode).
+ * dev - led udevice (child udevice)
+ * value - PWM value (0 - 255)
+ */
+static int lp5562_led_set_pwm(struct udevice *dev, u8 value)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+
+ if (lp5562_led_reg_update(dev_get_parent(dev), priv->reg_pwm,
+ value, 0xff) != 0)
+ return -EINVAL;
+
+ /* set LED to I2C register mode */
+ return lp5562_led_set_control_mode(dev, I2C);
+}
+
+/*
+ * Return the led's current state
+ * dev - led udevice (child udevice)
+ *
+ */
+static enum led_state_t lp5562_led_get_state(struct udevice *dev)
+{
+ enum led_state_t state = LEDST_ON;
+
+ if (lp5562_led_get_pwm(dev) == REG_PWM_MIN_VALUE)
+ state = LEDST_OFF;
+
+#ifdef CONFIG_LED_BLINK
+ if (lp5562_led_get_control_mode(dev) != I2C)
+ state = LEDST_BLINK;
+#endif
+
+ return state;
+}
+
+/*
+ * Set the led state
+ * dev - led udevice (child udevice)
+ * state - State to set the LED to
+ */
+static int lp5562_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+#ifdef CONFIG_LED_BLINK
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+#endif
+
+ switch (state) {
+ case LEDST_OFF:
+ return lp5562_led_set_pwm(dev, REG_PWM_MIN_VALUE);
+ case LEDST_ON:
+ return lp5562_led_set_pwm(dev, REG_PWM_MAX_VALUE);
+#ifdef CONFIG_LED_BLINK
+ case LEDST_BLINK:
+ return lp5562_led_set_control_mode(dev, priv->enginenum);
+#endif
+ case LEDST_TOGGLE:
+ if (lp5562_led_get_state(dev) == LEDST_OFF)
+ return lp5562_led_set_state(dev, LEDST_ON);
+ else
+ return lp5562_led_set_state(dev, LEDST_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_LED_BLINK
+/*
+ * Set the blink period of an LED; note blue and white share the same
+ * engine so changing the period of one affects the other.
+ * dev - led udevice (child udevice)
+ * period_ms - blink period in ms
+ */
+static int lp5562_led_set_period(struct udevice *dev, int period_ms)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 opcode = 0;
+ u16 program[7];
+ u16 wait_time;
+
+ /* Blink is implemented as an engine program. Simple on/off
+ * for short periods, or fade in/fade out for longer periods:
+ *
+ * if (period_ms < 500):
+ * set PWM to 100%
+ * pause for period / 2
+ * set PWM to 0%
+ * pause for period / 2
+ * goto start
+ *
+ * else
+ * raise PWM 0% -> 50% in 62.7 ms
+ * raise PWM 50% -> 100% in 62.7 ms
+ * pause for (period - 4 * 62.7) / 2
+ * lower PWM 100% -> 50% in 62.7 ms
+ * lower PWM 50% -> 0% in 62.7 ms
+ * pause for (period - 4 * 62.7) / 2
+ * goto start
+ */
+
+ if (period_ms < MIN_BLINK_PERIOD)
+ period_ms = MIN_BLINK_PERIOD;
+ else if (period_ms > MAX_BLINK_PERIOD)
+ period_ms = MAX_BLINK_PERIOD;
+
+ if (period_ms < 500) {
+ /* Simple on/off blink */
+ wait_time = period_ms / 2;
+
+ /* 1st command is full brightness */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ REG_PWM_MAX_VALUE;
+
+ /* 2nd command is wait (period / 2) using 15.6ms steps */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 3rd command is 0% brightness */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT);
+
+ /* 4th command is wait (period / 2) using 15.6ms steps */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 5th command: repeat */
+ program[opcode++] = 0x00;
+ } else {
+ /* fade-in / fade-out blink */
+ wait_time = ((period_ms - 251) / 2);
+
+ /* ramp up time is 256 * 0.49ms (125.4ms) done in 2 steps */
+ /* 1st command is ramp up 1/2 way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 2nd command is ramp up rest of the way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 3rd: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* ramp down is same as ramp up with sign bit set */
+ /* 4th command is ramp down 1/2 way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (1 << LED_PGRM_RAMP_SIGN_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 5th command is ramp down rest of the way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (1 << LED_PGRM_RAMP_SIGN_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 6th: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 7th command: repeat */
+ program[opcode++] = 0x00;
+ }
+
+ return lp5562_led_program_engine(dev_get_parent(dev), program,
+ opcode, priv->enginenum);
+}
+#endif
+
+static const struct led_ops lp5562_led_ops = {
+ .get_state = lp5562_led_get_state,
+ .set_state = lp5562_led_set_state,
+#ifdef CONFIG_LED_BLINK
+ .set_period = lp5562_led_set_period,
+#endif
+};
+
+static int lp5562_led_probe(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 current;
+ int ret = 0;
+
+ /* Child LED nodes */
+ switch (dev_read_addr(dev)) {
+ case 0:
+ priv->reg_current = REG_R_CUR;
+ priv->reg_pwm = REG_R_PWM;
+ priv->map_shift = REG_LED_MAP_R_ENG_SHIFT;
+ priv->enginenum = 1;
+ break;
+ case 1:
+ priv->reg_current = REG_G_CUR;
+ priv->reg_pwm = REG_G_PWM;
+ priv->map_shift = REG_LED_MAP_G_ENG_SHIFT;
+ priv->enginenum = 2;
+ break;
+ case 2:
+ priv->reg_current = REG_B_CUR;
+ priv->reg_pwm = REG_B_PWM;
+ priv->map_shift = REG_LED_MAP_B_ENG_SHIFT;
+ priv->enginenum = 3; /* shared with white */
+ break;
+ case 3:
+ priv->reg_current = REG_W_CUR;
+ priv->map_shift = REG_LED_MAP_W_ENG_SHIFT;
+ priv->enginenum = 3; /* shared with blue */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ current = dev_read_u8_default(dev, "max-cur", DEFAULT_CURRENT);
+
+ ret = lp5562_led_reg_update(dev_get_parent(dev), priv->reg_current,
+ current, 0xff);
+
+ return ret;
+}
+
+static int lp5562_led_bind(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ /*
+ * For the child nodes, parse a "chan-name" property, since
+ * the DT bindings for this device use that instead of
+ * "label".
+ */
+ uc_plat->label = dev_read_string(dev, "chan-name");
+
+ return 0;
+}
+
+U_BOOT_DRIVER(lp5562_led) = {
+ .name = "lp5562-led",
+ .id = UCLASS_LED,
+ .bind = lp5562_led_bind,
+ .probe = lp5562_led_probe,
+ .priv_auto = sizeof(struct lp5562_led_priv),
+ .ops = &lp5562_led_ops,
+};
+
+
+static int lp5562_led_wrap_probe(struct udevice *dev)
+{
+ struct lp5562_led_wrap_priv *priv = dev_get_priv(dev);
+ u8 clock_mode;
+ int ret;
+
+ /* Enable gpio if needed */
+ if (gpio_request_by_name(dev, "enabled-gpios", 0,
+ &priv->enable_gpio, GPIOD_IS_OUT) == 0) {
+ dm_gpio_set_value(&priv->enable_gpio, 1);
+ udelay(1000);
+ }
+
+ /* Ensure all registers have default values. */
+ ret = lp5562_led_reg_update(dev, REG_RESET, REG_RESET_RESET, 0xff);
+ if (ret)
+ return ret;
+ udelay(10000);
+
+ /* Enable the chip */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE, REG_ENABLE_CHIP_ENABLE, 0xff);
+ if (ret)
+ return ret;
+
+ /*
+ * The DT bindings say 0=auto, 1=internal, 2=external, while
+ * the register[0:1] values are 0=external, 1=internal,
+ * 2=auto.
+ */
+ clock_mode = dev_read_u8_default(dev, "clock-mode", 0);
+ ret = lp5562_led_reg_update(dev, REG_CONFIG, 2 - clock_mode, REG_CONFIG_CLK_MASK);
+
+ return ret;
+}
+
+static int lp5562_led_wrap_bind(struct udevice *dev)
+{
+ return led_bind_generic(dev, "lp5562-led");
+}
+
+static const struct udevice_id lp5562_led_ids[] = {
+ { .compatible = "ti,lp5562" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(lp5562_led_wrap) = {
+ .name = "lp5562-led-wrap",
+ .id = UCLASS_NOP,
+ .of_match = lp5562_led_ids,
+ .bind = lp5562_led_wrap_bind,
+ .probe = lp5562_led_wrap_probe,
+ .priv_auto = sizeof(struct lp5562_led_wrap_priv),
+};
#include <errno.h>
#include <led.h>
#include <malloc.h>
-#include <dm/lists.h>
#include <pwm.h>
#define LEDS_PWM_DRIVER_NAME "led_pwm"
static int led_pwm_bind(struct udevice *parent)
{
- struct udevice *dev;
- ofnode node;
- int ret;
-
- dev_for_each_subnode(node, parent) {
- ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME,
- ofnode_get_name(node),
- node, &dev);
- if (ret)
- return ret;
- }
- return 0;
+ return led_bind_generic(parent, LEDS_PWM_DRIVER_NAME);
}
static const struct led_ops led_pwm_ops = {
#include <common.h>
#include <log.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <dm.h>
#include <mailbox-uclass.h>
#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <linux/arm-smccc.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <wait_bit.h>
#define IPI_BIT_MASK_PMU0 0x10000
#define IPI_INT_REG_BASE_APU 0xFF300000
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN 0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+
+/*
+ * Flag to indicate if notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK BIT(0)
+
+/*
+ * Flag to indicate if notification interrupt
+ * to be enabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK BIT(0)
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
struct ipi_int_regs {
u32 trig; /* 0x0 */
u32 obs; /* 0x4 */
void __iomem *local_res_regs;
void __iomem *remote_req_regs;
void __iomem *remote_res_regs;
+ u32 remote_id;
+ u32 local_id;
+ bool el3_supported;
};
+static int zynqmp_ipi_fw_call(struct zynqmp_ipi *ipi_mbox,
+ unsigned long a0, unsigned long a3)
+{
+ struct arm_smccc_res res = {0};
+ unsigned long a1, a2;
+
+ a1 = ipi_mbox->local_id;
+ a2 = ipi_mbox->remote_id;
+ arm_smccc_smc(a0, a1, a2, a3, 0, 0, 0, 0, &res);
+
+ return (int)res.a0;
+}
+
static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
{
const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
for (size_t i = 0; i < msg->len; i++)
writel(msg->buf[i], &mbx[i]);
+ /* Use SMC calls for Exception Level less than 3 where TF-A is available */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0);
+
+ debug("%s, send %ld bytes\n", __func__, msg->len);
+
+ return ret;
+ }
+
+ /* Return if EL3 is not supported */
+ if (!zynqmp->el3_supported) {
+ dev_err(chan->dev, "mailbox in EL3 only supported for zynqmp");
+ return -EOPNOTSUPP;
+ }
+
/* Write trigger interrupt */
writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig);
struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
u32 *mbx = (u32 *)zynqmp->local_res_regs;
+ int ret = 0;
/*
* PMU Firmware does not trigger IPI interrupt for API call responses so
- * there is no need to check ISR flags
+ * there is no need to check ISR flags for EL3.
*/
for (size_t i = 0; i < msg->len; i++)
msg->buf[i] = readl(&mbx[i]);
+ /* Ack to remote if EL is not 3 */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK,
+ IPI_SMC_ACK_EIRQ_MASK);
+ }
+
debug("%s, recv %ld bytes\n", __func__, msg->len);
- return 0;
+ return ret;
};
-static int zynqmp_ipi_probe(struct udevice *dev)
+static int zynqmp_ipi_dest_probe(struct udevice *dev)
{
struct zynqmp_ipi *zynqmp = dev_get_priv(dev);
struct resource res;
ofnode node;
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
- /* Get subnode where the regs are defined */
- /* Note IPI mailbox node needs to be the first one in DT */
- node = ofnode_first_subnode(dev_ofnode(dev));
+ node = dev_ofnode(dev);
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
+ zynqmp->el3_supported = true;
+
+ ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id);
+ if (ret) {
+ dev_err(dev, "can't get local ipi id\n");
+ return ret;
+ }
+
+ ret = ofnode_read_u32(node, "xlnx,ipi-id", &zynqmp->remote_id);
+ if (ret) {
+ dev_err(dev, "can't get remote ipi id\n");
+ return ret;
+ }
if (ofnode_read_resource_byname(node, "local_request_region", &res)) {
dev_err(dev, "No reg property for local_request_region\n");
};
zynqmp->local_req_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->local_req_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "local_response_region", &res)) {
dev_err(dev, "No reg property for local_response_region\n");
};
zynqmp->local_res_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->local_res_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "remote_request_region", &res)) {
dev_err(dev, "No reg property for remote_request_region\n");
};
zynqmp->remote_req_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->remote_req_regs)
+ return -EINVAL;
if (ofnode_read_resource_byname(node, "remote_response_region", &res)) {
dev_err(dev, "No reg property for remote_response_region\n");
};
zynqmp->remote_res_regs = devm_ioremap(dev, res.start,
(res.start - res.end));
+ if (!zynqmp->remote_res_regs)
+ return -EINVAL;
return 0;
};
-static const struct udevice_id zynqmp_ipi_ids[] = {
- { .compatible = "xlnx,zynqmp-ipi-mailbox" },
- { }
+static int zynqmp_ipi_probe(struct udevice *dev)
+{
+ struct udevice *cdev;
+ ofnode cnode;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ dev_for_each_subnode(cnode, dev) {
+ ret = device_bind_driver_to_node(dev, "zynqmp_ipi_dest",
+ ofnode_get_name(cnode),
+ cnode, &cdev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
};
-struct mbox_ops zynqmp_ipi_mbox_ops = {
+struct mbox_ops zynqmp_ipi_dest_mbox_ops = {
.send = zynqmp_ipi_send,
.recv = zynqmp_ipi_recv,
};
+static const struct udevice_id zynqmp_ipi_dest_ids[] = {
+ { .compatible = "xlnx,zynqmp-ipi-dest-mailbox" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_ipi_dest) = {
+ .name = "zynqmp_ipi_dest",
+ .id = UCLASS_MAILBOX,
+ .of_match = zynqmp_ipi_dest_ids,
+ .probe = zynqmp_ipi_dest_probe,
+ .priv_auto = sizeof(struct zynqmp_ipi),
+ .ops = &zynqmp_ipi_dest_mbox_ops,
+};
+
+static const struct udevice_id zynqmp_ipi_ids[] = {
+ { .compatible = "xlnx,zynqmp-ipi-mailbox" },
+ { }
+};
+
U_BOOT_DRIVER(zynqmp_ipi) = {
.name = "zynqmp_ipi",
- .id = UCLASS_MAILBOX,
+ .id = UCLASS_NOP,
.of_match = zynqmp_ipi_ids,
.probe = zynqmp_ipi_probe,
- .priv_auto = sizeof(struct zynqmp_ipi),
- .ops = &zynqmp_ipi_mbox_ops,
+ .flags = DM_FLAG_PROBE_AFTER_BIND,
};
#include <linux/err.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
+#include <linux/time.h>
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x0
#define FMC2_BTR_DATLAT_MAX 0xf
#define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
-#define FMC2_NSEC_PER_SEC 1000000000L
-
enum stm32_fmc2_ebi_bank {
FMC2_EBI1 = 0,
FMC2_EBI2,
int cs, u32 setup)
{
unsigned long hclk = clk_get_rate(&ebi->clk);
- unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
return DIV_ROUND_UP(setup * 1000, hclkp);
}
*/
#include <common.h>
+#include <asm/arch/hardware.h>
#include <asm/ti-common/ti-aemif.h>
#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4)
Hidden option to enable QEMU fw_cfg interface and uclass. This will
be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+config QFW_ACPI
+ bool
+ default y
+ depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
+ help
+ Hidden option to read ACPI tables from QEMU.
+
config QFW_PIO
bool
depends on QFW
ie. the FPGA device.
config SPL_FS_LOADER
- bool "Enable loader driver for file system"
+ bool "Enable loader driver for file system in SPL"
depends on SPL
help
This is file system generic loader which can be used to load
obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
ifdef CONFIG_QFW
obj-y += qfw.o
+obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o
obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
if (!gsc_wd_disable(dev))
return CMD_RET_SUCCESS;
} else if (strcasecmp(argv[1], "thermal") == 0) {
- char *cmd, *val;
+ const char *cmd, *val;
- cmd = (argc > 2) ? argv[2] : NULL;
- val = (argc > 3) ? argv[3] : NULL;
+ cmd = cmd_arg2(argc, argv);
+ val = cmd_arg3(argc, argv);
if (!gsc_thermal(dev, cmd, val))
return CMD_RET_SUCCESS;
}
#define LOG_CATEGORY UCLASS_QFW
#include <common.h>
+#include <acpi/acpi_table.h>
#include <bootdev.h>
#include <bootflow.h>
#include <bootmeth.h>
#include <tables_csum.h>
#include <asm/acpi_table.h>
-#if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX)
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- * (either high memory or low memory)
- * @addr : The address that should be used for low memory allcation. If the
- * memory allocation request is 'ZONE_HIGH' then this parameter will
- * be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct udevice *dev,
- struct bios_linker_entry *entry, ulong *addr)
-{
- uint32_t size, align;
- struct fw_file *file;
- unsigned long aligned_addr;
-
- align = le32_to_cpu(entry->alloc.align);
- /* align must be power of 2 */
- if (align & (align - 1)) {
- printf("error: wrong alignment %u\n", align);
- return -EINVAL;
- }
-
- file = qfw_find_file(dev, entry->alloc.file);
- if (!file) {
- printf("error: can't find file %s\n", entry->alloc.file);
- return -ENOENT;
- }
-
- size = be32_to_cpu(file->cfg.size);
-
- /*
- * ZONE_HIGH means we need to allocate from high memory, since
- * malloc space is already at the end of RAM, so we directly use it.
- * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
- * in which is low memory
- */
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
- aligned_addr = (unsigned long)memalign(align, size);
- if (!aligned_addr) {
- printf("error: allocating resource\n");
- return -ENOMEM;
- }
- if (aligned_addr < gd->arch.table_start_high)
- gd->arch.table_start_high = aligned_addr;
- if (aligned_addr + size > gd->arch.table_end_high)
- gd->arch.table_end_high = aligned_addr + size;
-
- } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
- aligned_addr = ALIGN(*addr, align);
- } else {
- printf("error: invalid allocation zone\n");
- return -EINVAL;
- }
-
- debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
- file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
- qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size,
- (void *)aligned_addr);
- file->addr = aligned_addr;
-
- /* adjust address for low memory allocation */
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
- *addr = (aligned_addr + size);
-
- return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- * ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct udevice *dev,
- struct bios_linker_entry *entry)
-{
- struct fw_file *dest, *src;
- uint32_t offset = le32_to_cpu(entry->pointer.offset);
- uint64_t pointer = 0;
-
- dest = qfw_find_file(dev, entry->pointer.dest_file);
- if (!dest || !dest->addr)
- return -ENOENT;
- src = qfw_find_file(dev, entry->pointer.src_file);
- if (!src || !src->addr)
- return -ENOENT;
-
- debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
- dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
- memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
- pointer = le64_to_cpu(pointer);
- pointer += (unsigned long)src->addr;
- pointer = cpu_to_le64(pointer);
- memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
- return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- * checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct udevice *dev,
- struct bios_linker_entry *entry)
-{
- struct fw_file *file;
- uint8_t *data, cksum = 0;
- uint8_t *cksum_start;
-
- file = qfw_find_file(dev, entry->cksum.file);
- if (!file || !file->addr)
- return -ENOENT;
-
- data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
- cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
- cksum = table_compute_checksum(cksum_start,
- le32_to_cpu(entry->cksum.length));
- *data = cksum;
-
- return 0;
-}
-
-/* This function loads and patches ACPI tables provided by QEMU */
-ulong write_acpi_tables(ulong addr)
-{
- int i, ret;
- struct fw_file *file;
- struct bios_linker_entry *table_loader;
- struct bios_linker_entry *entry;
- uint32_t size;
- struct udevice *dev;
-
- ret = qfw_get_dev(&dev);
- if (ret) {
- printf("error: no qfw\n");
- return addr;
- }
-
- /* make sure fw_list is loaded */
- ret = qfw_read_firmware_list(dev);
- if (ret) {
- printf("error: can't read firmware file list\n");
- return addr;
- }
-
- file = qfw_find_file(dev, "etc/table-loader");
- if (!file) {
- printf("error: can't find etc/table-loader\n");
- return addr;
- }
-
- size = be32_to_cpu(file->cfg.size);
- if ((size % sizeof(*entry)) != 0) {
- printf("error: table-loader maybe corrupted\n");
- return addr;
- }
-
- table_loader = malloc(size);
- if (!table_loader) {
- printf("error: no memory for table-loader\n");
- return addr;
- }
-
- /* QFW always puts tables at high addresses */
- gd->arch.table_start_high = (ulong)table_loader;
- gd->arch.table_end_high = (ulong)table_loader;
-
- qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
-
- for (i = 0; i < (size / sizeof(*entry)); i++) {
- entry = table_loader + i;
- switch (le32_to_cpu(entry->command)) {
- case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
- ret = bios_linker_allocate(dev, entry, &addr);
- if (ret)
- goto out;
- break;
- case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
- ret = bios_linker_add_pointer(dev, entry);
- if (ret)
- goto out;
- break;
- case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
- ret = bios_linker_add_checksum(dev, entry);
- if (ret)
- goto out;
- break;
- default:
- break;
- }
- }
-
-out:
- if (ret) {
- struct fw_cfg_file_iter iter;
- for (file = qfw_file_iter_init(dev, &iter);
- !qfw_file_iter_end(&iter);
- file = qfw_file_iter_next(&iter)) {
- if (file->addr) {
- free((void *)file->addr);
- file->addr = 0;
- }
- }
- }
-
- free(table_loader);
-
- gd_set_acpi_start(acpi_get_rsdp_addr());
-
- return addr;
-}
-
-ulong acpi_get_rsdp_addr(void)
-{
- int ret;
- struct fw_file *file;
- struct udevice *dev;
-
- ret = qfw_get_dev(&dev);
- if (ret) {
- printf("error: no qfw\n");
- return 0;
- }
-
- file = qfw_find_file(dev, "etc/acpi/rsdp");
- return file->addr;
-}
-#endif
-
static void qfw_read_entry_io(struct qfw_dev *qdev, u16 entry, u32 size,
void *address)
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
+ */
+
+#define LOG_CATEGORY UCLASS_QFW
+
+#include <acpi/acpi_table.h>
+#include <errno.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <qfw.h>
+#include <tables_csum.h>
+#include <stdio.h>
+#include <linux/sizes.h>
+#include <asm/byteorder.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ * (either high memory or low memory)
+ * @addr : The address that should be used for low memory allcation. If the
+ * memory allocation request is 'ZONE_HIGH' then this parameter will
+ * be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct udevice *dev,
+ struct bios_linker_entry *entry, ulong *addr)
+{
+ uint32_t size, align;
+ struct fw_file *file;
+ unsigned long aligned_addr;
+
+ align = le32_to_cpu(entry->alloc.align);
+ /* align must be power of 2 */
+ if (align & (align - 1)) {
+ printf("error: wrong alignment %u\n", align);
+ return -EINVAL;
+ }
+
+ file = qfw_find_file(dev, entry->alloc.file);
+ if (!file) {
+ printf("error: can't find file %s\n", entry->alloc.file);
+ return -ENOENT;
+ }
+
+ size = be32_to_cpu(file->cfg.size);
+
+ /*
+ * ZONE_HIGH means we need to allocate from high memory, since
+ * malloc space is already at the end of RAM, so we directly use it.
+ * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+ * in which is low memory
+ */
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+ aligned_addr = (unsigned long)memalign(align, size);
+ if (!aligned_addr) {
+ printf("error: allocating resource\n");
+ return -ENOMEM;
+ }
+ if (aligned_addr < gd->arch.table_start_high)
+ gd->arch.table_start_high = aligned_addr;
+ if (aligned_addr + size > gd->arch.table_end_high)
+ gd->arch.table_end_high = aligned_addr + size;
+
+ } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+ aligned_addr = ALIGN(*addr, align);
+ } else {
+ printf("error: invalid allocation zone\n");
+ return -EINVAL;
+ }
+
+ debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
+ file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+ qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size,
+ (void *)aligned_addr);
+ file->addr = aligned_addr;
+
+ /* adjust address for low memory allocation */
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+ *addr = (aligned_addr + size);
+
+ return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ * ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct udevice *dev,
+ struct bios_linker_entry *entry)
+{
+ struct fw_file *dest, *src;
+ uint32_t offset = le32_to_cpu(entry->pointer.offset);
+ uint64_t pointer = 0;
+
+ dest = qfw_find_file(dev, entry->pointer.dest_file);
+ if (!dest || !dest->addr)
+ return -ENOENT;
+ src = qfw_find_file(dev, entry->pointer.src_file);
+ if (!src || !src->addr)
+ return -ENOENT;
+
+ debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
+ dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+ memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+ pointer = le64_to_cpu(pointer);
+ pointer += (unsigned long)src->addr;
+ pointer = cpu_to_le64(pointer);
+ memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+ return 0;
+}
+
+/*
+ * This function updates checksum fields of ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells where to update ACPI table
+ * checksums
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_checksum(struct udevice *dev,
+ struct bios_linker_entry *entry)
+{
+ struct fw_file *file;
+ uint8_t *data, cksum = 0;
+ uint8_t *cksum_start;
+
+ file = qfw_find_file(dev, entry->cksum.file);
+ if (!file || !file->addr)
+ return -ENOENT;
+
+ data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
+ cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
+ cksum = table_compute_checksum(cksum_start,
+ le32_to_cpu(entry->cksum.length));
+ *data = cksum;
+
+ return 0;
+}
+
+/* This function loads and patches ACPI tables provided by QEMU */
+ulong write_acpi_tables(ulong addr)
+{
+ int i, ret;
+ struct fw_file *file;
+ struct bios_linker_entry *table_loader;
+ struct bios_linker_entry *entry;
+ uint32_t size;
+ struct udevice *dev;
+
+ ret = qfw_get_dev(&dev);
+ if (ret) {
+ printf("error: no qfw\n");
+ return addr;
+ }
+
+ /* make sure fw_list is loaded */
+ ret = qfw_read_firmware_list(dev);
+ if (ret) {
+ printf("error: can't read firmware file list\n");
+ return addr;
+ }
+
+ file = qfw_find_file(dev, "etc/table-loader");
+ if (!file) {
+ printf("error: can't find etc/table-loader\n");
+ return addr;
+ }
+
+ size = be32_to_cpu(file->cfg.size);
+ if ((size % sizeof(*entry)) != 0) {
+ printf("error: table-loader maybe corrupted\n");
+ return addr;
+ }
+
+ table_loader = malloc(size);
+ if (!table_loader) {
+ printf("error: no memory for table-loader\n");
+ return addr;
+ }
+
+ /* QFW always puts tables at high addresses */
+ gd->arch.table_start_high = (ulong)table_loader;
+ gd->arch.table_end_high = (ulong)table_loader;
+
+ qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
+
+ for (i = 0; i < (size / sizeof(*entry)); i++) {
+ entry = table_loader + i;
+ switch (le32_to_cpu(entry->command)) {
+ case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
+ ret = bios_linker_allocate(dev, entry, &addr);
+ if (ret)
+ goto out;
+ break;
+ case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+ ret = bios_linker_add_pointer(dev, entry);
+ if (ret)
+ goto out;
+ break;
+ case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+ ret = bios_linker_add_checksum(dev, entry);
+ if (ret)
+ goto out;
+ break;
+ default:
+ break;
+ }
+ }
+
+out:
+ if (ret) {
+ struct fw_cfg_file_iter iter;
+ for (file = qfw_file_iter_init(dev, &iter);
+ !qfw_file_iter_end(&iter);
+ file = qfw_file_iter_next(&iter)) {
+ if (file->addr) {
+ free((void *)file->addr);
+ file->addr = 0;
+ }
+ }
+ }
+
+ free(table_loader);
+
+ gd_set_acpi_start(acpi_get_rsdp_addr());
+
+ return addr;
+}
+
+ulong acpi_get_rsdp_addr(void)
+{
+ int ret;
+ struct fw_file *file;
+ struct udevice *dev;
+
+ ret = qfw_get_dev(&dev);
+ if (ret) {
+ printf("error: no qfw\n");
+ return 0;
+ }
+
+ file = qfw_find_file(dev, "etc/acpi/rsdp");
+ return file->addr;
+}
+
+#ifndef CONFIG_X86
+static int evt_write_acpi_tables(void)
+{
+ ulong addr, end;
+ void *ptr;
+
+ /* Reserve 64K for ACPI tables, aligned to a 4K boundary */
+ ptr = memalign(SZ_4K, SZ_64K);
+ if (!ptr)
+ return -ENOMEM;
+ addr = map_to_sysmem(ptr);
+
+ /* Generate ACPI tables */
+ end = write_acpi_tables(addr);
+ gd->arch.table_start = addr;
+ gd->arch.table_end = addr;
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, evt_write_acpi_tables);
+#endif
if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
cfg->f_max = host->src_clk_freq;
- cfg->b_max = 1024;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
host->mmc = &plat->mmc;
*/
#define MMC_TIMEOUT_SHORT 20
-#define NSEC_PER_SEC 1000000000L
-
#define MAX_NO_OF_TAPS 64
#define EXT_CSD_POWER_CLASS 187 /* R/W */
* (actually 52MHz)
*/
cfg->f_min = 375000;
- cfg->f_max = 48000000;
+ cfg->f_max = dev_read_u32_default(dev, "max-frequency", 48000000);
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
else
ifneq ($(mtd-y),)
-obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd.o
+obj-$(CONFIG_SPL_MTD) += mtd.o
endif
obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/
This enables the driver for the NAND flash device found on
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
+config NAND_SANDBOX
+ bool "Support for NAND in sandbox"
+ depends on SANDBOX
+ select SYS_NAND_SELF_INIT
+ select SPL_SYS_NAND_SELF_INIT
+ select SPL_NAND_INIT
+ select SYS_NAND_SOFT_ECC
+ select BCH
+ select NAND_ECC_BCH
+ imply CMD_NAND
+ help
+ Enable a dummy NAND driver for sandbox. It simulates any number of
+ arbitrary NAND chips with a RAM buffer. It will also inject errors to
+ test ECC. At the moment, only 8-bit busses and single-chip devices are
+ supported.
+
config NAND_SUNXI
bool "Support for NAND on Allwinner SoCs"
default ARCH_SUNXI
And fetching device parameters flashed on device, by parsing
ONFI parameter page.
-config SYS_NAND_PAGE_COUNT
- hex "NAND chip page count"
- depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
- SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \
- NAND_OMAP_GPMC)
- help
- Number of pages in the NAND chip.
-
config SYS_NAND_PAGE_SIZE
hex "NAND chip page size"
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
MVEBU_SPL_BOOT_DEVICE_NAND || \
- (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || \
+ SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
help
Number of data bytes in one page for the NAND chip on the
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
+obj-$(CONFIG_NAND_SANDBOX) += sand_nand.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
#include <common.h>
#include <nand.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/mtd/nand_ecc.h>
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
nand_command(0, 0, 0, NAND_CMD_RESET);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
/* Unselect after operation */
void nand_deselect(void)
{
#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/mtd.h>
+#include <linux/time.h>
#include <mach/at91_sfr.h>
#include <nand.h>
#include <regmap.h>
#include "pmecc.h"
-#define NSEC_PER_SEC 1000000000L
-
#define ATMEL_HSMC_NFC_CFG 0x0
#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
return ret;
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, const void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- writew(p[i], addr);
-}
-
static u8 atmel_nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
#include <common.h>
#include <log.h>
+#include <system-constants.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <dm/device_compat.h>
static int nand_command(int block, int page, uint32_t offs, u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
if (nand_chip.select_chip)
nand_chip.select_chip(mtd, 0);
- page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ page_addr = page + block * SYS_NAND_BLOCK_PAGES;
hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Row address */
hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
nand_chip.select_chip(mtd, 0);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
void nand_deselect(void)
{
if (nand_chip.select_chip)
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return page_size;
+}
+
void nand_deselect(void) {}
return __raw_readw((u16 *)marker) != 0xffff;
}
+static int saved_page_size;
+
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
if (port_size == 8)
bad_marker = 5;
}
+ saved_page_size = page_size;
ver = ifc_in32(&gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
{
}
+unsigned int nand_page_size(void)
+{
+ return saved_page_size;
+}
+
void nand_deselect(void)
{
}
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return BYTES_PER_PAGE;
+}
+
#endif /* CONFIG_SPL_BUILD */
return SZ_2G;
}
+unsigned int nand_page_size(void)
+{
+ return nfc_dev.nand.mtd.writesize;
+}
+
void nand_deselect(void)
{
}
#include <common.h>
#include <hang.h>
#include <nand.h>
+#include <system-constants.h>
#include <linux/mtd/rawnand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
* Check if we have crossed a block boundary, and if so
* check for bad block.
*/
- if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
+ if (!(page % SYS_NAND_BLOCK_PAGES)) {
/*
* Yes, new block. See if this block is good. If not,
* loop until we find a good block.
*/
while (is_badblock(page)) {
- page = page + CONFIG_SYS_NAND_PAGE_COUNT;
+ page = page + SYS_NAND_BLOCK_PAGES;
/* Check i we've reached the end of flash. */
if (page >= maxpages)
return -1;
void nand_init(void) {}
void nand_deselect(void) {}
+
+unsigned int nand_page_size(void)
+{
+ return CONFIG_SYS_NAND_PAGE_SIZE;
+}
#include <linux/errno.h>
#include <linux/mtd/rawnand.h>
#include <linux/sizes.h>
+#include <linux/time.h>
#include <linux/types.h>
#include <linux/math64.h>
#endif
#define MXS_NAND_BCH_TIMEOUT 10000
-#define USEC_PER_SEC 1000000
-#define NSEC_PER_SEC 1000000000L
#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
void nand_deselect(void)
{
}
sprintf(dev_name[devnum], "nand%d", devnum);
mtd->name = dev_name[devnum];
-#ifdef CONFIG_MTD
/*
* Add MTD device so that we can reference it later
* via the mtdcore infrastructure (e.g. ubi).
*/
add_mtd_device(mtd);
-#endif
total_nand_size += mtd->size / 1024;
return 0;
}
+void nand_unregister(struct mtd_info *mtd)
+{
+ int devnum = nand_mtd_to_devnum(mtd);
+
+ if (devnum < 0)
+ return;
+
+ if (nand_curr_device == devnum)
+ nand_curr_device = -1;
+
+ total_nand_size -= mtd->size / 1024;
+
+ del_mtd_device(nand_info[devnum]);
+
+ nand_info[devnum] = NULL;
+}
+
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static void nand_init_chip(int i)
{
#endif
#ifdef CONFIG_MTD_CONCAT
+struct mtd_info *concat_mtd;
+
static void create_mtd_concat(void)
{
struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE];
}
}
if (nand_devices_found > 1) {
- struct mtd_info *mtd;
char c_mtd_name[16];
/*
* We detected multiple devices. Concatenate them together.
*/
sprintf(c_mtd_name, "nand%d", nand_devices_found);
- mtd = mtd_concat_create(nand_info_list, nand_devices_found,
- c_mtd_name);
+ concat_mtd = mtd_concat_create(nand_info_list,
+ nand_devices_found, c_mtd_name);
- if (mtd == NULL)
+ if (!concat_mtd)
return;
- nand_register(nand_devices_found, mtd);
+ nand_register(nand_devices_found, concat_mtd);
}
return;
}
+
+static void destroy_mtd_concat(void)
+{
+ if (!concat_mtd)
+ return;
+
+ mtd_concat_destroy(concat_mtd);
+ concat_mtd = NULL;
+}
#else
static void create_mtd_concat(void)
{
}
+
+static void destroy_mtd_concat(void)
+{
+}
#endif
unsigned long nand_size(void)
return total_nand_size;
}
+static int initialized;
+
void nand_init(void)
{
- static int initialized;
-
/*
* Avoid initializing NAND Flash multiple times,
* otherwise it will calculate a wrong total size.
create_mtd_concat();
}
+
+void nand_reinit(void)
+{
+ int i;
+
+ destroy_mtd_concat();
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ assert(!nand_info[i]);
+
+ initialized = 0;
+ nand_init();
+}
+
+unsigned int nand_page_size(void)
+{
+ struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
+
+ return mtd ? mtd->writesize : 1;
+}
chip->write_buf(mtd, (uint8_t *)&word, 2);
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
-
- for (i = 0; i < len; i++)
- writew(p[i], addr);
-}
-
/**
* nand_write_buf - [DEFAULT] write buffer to chip
* @mtd: MTD device structure
else if (chip->jedec_version)
pr_info("%s %s\n", manufacturer_desc->name,
chip->jedec_params.model);
- else
+ else if (manufacturer_desc)
pr_info("%s %s\n", manufacturer_desc->name, type->name);
#else
if (chip->jedec_version)
pr_info("%s %s\n", manufacturer_desc->name,
chip->jedec_params.model);
- else
+ else if (manufacturer_desc)
pr_info("%s %s\n", manufacturer_desc->name, type->name);
-
- pr_info("%s %s\n", manufacturer_desc->name,
- type->name);
#endif
pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
/* Skip bad blocks */
- while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+ while (size && page < SYS_NAND_BLOCK_PAGES) {
nand_read_page(block, page, dst);
+
+ size -= min(size, CONFIG_SYS_NAND_PAGE_SIZE -
+ page_offset);
/*
* When offs is not aligned to page address the
* extra offset is copied to dst as well. Copy
#include <common.h>
#include <nand.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
while (!this->dev_ready(mtd))
;
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
nand_chip.select_chip(mtd, 0);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
/* Unselect after operation */
void nand_deselect(void)
{
#include <linux/mtd/nand_bch.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
+#include <linux/time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
#define OCTEONTX_NAND_DRIVER_NAME "octeontx_nand"
#define NDF_TIMEOUT 1000 /** Timeout in ms */
-#define USEC_PER_SEC 1000000 /** Linux compatibility */
#ifndef NAND_MAX_CHIPS
# define NAND_MAX_CHIPS 8 /** Linux compatibility */
#endif
#include <common.h>
#include <log.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <linux/errno.h>
static int nand_read_page(int block, int page, uchar *dst)
{
- int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page;
+ int page_addr = block * SYS_NAND_BLOCK_PAGES + page;
loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
int ret;
size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Sean Anderson <seanga2@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_MTD
+#include <errno.h>
+#include <hexdump.h>
+#include <log.h>
+#include <nand.h>
+#include <os.h>
+#include <rand.h>
+#include <spl.h>
+#include <system-constants.h>
+#include <dm/device_compat.h>
+#include <dm/read.h>
+#include <dm/uclass.h>
+#include <asm/bitops.h>
+#include <linux/bitmap.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/sizes.h>
+
+enum sand_nand_state {
+ STATE_READY,
+ STATE_IDLE,
+ STATE_READ,
+ STATE_READ_ID,
+ STATE_READ_ONFI,
+ STATE_PARAM_ONFI,
+ STATE_STATUS,
+ STATE_PROG,
+ STATE_ERASE,
+};
+
+static const char *const state_name[] = {
+ [STATE_READY] = "READY",
+ [STATE_IDLE] = "IDLE",
+ [STATE_READ] = "READ",
+ [STATE_READ_ID] = "READ_ID",
+ [STATE_READ_ONFI] = "READ_ONFI",
+ [STATE_PARAM_ONFI] = "PARAM_ONFI",
+ [STATE_STATUS] = "STATUS",
+ [STATE_PROG] = "PROG",
+ [STATE_ERASE] = "ERASE",
+};
+
+/**
+ * struct sand_nand_chip - Per-device private data
+ * @nand: The nand chip
+ * @node: The next device in this controller
+ * @programmed: Bitmap of whether sectors are programmed
+ * @id: ID to report for NAND_CMD_READID
+ * @id_len: Length of @id
+ * @onfi: Three copies of ONFI parameter page
+ * @status: Status to report for NAND_CMD_STATUS
+ * @chunksize: Size of one "chunk" (page + oob) in bytes
+ * @pageize: Size of one page in bytes
+ * @pages: Total number of pages
+ * @pages_per_erase: Number of pages per eraseblock
+ * @err_count: Number of errors to inject per @err_step_bits of data
+ * @err_step_bits: Number of data bits per error "step"
+ * @err_steps: Number of err steps in a page
+ * @cs: Chip select for this device
+ * @state: Current state of the device
+ * @column: Column of the most-recent command
+ * @page_addr: Page address of the most-recent command
+ * @fd: File descriptor for the backing data
+ * @fd_page_addr: Page address that @fd is seek'd to
+ * @selected: Whether this device is selected
+ * @tmp: "Cache" buffer used to store transferred data before committing it
+ * @tmp_dirty: Whether @tmp is dirty (modified) or clean (all ones)
+ *
+ * Data is stored with the OOB area in-line. For example, with 512-byte pages
+ * and and 16-byte OOB areas, the first page would start at offset 0, the second
+ * at offset 528, the third at offset 1056, and so on
+ */
+struct sand_nand_chip {
+ struct nand_chip nand;
+ struct list_head node;
+ long *programmed;
+ const u8 *id;
+ u32 chunksize, pagesize, pages, pages_per_erase;
+ u32 err_count, err_step_bits, err_steps, ecc_bits;
+ unsigned int cs;
+ enum sand_nand_state state;
+ int column, page_addr, fd, fd_page_addr;
+ bool selected, tmp_dirty;
+ u8 status;
+ u8 id_len;
+ u8 tmp[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+ u8 onfi[sizeof(struct nand_onfi_params) * 3];
+};
+
+#define SAND_DEBUG(chip, fmt, ...) \
+ dev_dbg((chip)->nand.mtd.dev, "%u (%s): " fmt, (chip)->cs, \
+ state_name[(chip)->state], ##__VA_ARGS__)
+
+static inline void to_state(struct sand_nand_chip *chip,
+ enum sand_nand_state new_state)
+{
+ if (new_state != chip->state)
+ SAND_DEBUG(chip, "to state %s\n", state_name[new_state]);
+ chip->state = new_state;
+}
+
+static inline struct sand_nand_chip *to_sand_nand(struct nand_chip *nand)
+{
+ return container_of(nand, struct sand_nand_chip, nand);
+}
+
+struct sand_nand_priv {
+ struct list_head chips;
+};
+
+static int sand_nand_dev_ready(struct mtd_info *mtd)
+{
+ return 1;
+}
+
+static int sand_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ u8 status;
+
+ return nand_status_op(chip, &status) ?: status;
+}
+
+static int sand_nand_seek(struct sand_nand_chip *chip)
+{
+ if (chip->fd_page_addr == chip->page_addr)
+ return 0;
+
+ if (os_lseek(chip->fd, (off_t)chip->page_addr * chip->chunksize,
+ OS_SEEK_SET) < 0) {
+ SAND_DEBUG(chip, "could not seek: %d\n", errno);
+ return -EIO;
+ }
+
+ chip->fd_page_addr = chip->page_addr;
+ return 0;
+}
+
+static void sand_nand_inject_error(struct sand_nand_chip *chip,
+ unsigned int step, unsigned int pos)
+{
+ int byte, index;
+
+ if (pos < chip->err_step_bits) {
+ __change_bit(step * chip->err_step_bits + pos, chip->tmp);
+ return;
+ }
+
+ /*
+ * Only ECC bytes are covered in the OOB area, so
+ * pretend that those are the only bytes which can have
+ * errors.
+ */
+ byte = (pos - chip->err_step_bits + step * chip->ecc_bits) / 8;
+ index = chip->nand.ecc.layout->eccpos[byte];
+ /* Avoid endianness issues by working with bytes */
+ chip->tmp[chip->pagesize + index] ^= BIT(pos & 0x7);
+}
+
+static int sand_nand_read(struct sand_nand_chip *chip)
+{
+ unsigned int i, stop = 0;
+
+ if (chip->column == chip->pagesize)
+ stop = chip->err_step_bits;
+
+ if (test_bit(chip->page_addr, chip->programmed)) {
+ if (sand_nand_seek(chip))
+ return -EIO;
+
+ if (os_read(chip->fd, chip->tmp, chip->chunksize) !=
+ chip->chunksize) {
+ SAND_DEBUG(chip, "could not read: %d\n", errno);
+ return -EIO;
+ }
+ chip->fd_page_addr++;
+ } else if (chip->tmp_dirty) {
+ memset(chip->tmp + chip->column, 0xff,
+ chip->chunksize - chip->column);
+ }
+
+ /*
+ * Inject some errors; this is Method A from "An Efficient Algorithm for
+ * Sequential Random Sampling" (Vitter 87). This is still slow when
+ * generating a lot (dozens) of ECC errors.
+ *
+ * To avoid generating too many errors in any one ECC step, we separate
+ * our error generation by ECC step.
+ */
+ chip->tmp_dirty = true;
+ for (i = 0; i < chip->err_steps; i++) {
+ u32 bit_errors = chip->err_count;
+ unsigned int j = chip->err_step_bits + chip->ecc_bits;
+
+ while (bit_errors) {
+ unsigned int u = rand();
+ float quot = 1ULL << 32;
+
+ do {
+ quot *= j - bit_errors;
+ quot /= j;
+ j--;
+
+ if (j < stop)
+ goto next;
+ } while (u < quot);
+
+ sand_nand_inject_error(chip, i, j);
+ bit_errors--;
+ }
+next:
+ ;
+ }
+
+ return 0;
+}
+
+static void sand_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+ enum sand_nand_state new_state = chip->state;
+
+ SAND_DEBUG(chip, "command=%02x column=%d page_addr=%d\n", command,
+ column, page_addr);
+
+ if (!chip->selected)
+ return;
+
+ switch (chip->state) {
+ case STATE_READY:
+ if (command == NAND_CMD_RESET)
+ goto reset;
+ break;
+ case STATE_PROG:
+ new_state = STATE_IDLE;
+ if (command != NAND_CMD_PAGEPROG ||
+ test_and_set_bit(chip->page_addr, chip->programmed)) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (sand_nand_seek(chip)) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (os_write(chip->fd, chip->tmp, chip->chunksize) !=
+ chip->chunksize) {
+ SAND_DEBUG(chip, "could not write: %d\n", errno);
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ chip->fd_page_addr++;
+ break;
+ case STATE_ERASE:
+ new_state = STATE_IDLE;
+ if (command != NAND_CMD_ERASE2) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (chip->page_addr < 0 ||
+ chip->page_addr >= chip->pages ||
+ chip->page_addr % chip->pages_per_erase)
+ chip->status |= NAND_STATUS_FAIL;
+ else
+ bitmap_clear(chip->programmed, chip->page_addr,
+ chip->pages_per_erase);
+ break;
+ default:
+ chip->column = column;
+ chip->page_addr = page_addr;
+ switch (command) {
+ case NAND_CMD_READOOB:
+ if (column >= 0)
+ chip->column += chip->pagesize;
+ fallthrough;
+ case NAND_CMD_READ0:
+ new_state = STATE_IDLE;
+ if (page_addr < 0 || page_addr >= chip->pages)
+ break;
+
+ if (chip->column < 0 || chip->column >= chip->chunksize)
+ break;
+
+ if (sand_nand_read(chip))
+ break;
+
+ chip->page_addr = page_addr;
+ new_state = STATE_READ;
+ break;
+ case NAND_CMD_ERASE1:
+ new_state = STATE_ERASE;
+ chip->status = ~NAND_STATUS_FAIL;
+ break;
+ case NAND_CMD_STATUS:
+ new_state = STATE_STATUS;
+ chip->column = 0;
+ break;
+ case NAND_CMD_SEQIN:
+ new_state = STATE_PROG;
+ chip->status = ~NAND_STATUS_FAIL;
+ if (page_addr < 0 || page_addr >= chip->pages ||
+ chip->column < 0 ||
+ chip->column >= chip->chunksize) {
+ chip->status |= NAND_STATUS_FAIL;
+ } else if (chip->tmp_dirty) {
+ memset(chip->tmp, 0xff, chip->chunksize);
+ chip->tmp_dirty = false;
+ }
+ break;
+ case NAND_CMD_READID:
+ if (chip->onfi[0] && column == 0x20)
+ new_state = STATE_READ_ONFI;
+ else
+ new_state = STATE_READ_ID;
+ chip->column = 0;
+ break;
+ case NAND_CMD_PARAM:
+ if (chip->onfi[0] && !column)
+ new_state = STATE_PARAM_ONFI;
+ else
+ new_state = STATE_IDLE;
+ break;
+ case NAND_CMD_RESET:
+reset:
+ new_state = STATE_IDLE;
+ chip->column = -1;
+ chip->page_addr = -1;
+ chip->status = ~NAND_STATUS_FAIL;
+ break;
+ default:
+ new_state = STATE_IDLE;
+ SAND_DEBUG(chip, "Unsupported command %02x\n", command);
+ }
+ }
+
+ to_state(chip, new_state);
+}
+
+static void sand_nand_select_chip(struct mtd_info *mtd, int n)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ chip->selected = !n;
+}
+
+static void sand_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+ unsigned int to_copy;
+ int src_len = 0;
+ const u8 *src = NULL;
+
+ if (!chip->selected)
+ goto copy;
+
+ switch (chip->state) {
+ case STATE_READ:
+ src = chip->tmp;
+ src_len = chip->chunksize;
+ break;
+ case STATE_READ_ID:
+ src = chip->id;
+ src_len = chip->id_len;
+ break;
+ case STATE_READ_ONFI:
+ src = "ONFI";
+ src_len = 4;
+ break;
+ case STATE_PARAM_ONFI:
+ src = chip->onfi;
+ src_len = sizeof(chip->onfi);
+ break;
+ case STATE_STATUS:
+ src = &chip->status;
+ src_len = 1;
+ break;
+ default:
+ break;
+ }
+
+copy:
+ if (chip->column >= 0)
+ to_copy = max(min(len, src_len - chip->column), 0);
+ else
+ to_copy = 0;
+ memcpy(buf, src + chip->column, to_copy);
+ memset(buf + to_copy, 0xff, len - to_copy);
+ chip->column += to_copy;
+
+ if (len == 1) {
+ SAND_DEBUG(chip, "read [ %02x ]\n", buf[0]);
+ } else if (src_len) {
+ SAND_DEBUG(chip, "read %d bytes\n", len);
+#ifdef VERBOSE_DEBUG
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
+#endif
+ }
+
+ if (src_len && chip->column == src_len)
+ to_state(chip, STATE_IDLE);
+}
+
+static u8 sand_nand_read_byte(struct mtd_info *mtd)
+{
+ u8 ret;
+
+ sand_nand_read_buf(mtd, &ret, 1);
+ return ret;
+}
+
+static u16 sand_nand_read_word(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ SAND_DEBUG(chip, "16-bit access unsupported\n");
+ return sand_nand_read_byte(mtd) | 0xff00;
+}
+
+static void sand_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ SAND_DEBUG(chip, "write %d bytes\n", len);
+#ifdef VERBOSE_DEBUG
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
+#endif
+
+ if (chip->state != STATE_PROG || chip->status & NAND_STATUS_FAIL)
+ return;
+
+ chip->tmp_dirty = true;
+ len = min((unsigned int)len, chip->chunksize - chip->column);
+ memcpy(chip->tmp + chip->column, buf, len);
+ chip->column += len;
+}
+
+static struct nand_chip *nand_chip;
+
+int sand_nand_remove(struct udevice *dev)
+{
+ struct sand_nand_priv *priv = dev_get_priv(dev);
+ struct sand_nand_chip *chip;
+
+ list_for_each_entry(chip, &priv->chips, node) {
+ struct nand_chip *nand = &chip->nand;
+
+ if (nand_chip == nand)
+ nand_chip = NULL;
+
+ nand_unregister(nand_to_mtd(nand));
+ free(chip->programmed);
+ os_close(chip->fd);
+ free(chip);
+ }
+
+ return 0;
+}
+
+static int sand_nand_probe(struct udevice *dev)
+{
+ struct sand_nand_priv *priv = dev_get_priv(dev);
+ struct sand_nand_chip *chip;
+ int ret, devnum = 0;
+ ofnode np;
+
+ INIT_LIST_HEAD(&priv->chips);
+
+ dev_for_each_subnode(np, dev) {
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ u32 erasesize, oobsize, pagesize, pages;
+ u32 err_count, err_step_size;
+ off_t expected_size;
+ char filename[30];
+ fdt_addr_t cs;
+ const u8 *id, *onfi;
+ int id_len, onfi_len;
+
+ cs = ofnode_get_addr_size_index_notrans(np, 0, NULL);
+ if (cs == FDT_ADDR_T_NONE) {
+ dev_dbg(dev, "Invalid cs for chip %s\n",
+ ofnode_get_name(np));
+ ret = -ENOENT;
+ goto err;
+ }
+
+ id = ofnode_read_prop(np, "sandbox,id", &id_len);
+ if (!id) {
+ dev_dbg(dev, "No sandbox,id property for chip %s\n",
+ ofnode_get_name(np));
+ ret = -EINVAL;
+ goto err;
+ }
+
+ onfi = ofnode_read_prop(np, "sandbox,onfi", &onfi_len);
+ if (onfi && onfi_len != sizeof(struct nand_onfi_params)) {
+ dev_dbg(dev, "Invalid length %d for onfi params\n",
+ onfi_len);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,erasesize", &erasesize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,erasesize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,oobsize", &oobsize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,oobsize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,pagesize", &pagesize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,pagesize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,pages", &pages);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,pages property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,err-count", &err_count);
+ if (ret) {
+ dev_dbg(dev,
+ "No sandbox,err-count property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,err-step-size",
+ &err_step_size);
+ if (ret) {
+ dev_dbg(dev,
+ "No sandbox,err-step-size property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ chip = calloc(sizeof(*chip), 1);
+ if (!chip) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ chip->cs = cs;
+ chip->id = id;
+ chip->id_len = id_len;
+ chip->chunksize = pagesize + oobsize;
+ chip->pagesize = pagesize;
+ chip->pages = pages;
+ chip->pages_per_erase = erasesize / pagesize;
+ memset(chip->tmp, 0xff, chip->chunksize);
+
+ chip->err_count = err_count;
+ chip->err_step_bits = err_step_size * 8;
+ chip->err_steps = pagesize / err_step_size;
+
+ expected_size = (off_t)pages * chip->chunksize;
+ snprintf(filename, sizeof(filename),
+ "/tmp/u-boot.nand%d.XXXXXX", devnum);
+ chip->fd = os_mktemp(filename, expected_size);
+ if (chip->fd < 0) {
+ dev_dbg(dev, "Could not create temp file %s\n",
+ filename);
+ ret = chip->fd;
+ goto err_chip;
+ }
+
+ chip->programmed = calloc(sizeof(long),
+ BITS_TO_LONGS(pages));
+ if (!chip->programmed) {
+ ret = -ENOMEM;
+ goto err_fd;
+ }
+
+ if (onfi) {
+ memcpy(chip->onfi, onfi, onfi_len);
+ memcpy(chip->onfi + onfi_len, onfi, onfi_len);
+ memcpy(chip->onfi + 2 * onfi_len, onfi, onfi_len);
+ }
+
+ nand = &chip->nand;
+ nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN;
+ nand->flash_node = np;
+ nand->dev_ready = sand_nand_dev_ready;
+ nand->cmdfunc = sand_nand_command;
+ nand->waitfunc = sand_nand_wait;
+ nand->select_chip = sand_nand_select_chip;
+ nand->read_byte = sand_nand_read_byte;
+ nand->read_word = sand_nand_read_word;
+ nand->read_buf = sand_nand_read_buf;
+ nand->write_buf = sand_nand_write_buf;
+ nand->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
+
+ mtd = nand_to_mtd(nand);
+ mtd->dev = dev;
+
+ ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
+ if (ret) {
+ dev_dbg(dev, "Could not scan chip %s: %d\n",
+ ofnode_get_name(np), ret);
+ goto err_prog;
+ }
+ chip->ecc_bits = nand->ecc.layout->eccbytes * 8 /
+ chip->err_steps;
+
+ ret = nand_register(devnum, mtd);
+ if (ret) {
+ dev_dbg(dev, "Could not register nand %d: %d\n", devnum,
+ ret);
+ goto err_prog;
+ }
+
+ if (!nand_chip)
+ nand_chip = nand;
+
+ list_add_tail(&chip->node, &priv->chips);
+ devnum++;
+ continue;
+
+err_prog:
+ free(chip->programmed);
+err_fd:
+ os_close(chip->fd);
+err_chip:
+ free(chip);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ sand_nand_remove(dev);
+ return ret;
+}
+
+static const struct udevice_id sand_nand_ids[] = {
+ { .compatible = "sandbox,nand" },
+ { }
+};
+
+U_BOOT_DRIVER(sand_nand) = {
+ .name = "sand-nand",
+ .id = UCLASS_MTD,
+ .of_match = sand_nand_ids,
+ .probe = sand_nand_probe,
+ .remove = sand_nand_remove,
+ .priv_auto = sizeof(struct sand_nand_priv),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int err;
+
+ err = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_REF(sand_nand),
+ &dev);
+ if (err && err != -ENODEV)
+ log_info("Failed to get sandbox NAND: %d\n", err);
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
+void nand_deselect(void)
+{
+ nand_chip->select_chip(nand_to_mtd(nand_chip), -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct mtd_info *mtd = nand_to_mtd(nand_chip);
+
+ return mtd_block_isbad(mtd, block << mtd->erasesize_shift);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+ struct mtd_info *mtd = nand_to_mtd(nand_chip);
+ loff_t ofs = ((loff_t)block << mtd->erasesize_shift) +
+ ((loff_t)page << mtd->writesize_shift);
+ size_t len = mtd->writesize;
+
+ return nand_read(mtd, ofs, &len, dst);
+}
+
+#include "nand_spl_loaders.c"
+#endif /* CONFIG_SPL_NAND_INIT */
#include <linux/ioport.h>
#include <linux/mtd/rawnand.h>
#include <linux/printk.h>
+#include <linux/time.h>
/* Bad block marker length */
#define FMC2_BBM_LEN 2
#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
-#define FMC2_NSEC_PER_SEC 1000000000L
-
#define FMC2_TIMEOUT_5S 5000000
enum stm32_fmc2_ecc {
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct stm32_fmc2_timings *tims = &nand->timings;
unsigned long hclk = clk_get_rate(&nfc->clk);
- unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
unsigned long timing, tar, tclr, thiz, twait;
unsigned long tset_mem, tset_att, thold_mem, thold_att;
return 0;
}
+static struct nfc_config conf;
+
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
{
- static struct nfc_config conf = { };
int ret;
ret = nand_detect_config(&conf, offs, dest);
return nand_read_buffer(&conf, offs, size, dest);
}
+unsigned int nand_page_size(void)
+{
+ return conf.page_size;
+}
+
void nand_deselect(void)
{
struct sunxi_ccm_reg *const ccm =
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
+spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs += toshiba.o winbond.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
¶gon_spinand_manufacturer,
&toshiba_spinand_manufacturer,
&winbond_spinand_manufacturer,
+ &esmt_c8_spinand_manufacturer,
};
static int spinand_manufacturer_match(struct spinand_device *spinand,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author:
+ * Chuanhong Guo <gch981213@gmail.com> - the main driver logic
+ * Martin Kurbanov <mmkurbanov@sberdevices.ru> - OOB layout
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+/* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */
+#define SPINAND_MFR_ESMT_C8 0xc8
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+/*
+ * OOB spare area map (64 bytes)
+ *
+ * Bad Block Markers
+ * filled by HW and kernel Reserved
+ * | +-----------------------+-----------------------+
+ * | | | |
+ * | | OOB free data Area |non ECC protected |
+ * | +-------------|-----+-----------------|-----+-----------------|-----+
+ * | | | | | | | |
+ * +-|---|----------+--|-----|--------------+--|-----|--------------+--|-----|--------------+
+ * | | | section0 | | | section1 | | | section2 | | | section3 |
+ * +-v-+-v-+---+----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+
+ * | | | | | | | | | | | | | | | | |
+ * |0:1|2:3|4:7|8:15|16:17|18:19|20:23|24:31|32:33|34:35|36:39|40:47|48:49|50:51|52:55|56:63|
+ * | | | | | | | | | | | | | | | | |
+ * +---+---+-^-+--^-+-----+-----+--^--+--^--+-----+-----+--^--+--^--+-----+-----+--^--+--^--+
+ * | | | | | | | |
+ * | +----------------|-----+-----------------|-----+-----------------|-----+
+ * | ECC Area|(Main + Spare) - filled|by ESMT NAND HW |
+ * | | | |
+ * +---------------------+-----------------------+-----------------------+
+ * OOB ECC protected Area - not used due to
+ * partial programming from some filesystems
+ * (like JFFS2 with cleanmarkers)
+ */
+
+#define ESMT_OOB_SECTION_COUNT 4
+#define ESMT_OOB_SECTION_SIZE(nand) \
+ (nanddev_per_page_oobsize(nand) / ESMT_OOB_SECTION_COUNT)
+#define ESMT_OOB_FREE_SIZE(nand) \
+ (ESMT_OOB_SECTION_SIZE(nand) / 2)
+#define ESMT_OOB_ECC_SIZE(nand) \
+ (ESMT_OOB_SECTION_SIZE(nand) - ESMT_OOB_FREE_SIZE(nand))
+#define ESMT_OOB_BBM_SIZE 2
+
+static int f50l1g41lb_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+
+ if (section >= ESMT_OOB_SECTION_COUNT)
+ return -ERANGE;
+
+ region->offset = section * ESMT_OOB_SECTION_SIZE(nand) +
+ ESMT_OOB_FREE_SIZE(nand);
+ region->length = ESMT_OOB_ECC_SIZE(nand);
+
+ return 0;
+}
+
+static int f50l1g41lb_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+
+ if (section >= ESMT_OOB_SECTION_COUNT)
+ return -ERANGE;
+
+ /*
+ * Reserve space for bad blocks markers (section0) and
+ * reserved bytes (sections 1-3)
+ */
+ region->offset = section * ESMT_OOB_SECTION_SIZE(nand) + 2;
+
+ /* Use only 2 non-protected ECC bytes per each OOB section */
+ region->length = 2;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = {
+ .ecc = f50l1g41lb_ooblayout_ecc,
+ .rfree = f50l1g41lb_ooblayout_free,
+};
+
+static const struct spinand_info esmt_c8_spinand_table[] = {
+ SPINAND_INFO("F50L1G41LB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
+ SPINAND_INFO("F50D1G41LB",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
+};
+
+static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer esmt_c8_spinand_manufacturer = {
+ .id = SPINAND_MFR_ESMT_C8,
+ .name = "ESMT",
+ .chips = esmt_c8_spinand_table,
+ .nchips = ARRAY_SIZE(esmt_c8_spinand_table),
+ .ops = &esmt_spinand_manuf_ops,
+};
puts("Flex-");
puts("OneNAND: ");
-#ifdef CONFIG_MTD
/*
* Add MTD device so that we can reference it later
* via the mtdcore infrastructure (e.g. ubi).
*/
onenand_mtd.name = dev_name;
add_mtd_device(&onenand_mtd);
-#endif
}
print_size(onenand_chip.chipsize, "\n");
}
help
Add support for various Macronix SPI flash chips (MX25Lxxx)
+config SPI_FLASH_SILICONKAISER
+ bool "Silicon Kaiser SPI flash support"
+ help
+ Add support for various Silicon Kaiser SPI flash chips (SK25Lxxx)
+
config SPI_FLASH_SPANSION
bool "Spansion SPI flash support"
help
Add support for various XTX (XTX Technology Limited)
SPI flash chips (XT25xxx).
+config SPI_FLASH_ZBIT
+ bool "ZBIT SPI flash support"
+ help
+ Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx).
+
endif
config SPI_FLASH_USE_4K_SECTORS
return ret;
}
+/**
+ * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
+ * @nor: pointer to a 'struct spi_nor'
+ * @addr: offset in the SFDP area to start reading data from
+ * @len: number of bytes to read
+ * @buf: buffer where the SFDP data are copied into
+ *
+ * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
+ * guaranteed to be dma-safe.
+ *
+ * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
+ * otherwise.
+ */
+static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
+ size_t len, void *buf)
+{
+ void *dma_safe_buf;
+ int ret;
+
+ dma_safe_buf = kmalloc(len, GFP_KERNEL);
+ if (!dma_safe_buf)
+ return -ENOMEM;
+
+ ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
+ memcpy(buf, dma_safe_buf, len);
+ kfree(dma_safe_buf);
+
+ return ret;
+}
+
/* Fast Read settings. */
static void
bfpt_header->length * sizeof(u32));
addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
memset(&bfpt, 0, sizeof(bfpt));
- err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
+ err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
if (err < 0)
return err;
int i, err;
/* Get the SFDP header. */
- err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
+ err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
if (err < 0)
return err;
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {
+ INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
{ INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
#endif
+#ifdef CONFIG_SPI_FLASH_SILICONKAISER
+ { INFO("sk25lp128", 0x257018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+#endif
+
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* Micron */
{ INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
+ { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_FSR) },
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_MT35XU
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("xt55q02g", 0x0b601C, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
/* adding these wide voltage QSPI flash parts */
{ INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+#endif
+#ifdef CONFIG_SPI_FLASH_ZBIT
+ /* Zbit Semiconductor Inc. */
+ { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
{ },
};
depends on MCFFEC
bool "Invalidate icache during ethernet operations"
-config FSLDMAFEC
- bool "ColdFire DMA Ethernet Support"
- select PHYLIB
- select SYS_DISCOVER_PHY
- help
- This driver supports the network interface units in the
- ColdFire family.
-
config KS8851_MLL
bool "Microchip KS8851-MLL controller driver"
help
This driver is used for the MDIO mux found on the Amlogic G12A & compatible
SoCs.
+config MDIO_MUX_MESON_GXL
+ bool "MDIO MUX for Amlogic Meson GXL SoCs"
+ depends on DM_MDIO_MUX
+ help
+ This driver is used for the MDIO mux found on the Amlogic GXL & compatible
+ SoCs.
+
endif # NETDEVICES
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FMAN_ENET) += fm/
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
-obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o
+obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o
obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
.compatible = "nxp,imx8mp-dwmac-eqos",
.data = (ulong)&eqos_imx_config
},
+ {
+ .compatible = "nxp,imx93-dwmac-eqos",
+ .data = (ulong)&eqos_imx_config
+ },
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
{
ulong rate;
int ret;
+ if (device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
+ return 0;
+
debug("%s(dev=%p):\n", __func__, dev);
if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*/
-#include <common.h>
#include <env.h>
#include <fs_loader.h>
#include <image.h>
#ifndef __FM_H__
#define __FM_H__
-#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <fsl_fman.h>
*/
/* Perform extra checking */
-#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/bug.h>
/* Trace the 3 different classes of read/write access to QBMan. #undef as
* required. */
+#include <config.h>
#include <linux/bug.h>
#include <linux/printk.h>
#undef QBMAN_CCSR_TRACE
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * Conversion to DM
- * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <hang.h>
-#include <malloc.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include <asm/immap.h>
-#include <asm/fsl_mcdmafec.h>
-
-#include "MCD_dma.h"
-
-#undef ET_DEBUG
-#undef MII_DEBUG
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-#define PKT_MAXBUF_SIZE 1518
-#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
-
-/* RxBD bits definitions */
-#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
- BD_ENET_RX_OV | BD_ENET_RX_TR)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_eth_info(struct fec_info_dma *info)
-{
- /* setup Receive and Transmit buffer descriptor */
-#ifdef CFG_SYS_FEC_BUF_USE_SRAM
- static u32 tmp;
-
- if (info->index == 0)
- tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
- else
- info->rxbd = (cbd_t *)DBUF_LENGTH;
-
- info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
- tmp = (u32)info->rxbd;
- info->txbd =
- (cbd_t *)((u32)info->txbd + tmp +
- (PKTBUFSRX * sizeof(cbd_t)));
- tmp = (u32)info->txbd;
- info->txbuf =
- (char *)((u32)info->txbuf + tmp +
- (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- tmp = (u32)info->txbuf;
-#else
- info->rxbd =
- (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (PKTBUFSRX * sizeof(cbd_t)));
- info->txbd =
- (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- info->txbuf =
- (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
-#endif
-
-#ifdef ET_DEBUG
- printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
-#endif
- info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
-}
-
-static void fec_halt(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- int counter = 0xffff;
-
- /* issue graceful stop command to the FEC transmitter if necessary */
- fecp->tcr |= FEC_TCR_GTS;
-
- /* wait for graceful stop to register */
- while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
- ;
-
- /* Disable DMA tasks */
- MCD_killDma(info->tx_task);
- MCD_killDma(info->rx_task);
-
- /* Disable the Ethernet Controller */
- fecp->ecr &= ~FEC_ECR_ETHER_EN;
-
- /* Clear FIFO status registers */
- fecp->rfsr &= FIFO_ERRSTAT;
- fecp->tfsr &= FIFO_ERRSTAT;
-
- fecp->frst = 0x01000000;
-
- /* Issue a reset command to the FEC chip */
- fecp->ecr |= FEC_ECR_RESET;
-
- /* wait at least 20 clock cycles */
- mdelay(10);
-
-#ifdef ET_DEBUG
- printf("Ethernet task stopped\n");
-#endif
-}
-
-#ifdef ET_DEBUG
-static void dbg_fec_regs(struct eth_device *dev)
-{
- struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
-
- printf("=====\n");
- printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
- printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
- printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
- printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
- printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
- printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
- printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
- printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
- printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
- printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
- printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
- printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
- printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
- printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
- printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
- printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
- printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
- printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
- printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
- printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
- printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
- printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
- printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
- printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
- printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
- printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
- printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
- printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
- printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
- printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
- printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
- printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
- printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
- printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
- printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
-}
-#endif
-
-static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
-{
- struct bd_info *bd = gd->bd;
-
- if ((dup_spd >> 16) == FULL) {
- /* Set maximum frame length */
- fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
- FEC_RCR_PROM | 0x100;
- fecp->tcr = FEC_TCR_FDEN;
- } else {
- /* Half duplex mode */
- fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
- FEC_RCR_MII_MODE | FEC_RCR_DRT;
- fecp->tcr &= ~FEC_TCR_FDEN;
- }
-
- if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef MII_DEBUG
- printf("100Mbps\n");
-#endif
- bd->bi_ethspeed = 100;
- } else {
-#ifdef MII_DEBUG
- printf("10Mbps\n");
-#endif
- bd->bi_ethspeed = 10;
- }
-}
-
-static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
-{
- u8 curr_byte; /* byte for which to compute the CRC */
- int byte; /* loop - counter */
- int bit; /* loop - counter */
- u32 crc = 0xffffffff; /* initial value */
-
- for (byte = 0; byte < 6; byte++) {
- curr_byte = mac[byte];
- for (bit = 0; bit < 8; bit++) {
- if ((curr_byte & 0x01) ^ (crc & 0x01)) {
- crc >>= 1;
- crc = crc ^ 0xedb88320;
- } else {
- crc >>= 1;
- }
- curr_byte >>= 1;
- }
- }
-
- crc = crc >> 26;
-
- /* Set individual hash table register */
- if (crc >= 32) {
- fecp->ialr = (1 << (crc - 32));
- fecp->iaur = 0;
- } else {
- fecp->ialr = 0;
- fecp->iaur = (1 << crc);
- }
-
- /* Set physical address */
- fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
- fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
-
- /* Clear multicast address hash table */
- fecp->gaur = 0;
- fecp->galr = 0;
-}
-
-static int fec_init(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- int rval, i;
- uchar enetaddr[6];
-
-#ifdef ET_DEBUG
- printf("fec_init: iobase 0x%08x ...\n", info->iobase);
-#endif
-
- fecpin_setclear(info, 1);
- fec_halt(dev);
-
- mii_init();
- set_fec_duplex_speed(fecp, info->dup_spd);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set station address */
- if (info->index == 0)
- rval = eth_env_get_enetaddr("ethaddr", enetaddr);
- else
- rval = eth_env_get_enetaddr("eth1addr", enetaddr);
-
- if (!rval) {
- puts("Please set a valid MAC address\n");
- return -EINVAL;
- }
-
- fec_set_hwaddr(fecp, enetaddr);
-
- /* Set Opcode/Pause Duration Register */
- fecp->opd = 0x00010020;
-
- /* Setup Buffers and Buffer Descriptors */
- info->rx_idx = 0;
- info->tx_idx = 0;
-
- /* Setup Receiver Buffer Descriptors (13.14.24.18)
- * Settings: Empty, Wrap */
- for (i = 0; i < PKTBUFSRX; i++) {
- info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
- info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
- }
- info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
- * Settings: Last, Tx CRC */
- for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
- info->txbd[i].cbd_sc = 0;
- info->txbd[i].cbd_datlen = 0;
- info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
- }
- info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- info->used_tbd_idx = 0;
- info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
-
- /* Set Rx FIFO alarm and granularity value */
- fecp->rfcr = 0x0c000000;
- fecp->rfar = 0x0000030c;
-
- /* Set Tx FIFO granularity value */
- fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
- fecp->tfar = 0x00000080;
-
- fecp->tfwr = 0x2;
- fecp->ctcwr = 0x03000000;
-
- /* Enable DMA receive task */
- MCD_startDma(info->rx_task,
- (s8 *)info->rxbd,
- 0,
- (s8 *)&fecp->rfdr,
- 4,
- 0,
- 4,
- info->rx_init,
- info->rx_pri,
- (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
- );
-
- /* Enable DMA tx task with no ready buffer descriptors */
- MCD_startDma(info->tx_task,
- (s8 *)info->txbd,
- 0,
- (s8 *)&fecp->tfdr,
- 4,
- 0,
- 4,
- info->tx_init,
- info->tx_pri,
- (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
- );
-
- /* Now enable the transmit and receive processing */
- fecp->ecr |= FEC_ECR_ETHER_EN;
-
- return 0;
-}
-
-static int mcdmafec_init(struct udevice *dev)
-{
- return fec_init(dev);
-}
-
-static int mcdmafec_send(struct udevice *dev, void *packet, int length)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- cbd_t *p_tbd, *p_used_tbd;
- u16 phy_status;
-
- miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
-
- /* process all the consumed TBDs */
- while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
- p_used_tbd = &info->txbd[info->used_tbd_idx];
- if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
-#ifdef ET_DEBUG
- printf("Cannot clean TBD %d, in use\n",
- info->clean_tbd_num);
-#endif
- return 0;
- }
-
- /* clean this buffer descriptor */
- if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
- p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
- else
- p_used_tbd->cbd_sc = 0;
-
- /* update some indeces for a correct handling of TBD ring */
- info->clean_tbd_num++;
- info->used_tbd_idx = (info->used_tbd_idx + 1)
- % CFG_SYS_TX_ETH_BUFFER;
- }
-
- /* Check for valid length of data. */
- if (length > 1500 || length <= 0)
- return -1;
-
- /* Check the number of vacant TxBDs. */
- if (info->clean_tbd_num < 1) {
- printf("No available TxBDs ...\n");
- return -1;
- }
-
- /* Get the first TxBD to send the mac header */
- p_tbd = &info->txbd[info->tx_idx];
- p_tbd->cbd_datlen = length;
- p_tbd->cbd_bufaddr = (u32)packet;
- p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
- info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
-
- /* Enable DMA transmit task */
- MCD_continDma(info->tx_task);
-
- info->clean_tbd_num -= 1;
-
- /* wait until frame is sent . */
- while (p_tbd->cbd_sc & BD_ENET_TX_READY)
- udelay(10);
-
- return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
-}
-
-static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
-
- cbd_t *prbd = &info->rxbd[info->rx_idx];
- u32 ievent;
- int frame_length, len = 0;
-
- /* Check if any critical events have happened */
- ievent = fecp->eir;
- if (ievent != 0) {
- fecp->eir = ievent;
-
- if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
- printf("fec_recv: error\n");
- fec_halt(dev);
- fec_init(dev);
- return 0;
- }
-
- if (ievent & FEC_EIR_HBERR) {
- /* Heartbeat error */
- fecp->tcr |= FEC_TCR_GTS;
- }
-
- if (ievent & FEC_EIR_GRA) {
- /* Graceful stop complete */
- if (fecp->tcr & FEC_TCR_GTS) {
- printf("fec_recv: tcr_gts\n");
- fec_halt(dev);
- fecp->tcr &= ~FEC_TCR_GTS;
- fec_init(dev);
- }
- }
- }
-
- if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
- if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
- !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
- ((prbd->cbd_datlen - 4) > 14)) {
- /* Get buffer address and size */
- frame_length = prbd->cbd_datlen - 4;
-
- /* Fill the buffer and pass it to upper layers */
- net_process_received_packet((uchar *)prbd->cbd_bufaddr,
- frame_length);
- len = frame_length;
- }
-
- /* Reset buffer descriptor as empty */
- if (info->rx_idx == (PKTBUFSRX - 1))
- prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- else
- prbd->cbd_sc = BD_ENET_RX_EMPTY;
-
- prbd->cbd_datlen = PKTSIZE_ALIGN;
-
- /* Now, we have an empty RxBD, restart the DMA receive task */
- MCD_continDma(info->rx_task);
-
- /* Increment BD count */
- info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
- }
-
- return len;
-}
-
-static void mcdmafec_halt(struct udevice *dev)
-{
- fec_halt(dev);
-}
-
-static const struct eth_ops mcdmafec_ops = {
- .start = mcdmafec_init,
- .send = mcdmafec_send,
- .recv = mcdmafec_recv,
- .stop = mcdmafec_halt,
-};
-
-/*
- * Boot sequence, called just after mcffec_of_to_plat,
- * as DM way, it replaces old mcffec_initialize.
- */
-static int mcdmafec_probe(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_plat(dev);
- int node = dev_of_offset(dev);
- int retval;
- const u32 *val;
-
- info->index = dev_seq(dev);
- info->iobase = pdata->iobase;
- info->miibase = pdata->iobase;
- info->phy_addr = -1;
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
- if (val)
- info->rx_task = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
- if (val)
- info->tx_task = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
- if (val)
- info->rx_pri = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
- if (val)
- info->tx_pri = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
- if (val)
- info->rx_init = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
- if (val)
- info->tx_init = fdt32_to_cpu(*val);
-
-#ifdef CFG_SYS_FEC_BUF_USE_SRAM
- u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
-#endif
- init_eth_info(info);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- info->bus = mdio_alloc();
- if (!info->bus)
- return -ENOMEM;
- strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
- info->bus->read = mcffec_miiphy_read;
- info->bus->write = mcffec_miiphy_write;
-
- retval = mdio_register(info->bus);
- if (retval < 0)
- return retval;
-#endif
-
- return 0;
-}
-
-static int mcdmafec_remove(struct udevice *dev)
-{
- struct fec_info_dma *priv = dev_get_priv(dev);
-
- mdio_unregister(priv->bus);
- mdio_free(priv->bus);
-
- return 0;
-}
-
-/*
- * Boot sequence, called 1st
- */
-static int mcdmafec_of_to_plat(struct udevice *dev)
-{
- struct eth_pdata *pdata = dev_get_plat(dev);
- const u32 *val;
-
- pdata->iobase = dev_read_addr(dev);
- /* Default to 10Mbit/s */
- pdata->max_speed = 10;
-
- val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
- if (val)
- pdata->max_speed = fdt32_to_cpu(*val);
-
- return 0;
-}
-
-static const struct udevice_id mcdmafec_ids[] = {
- { .compatible = "fsl,mcf-dma-fec" },
- { }
-};
-
-U_BOOT_DRIVER(mcffec) = {
- .name = "mcdmafec",
- .id = UCLASS_ETH,
- .of_match = mcdmafec_ids,
- .of_to_plat = mcdmafec_of_to_plat,
- .probe = mcdmafec_probe,
- .remove = mcdmafec_remove,
- .ops = &mcdmafec_ops,
- .priv_auto = sizeof(struct fec_info_dma),
- .plat_auto = sizeof(struct eth_pdata),
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Baylibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+
+#define ETH_REG2 0x0
+#define REG2_PHYID GENMASK(21, 0)
+#define EPHY_GXL_ID 0x110181
+#define REG2_LEDACT GENMASK(23, 22)
+#define REG2_LEDLINK GENMASK(25, 24)
+#define REG2_DIV4SEL BIT(27)
+#define REG2_ADCBYPASS BIT(30)
+#define REG2_CLKINSEL BIT(31)
+#define ETH_REG3 0x4
+#define REG3_ENH BIT(3)
+#define REG3_CFGMODE GENMASK(6, 4)
+#define REG3_AUTOMDIX BIT(7)
+#define REG3_PHYADDR GENMASK(12, 8)
+#define REG3_PWRUPRST BIT(21)
+#define REG3_PWRDOWN BIT(22)
+#define REG3_LEDPOL BIT(23)
+#define REG3_PHYMDI BIT(26)
+#define REG3_CLKINEN BIT(29)
+#define REG3_PHYIP BIT(30)
+#define REG3_PHYEN BIT(31)
+#define ETH_REG4 0x8
+#define REG4_PWRUPRSTSIG BIT(0)
+
+#define MESON_GXL_MDIO_EXTERNAL_ID 0
+#define MESON_GXL_MDIO_INTERNAL_ID 1
+
+struct mdio_mux_meson_gxl_priv {
+ phys_addr_t regs;
+};
+
+static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
+{
+ u32 val;
+
+ /* Setup the internal phy */
+ val = (REG3_ENH |
+ FIELD_PREP(REG3_CFGMODE, 0x7) |
+ REG3_AUTOMDIX |
+ FIELD_PREP(REG3_PHYADDR, 8) |
+ REG3_LEDPOL |
+ REG3_PHYMDI |
+ REG3_CLKINEN |
+ REG3_PHYIP);
+
+ writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
+ writel(val, priv->regs + ETH_REG3);
+ mdelay(10);
+
+ /* NOTE: The HW kept the phy id configurable at runtime.
+ * The id below is arbitrary. It is the one used in the vendor code.
+ * The only constraint is that it must match the one in
+ * drivers/net/phy/meson-gxl.c to properly match the PHY.
+ */
+ writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
+ priv->regs + ETH_REG2);
+
+ /* Enable the internal phy */
+ val |= REG3_PHYEN;
+ writel(val, priv->regs + ETH_REG3);
+ writel(0, priv->regs + ETH_REG4);
+
+ /* The phy needs a bit of time to power up */
+ mdelay(10);
+
+ return 0;
+}
+
+static int meson_gxl_enable_external_mdio(struct mdio_mux_meson_gxl_priv *priv)
+{
+ /* Reset the mdio bus mux to the external phy */
+ writel(0, priv->regs + ETH_REG3);
+
+ return 0;
+}
+
+static int mdio_mux_meson_gxl_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(mux);
+
+ debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ switch (sel) {
+ case MESON_GXL_MDIO_EXTERNAL_ID:
+ return meson_gxl_enable_external_mdio(priv);
+ case MESON_GXL_MDIO_INTERNAL_ID:
+ return meson_gxl_enable_internal_mdio(priv);
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_meson_gxl_ops = {
+ .select = mdio_mux_meson_gxl_select,
+};
+
+static int mdio_mux_meson_gxl_probe(struct udevice *dev)
+{
+ struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_meson_gxl_ids[] = {
+ { .compatible = "amlogic,gxl-mdio-mux" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_meson_gxl) = {
+ .name = "mdio_mux_meson_gxl",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_meson_gxl_ids,
+ .probe = mdio_mux_meson_gxl_probe,
+ .ops = &mdio_mux_meson_gxl_ops,
+ .priv_auto = sizeof(struct mdio_mux_meson_gxl_priv),
+};
* Copyright (c) 2018 Microsemi Corporation
*/
+#include <errno.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include "mscc_mac_table.h"
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
-
#define ETH_LEN 6
#define MAC_VID 1
* Copyright (c) 2018 Microsemi Corporation
*/
+#include <errno.h>
#include <log.h>
#include <linux/bitops.h>
#include <linux/delay.h>
* Copyright (c) 2018 Microsemi Corporation
*/
-#include <common.h>
-
enum mscc_regs_qs {
MSCC_QS_XTR_RD,
MSCC_QS_XTR_FLUSH,
.writeext = &rtl8211f_phy_extwrite,
};
+/* Support for RTL8211F-VD PHY */
+U_BOOT_PHY_DRIVER(rtl8211fvd) = {
+ .name = "RealTek RTL8211F-VD",
+ .uid = 0x1cc878,
+ .mask = 0xffffff,
+ .features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211f_probe,
+ .config = &rtl8211f_config,
+ .startup = &rtl8211f_startup,
+ .shutdown = &genphy_shutdown,
+ .readext = &rtl8211f_phy_extread,
+ .writeext = &rtl8211f_phy_extwrite,
+};
+
/* Support for RTL8201F PHY */
U_BOOT_PHY_DRIVER(rtl8201f) = {
.name = "RealTek RTL8201F 10/100Mbps Ethernet",
* based on source code of Shlomi Gridish
*/
-#include <common.h>
#include <malloc.h>
#include <linux/errno.h>
#include <asm/io.h>
ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
&axistream_node);
- if (ret) {
- printf("%s: axistream is not found\n", __func__);
- return -EINVAL;
- }
+ if (!ret)
+ plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
+ else
+ plat->dmatx = (struct axidma_reg *)dev_read_addr_index(dev, 1);
- plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node);
if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
#ifndef _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
#define _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
-#include <common.h>
-
void ft_pci_setup_ls(void *blob, struct bd_info *bd);
#ifdef CONFIG_PCIE_LAYERSCAPE_GEN4
#include <common.h>
#include <dm.h>
#include <pci.h>
-#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/printk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/err.h>
/**
* struct xilinx_pcie - Xilinx PCIe controller state
/* Register definitions */
#define XILINX_PCIE_REG_PSCR 0x144
#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
+#define XILINX_PCIE_REG_RPSC 0x148
+#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
/**
* pcie_xilinx_link_up() - Check whether the PCIe link is up
static int pcie_xilinx_of_to_plat(struct udevice *dev)
{
struct xilinx_pcie *pcie = dev_get_priv(dev);
- struct fdt_resource reg_res;
- DECLARE_GLOBAL_DATA_PTR;
- int err;
-
- err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
- 0, ®_res);
- if (err < 0) {
- pr_err("\"reg\" resource not found\n");
- return err;
- }
-
- pcie->cfg_base = map_physmem(reg_res.start,
- fdt_resource_size(®_res),
- MAP_NOCACHE);
+ fdt_addr_t addr;
+ fdt_size_t size;
+ u32 rpsc;
+
+ addr = dev_read_addr_size(dev, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ pcie->cfg_base = devm_ioremap(dev, addr, size);
+ if (IS_ERR(pcie->cfg_base))
+ return PTR_ERR(pcie->cfg_base);
+
+ /* Enable the Bridge enable bit */
+ rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+ rpsc |= XILINX_PCIE_REG_RPSC_BEN;
+ __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
return 0;
}
#ifndef PCIE_CADENCE_H
#define PCIE_CADENCE_H
-#include <common.h>
#include <pci_ep.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/bitfield.h>
+#include <linux/time.h>
/* [31] soft reset for the phy.
* 1: reset. 0: dessert the reset.
#define MIPI_DSI_TEST_CTRL0 0x3c
#define MIPI_DSI_TEST_CTRL1 0x40
-#define NSEC_PER_MSEC 1000000L
-
struct phy_meson_axg_mipi_dphy_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
#include <common.h>
#include <div64.h>
+#include <linux/time.h>
#include <phy-mipi-dphy.h>
-#define PSEC_PER_SEC 1000000000000LL
-
/*
* Minimum D-PHY timings based on MIPI D-PHY specification. Derived
* from the valid ranges specified in Section 6.9, Table 14, Page 41
return 0;
}
-static int imx8mq_usb_phy_exit(struct phy *usb_phy)
-{
- return imx8mq_usb_phy_power_off(usb_phy);
-}
-
struct phy_ops imx8mq_usb_phy_ops = {
.init = imx8mpq_usb_phy_init,
.power_on = imx8mq_usb_phy_power_on,
.power_off = imx8mq_usb_phy_power_off,
- .exit = imx8mq_usb_phy_exit,
};
int imx8mq_usb_phy_probe(struct udevice *dev)
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/math64.h>
+#include <linux/time.h>
#include <phy-mipi-dphy.h>
#include <reset.h>
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
-#define PSEC_PER_SEC 1000000000000LL
-
#define msleep(a) udelay(a * 1000)
enum phy_max_rate {
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
+source "drivers/pinctrl/tegra/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/starfive/Kconfig"
obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
+obj-$(CONFIG_$(SPL_)PINCTRL_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
#ifndef _PINCTRL_MTMIPS_COMMON_H_
#define _PINCTRL_MTMIPS_COMMON_H_
-#include <common.h>
-
struct mtmips_pmx_func {
const char *name;
int value;
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },
{ .compatible = "st,stm32mp135-pinctrl" },
+ { .compatible = "st,stm32mp257-pinctrl" },
+ { .compatible = "st,stm32mp257-z-pinctrl" },
{ }
};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+config PINCTRL_TEGRA
+ bool "Nvidia Tegra pinctrl driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Nvidia Tegra SoCs.
+ The driver is an overlay to existing driver and allows
+ the usage of dedicated device tree node which contains
+ full description of each pin.
+
+config SPL_PINCTRL_TEGRA
+ bool "Nvidia Tegra SPL pinctrl driver"
+ depends on SPL_PINCTRL
+ help
+ Enables support of pre-DM version of pin multiplexing
+ control driver used on SPL stage for board setup and
+ available for backwards compatibility purpose.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_TEGRA20
+obj-y += pinctrl-tegra20.o
+else
+obj-y += pinctrl-tegra.o
+endif
+endif
+
+obj-y += pinmux-common.o
+
+obj-$(CONFIG_TEGRA20) += pinmux-tegra20.o funcmux-tegra20.o
+obj-$(CONFIG_TEGRA30) += pinmux-tegra30.o funcmux-tegra30.o
+obj-$(CONFIG_TEGRA114) += pinmux-tegra114.o funcmux-tegra114.o
+obj-$(CONFIG_TEGRA124) += pinmux-tegra124.o funcmux-tegra124.o
+obj-$(CONFIG_TEGRA210) += pinmux-tegra210.o funcmux-tegra210.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <stdlib.h>
+
+#include <asm/arch/pinmux.h>
+
+static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
+{
+ struct pmux_drvgrp_config *drive_group;
+ int i, ret, pad_id;
+ const char **pads;
+
+ drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL);
+ if (!drive_group) {
+ log_debug("%s: cannot allocate drive group array\n", __func__);
+ return;
+ }
+
+ drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
+ drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
+ drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
+ drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+ drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
+ drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
+ drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+#endif
+
+ for (i = 1; i < drvcnt; i++)
+ memcpy(&drive_group[i], &drive_group[0], sizeof(drive_group[0]));
+
+ ret = dev_read_string_list(config, "nvidia,pins", &pads);
+ if (ret < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ goto exit;
+ }
+
+ for (i = 0; i < drvcnt; i++) {
+ for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++)
+ if (tegra_pinctrl_to_drvgrp[pad_id])
+ if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) {
+ drive_group[i].drvgrp = pad_id;
+ break;
+ }
+
+ debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i],
+ drive_group[i].drvgrp, drive_group[i].slwf,
+ drive_group[i].slwr, drive_group[i].drvup,
+ drive_group[i].drvdn);
+ }
+
+ pinmux_config_drvgrp_table(drive_group, drvcnt);
+
+ free(pads);
+exit:
+ kfree(drive_group);
+}
+
+static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
+{
+ struct pmux_pingrp_config *pinmux_group;
+ int i, ret, pin_id;
+ const char *function;
+ const char **pins;
+
+ pinmux_group = kmalloc_array(pincnt, sizeof(*pinmux_group), GFP_KERNEL);
+ if (!pinmux_group) {
+ log_debug("%s: cannot allocate pinmux group array\n", __func__);
+ return;
+ }
+
+ /* decode function id and fill the first copy of pmux_pingrp_config */
+ function = dev_read_string(config, "nvidia,function");
+ if (function)
+ for (i = 0; i < PMUX_FUNC_COUNT; i++)
+ if (tegra_pinctrl_to_func[i])
+ if (!strcmp(function, tegra_pinctrl_to_func[i]))
+ break;
+
+ pinmux_group[0].func = i;
+
+ pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
+ pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
+ pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
+ pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
+ pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
+ pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
+ pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+ pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+ pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+ pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+#endif
+
+ for (i = 1; i < pincnt; i++)
+ memcpy(&pinmux_group[i], &pinmux_group[0], sizeof(pinmux_group[0]));
+
+ ret = dev_read_string_list(config, "nvidia,pins", &pins);
+ if (ret < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ goto exit;
+ }
+
+ for (i = 0; i < pincnt; i++) {
+ for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
+ if (tegra_pinctrl_to_pingrp[pin_id])
+ if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) {
+ pinmux_group[i].pingrp = pin_id;
+ break;
+ }
+
+ debug("%s pinmap: %d, %d, %d, %d\n", pins[i],
+ pinmux_group[i].pingrp, pinmux_group[i].func,
+ pinmux_group[i].pull, pinmux_group[i].tristate);
+ }
+
+ pinmux_config_pingrp_table(pinmux_group, pincnt);
+
+ free(pins);
+exit:
+ kfree(pinmux_group);
+}
+
+static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct udevice *child;
+ int ret;
+ const char *name;
+
+ device_foreach_child(child, config) {
+ /* Pinmux node can contain pins and drives */
+ ret = dev_read_string_index(child, "nvidia,pins", 0,
+ &name);
+ if (ret < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ return ret;
+ }
+
+ ret = dev_read_string_count(child, "nvidia,pins");
+ if (ret < 0) {
+ log_debug("%s: could not count nvidia,pins\n", __func__);
+ return ret;
+ }
+
+ if (!strncmp(name, "drive_", 6))
+ /* Drive node is detected */
+ tegra_pinctrl_set_drive(child, ret);
+ else
+ /* Pin node is detected */
+ tegra_pinctrl_set_pin(child, ret);
+ }
+
+ return 0;
+}
+
+static int tegra_pinctrl_get_pins_count(struct udevice *dev)
+{
+ return PMUX_PINGRP_COUNT;
+}
+
+static const char *tegra_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_pingrp[selector];
+}
+
+static int tegra_pinctrl_get_groups_count(struct udevice *dev)
+{
+ return PMUX_DRVGRP_COUNT;
+}
+
+static const char *tegra_pinctrl_get_group_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_drvgrp[selector];
+}
+
+static int tegra_pinctrl_get_functions_count(struct udevice *dev)
+{
+ return PMUX_FUNC_COUNT;
+}
+
+static const char *tegra_pinctrl_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_func[selector];
+}
+
+const struct pinctrl_ops tegra_pinctrl_ops = {
+ .get_pins_count = tegra_pinctrl_get_pins_count,
+ .get_pin_name = tegra_pinctrl_get_pin_name,
+ .get_groups_count = tegra_pinctrl_get_groups_count,
+ .get_group_name = tegra_pinctrl_get_group_name,
+ .get_functions_count = tegra_pinctrl_get_functions_count,
+ .get_function_name = tegra_pinctrl_get_function_name,
+ .set_state = tegra_pinctrl_set_state,
+};
+
+static int tegra_pinctrl_bind(struct udevice *dev)
+{
+ /*
+ * Make sure that the pinctrl driver gets probed after binding
+ * to provide initial configuration and assure that further
+ * probed devices are working correctly.
+ */
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+ return 0;
+}
+
+static const struct udevice_id tegra_pinctrl_ids[] = {
+ { .compatible = "nvidia,tegra30-pinmux" },
+ { .compatible = "nvidia,tegra114-pinmux" },
+ { },
+};
+
+U_BOOT_DRIVER(tegra_pinctrl) = {
+ .name = "tegra_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = tegra_pinctrl_ids,
+ .bind = tegra_pinctrl_bind,
+ .ops = &tegra_pinctrl_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <stdlib.h>
+
+#include <asm/arch/pinmux.h>
+
+static void tegra_pinctrl_set_pin(struct udevice *config)
+{
+ int i, count, pin_id, ret;
+ int pull, tristate;
+ const char **pins;
+
+ ret = dev_read_u32(config, "nvidia,pull", &pull);
+ if (ret)
+ pull = ret;
+
+ ret = dev_read_u32(config, "nvidia,tristate", &tristate);
+ if (ret)
+ tristate = ret;
+
+ count = dev_read_string_list(config, "nvidia,pins", &pins);
+ if (count < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < count; i++) {
+ for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
+ if (tegra_pinctrl_to_pingrp[pin_id])
+ if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
+ break;
+
+ if (pull >= 0)
+ pinmux_set_pullupdown(pin_id, pull);
+
+ if (tristate >= 0) {
+ if (!tristate)
+ pinmux_tristate_disable(pin_id);
+ else
+ pinmux_tristate_enable(pin_id);
+ }
+ }
+
+ free(pins);
+}
+
+static void tegra_pinctrl_set_func(struct udevice *config)
+{
+ int i, count, func_id, pin_id;
+ const char *function;
+ const char **pins;
+
+ function = dev_read_string(config, "nvidia,function");
+ if (function)
+ for (i = 0; i < PMUX_FUNC_COUNT; i++)
+ if (tegra_pinctrl_to_func[i])
+ if (!strcmp(function, tegra_pinctrl_to_func[i]))
+ break;
+
+ func_id = i;
+
+ count = dev_read_string_list(config, "nvidia,pins", &pins);
+ if (count < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < count; i++) {
+ for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
+ if (tegra_pinctrl_to_pingrp[pin_id])
+ if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
+ break;
+
+ debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id);
+
+ pinmux_set_func(pin_id, func_id);
+ }
+
+ free(pins);
+}
+
+static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct udevice *child;
+
+ device_foreach_child(child, config) {
+ /*
+ * Tegra20 pinmux is set differently then any other
+ * Tegra SOC. Nodes are arranged by function muxing,
+ * then actual pins setup (with node name prefix
+ * conf_*) and then drive setup.
+ */
+ if (!strncmp(child->name, "conf_", 5))
+ tegra_pinctrl_set_pin(child);
+ else if (!strncmp(child->name, "drive_", 6))
+ debug("%s: drive configuration is not supported\n", __func__);
+ else
+ tegra_pinctrl_set_func(child);
+ }
+
+ return 0;
+}
+
+static int tegra_pinctrl_get_pins_count(struct udevice *dev)
+{
+ return PMUX_PINGRP_COUNT;
+}
+
+static const char *tegra_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_pingrp[selector];
+}
+
+static int tegra_pinctrl_get_groups_count(struct udevice *dev)
+{
+ return PMUX_DRVGRP_COUNT;
+}
+
+static const char *tegra_pinctrl_get_group_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_drvgrp[selector];
+}
+
+static int tegra_pinctrl_get_functions_count(struct udevice *dev)
+{
+ return PMUX_FUNC_COUNT;
+}
+
+static const char *tegra_pinctrl_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return tegra_pinctrl_to_func[selector];
+}
+
+const struct pinctrl_ops tegra_pinctrl_ops = {
+ .get_pins_count = tegra_pinctrl_get_pins_count,
+ .get_pin_name = tegra_pinctrl_get_pin_name,
+ .get_groups_count = tegra_pinctrl_get_groups_count,
+ .get_group_name = tegra_pinctrl_get_group_name,
+ .get_functions_count = tegra_pinctrl_get_functions_count,
+ .get_function_name = tegra_pinctrl_get_function_name,
+ .set_state = tegra_pinctrl_set_state,
+};
+
+static int tegra_pinctrl_bind(struct udevice *dev)
+{
+ /*
+ * Make sure that the pinctrl driver gets probed after binding
+ * to provide initial configuration and assure that further
+ * probed devices are working correctly.
+ */
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+ return 0;
+}
+
+static const struct udevice_id tegra_pinctrl_ids[] = {
+ { .compatible = "nvidia,tegra20-pinmux" },
+ { },
+};
+
+U_BOOT_DRIVER(tegra_pinctrl) = {
+ .name = "tegra_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = tegra_pinctrl_ids,
+ .bind = tegra_pinctrl_bind,
+ .ops = &tegra_pinctrl_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ PMUX_FUNC_##f2, \
+ PMUX_FUNC_##f3, \
+ }, \
+ }
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra210_pingroups[] = {
+ /* pin, f0, f1, f2, f3 */
+ /* Offset 0x3000 */
+ PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
+ PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
+ PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
+ PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
+ PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
+ PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
+ PIN_RESERVED,
+ PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
+ PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
+ PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
+ PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
+ PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
+ PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
+ PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
+ PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
+ PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
+ PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
+ PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
+ PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
+ PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
+ PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
+ PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
+ PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
+ PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
+ PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
+ PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
+ PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
+ PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
+ PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
+ PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
+ PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
+ PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
+ PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
+ PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
+ PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
+ PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
+ PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
+ PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
+ PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
+ PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
+ PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
+ PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
+ PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
+ PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
+ PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
+ PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
+ PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
+ PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
+ PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
+ PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
+ PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
+ PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
+ PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
+ PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
+ PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
+ PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
+ PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
+ PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
+ PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
+ PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
+ PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
+ PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
+ PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
+ PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
+ PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
+ PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
+ PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
+ PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
+ PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
+ PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
+ PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
+ PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
+ PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
+ PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
- default AXP305_POWER if MACH_SUN50I_H616
default AXP818_POWER if MACH_SUN8I_A83T
default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S
}
}
+ if (IS_ENABLED(CONFIG_MAX77663_GPIO)) {
+ ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER,
+ "gpio", NULL);
+ if (ret) {
+ log_err("cannot bind GPIOs (ret = %d)\n", ret);
+ return ret;
+ }
+ }
+
regulators_node = dev_read_subnode(dev, "regulators");
if (!ofnode_valid(regulators_node)) {
log_err("%s regulators subnode not found!\n", dev->name);
static int palmas_bind(struct udevice *dev)
{
ofnode pmic_node = ofnode_null(), regulators_node;
- ofnode subnode;
+ ofnode subnode, gpio_node;
int children, ret;
if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) {
}
}
+ gpio_node = ofnode_find_subnode(dev_ofnode(dev), "gpio");
+ if (ofnode_valid(gpio_node)) {
+ ret = device_bind_driver_to_node(dev, PALMAS_GPIO_DRIVER,
+ "gpio", gpio_node, NULL);
+ if (ret)
+ log_err("cannot bind GPIOs (ret = %d)\n", ret);
+ }
+
dev_for_each_subnode(subnode, dev) {
const char *name;
char *temp;
#include <dm/device_compat.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
+#include <linux/time.h>
#include <asm/io.h>
/* The channel number of Aspeed pwm controller */
/* PWM fixed value */
#define PWM_ASPEED_FIXED_PERIOD 0xff
-#define NSEC_PER_SEC 1000000000L
-
struct aspeed_pwm_priv {
struct clk clk;
struct regmap *regmap;
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/time.h>
#include <pwm.h>
#define PERIOD_BITS 16
#define PWM_MAX_PRES 10
-#define NSEC_PER_SEC 1000000000L
#define PWM_ENA 0x04
#define PWM_CHANNEL_OFFSET 0x20
#include <linux/bitfield.h>
#include <linux/math64.h>
#include <linux/log2.h>
+#include <linux/time.h>
#include <dm/device_compat.h>
#define CLOCK_CONTROL 0
#define COUNTER_INTERVAL_ENABLE BIT(1)
#define COUNTER_COUNTING_DISABLE BIT(0)
-#define NSEC_PER_SEC 1000000000L
-
#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
#define TTC_CLOCK_CONTROL(reg, channel) \
TTC_REG((reg) + CLOCK_CONTROL, (channel))
#include <linux/math64.h>
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
-
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
#define REG_PWM_A 0x0
#define REG_PWM_B 0x4
#include <div64.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/time.h>
/* PWM registers and bits definitions */
#define PWMCON 0x00
#define PWM_CLK_DIV_MAX 7
#define MAX_PWM_NUM 8
-#define NSEC_PER_SEC 1000000000L
-
enum mtk_pwm_reg_ver {
PWM_REG_V1,
PWM_REG_V2,
#include <dm/device_compat.h>
#include <pwm.h>
#include <asm/io.h>
-
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
/* Time base module registers */
#define TI_EHRPWM_TBCTL 0x00
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
* based on source code of Shlomi Gridish
*/
-#include <common.h>
#include <malloc.h>
#include <command.h>
#include <asm/global_data.h>
#include <asm/armv8/mmu.h>
#include <asm/arch/cpu.h>
#endif
+#ifdef CONFIG_PPC
+#include <asm/ppc.h>
+#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
* @data: Pointer to DSP specific boot data structure
* @mem: Array of available memories
* @num_mem: Number of available memories
+ * @in_use: flag to tell if the core is already in use.
*/
struct k3_dsp_privdata {
struct reset_ctl dsp_rst;
struct k3_dsp_boot_data *data;
struct k3_dsp_mem *mem;
int num_mems;
+ bool in_use;
};
/*
u32 boot_vector;
int ret;
+ if (dsp->in_use) {
+ dev_err(dev,
+ "Invalid op: Trying to load/start on already running core %d\n",
+ dsp->tsp.proc_id);
+ return -EINVAL;
+ }
+
dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
ret = ti_sci_proc_request(&dsp->tsp);
if (ret)
ti_sci_proc_power_domain_off(&dsp->tsp);
}
+ dsp->in_use = true;
proc_release:
ti_sci_proc_release(&dsp->tsp);
dev_dbg(dev, "%s\n", __func__);
+ dsp->in_use = false;
ti_sci_proc_request(&dsp->tsp);
reset_assert(&dsp->dsp_rst);
ti_sci_proc_power_domain_off(&dsp->tsp);
.read = arm_rndr_read,
};
-static int arm_rndr_probe(struct udevice *dev)
+static int arm_rndr_bind(struct udevice *dev)
{
if (!cpu_has_rndr())
- return -ENODEV;
+ return -ENOENT;
return 0;
}
.name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = &arm_rndr_ops,
- .probe = arm_rndr_probe,
+ .bind = arm_rndr_bind,
};
U_BOOT_DRVINFO(cpu_arm_rndr) = {
}
break;
case DEAD:
- return -ENODEV;
+ return -ENOENT;
}
}
}
/**
- * riscv_zkr_probe() - check if the seed register is available
+ * riscv_zkr_bind() - check if the seed register is available
*
- * If the SBI software has not set mseccfg.sseed=1 or the Zkr
- * extension is not available this probe function will result
- * in an exception. Currently we cannot recover from this.
+ * If the SBI software has not set mseccfg.sseed=1 or the Zkr extension is not
+ * available, reading the seed register will result in an exception from which
+ * this function safely resumes.
*
* @dev: RNG device
* Return: 0 if successfully probed
*/
-static int riscv_zkr_probe(struct udevice *dev)
+static int riscv_zkr_bind(struct udevice *dev)
{
struct resume_data resume;
int ret;
val = read_seed();
set_resume(NULL);
if (ret)
- return -ENODEV;
+ return -ENOENT;
+
+ return 0;
+}
+
+/**
+ * riscv_zkr_probe() - check if entropy is available
+ *
+ * The bind method already checked that the seed register can be read without
+ * excpetiong. Here we wait for the self test to finish and entropy becoming
+ * available.
+ *
+ * @dev: RNG device
+ * Return: 0 if successfully probed
+ */
+static int riscv_zkr_probe(struct udevice *dev)
+{
+ u32 val;
do {
val = read_seed();
} while (val == BIST || val == WAIT);
if (val == DEAD)
- return -ENODEV;
+ return -ENOENT;
return 0;
}
.name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = &riscv_zkr_ops,
+ .bind = riscv_zkr_bind,
.probe = riscv_zkr_probe,
};
config SCSI
- bool "Support SCSI controllers"
+ bool "Support SCSI controllers with driver model"
help
This enables support for SCSI (Small Computer System Interface),
a parallel interface widely used with storage peripherals such as
hard drives and optical drives. The SCSI standards define physical
interfaces as well as protocols for controlling devices and
- tranferring data.
-
-config DM_SCSI
- bool "Support SCSI controllers with driver model"
- help
- This option enables the SCSI (Small Computer System Interface) uclass
- which supports SCSI and SATA HDDs. For every device configuration
- (IDs/LUNs) a block device is created with RAW read/write and
- filesystem support.
-
-if SCSI && !DM_SCSI
-
-config SCSI_AHCI_PLAT
- bool "Platform-specific init of AHCI"
- help
- This enables a way for boards to set up an AHCI device manually, by
- called ahci_init() and providing an ahci_reset() mechanism.
-
- This is deprecated. An AHCI driver should be provided instead.
-
-config SYS_SCSI_MAX_SCSI_ID
- int "Maximum supported SCSI ID"
- default 1
- help
- Sets the maximum number of SCSI IDs to scan when looking for devices.
- IDs from 0 to (this value - 1) are scanned.
-
- This is deprecated and is not needed when BLK is enabled.
-
-config SYS_SCSI_MAX_LUN
- int "Maximum support SCSI LUN"
- default 1
- help
- Sets the maximum number of SCSI Logical Unit Numbers (LUNs) to scan on
- devices. LUNs from 0 to (this value - 1) are scanned.
-
- This is deprecated and is not needed when CONFIG_DM_SCSI is enabled.
-
-endif
+ tranferring data. For every device configuration (IDs/LUNs) a block
+ device is created with RAW read/write and filesystem support.
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
-obj-$(CONFIG_SCSI) += scsi.o
-
+obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
ifdef CONFIG_SCSI
-ifdef CONFIG_DM_SCSI
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o
+obj-$(CONFIG_SANDBOX) += sandbox_scsi.o
+obj-$(CONFIG_SANDBOX) += scsi_emul.o
endif
endif
-endif
-
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_SATA
-obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
-obj-$(CONFIG_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
endif
endif
-
-ifdef CONFIG_SCSI
-obj-$(CONFIG_SANDBOX) += sandbox_scsi.o
-obj-$(CONFIG_SANDBOX) += scsi_emul.o
-endif
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
-#if !defined(CONFIG_DM_SCSI)
-# ifdef CFG_SCSI_DEV_LIST
-# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST
-# else
-# ifdef CONFIG_SATA_ULI5288
-
-# define SCSI_VEND_ID 0x10b9
-# define SCSI_DEV_ID 0x5288
-
-# elif !defined(CONFIG_SCSI_AHCI_PLAT)
-# error no scsi device defined
-# endif
-# define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-# endif
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
- !defined(CONFIG_DM_SCSI)
-const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
-#endif
static struct scsi_cmd tempccb; /* temporary scsi command buffer */
DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */
-#if !defined(CONFIG_DM_SCSI)
-static int scsi_max_devs; /* number of highest available scsi device */
-
-static int scsi_curr_dev; /* current device */
-
-static struct blk_desc scsi_dev_desc[SCSI_MAX_DEVICE];
-#endif
-
/* almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
}
-#ifdef CONFIG_BLK
static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start,
unsigned short blocks)
{
return 1;
}
#endif /* CONFIG_BOUNCE_BUFFER */
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
- !defined(CONFIG_DM_SCSI)
-void scsi_init(void)
-{
- int busdevfunc = -1;
- int i;
- /*
- * Find a device from the list, this driver will support a single
- * controller.
- */
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- /* get PCI Device ID */
- struct udevice *dev;
- int ret;
-
- ret = dm_pci_find_device(scsi_device_list[i].vendor,
- scsi_device_list[i].device, 0, &dev);
- if (!ret) {
- busdevfunc = dm_pci_get_bdf(dev);
- break;
- }
- if (busdevfunc != -1)
- break;
- }
-
- if (busdevfunc == -1) {
- printf("Error: SCSI Controller(s) ");
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- printf("%04X:%04X ",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device);
- }
- printf("not found\n");
- return;
- }
-#ifdef DEBUG
- else {
- printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device,
- (busdevfunc >> 16) & 0xFF,
- (busdevfunc >> 11) & 0x1F,
- (busdevfunc >> 8) & 0x7);
- }
-#endif
- bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
- scsi_low_level_init(busdevfunc);
- scsi_scan(true);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
-}
-#endif
/* copy src to dest, skipping leading and trailing blanks
* and null terminate the string
#endif /* CONFIG_BOUNCE_BUFFER */
}
-#if !defined(CONFIG_DM_SCSI)
-/**
- * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties
- *
- * @dev_desc: Block device description pointer
- * @devnum: Device number
- */
-static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum)
-{
- dev_desc->lba = 0;
- dev_desc->blksz = 0;
- dev_desc->uclass_id = UCLASS_SCSI;
- dev_desc->devnum = devnum;
- dev_desc->part_type = PART_TYPE_UNKNOWN;
-
- scsi_init_dev_desc_priv(dev_desc);
-}
-#endif
-
/**
* scsi_detect_dev - Detect scsi device
*
* (re)-scan the scsi bus and reports scsi device info
* to the user if mode = 1
*/
-#if defined(CONFIG_DM_SCSI)
static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose)
{
int ret;
return 0;
}
-#else
-int scsi_scan(bool verbose)
-{
- unsigned char i, lun;
- int ret;
-
- if (verbose)
- printf("scanning bus for devices...\n");
- for (i = 0; i < SCSI_MAX_DEVICE; i++)
- scsi_init_dev_desc(&scsi_dev_desc[i], i);
-
- scsi_max_devs = 0;
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
- for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- struct blk_desc *bdesc = &scsi_dev_desc[scsi_max_devs];
-
- ret = scsi_detect_dev(NULL, i, lun, bdesc);
- if (ret)
- continue;
- part_init(bdesc);
-
- if (verbose) {
- printf(" Device %d: ", bdesc->devnum);
- dev_print(bdesc);
- }
- scsi_max_devs++;
- } /* next LUN */
- }
- if (scsi_max_devs > 0)
- scsi_curr_dev = 0;
- else
- scsi_curr_dev = -1;
-
- printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
- env_set_ulong("scsidevs", scsi_max_devs);
-#endif
- return 0;
-}
-#endif
-#ifdef CONFIG_BLK
static const struct blk_ops scsi_blk_ops = {
.read = scsi_read,
.write = scsi_write,
.id = UCLASS_BLK,
.ops = &scsi_blk_ops,
};
-#else
-U_BOOT_LEGACY_BLK(scsi) = {
- .uclass_idname = "scsi",
- .uclass_id = UCLASS_SCSI,
- .max_devs = SCSI_MAX_DEVICE,
- .desc = scsi_dev_desc,
-};
-#endif
#include <dm.h>
#include <errno.h>
#include <linux/delay.h>
+#include <linux/time.h>
#include <misc.h>
#include <serial.h>
#define UART_OVERSAMPLING 32
#define STALE_TIMEOUT 160
-#define USEC_PER_SEC 1000000L
-
/* Registers*/
#define GENI_FORCE_DEFAULT_REG 0x20
#define GENI_SER_M_CLK_CFG 0x48
struct npcm_uart *uart = plat->reg;
u16 divisor;
+ if (IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT))
+ return 0;
+
/* BaudOut = UART Clock / (16 * [Divisor + 2]) */
- divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate) - 2;
setbits_8(&uart->lcr, LCR_DLAB);
writeb(divisor & 0xff, &uart->dll);
static int npcm_serial_probe(struct udevice *dev)
{
struct npcm_serial_plat *plat = dev_get_plat(dev);
- struct npcm_uart *uart = plat->reg;
+ struct npcm_uart *uart;
struct clk clk, parent;
u32 freq;
int ret;
plat->reg = dev_read_addr_ptr(dev);
- freq = dev_read_u32_default(dev, "clock-frequency", 0);
+ uart = plat->reg;
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
+ if (!IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) {
+ freq = dev_read_u32_default(dev, "clock-frequency", 24000000);
- ret = clk_get_by_index(dev, 1, &parent);
- if (!ret) {
- ret = clk_set_parent(&clk, &parent);
- if (ret)
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
return ret;
- }
- ret = clk_set_rate(&clk, freq);
- if (ret < 0)
- return ret;
- plat->uart_clk = ret;
+ ret = clk_get_by_index(dev, 1, &parent);
+ if (!ret) {
+ ret = clk_set_parent(&clk, &parent);
+ if (ret)
+ return ret;
+ }
+
+ if (freq) {
+ ret = clk_set_rate(&clk, freq);
+ if (ret < 0)
+ return ret;
+ }
+ plat->uart_clk = clk_get_rate(&clk);
+ }
/* Disable all interrupt */
writeb(0, &uart->ier);
*/
#define ONE_BYTE_B115200_US 87
-static void _stm32_serial_setbrg(fdt_addr_t base,
+static void _stm32_serial_setbrg(void __iomem *base,
struct stm32_uart_info *uart_info,
u32 clock_rate,
int baudrate)
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
- u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+ void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
u32 config = 0;
uint parity = SERIAL_GET_PARITY(serial_config);
uint bits = SERIAL_GET_BITS(serial_config);
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ void __iomem *base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
if ((isr & USART_ISR_RXNE) == 0)
return readl(base + RDR_OFFSET(stm32f4));
}
-static int _stm32_serial_putc(fdt_addr_t base,
+static int _stm32_serial_putc(void __iomem *base,
struct stm32_uart_info *uart_info,
const char c)
{
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ void __iomem *base = plat->base;
if (input)
return readl(base + ISR_OFFSET(stm32f4)) &
USART_ISR_TXE ? 0 : 1;
}
-static void _stm32_serial_init(fdt_addr_t base,
+static void _stm32_serial_init(void __iomem *base,
struct stm32_uart_info *uart_info)
{
bool stm32f4 = uart_info->stm32f4;
static int stm32_serial_of_to_plat(struct udevice *dev)
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
- plat->base = dev_read_addr(dev);
- if (plat->base == FDT_ADDR_T_NONE)
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+ plat->base = (void __iomem *)addr;
+
return 0;
}
static inline void _debug_uart_init(void)
{
- fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
_stm32_serial_init(base, uart_info);
static inline void _debug_uart_putc(int c)
{
- fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
/* Information about a serial port */
struct stm32x7_serial_plat {
- fdt_addr_t base; /* address of registers in physical memory */
+ void __iomem *base; /* address of registers in physical memory */
struct stm32_uart_info *uart_info;
unsigned long int clock_rate;
};
#include <errno.h>
#include <common.h>
+#include <asm/io.h>
#include <asm/ti-common/keystone_serdes.h>
#include <linux/bitops.h>
/* transfer loop */
while (data_bytes > 0) {
- size_t curr_step = min(step_size, data_bytes);
+ size_t curr_step = min(step_size, (size_t)data_bytes);
int ret;
/* copy tx data */
#include <common.h>
#include <clk.h>
#include <log.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <linux/io.h>
#include <linux/sizes.h>
+#include <linux/time.h>
#include <zynqmp_firmware.h>
#include "cadence_qspi.h"
#include <dt-bindings/power/xlnx-versal-power.h>
-#define NSEC_PER_SEC 1000000000L
-
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
#define CQSPI_READ 2
return 0;
}
+__weak ofnode cadence_qspi_get_subnode(struct udevice *dev)
+{
+ return dev_read_first_subnode(dev);
+}
+
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
/* All other parameters are embedded in the child node */
- subnode = dev_read_first_subnode(bus);
+ subnode = cadence_qspi_get_subnode(bus);
if (!ofnode_valid(subnode)) {
printf("Error: subnode with SPI flash config missing!\n");
return -ENODEV;
int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv);
int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
int cadence_qspi_versal_flash_reset(struct udevice *dev);
+ofnode cadence_qspi_get_subnode(struct udevice *dev);
void cadence_qspi_apb_enable_linear_mode(bool enable);
#endif /* __CADENCE_QSPI_H__ */
}
/* Timeout, still in busy mode. */
- printf("QSPI: QSPI is still busy after poll for %d times.\n",
- CQSPI_REG_RETRY);
+ printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout);
return 0;
}
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <common.h>
#include <log.h>
#include <spi.h>
#include <malloc.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>
-
-/* linux/include/time.h */
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
DECLARE_GLOBAL_DATA_PTR;
#include <spi-mem.h>
#include <asm/io.h>
#include <linux/log2.h>
+#include <linux/time.h>
#include <linux/iopoll.h>
#include <linux/bitfield.h>
return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
val, (val & mask) == mask,
- 200 * 1000);
+ 200 * USEC_PER_MSEC);
}
static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc,
writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
memcpy(&data, buf + len - pad, pad);
if (speed > priv->max_hz)
speed = priv->max_hz;
- divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1);
+ divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed)) - 1;
if (divisor > MAX_DIV)
divisor = MAX_DIV;
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
#define SPISSR_MASK(cs) (1 << (cs))
#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
-#define SPISSR_OFF ~0UL
+#define SPISSR_OFF (~0U)
/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE 0x0a
u8 startup;
};
+static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs)
+{
+ u8 sr;
+ int n_words = 0;
+
+ /*
+ * Before the buffer_size detection reset the core
+ * to make sure to start with a clean state.
+ */
+ writel(SPISSR_RESET_VALUE, ®s->srr);
+
+ /* Fill the Tx FIFO with as many words as possible */
+ do {
+ writel(0, ®s->spidtr);
+ sr = readl(®s->spisr);
+ n_words++;
+ } while (!(sr & SPISR_TX_FULL));
+
+ return n_words;
+}
+
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
regs = priv->regs = dev_read_addr_ptr(bus);
priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
+ if (!priv->fifo_depth)
+ priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
writel(SPISSR_RESET_VALUE, ®s->srr);
return i;
}
-static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
+static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 len)
{
- struct udevice *bus = spi->dev->parent;
+ struct udevice *bus = dev->parent;
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
u32 count, txbytes, rxbytes;
return 0;
}
-static void xilinx_spi_startup_block(struct spi_slave *spi)
+static void xilinx_spi_startup_block(struct udevice *dev)
{
- struct dm_spi_slave_plat *slave_plat =
- dev_get_parent_plat(spi->dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
unsigned char txp;
unsigned char rxp[8];
* Perform a dummy read as a work around for
* the startup block issue.
*/
- spi_cs_activate(spi->dev, slave_plat->cs);
+ spi_cs_activate(dev, slave_plat->cs);
txp = 0x9f;
- start_transfer(spi, (void *)&txp, NULL, 1);
+ start_transfer(dev, (void *)&txp, NULL, 1);
- start_transfer(spi, NULL, (void *)rxp, 6);
+ start_transfer(dev, NULL, (void *)rxp, 6);
- spi_cs_deactivate(spi->dev);
+ spi_cs_deactivate(dev);
+}
+
+static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ int ret;
+
+ spi_cs_activate(dev, slave_plat->cs);
+ ret = start_transfer(dev, dout, din, bitlen / 8);
+ spi_cs_deactivate(dev);
+ return ret;
}
static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
* as QSPI provides command. So first command fails.
*/
if (!startup) {
- xilinx_spi_startup_block(spi);
+ xilinx_spi_startup_block(spi->dev);
startup++;
}
spi_cs_activate(spi->dev, slave_plat->cs);
if (op->cmd.opcode) {
- ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
+ ret = start_transfer(spi->dev, (void *)&op->cmd.opcode,
+ NULL, 1);
if (ret)
goto done;
}
addr_buf[i] = op->addr.val >>
(8 * (op->addr.nbytes - i - 1));
- ret = start_transfer(spi, (void *)addr_buf, NULL,
+ ret = start_transfer(spi->dev, (void *)addr_buf, NULL,
op->addr.nbytes);
if (ret)
goto done;
dummy_len = (op->dummy.nbytes * op->data.buswidth) /
op->dummy.buswidth;
- ret = start_transfer(spi, NULL, NULL, dummy_len);
+ ret = start_transfer(spi->dev, NULL, NULL, dummy_len);
if (ret)
goto done;
}
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN) {
- ret = start_transfer(spi, NULL,
+ ret = start_transfer(spi->dev, NULL,
op->data.buf.in, op->data.nbytes);
} else {
- ret = start_transfer(spi, op->data.buf.out,
+ ret = start_transfer(spi->dev, op->data.buf.out,
NULL, op->data.nbytes);
}
if (ret)
static const struct dm_spi_ops xilinx_spi_ops = {
.claim_bus = xilinx_spi_claim_bus,
.release_bus = xilinx_spi_release_bus,
+ .xfer = xilinx_spi_xfer,
.set_speed = xilinx_spi_set_speed,
.set_mode = xilinx_spi_set_mode,
.mem_ops = &xilinx_spi_mem_ops,
if SYSINFO
+config SYSINFO_EXTRA
+ bool "Show extra information on startup"
+ help
+ Enable this to see extra information on startup. Normally only the
+ model is shown, but with this option the vendor and any prior-stage
+ firmware's version and date are shown as well.
+
config SPL_SYSINFO
depends on SPL_DM
bool "Enable board driver support in SPL"
int r;
if (type != SYSRESET_POWER_OFF)
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
debug("GPIO poweroff\n");
psci_sys_poweroff();
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
state->last_sysreset = type;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
return -EACCES;
sandbox_exit();
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
return ret;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
return ret;
return -EINPROGRESS;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
outb(value, IO_PORT_RESET);
if (ret)
return ret;
+ if (!shm_size) {
+ *count = 0;
+ return 0;
+ }
+
ret = tee_shm_alloc(dev, shm_size, 0, shm);
if (ret) {
dev_err(dev, "Failed to allocated shared memory: %d\n", ret);
ret = enum_services(dev, &service_list, &service_count, tee_sess,
PTA_CMD_GET_DEVICES);
- if (!ret)
+ if (!ret && service_count)
ret = bind_service_list(dev, service_list, service_count);
tee_shm_free(service_list);
+ service_list = NULL;
ret2 = enum_services(dev, &service_list, &service_count, tee_sess,
PTA_CMD_GET_DEVICES_SUPP);
- if (!ret2)
+ if (!ret2 && service_count)
ret2 = bind_service_list(dev, service_list, service_count);
tee_shm_free(service_list);
if (IS_ENABLED(CONFIG_OPTEE_SERVICE_DISCOVERY)) {
ret = bind_service_drivers(dev);
if (ret)
- return ret;
+ dev_warn(dev, "optee service enumeration failed: %d\n", ret);
} else if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
/*
* Discovery of TAs on the TEE bus is not supported in U-Boot:
#include <reset.h>
#include <timer.h>
#include <dm/device_compat.h>
-#include <linux/kconfig.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 StarFive, Inc. All rights reserved.
- * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ * Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
*/
#include <common.h>
int ret;
priv->base = dev_read_addr_ptr(dev);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ if (!priv->base)
+ return -EINVAL;
timer_channel = dev_read_u32_default(dev, "channel", 0);
priv->base = priv->base + (0x40 * timer_channel);
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
- /* Initiate timer, channel 0 */
- /* Unmask Interrupt Mask */
+ /*
+ * Initiate timer, channel 0
+ * Unmask Interrupt Mask
+ */
writel(0, priv->base + STF_TIMER_INT_MASK);
/* Single run mode Setting */
if (dev_read_bool(dev, "single-run"))
writel(1, priv->base + STF_TIMER_CTL);
/* Set Reload value */
- priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff);
+ priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U);
writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
/* Enable to start timer */
writel(1, priv->base + STF_TIMER_ENABLE);
};
U_BOOT_DRIVER(jh8100_starfive_timer) = {
- .name = "jh8100_starfive_timer",
+ .name = "starfive_timer",
.id = UCLASS_TIMER,
.of_match = starfive_ids,
.probe = starfive_probe,
err = clk_get_by_index(dev, 0, &timer_clk);
if (!err) {
ret = clk_get_rate(&timer_clk);
- if (IS_ERR_VALUE(ret))
- return ret;
- uc_priv->clock_rate = ret;
- } else {
- uc_priv->clock_rate =
- dev_read_u32_default(dev, "clock-frequency", 0);
+ if (!IS_ERR_VALUE(ret)) {
+ uc_priv->clock_rate = ret;
+ return 0;
+ }
}
+
+ uc_priv->clock_rate = dev_read_u32_default(dev, "clock-frequency", 0);
}
return 0;
u8 status;
int ret;
- if (!chip)
- return -ENODEV;
-
ret = tpm_tis_request_locality(dev, 0);
if (ret < 0)
return -EBUSY;
config UFS
bool "Support UFS controllers"
- depends on DM_SCSI
+ depends on SCSI
select CHARSET
help
This selects support for Universal Flash Subsystem (UFS).
This selects the platform driver for the Cadence UFS host
controller present on present TI's J721e devices.
+config UFS_PCI
+ bool "PCI bus based UFS Controller support"
+ depends on PCI && UFS
+ help
+ This selects the PCI UFS Host Controller Interface. Select this if
+ you have UFS Host Controller with PCI Interface.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
config TI_J721E_UFS
bool "Glue Layer driver for UFS on TI J721E devices"
help
obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o
obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o
obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
+obj-$(CONFIG_UFS_PCI) += ufs-pci.o
obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/time.h>
#include "ufs.h"
-#define USEC_PER_SEC 1000000L
-
#define CDNS_UFS_REG_HCLKDIV 0xFC
#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <ufs.h>
+#include <dm/device_compat.h>
+#include "ufs.h"
+
+static int ufs_pci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ufs_scsi_bind(dev, &scsi_dev);
+}
+
+static int ufs_pci_probe(struct udevice *dev)
+{
+ int err;
+
+ err = ufshcd_probe(dev, NULL);
+ if (err)
+ dev_err(dev, "%s failed (ret=%d)\n", __func__, err);
+
+ return err;
+}
+
+U_BOOT_DRIVER(ufs_pci) = {
+ .name = "ufs_pci",
+ .id = UCLASS_UFS,
+ .bind = ufs_pci_bind,
+ .probe = ufs_pci_probe,
+};
+
+static struct pci_device_id ufs_supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_UFS) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(ufs_pci, ufs_supported);
// SPDX-License-Identifier: GPL-2.0
/**
- * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver
+ * ufs-uclass.c - Universal Flash Storage (UFS) Uclass driver
*
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
// SPDX-License-Identifier: GPL-2.0+
/**
- * ufs.c - Universal Flash Subsystem (UFS) driver
+ * ufs.c - Universal Flash Storage (UFS) driver
*
* Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
* to u-boot.
UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
0);
if (err) {
- dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
+ dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n",
__func__, peer, i, err);
break;
}
ufshcd_enable_run_stop_reg(hba);
} else {
dev_err(hba->dev,
- "Host controller not ready to process requests");
+ "Host controller not ready to process requests\n");
err = -EIO;
goto out;
}
memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
} else {
dev_warn(hba->dev,
- "%s: Response size is bigger than buffer",
+ "%s: Response size is bigger than buffer\n",
__func__);
return -EINVAL;
}
&header_len);
if (ret) {
- dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
+ dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n",
__func__, desc_id);
return ret;
} else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
- dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
+ dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n",
__func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
desc_id);
ret = -EINVAL;
/* Sanity checks */
if (ret || !buff_len) {
- dev_err(hba->dev, "%s: Failed to get full descriptor length",
+ dev_err(hba->dev, "%s: Failed to get full descriptor length\n",
__func__);
return ret;
}
&buff_len);
if (ret) {
- dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
+ dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
__func__, desc_id, desc_index, param_offset, ret);
goto out;
}
/* Sanity check */
if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
- dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
+ dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
__func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
ret = -EINVAL;
goto out;
struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
struct scsi_plat *scsi_plat;
struct udevice *scsi_dev;
+ void __iomem *mmio_base;
int err;
device_find_first_child(ufs_dev, &scsi_dev);
hba->dev = ufs_dev;
hba->ops = hba_ops;
- hba->mmio_base = dev_read_addr_ptr(ufs_dev);
+
+ if (device_is_on_pci_bus(ufs_dev)) {
+ mmio_base = dm_pci_map_bar(ufs_dev, PCI_BASE_ADDRESS_0, 0, 0,
+ PCI_REGION_TYPE, PCI_REGION_MEM);
+ } else {
+ mmio_base = dev_read_addr_ptr(ufs_dev);
+ }
+ hba->mmio_base = mmio_base;
/* Set descriptor lengths to specification defaults */
ufshcd_def_desc_sizes(hba);
hba->version != UFSHCI_VERSION_11 &&
hba->version != UFSHCI_VERSION_20 &&
hba->version != UFSHCI_VERSION_21 &&
- hba->version != UFSHCI_VERSION_30)
+ hba->version != UFSHCI_VERSION_30 &&
+ hba->version != UFSHCI_VERSION_31)
dev_err(hba->dev, "invalid UFS version 0x%x\n",
hba->version);
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
+ UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
};
/* Interrupt disable masks */
*/
#include <common.h>
-#include <asm-generic/io.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/usb/gadget.h>
#include <linux/bitfield.h>
#include <linux/math64.h>
+#include <linux/time.h>
#include "core.h"
#include "gadget.h"
#include "linux-compat.h"
-#define NSEC_PER_SEC 1000000000L
-
static LIST_HEAD(dwc3_list);
/* -------------------------------------------------------------------------- */
#include <common.h>
#include <log.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <generic-phy.h>
#include <linux/delay.h>
+#include <linux/io.h>
#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#define DEBUG
#include <common.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <generic-phy.h>
+#include <linux/io.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
bool "USB Gadget Support"
depends on DM
select DM_USB
+ imply CMD_BIND
help
USB is a master/slave protocol, organized with one master
host (such as a PC) controlling up to 127 peripheral devices.
#ifndef __BCM_UDC_OTG_H
#define __BCM_UDC_OTG_H
-#include <common.h>
-
static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask)
{
writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr));
unsigned int short_packet_received:1;
unsigned int bad_lun_okay:1;
unsigned int running:1;
+ unsigned int eject:1;
int thread_wakeup_needed;
struct completion thread_notifier;
}
if (k == 10) {
+ /* Handle START-STOP UNIT */
+ if (common->eject)
+ return -EPIPE;
+
/* Handle CTRL+C */
if (ctrlc())
return -EPIPE;
return -EINVAL;
}
+ common->eject = 1;
+
return 0;
}
{
debug("%s: sector %lx, count %lx, buf %lx\n",
__func__, sector, count, (ulong)buf);
- memcpy(buf, (void *)(load->dev + sector), count);
+ memcpy(buf, (void *)(load->priv + sector), count);
return count;
}
struct spl_load_info load;
debug("Found FIT\n");
- load.dev = header;
- load.bl_len = 1;
+ load.priv = header;
+ spl_set_bl_len(&load, 1);
load.read = sdp_load_read;
spl_load_simple_fit(spl_image, &load, 0,
header);
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- load.dev = header;
- load.bl_len = 1;
+ load.priv = header;
+ spl_set_bl_len(&load, 1);
load.read = sdp_load_read;
spl_load_imx_container(spl_image, &load, 0);
return SDP_EXIT;
int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
{
struct usb_udc *udc = NULL;
+ unsigned int udc_count = 0;
int ret;
if (!driver || !driver->bind || !driver->setup)
mutex_lock(&udc_lock);
list_for_each_entry(udc, &udc_list, list) {
+ udc_count++;
+
/* For now we take the first one */
if (!udc->driver)
goto found;
}
- printf("couldn't find an available UDC\n");
+ if (!udc_count)
+ printf("No UDC available in the system\n");
+ else
+ /* When this happens, users should 'unbind <class> <index>'
+ * using the output of 'dm tree' and looking at the line right
+ * after the USB peripheral/device controller.
+ */
+ printf("All UDCs in use (%d available), use the unbind command\n",
+ udc_count);
mutex_unlock(&udc_lock);
return -ENODEV;
found:
#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
#define __MUSB_LINUX_PLATFORM_ARCH_H__
-#ifndef __UBOOT__
#include <linux/io.h>
-#else
-#include <asm/io.h>
-#endif
-
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
- && !defined(CONFIG_PPC32) \
- && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
- && !defined(CONFIG_M68K)
-static inline void readsl(const void __iomem *addr, void *buf, int len)
- { insl((unsigned long)addr, buf, len); }
-static inline void readsw(const void __iomem *addr, void *buf, int len)
- { insw((unsigned long)addr, buf, len); }
-static inline void readsb(const void __iomem *addr, void *buf, int len)
- { insb((unsigned long)addr, buf, len); }
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
- { outsl((unsigned long)addr, buf, len); }
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
- { outsw((unsigned long)addr, buf, len); }
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
- { outsb((unsigned long)addr, buf, len); }
-
-#endif
/* NOTE: these offsets are all in bytes */
config CONSOLE_TRUETYPE
bool "Support a console that uses TrueType fonts"
- select CMD_SELECT_FONT
help
TrueTrype fonts can provide outline-drawing capability rather than
needing to provide a bitmap for each font and size that is needed.
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include <linux/time.h>
#include <video_bridge.h>
#define HWVER_131 0x31333100 /* IP version 1.31 */
#define PHY_STATUS_TIMEOUT_US 10000
#define CMD_PKT_STATUS_TIMEOUT_US 20000
-#define MSEC_PER_SEC 1000
-
struct dw_mipi_dsi {
struct mipi_dsi_host dsi_host;
struct mipi_dsi_device *device;
#include <common.h>
#include <dm.h>
-#include <common.h>
#include <display.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <linux/bitops.h>
+#include <linux/time.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
-#define USEC_PER_SEC 1000000L
-
/*
* DSI wrapper registers & bit definitions
* Note: registers are named as in the Reference Manual
setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
}
+#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
+static int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+ u32 sdram_size = gd->ram_size;
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 dma_size;
+ int ret;
+
+ ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size);
+ if (ret) {
+ dev_err(dev, "failed to get dma address\n");
+ return ret;
+ }
+
+ uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align);
+ return 0;
+}
+#else
+static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+ /* Delegate framebuffer allocation to video-uclass */
+ return 0;
+}
+#endif
+
static int stm32_ltdc_probe(struct udevice *dev)
{
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
priv->crop_h = timings.vactive.typ;
priv->alpha = 0xFF;
+ ret = stm32_ltdc_alloc_fb(dev);
+ if (ret)
+ return ret;
+
dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
timings.hactive.typ, timings.vactive.typ,
VNBITS(priv->l2bpp), uc_plat->base);
#include <panel.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/time.h>
#include <power/regulator.h>
#include <asm/gpio.h>
#include "mipi-phy.h"
-#define USEC_PER_SEC 1000000L
-#define NSEC_PER_SEC 1000000000L
-
struct tegra_dsi_priv {
struct mipi_dsi_host host;
struct mipi_dsi_device device;
config VIRTIO_NET
bool "virtio net driver"
- depends on VIRTIO
+ depends on VIRTIO && NETDEVICES
help
This is the virtual net driver for virtio. It can be used with
QEMU based targets.
Enable the STM32 watchdog (IWDG) driver. Enable support to
configure STM32's on-SoC watchdog.
+config WDT_STARFIVE
+ bool "StarFive watchdog timer support"
+ depends on WDT
+ imply WATCHDOG
+ help
+ Enable support for the watchdog timer of StarFive JH7110 SoC.
+
config WDT_SUNXI
bool "Allwinner sunxi watchdog timer support"
depends on WDT && ARCH_SUNXI
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
+obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Starfive Watchdog driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <wdt.h>
+#include <linux/iopoll.h>
+
+/* JH7110 Watchdog register define */
+#define STARFIVE_WDT_JH7110_LOAD 0x000
+#define STARFIVE_WDT_JH7110_VALUE 0x004
+#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
+ * [0]: reset enable;
+ * [1]: interrupt enable && watchdog enable
+ * [31:2]: reserved.
+ */
+#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
+#define STARFIVE_WDT_JH7110_IMS 0x014
+#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
+
+/* WDOGCONTROL */
+#define STARFIVE_WDT_ENABLE 0x1
+#define STARFIVE_WDT_EN_SHIFT 0
+#define STARFIVE_WDT_RESET_EN 0x1
+#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
+
+/* WDOGLOCK */
+#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
+
+/* WDOGINTCLR */
+#define STARFIVE_WDT_INTCLR 0x1
+#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
+
+#define STARFIVE_WDT_MAXCNT 0xffffffff
+#define STARFIVE_WDT_DEFAULT_TIME (15)
+#define STARFIVE_WDT_DELAY_US 0
+#define STARFIVE_WDT_TIMEOUT_US 10000
+
+/* module parameter */
+#define STARFIVE_WDT_EARLY_ENA 0
+
+struct starfive_wdt_variant {
+ unsigned int control; /* Watchdog Control Resgister for reset enable */
+ unsigned int load; /* Watchdog Load register */
+ unsigned int reload; /* Watchdog Reload Control register */
+ unsigned int enable; /* Watchdog Enable Register */
+ unsigned int value; /* Watchdog Counter Value Register */
+ unsigned int int_clr; /* Watchdog Interrupt Clear Register */
+ unsigned int unlock; /* Watchdog Lock Register */
+ unsigned int int_status; /* Watchdog Interrupt Status Register */
+
+ u32 unlock_key;
+ char enrst_shift;
+ char en_shift;
+ bool intclr_check; /* whether need to check it before clearing interrupt */
+ char intclr_ava_shift;
+ bool double_timeout; /* The watchdog need twice timeout to reboot */
+};
+
+struct starfive_wdt_priv {
+ void __iomem *base;
+ struct clk *core_clk;
+ struct clk *apb_clk;
+ struct reset_ctl_bulk *rst;
+ const struct starfive_wdt_variant *variant;
+ unsigned long freq;
+ u32 count; /* count of timeout */
+ u32 reload; /* restore the count */
+};
+
+/* Register layout and configuration for the JH7110 */
+static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
+ .control = STARFIVE_WDT_JH7110_CONTROL,
+ .load = STARFIVE_WDT_JH7110_LOAD,
+ .enable = STARFIVE_WDT_JH7110_CONTROL,
+ .value = STARFIVE_WDT_JH7110_VALUE,
+ .int_clr = STARFIVE_WDT_JH7110_INTCLR,
+ .unlock = STARFIVE_WDT_JH7110_LOCK,
+ .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
+ .int_status = STARFIVE_WDT_JH7110_IMS,
+ .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
+ .en_shift = STARFIVE_WDT_EN_SHIFT,
+ .intclr_check = false,
+ .double_timeout = true,
+};
+
+static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt)
+{
+ int ret;
+
+ ret = clk_enable(wdt->apb_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(wdt->core_clk);
+ if (ret) {
+ clk_disable(wdt->apb_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt)
+{
+ clk_disable(wdt->core_clk);
+ clk_disable(wdt->apb_clk);
+}
+
+/* Write unlock-key to unlock. Write other value to lock. */
+static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt)
+{
+ writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
+}
+
+static void starfive_wdt_lock(struct starfive_wdt_priv *wdt)
+{
+ writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
+}
+
+/* enable watchdog interrupt to reset/reboot */
+static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->control);
+ val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
+ writel(val, wdt->base + wdt->variant->control);
+}
+
+/* waiting interrupt can be free to clear */
+static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt)
+{
+ u32 value;
+
+ return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value,
+ !(value & BIT(wdt->variant->intclr_ava_shift)),
+ STARFIVE_WDT_TIMEOUT_US);
+}
+
+/* clear interrupt signal before initialization or reload */
+static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt)
+{
+ int ret;
+
+ if (wdt->variant->intclr_check) {
+ ret = starfive_wdt_wait_int_free(wdt);
+ if (ret)
+ return ret;
+ }
+ writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
+
+ return 0;
+}
+
+static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt,
+ u32 val)
+{
+ writel(val, wdt->base + wdt->variant->load);
+}
+
+/* enable watchdog */
+static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->enable);
+ val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
+ writel(val, wdt->base + wdt->variant->enable);
+}
+
+/* disable watchdog */
+static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt)
+{
+ u32 val;
+
+ val = readl(wdt->base + wdt->variant->enable);
+ val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
+ writel(val, wdt->base + wdt->variant->enable);
+}
+
+static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt,
+ u32 count)
+{
+ starfive_wdt_set_count(wdt, count);
+
+ /* 7100 need set any value to reload register and could reload value to counter */
+ if (wdt->variant->reload)
+ writel(0x1, wdt->base + wdt->variant->reload);
+}
+
+static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ int ret;
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ /* disable watchdog, to be safe */
+ starfive_wdt_disable(wdt);
+
+ starfive_wdt_enable_reset(wdt);
+ ret = starfive_wdt_int_clr(wdt);
+ if (ret)
+ goto exit;
+
+ wdt->count = (timeout_ms / 1000) * wdt->freq;
+ if (wdt->variant->double_timeout)
+ wdt->count /= 2;
+
+ starfive_wdt_set_count(wdt, wdt->count);
+ starfive_wdt_enable(wdt);
+
+exit:
+ starfive_wdt_lock(wdt);
+ return ret;
+}
+
+static int starfive_wdt_stop(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ starfive_wdt_disable(wdt);
+ starfive_wdt_lock(wdt);
+
+ return 0;
+}
+
+static int starfive_wdt_reset(struct udevice *dev)
+{
+ int ret;
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ starfive_wdt_unlock(wdt);
+ ret = starfive_wdt_int_clr(wdt);
+ if (ret)
+ goto exit;
+
+ starfive_wdt_set_reload_count(wdt, wdt->count);
+
+exit:
+ starfive_wdt_lock(wdt);
+
+ return ret;
+}
+
+static const struct wdt_ops starfive_wdt_ops = {
+ .start = starfive_wdt_start,
+ .stop = starfive_wdt_stop,
+ .reset = starfive_wdt_reset,
+};
+
+static int starfive_wdt_probe(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+ int ret;
+
+ ret = starfive_wdt_enable_clock(wdt);
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(wdt->rst);
+ if (ret)
+ goto err_reset;
+
+ wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev);
+
+ wdt->freq = clk_get_rate(wdt->core_clk);
+ if (!wdt->freq) {
+ ret = -EINVAL;
+ goto err_get_freq;
+ }
+
+ return 0;
+
+err_get_freq:
+ reset_assert_bulk(wdt->rst);
+err_reset:
+ starfive_wdt_disable_clock(wdt);
+
+ return ret;
+}
+
+static int starfive_wdt_of_to_plat(struct udevice *dev)
+{
+ struct starfive_wdt_priv *wdt = dev_get_priv(dev);
+
+ wdt->base = (void *)dev_read_addr(dev);
+ if (!wdt->base)
+ return -ENODEV;
+
+ wdt->apb_clk = devm_clk_get(dev, "apb");
+ if (IS_ERR(wdt->apb_clk))
+ return -ENODEV;
+
+ wdt->core_clk = devm_clk_get(dev, "core");
+ if (IS_ERR(wdt->core_clk))
+ return -ENODEV;
+
+ wdt->rst = devm_reset_bulk_get(dev);
+ if (IS_ERR(wdt->rst))
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct udevice_id starfive_wdt_ids[] = {
+ {
+ .compatible = "starfive,jh7110-wdt",
+ .data = (ulong)&starfive_wdt_jh7110_variant
+ }, {
+ /* sentinel */
+ }
+};
+
+U_BOOT_DRIVER(starfive_wdt) = {
+ .name = "starfive_wdt",
+ .id = UCLASS_WDT,
+ .of_match = starfive_wdt_ids,
+ .priv_auto = sizeof(struct starfive_wdt_priv),
+ .probe = starfive_wdt_probe,
+ .of_to_plat = starfive_wdt_of_to_plat,
+ .ops = &starfive_wdt_ops,
+};
#include <wdt.h>
#include <asm/io.h>
#include <linux/delay.h>
-
-#define MSEC_PER_SEC 1000
+#include <linux/time.h>
#define WDT_MAX_TIMEOUT 16
#define WDT_TIMEOUT_MASK 0xf
memcpy(blk_dev->bounce_buffer, buffer, desc->blksz);
aiocb.aio_nbytes = unaligned ? desc->blksz :
- min((size_t)(BLKIF_MAX_SEGMENTS_PER_REQUEST * PAGE_SIZE),
+ min((size_t)((BLKIF_MAX_SEGMENTS_PER_REQUEST - 1)
+ * PAGE_SIZE),
(size_t)(blocks_todo * desc->blksz));
blkfront_io(&aiocb, write);
};
/*
- * This env_set() function is defined in cmd/nvedit.c, since it calls
- * _do_env_set(), whis is a static function in that file.
- *
- * int env_set(const char *varname, const char *varvalue);
+ * This variable is incremented each time we set an environment variable so we
+ * can be check via env_get_id() to see if the environment has changed or not.
+ * This makes it possible to reread an environment variable only if the
+ * environment was changed, typically used by networking code.
*/
+static int env_id = 1;
+
+int env_get_id(void)
+{
+ return env_id;
+}
+
+void env_inc_id(void)
+{
+ env_id++;
+}
+
+int env_do_env_set(int flag, int argc, char *const argv[], int env_flag)
+{
+ int i, len;
+ char *name, *value, *s;
+ struct env_entry e, *ep;
+
+ debug("Initial value for argc=%d\n", argc);
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI)
+ if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
+ return do_env_set_efi(NULL, flag, --argc, ++argv);
+#endif
+
+ while (argc > 1 && **(argv + 1) == '-') {
+ char *arg = *++argv;
+
+ --argc;
+ while (*++arg) {
+ switch (*arg) {
+ case 'f': /* force */
+ env_flag |= H_FORCE;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+ }
+ debug("Final value for argc=%d\n", argc);
+ name = argv[1];
+
+ if (strchr(name, '=')) {
+ printf("## Error: illegal character '='"
+ "in variable name \"%s\"\n", name);
+ return 1;
+ }
+
+ env_inc_id();
+
+ /* Delete only ? */
+ if (argc < 3 || argv[2] == NULL) {
+ int rc = hdelete_r(name, &env_htab, env_flag);
+
+ /* If the variable didn't exist, don't report an error */
+ return rc && rc != -ENOENT ? 1 : 0;
+ }
+
+ /*
+ * Insert / replace new value
+ */
+ for (i = 2, len = 0; i < argc; ++i)
+ len += strlen(argv[i]) + 1;
+
+ value = malloc(len);
+ if (value == NULL) {
+ printf("## Can't malloc %d bytes\n", len);
+ return 1;
+ }
+ for (i = 2, s = value; i < argc; ++i) {
+ char *v = argv[i];
+
+ while ((*s++ = *v++) != '\0')
+ ;
+ *(s - 1) = ' ';
+ }
+ if (s != value)
+ *--s = '\0';
+
+ e.key = name;
+ e.data = value;
+ hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag);
+ free(value);
+ if (!ep) {
+ printf("## Error inserting \"%s\" variable, errno=%d\n",
+ name, errno);
+ return 1;
+ }
+
+ return 0;
+}
+
+int env_set(const char *varname, const char *varvalue)
+{
+ const char * const argv[4] = { "setenv", varname, varvalue, NULL };
+
+ /* before import into hashtable */
+ if (!(gd->flags & GD_FLG_ENV_READY))
+ return 1;
+
+ if (varvalue == NULL || varvalue[0] == '\0')
+ return env_do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC);
+ else
+ return env_do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
+}
/**
* Set an environment variable to an integer value
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
*/
+#ifdef USE_HOSTCC
#include <linux/kconfig.h>
+#endif
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
- if (!ext4fs_mount(info.size)) {
+ if (!ext4fs_mount()) {
printf("\n** Unable to use %s %s for saveenv **\n",
ifname, dev_and_part);
return 1;
dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
- if (!ext4fs_mount(info.size)) {
+ if (!ext4fs_mount()) {
printf("\n** Unable to use %s %s for loading the env **\n",
ifname, dev_and_part);
goto err_env_relocate;
.location = ENVL_MMC,
ENV_NAME("MMC")
.load = env_mmc_load,
-#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_SPL_BUILD)
.save = env_save_ptr(env_mmc_save),
.erase = ENV_ERASE_PTR(env_mmc_erase)
#endif
{
struct btrfs_fs_info *fs_info = current_fs_info;
struct btrfs_root *root;
- loff_t real_size = 0;
+ loff_t real_size;
u64 ino;
u8 type;
int ret;
return -EINVAL;
}
- if (!len) {
- ret = btrfs_size(file, &real_size);
- if (ret < 0) {
- error("Failed to get inode size: %s", file);
- return ret;
- }
- len = real_size;
+ ret = btrfs_size(file, &real_size);
+ if (ret < 0) {
+ error("Failed to get inode size: %s", file);
+ return ret;
}
- if (len > real_size - offset)
+ if (!len || len > real_size - offset)
len = real_size - offset;
ret = btrfs_file_read(root, ino, offset, len, buf);
#ifndef __BTRFS_CTREE_H__
#define __BTRFS_CTREE_H__
-#include <common.h>
#include <compiler.h>
#include <linux/rbtree.h>
#include <linux/bug.h>
return -1;
}
-int ext4fs_mount(unsigned part_length)
+int ext4fs_mount(void)
{
struct ext2_data *data;
int status;
{
ext4fs_set_blk_dev(fs_dev_desc, fs_partition);
- if (!ext4fs_mount(fs_partition->size)) {
+ if (!ext4fs_mount()) {
ext4fs_close();
return -1;
}
#include <fs.h>
#include <log.h>
#include <asm/byteorder.h>
+#include <asm/unaligned.h>
#include <part.h>
#include <malloc.h>
#include <memalign.h>
#include <asm/cache.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
+#include <linux/log2.h>
+
+/* maximum number of clusters for FAT12 */
+#define MAX_FAT12 0xFF4
/*
* Convert a string to lowercase. Converts at most 'len' characters,
return ret;
}
+/*
+ * Determine if the FAT type is FAT12 or FAT16
+ *
+ * Based on fat_fill_super() from the Linux kernel's fs/fat/inode.c
+ */
+static int determine_legacy_fat_bits(const boot_sector *bs)
+{
+ u16 fat_start = bs->reserved;
+ u32 dir_start = fat_start + bs->fats * bs->fat_length;
+ u32 rootdir_sectors = get_unaligned_le16(bs->dir_entries) *
+ sizeof(dir_entry) /
+ get_unaligned_le16(bs->sector_size);
+ u32 data_start = dir_start + rootdir_sectors;
+ u16 sectors = get_unaligned_le16(bs->sectors);
+ u32 total_sectors = sectors ? sectors : bs->total_sect;
+ u32 total_clusters = (total_sectors - data_start) /
+ bs->cluster_size;
+
+ return (total_clusters > MAX_FAT12) ? 16 : 12;
+}
+
+/*
+ * Determines if the boot sector's media field is valid
+ *
+ * Based on fat_valid_media() from Linux kernel's include/linux/msdos_fs.h
+ */
+static int fat_valid_media(u8 media)
+{
+ return media >= 0xf8 || media == 0xf0;
+}
+
+/*
+ * Determines if the given boot sector is valid
+ *
+ * Based on fat_read_bpb() from the Linux kernel's fs/fat/inode.c
+ */
+static int is_bootsector_valid(const boot_sector *bs)
+{
+ u16 sector_size = get_unaligned_le16(bs->sector_size);
+ u16 dir_per_block = sector_size / sizeof(dir_entry);
+
+ if (!bs->reserved)
+ return 0;
+
+ if (!bs->fats)
+ return 0;
+
+ if (!fat_valid_media(bs->media))
+ return 0;
+
+ if (!is_power_of_2(sector_size) ||
+ sector_size < 512 ||
+ sector_size > 4096)
+ return 0;
+
+ if (!is_power_of_2(bs->cluster_size))
+ return 0;
+
+ if (!bs->fat_length && !bs->fat32_length)
+ return 0;
+
+ if (get_unaligned_le16(bs->dir_entries) & (dir_per_block - 1))
+ return 0;
+
+ return 1;
+}
+
/*
* Read boot sector and volume info from a FAT filesystem
*/
if (disk_read(0, 1, block) < 0) {
debug("Error: reading block\n");
- goto fail;
+ ret = -1;
+ goto out_free;
}
memcpy(bs, block, sizeof(boot_sector));
bs->heads = FAT2CPU16(bs->heads);
bs->total_sect = FAT2CPU32(bs->total_sect);
+ if (!is_bootsector_valid(bs)) {
+ debug("Error: bootsector is invalid\n");
+ ret = -1;
+ goto out_free;
+ }
+
/* FAT32 entries */
- if (bs->fat_length == 0) {
+ if (!bs->fat_length && bs->fat32_length) {
/* Assume FAT32 */
bs->fat32_length = FAT2CPU32(bs->fat32_length);
bs->flags = FAT2CPU16(bs->flags);
*fatsize = 32;
} else {
vistart = (volume_info *)&(bs->fat32_length);
- *fatsize = 0;
+ *fatsize = determine_legacy_fat_bits(bs);
}
memcpy(volinfo, vistart, sizeof(volume_info));
- if (*fatsize == 32) {
- if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0)
- goto exit;
- } else {
- if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) {
- *fatsize = 12;
- goto exit;
- }
- if (strncmp(FAT16_SIGN, vistart->fs_type, SIGNLEN) == 0) {
- *fatsize = 16;
- goto exit;
- }
- }
-
- debug("Error: broken fs_type sign\n");
-fail:
- ret = -1;
-exit:
+out_free:
free(block);
return ret;
}
mydata->total_sect = bs.total_sect;
} else {
mydata->fatlength = bs.fat_length;
- mydata->total_sect = (bs.sectors[1] << 8) + bs.sectors[0];
+ mydata->total_sect = get_unaligned_le16(bs.sectors);
if (!mydata->total_sect)
mydata->total_sect = bs.total_sect;
}
mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats;
- mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
+ mydata->sect_size = get_unaligned_le16(bs.sector_size);
mydata->clust_size = bs.cluster_size;
if (mydata->sect_size != cur_part_info.blksz) {
log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n",
(mydata->clust_size * 2);
mydata->root_cluster = bs.root_cluster;
} else {
- mydata->rootdir_size = ((bs.dir_entries[1] * (int)256 +
- bs.dir_entries[0]) *
+ mydata->rootdir_size = (get_unaligned_le16(bs.dir_entries) *
sizeof(dir_entry)) /
mydata->sect_size;
mydata->data_begin = mydata->rootdir_sect +
memcpy(vol_label, volinfo.volume_label, 11);
vol_label[11] = '\0';
- volinfo.fs_type[5] = '\0';
- printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label);
+ printf("Filesystem: FAT%d \"%s\"\n", fatsize, vol_label);
return 0;
}
.ln = fs_ln_unsupported,
},
#endif
-#ifdef CONFIG_SEMIHOSTING
+#if CONFIG_IS_ENABLED(SEMIHOSTING)
{
.fstype = FS_TYPE_SEMIHOSTING,
.name = "semihosting",
if (argc > 7)
return CMD_RET_USAGE;
- if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) {
+ if (fs_set_blk_dev(argv[1], cmd_arg2(argc, argv), fstype)) {
log_err("Can't set block device\n");
return 1;
}
if (argc > 4)
return CMD_RET_USAGE;
- if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype))
+ if (fs_set_blk_dev(argv[1], cmd_arg2(argc, argv), fstype))
return 1;
if (fs_ls(argc >= 4 ? argv[3] : "/"))
#include <u-boot/zlib.h>
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+#include <u-boot/lz4.h>
+#endif
+
#if IS_ENABLED(CONFIG_ZSTD)
#include <linux/zstd.h>
#endif
case SQFS_COMP_ZLIB:
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
ctxt->zstd_workspace = malloc(zstd_dctx_workspace_bound());
case SQFS_COMP_ZLIB:
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
free(ctxt->zstd_workspace);
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ ret = LZ4_decompress_safe(source, dest, src_len, *dest_len);
+ if (ret < 0) {
+ printf("LZ4 decompression failed.\n");
+ return -EINVAL;
+ }
+
+ ret = 0;
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
ret = sqfs_zstd_decompress(ctxt, dest, *dest_len, source, src_len);
#define SQFS_COMP_LZ4 5
#define SQFS_COMP_ZSTD 6
-/* LZMA does not support any compression options */
-
-struct squashfs_gzip_opts {
- u32 compression_level;
- u16 window_size;
- u16 strategies;
-};
-
-struct squashfs_xz_opts {
- u32 dictionary_size;
- u32 executable_filters;
-};
-
-struct squashfs_lz4_opts {
- u32 version;
- u32 flags;
-};
-
-struct squashfs_zstd_opts {
- u32 compression_level;
-};
-
-struct squashfs_lzo_opts {
- u32 algorithm;
- u32 level;
-};
-
-union squashfs_compression_opts {
- struct squashfs_gzip_opts *gzip;
- struct squashfs_xz_opts *xz;
- struct squashfs_lz4_opts *lz4;
- struct squashfs_zstd_opts *zstd;
- struct squashfs_lzo_opts *lzo;
-};
-
int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest,
unsigned long *dest_len, void *source, u32 src_len);
int sqfs_decompressor_init(struct squashfs_ctxt *ctxt);
#include <part.h>
#include <stdint.h>
-#define SQFS_UNCOMPRESSED_DATA 0x0002
#define SQFS_MAGIC_NUMBER 0x73717368
/* The three first members of squashfs_dir_index make a total of 12 bytes */
#define SQFS_DIR_INDEX_BASE_LENGTH 12
#define SQFS_MAX_ENTRIES 512
/* Metadata blocks start by a 2-byte length header */
#define SQFS_HEADER_SIZE 2
-#define SQFS_LREG_INODE_MIN_SIZE 56
#define SQFS_DIR_HEADER_SIZE 12
#define SQFS_MISC_ENTRY_TYPE -1
#define SQFS_EMPTY_FILE_SIZE 3
#define SQFS_FRAGMENT_INDEX_OFFSET(A) ((A) % SQFS_MAX_ENTRIES)
#define SQFS_FRAGMENT_INDEX(A) ((A) / SQFS_MAX_ENTRIES)
#define SQFS_BLOCK_SIZE(A) ((A) & GENMASK(23, 0))
-#define SQFS_CHECK_FLAG(flag, bit) (((flag) >> (bit)) & 1)
/* Useful for both fragment and data blocks */
#define SQFS_COMPRESSED_BLOCK(A) (!((A) & BIT(24)))
-/* SQFS_COMPRESSED_DATA strictly used with super block's 'flags' member */
-#define SQFS_COMPRESSED_DATA(A) (!((A) & 0x0002))
#define SQFS_IS_FRAGMENTED(A) ((A) != 0xFFFFFFFF)
/*
* These two macros work as getters for a metada block header, retrieving the
#define SQFS_COMPRESSED_METADATA(A) (!((A) & BIT(15)))
#define SQFS_METADATA_SIZE(A) ((A) & GENMASK(14, 0))
-struct squashfs_super_block_flags {
- /* check: unused
- * uncompressed_ids: not supported
- */
- bool uncompressed_inodes;
- bool uncompressed_data;
- bool check;
- bool uncompressed_frags;
- bool no_frags;
- bool always_frags;
- bool duplicates;
- bool exportable;
- bool uncompressed_xattrs;
- bool no_xattrs;
- bool compressor_options;
- bool uncompressed_ids;
-};
-
#endif /* SQFS_UTILS_H */
void iput(struct inode *inode);
/* linux/include/time.h */
-#define NSEC_PER_SEC 1000000000L
#define get_seconds() 0
#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 })
#ifndef __YDIRECTENV_H__
#define __YDIRECTENV_H__
-#include <common.h>
#include <malloc.h>
#include <linux/compat.h>
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#ifndef _MCD_API_H
-#define _MCD_API_H
-
-/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
-#undef MCD_INCLUDE_EU
-
-/* Number of DMA channels */
-#define NCHANNELS 16
-
-/* Total number of variants */
-#ifdef MCD_INCLUDE_EU
-#define NUMOFVARIANTS 6
-#else
-#define NUMOFVARIANTS 4
-#endif
-
-/* Define sizes of the various tables */
-#define TASK_TABLE_SIZE (NCHANNELS*32)
-#define VAR_TAB_SIZE (128)
-#define CONTEXT_SAVE_SIZE (128)
-#define FUNCDESC_TAB_SIZE (256)
-
-#ifdef MCD_INCLUDE_EU
-#define FUNCDESC_TAB_NUM 16
-#else
-#define FUNCDESC_TAB_NUM 1
-#endif
-
-#ifndef DEFINESONLY
-
-/* Portability typedefs */
-#if 1
-#include "common.h"
-#else
-#ifndef s32
-typedef int s32;
-#endif
-#ifndef u32
-typedef unsigned int u32;
-#endif
-#ifndef s16
-typedef short s16;
-#endif
-#ifndef u16
-typedef unsigned short u16;
-#endif
-#ifndef s8
-typedef char s8;
-#endif
-#ifndef u8
-typedef unsigned char u8;
-#endif
-#endif
-
-/*
- * These structures represent the internal registers of the
- * multi-channel DMA
- */
-struct dmaRegs_s {
- u32 taskbar; /* task table base address */
- u32 currPtr;
- u32 endPtr;
- u32 varTablePtr;
- u16 dma_rsvd0;
- u16 ptdControl; /* ptd control */
- u32 intPending; /* interrupt pending */
- u32 intMask; /* interrupt mask */
- u16 taskControl[16]; /* task control */
- u8 priority[32]; /* priority */
- u32 initiatorMux; /* initiator mux control */
- u32 taskSize0; /* task size control 0. */
- u32 taskSize1; /* task size control 1. */
- u32 dma_rsvd1; /* reserved */
- u32 dma_rsvd2; /* reserved */
- u32 debugComp1; /* debug comparator 1 */
- u32 debugComp2; /* debug comparator 2 */
- u32 debugControl; /* debug control */
- u32 debugStatus; /* debug status */
- u32 ptdDebug; /* priority task decode debug */
- u32 dma_rsvd3[31]; /* reserved */
-};
-typedef volatile struct dmaRegs_s dmaRegs;
-
-#endif
-
-/* PTD contrl reg bits */
-#define PTD_CTL_TSK_PRI 0x8000
-#define PTD_CTL_COMM_PREFETCH 0x0001
-
-/* Task Control reg bits and field masks */
-#define TASK_CTL_EN 0x8000
-#define TASK_CTL_VALID 0x4000
-#define TASK_CTL_ALWAYS 0x2000
-#define TASK_CTL_INIT_MASK 0x1f00
-#define TASK_CTL_ASTRT 0x0080
-#define TASK_CTL_HIPRITSKEN 0x0040
-#define TASK_CTL_HLDINITNUM 0x0020
-#define TASK_CTL_ASTSKNUM_MASK 0x000f
-
-/* Priority reg bits and field masks */
-#define PRIORITY_HLD 0x80
-#define PRIORITY_PRI_MASK 0x07
-
-/* Debug Control reg bits and field masks */
-#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
-#define DBG_CTL_AUTO_ARM 0x00008000
-#define DBG_CTL_BREAK 0x00004000
-#define DBG_CTL_COMP1_TYP_MASK 0x00003800
-#define DBG_CTL_COMP2_TYP_MASK 0x00000070
-#define DBG_CTL_EXT_BREAK 0x00000004
-#define DBG_CTL_INT_BREAK 0x00000002
-
-/*
- * PTD Debug reg selector addresses
- * This reg must be written with a value to show the contents of
- * one of the desired internal register.
- */
-#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
-#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
- have initiators asserted */
-
-/* General return values */
-#define MCD_OK 0
-#define MCD_ERROR -1
-#define MCD_TABLE_UNALIGNED -2
-#define MCD_CHANNEL_INVALID -3
-
-/* MCD_initDma input flags */
-#define MCD_RELOC_TASKS 0x00000001
-#define MCD_NO_RELOC_TASKS 0x00000000
-#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
-
-/*
- * MCD_dmaStatus Status Values for each channel:
- * MCD_NO_DMA - No DMA has been requested since reset
- * MCD_IDLE - DMA active, but the initiator is currently inactive
- * MCD_RUNNING - DMA active, and the initiator is currently active
- * MCD_PAUSED - DMA active but it is currently paused
- * MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
- * MCD_DONE - the most recent DMA has completed
- */
-#define MCD_NO_DMA 1
-#define MCD_IDLE 2
-#define MCD_RUNNING 3
-#define MCD_PAUSED 4
-#define MCD_HALTED 5
-#define MCD_DONE 6
-
-/* MCD_startDma parameter defines */
-
-/* Constants for the funcDesc parameter */
-/*
- * MCD_NO_BYTE_SWAP - to disable byte swapping
- * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
- * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
- * value being DMAed
- * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
- * each 32-bit data value DMAed
- * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
- * MCD_BIT_REV - reverse the bits of each byte DMAed
- * MCD_CRC16 - to perform CRC-16 on DMAed data
- * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
- * MCD_CRC32 - to perform CRC-32 on DMAed data
- * MCD_CSUMINET - to perform internet checksums on DMAed data
- * MCD_NO_CSUM - to perform no checksumming
- */
-#define MCD_NO_BYTE_SWAP 0x00045670
-#define MCD_BYTE_REVERSE 0x00076540
-#define MCD_U16_REVERSE 0x00067450
-#define MCD_U16_BYTE_REVERSE 0x00054760
-#define MCD_NO_BIT_REV 0x00000000
-#define MCD_BIT_REV 0x00088880
-/* CRCing: */
-#define MCD_CRC16 0xc0100000
-#define MCD_CRCCCITT 0xc0200000
-#define MCD_CRC32 0xc0300000
-#define MCD_CSUMINET 0xc0400000
-#define MCD_NO_CSUM 0xa0000000
-
-#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
- MCD_NO_CSUM)
-#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
-
-/* Constants for the flags parameter */
-#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
-#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
-#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
-#define MCD_TT_FLAGS_MASK 0x000000ff
-#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
-
-#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
-#define MCD_CHAIN_DMA /* TBD */
-#define MCD_EU_DMA /* TBD */
-#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
-#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
-
-/* these flags are valid for MCD_startDma and the chained buffer descriptors */
-/*
- * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
- * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
- * MCD_INTERRUPT - to generate an interrupt after completion of the DMA
- * MCD_END_FRAME - tell the DMA to end the frame when transferring
- * last byte of data in buffer
- * MCD_CRC_RESTART - to empty out the accumulated checksum prior to
- * performing the DMA
- */
-#define MCD_BUF_READY 0x80000000
-#define MCD_WRAP 0x20000000
-#define MCD_INTERRUPT 0x10000000
-#define MCD_END_FRAME 0x08000000
-#define MCD_CRC_RESTART 0x40000000
-
-/* Defines for the FEC buffer descriptor control/status word*/
-#define MCD_FEC_BUF_READY 0x8000
-#define MCD_FEC_WRAP 0x2000
-#define MCD_FEC_INTERRUPT 0x1000
-#define MCD_FEC_END_FRAME 0x0800
-
-/* Defines for general intuitiveness */
-
-#define MCD_TRUE 1
-#define MCD_FALSE 0
-
-/* Three different cases for destination and source. */
-#define MINUS1 -1
-#define ZERO 0
-#define PLUS1 1
-
-#ifndef DEFINESONLY
-
-/* Task Table Entry struct*/
-typedef struct {
- u32 TDTstart; /* task descriptor table start */
- u32 TDTend; /* task descriptor table end */
- u32 varTab; /* variable table start */
- u32 FDTandFlags; /* function descriptor table start & flags */
- volatile u32 descAddrAndStatus;
- volatile u32 modifiedVarTab;
- u32 contextSaveSpace; /* context save space start */
- u32 literalBases;
-} TaskTableEntry;
-
-/* Chained buffer descriptor:
- * flags - flags describing the DMA
- * csumResult - checksum performed since last checksum reset
- * srcAddr - the address to move data from
- * destAddr - the address to move data to
- * lastDestAddr - the last address written to
- * dmaSize - the no of bytes to xfer independent of the xfer sz
- * next - next buffer descriptor in chain
- * info - private info about this descriptor; DMA does not affect it
- */
-typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
-struct MCD_bufDesc_struct {
- u32 flags;
- u32 csumResult;
- s8 *srcAddr;
- s8 *destAddr;
- s8 *lastDestAddr;
- u32 dmaSize;
- MCD_bufDesc *next;
- u32 info;
-};
-
-/* Progress Query struct:
- * lastSrcAddr - the most-recent or last, post-increment source address
- * lastDestAddr - the most-recent or last, post-increment destination address
- * dmaSize - the amount of data transferred for the current buffer
- * currBufDesc - pointer to the current buffer descriptor being DMAed
- */
-
-typedef volatile struct MCD_XferProg_struct {
- s8 *lastSrcAddr;
- s8 *lastDestAddr;
- u32 dmaSize;
- MCD_bufDesc *currBufDesc;
-} MCD_XferProg;
-
-/* FEC buffer descriptor */
-typedef volatile struct MCD_bufDescFec_struct {
- u16 statCtrl;
- u16 length;
- u32 dataPointer;
-} MCD_bufDescFec;
-
-/*************************************************************************/
-/* API function Prototypes - see MCD_dmaApi.c for further notes */
-
-/* MCD_startDma starts a particular kind of DMA:
- * srcAddr - the channel on which to run the DMA
- * srcIncr - the address to move data from, or buffer-descriptor address
- * destAddr - the amount to increment the source address per transfer
- * destIncr - the address to move data to
- * dmaSize - the amount to increment the destination address per transfer
- * xferSize - the number bytes in of each data movement (1, 2, or 4)
- * initiator - what device initiates the DMA
- * priority - priority of the DMA
- * flags - flags describing the DMA
- * funcDesc - description of byte swapping, bit swapping, and CRC actions
- */
-int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
- s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
- int priority, u32 flags, u32 funcDesc);
-
-/*
- * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
- * registers, relocating and creating the appropriate task structures, and
- * setting up some global settings
- */
-int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
-
-/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
-int MCD_dmaStatus(int channel);
-
-/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
-int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
-
-/*
- * MCD_killDma() halts the DMA on the requested channel, without any
- * intention of resuming the DMA.
- */
-int MCD_killDma(int channel);
-
-/*
- * MCD_continDma() continues a DMA which as stopped due to encountering an
- * unready buffer descriptor.
- */
-int MCD_continDma(int channel);
-
-/*
- * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
- * running on that channel).
- */
-int MCD_pauseDma(int channel);
-
-/*
- * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
- * running on that channel).
- */
-int MCD_resumeDma(int channel);
-
-/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
-int MCD_csumQuery(int channel, u32 * csum);
-
-/*
- * MCD_getCodeSize provides the packed size required by the microcoded task
- * and structures.
- */
-int MCD_getCodeSize(void);
-
-/*
- * MCD_getVersion provides a pointer to a version string and returns a
- * version number.
- */
-int MCD_getVersion(char **longVersion);
-
-/* macro for setting a location in the variable table */
-#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
-/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
- so I'm avoiding surrounding it with "do {} while(0)" */
-
-#endif /* DEFINESONLY */
-
-#endif /* _MCD_API_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
- /* This file is autogenerated. Do not change */
-#define CURRBD 4
-#define DCOUNT 6
-#define DESTPTR 5
-#define SRCPTR 7
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#ifndef MCD_TSK_INIT_H
-#define MCD_TSK_INIT_H 1
-
-/*
- * Do not edit!
- */
-
-/* Task 0 */
-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 1 */
-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 2 */
-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 3 */
-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 4 */
-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 5 */
-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
- volatile TaskTableEntry * taskTable, int channel);
-
-#endif /* MCD_TSK_INIT_H */
};
/* XSDT (Extended System Description Table) */
-struct acpi_xsdt {
+struct __packed acpi_xsdt {
struct acpi_table_header header;
u64 entry[MAX_ACPI_TABLES];
};
u8 reset_value;
u16 arm_boot_arch;
u8 minor_revision;
- u32 x_firmware_ctl_l;
- u32 x_firmware_ctl_h;
- u32 x_dsdt_l;
- u32 x_dsdt_h;
+ u64 x_firmware_ctrl;
+ u64 x_dsdt;
struct acpi_gen_regaddr x_pm1a_evt_blk;
struct acpi_gen_regaddr x_pm1b_evt_blk;
struct acpi_gen_regaddr x_pm1a_cnt_blk;
*/
int acpi_fill_csrt(struct acpi_ctx *ctx);
+/**
+ * acpi_get_rsdp_addr() - get ACPI RSDP table address
+ *
+ * This routine returns the ACPI RSDP table address in the system memory.
+ *
+ * @return: ACPI RSDP table address
+ */
+ulong acpi_get_rsdp_addr(void);
+
/**
* write_acpi_tables() - Write out the ACPI tables
*
*/
int sata_scan(struct udevice *dev);
-int ahci_init(void __iomem *base);
-int ahci_reset(void __iomem *base);
-
/**
* ahci_init_one_dm() - set up a single AHCI port
*
#endif
#ifdef CONFIG_SMBIOS
-#define gd_smbios_start() gd->smbios_start
+#define gd_smbios_start() gd->arch.smbios_start
#define gd_set_smbios_start(addr) gd->arch.smbios_start = addr
#else
#define gd_smbios_start() 0UL
* @GD_FLG_BLOBLIST_READY: bloblist is ready for use
*/
GD_FLG_BLOBLIST_READY = 0x800000,
+ /**
+ * @GD_FLG_HUSH_OLD_PARSER: Use hush old parser.
+ */
+ GD_FLG_HUSH_OLD_PARSER = 0x1000000,
+ /**
+ * @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser.
+ */
+ GD_FLG_HUSH_MODERN_PARSER = 0x2000000,
};
#endif /* __ASSEMBLY__ */
}
#endif
+/*
+ * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
+ *
+ * On some architectures memory mapped IO needs to be accessed differently.
+ * On the simple architectures, we just read/write the memory location
+ * directly.
+ */
+
+#ifndef __raw_readb
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ return *(const volatile u8 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readw
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ return *(const volatile u16 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readl
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ return *(const volatile u32 __force *)addr;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_readq
+#define __raw_readq __raw_readq
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+ return *(const volatile u64 __force *)addr;
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef __raw_writeb
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
+{
+ *(volatile u8 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writew
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 value, volatile void __iomem *addr)
+{
+ *(volatile u16 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writel
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 value, volatile void __iomem *addr)
+{
+ *(volatile u32 __force *)addr = value;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_writeq
+#define __raw_writeq __raw_writeq
+static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
+{
+ *(volatile u64 __force *)addr = value;
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+/*
+ * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
+ * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
+ */
+#ifndef readsb
+#define readsb readsb
+static inline void readsb(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u8 *buf = buffer;
+
+ do {
+ u8 x = __raw_readb(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef readsw
+#define readsw readsw
+static inline void readsw(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u16 *buf = buffer;
+
+ do {
+ u16 x = __raw_readw(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef readsl
+#define readsl readsl
+static inline void readsl(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u32 *buf = buffer;
+
+ do {
+ u32 x = __raw_readl(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef readsq
+#define readsq readsq
+static inline void readsq(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u64 *buf = buffer;
+
+ do {
+ u64 x = __raw_readq(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef writesb
+#define writesb writesb
+static inline void writesb(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u8 *buf = buffer;
+
+ do {
+ __raw_writeb(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef writesw
+#define writesw writesw
+static inline void writesw(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u16 *buf = buffer;
+
+ do {
+ __raw_writew(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef writesl
+#define writesl writesl
+static inline void writesl(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u32 *buf = buffer;
+
+ do {
+ __raw_writel(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef writesq
+#define writesq writesq
+static inline void writesq(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u64 *buf = buffer;
+
+ do {
+ __raw_writeq(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef PCI_IOBASE
+#define PCI_IOBASE ((void __iomem *)0)
+#endif
+
+/*
+ * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
+ * single I/O port multiple times.
+ */
+
+#ifndef insb
+#define insb insb
+static inline void insb(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insw
+#define insw insw
+static inline void insw(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insl
+#define insl insl
+static inline void insl(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsb
+#define outsb outsb
+static inline void outsb(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsw
+#define outsw outsw
+static inline void outsw(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsl
+#define outsl outsl
+static inline void outsl(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef ioread8_rep
+#define ioread8_rep ioread8_rep
+static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ readsb(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread16_rep
+#define ioread16_rep ioread16_rep
+static inline void ioread16_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsw(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread32_rep
+#define ioread32_rep ioread32_rep
+static inline void ioread32_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsl(addr, buffer, count);
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef ioread64_rep
+#define ioread64_rep ioread64_rep
+static inline void ioread64_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsq(addr, buffer, count);
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef iowrite8_rep
+#define iowrite8_rep iowrite8_rep
+static inline void iowrite8_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesb(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite16_rep
+#define iowrite16_rep iowrite16_rep
+static inline void iowrite16_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesw(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite32_rep
+#define iowrite32_rep iowrite32_rep
+static inline void iowrite32_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesl(addr, buffer, count);
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef iowrite64_rep
+#define iowrite64_rep iowrite64_rep
+static inline void iowrite64_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesq(addr, buffer, count);
+}
+#endif
+#endif /* CONFIG_64BIT */
+
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_GENERIC_IO_H__ */
#ifndef _ATMEL_LCD_H_
#define _ATMEL_LCD_H_
+#include <linux/types.h>
+
/**
* struct atmel_lcd_plat - platform data for Atmel LCDs with driver model
*
#ifndef __BCB_H__
#define __BCB_H__
+#include <part.h>
+
+enum bcb_field {
+ BCB_FIELD_COMMAND,
+ BCB_FIELD_STATUS,
+ BCB_FIELD_RECOVERY,
+ BCB_FIELD_STAGE
+};
+
#if IS_ENABLED(CONFIG_CMD_BCB)
-int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp);
+
+int bcb_find_partition_and_load(const char *iface,
+ int devnum, char *partp);
+int bcb_load(struct blk_desc *block_description,
+ struct disk_partition *disk_partition);
+int bcb_set(enum bcb_field field, const char *value);
+
+/**
+ * bcb_get() - get the field value.
+ * @field: field to get
+ * @value_out: buffer to copy bcb field value to
+ * @value_size: buffer size to avoid overflow in case
+ * value_out is smaller then the field value
+ */
+int bcb_get(enum bcb_field field, char *value_out, size_t value_size);
+
+int bcb_store(void);
+void bcb_reset(void);
+
#else
+
#include <linux/errno.h>
-static inline int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp)
+
+static inline int bcb_load(struct blk_desc *block_description,
+ struct disk_partition *disk_partition)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_find_partition_and_load(const char *iface,
+ int devnum, char *partp)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_set(enum bcb_field field, const char *value)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_get(enum bcb_field field, char *value_out)
{
return -EOPNOTSUPP;
}
+
+static inline int bcb_store(void)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void bcb_reset(void)
+{
+}
#endif
#endif /* __BCB_H__ */
#ifndef _BLKMAP_H
#define _BLKMAP_H
+#include <dm/lists.h>
+
+/**
+ * struct blkmap - Block map
+ *
+ * Data associated with a blkmap.
+ *
+ * @label: Human readable name of this blkmap
+ * @blk: Underlying block device
+ * @slices: List of slices associated with this blkmap
+ */
+struct blkmap {
+ char *label;
+ struct udevice *blk;
+ struct list_head slices;
+};
+
/**
* blkmap_map_linear() - Map region of other block device
*
*/
int blkmap_destroy(struct udevice *dev);
+/**
+ * blkmap_create_ramdisk() - Create new ramdisk with blkmap
+ *
+ * @label: Label of the new blkmap
+ * @image_addr: Target memory start address of this mapping
+ * @image_size: Target memory size of this mapping
+ * @devp: Updated with the address of the created blkmap device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
+ struct udevice **devp);
+
#endif /* _BLKMAP_H */
* which would add to code size. For Thumb-2 the code size needed in SPL is
* approximately 940 bytes (e.g. for chromebook_bob).
*
- * 5. Bloblist uses 16-byte alignment internally and is designed to start on a
- * 16-byte boundary. Its headers are multiples of 16 bytes. This makes it easier
- * to deal with data structures which need this level of alignment, such as ACPI
- * tables. For use in SPL and TPL the alignment can be relaxed, since it can be
- * relocated to an aligned address in U-Boot proper.
+ * 5. Bloblist uses 8-byte alignment internally and is designed to start on a
+ * 8-byte boundary. Its headers are 8 bytes long. It is possible to achieve
+ * larger alignment (e.g. 16 bytes) by adding a dummy header, For use in SPL and
+ * TPL the alignment can be relaxed, since it can be relocated to an aligned
+ * address in U-Boot proper.
*
* 6. Bloblist is designed to be passed to Linux as reserved memory. While linux
* doesn't understand the bloblist header, it can be passed the indivdual blobs.
*
* Copyright 2018 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
+ * Adjusted July 2023 to match Firmware handoff specification, Release 0.9
*/
#ifndef __BLOBLIST_H
#include <mapmem.h>
enum {
- BLOBLIST_VERSION = 0,
- BLOBLIST_MAGIC = 0xb00757a3,
- BLOBLIST_ALIGN = 16,
+ BLOBLIST_VERSION = 1,
+ BLOBLIST_MAGIC = 0x4a0fb10b,
+
+ BLOBLIST_BLOB_ALIGN_LOG2 = 3,
+ BLOBLIST_BLOB_ALIGN = 1 << BLOBLIST_BLOB_ALIGN_LOG2,
+
+ BLOBLIST_ALIGN_LOG2 = 3,
+ BLOBLIST_ALIGN = 1 << BLOBLIST_ALIGN_LOG2,
};
/* Supported tags - add new ones to tag_name in bloblist.c */
enum bloblist_tag_t {
- BLOBLISTT_NONE = 0,
+ BLOBLISTT_VOID = 0,
/*
* Standard area to allocate blobs used across firmware components, for
* projects.
*/
BLOBLISTT_AREA_FIRMWARE_TOP = 0x1,
+ /*
+ * Devicetree for use by firmware. On some platforms this is passed to
+ * the OS also
+ */
+ BLOBLISTT_CONTROL_FDT = 1,
+ BLOBLISTT_HOB_BLOCK = 2,
+ BLOBLISTT_HOB_LIST = 3,
+ BLOBLISTT_ACPI_TABLES = 4,
+ BLOBLISTT_TPM_EVLOG = 5,
+ BLOBLISTT_TPM_CRB_BASE = 6,
/* Standard area to allocate blobs used across firmware components */
- BLOBLISTT_AREA_FIRMWARE = 0x100,
+ BLOBLISTT_AREA_FIRMWARE = 0x10,
+ BLOBLISTT_TPM2_TCG_LOG = 0x10, /* TPM v2 log space */
+ BLOBLISTT_TCPA_LOG = 0x11, /* TPM log space */
/*
* Advanced Configuration and Power Interface Global Non-Volatile
* Sleeping table. This forms part of the ACPI tables passed to Linux.
*/
- BLOBLISTT_ACPI_GNVS = 0x100,
- BLOBLISTT_INTEL_VBT = 0x101, /* Intel Video-BIOS table */
- BLOBLISTT_TPM2_TCG_LOG = 0x102, /* TPM v2 log space */
- BLOBLISTT_TCPA_LOG = 0x103, /* TPM log space */
- BLOBLISTT_ACPI_TABLES = 0x104, /* ACPI tables for x86 */
- BLOBLISTT_SMBIOS_TABLES = 0x105, /* SMBIOS tables for x86 */
- BLOBLISTT_VBOOT_CTX = 0x106, /* Chromium OS verified boot context */
-
- /*
- * Project-specific tags are permitted here. Projects can be open source
- * or not, but the format of the data must be fuily documented in an
- * open source project, including all fields, bits, etc. Naming should
- * be: BLOBLISTT_<project>_<purpose_here>
- */
- BLOBLISTT_PROJECT_AREA = 0x8000,
- BLOBLISTT_U_BOOT_SPL_HANDOFF = 0x8000, /* Hand-off info from SPL */
- BLOBLISTT_VBE = 0x8001, /* VBE per-phase state */
- BLOBLISTT_U_BOOT_VIDEO = 0x8002, /* Video information from SPL */
+ BLOBLISTT_ACPI_GNVS = 0x12,
- /*
- * Vendor-specific tags are permitted here. Projects can be open source
- * or not, but the format of the data must be fuily documented in an
- * open source project, including all fields, bits, etc. Naming should
- * be BLOBLISTT_<vendor>_<purpose_here>
- */
- BLOBLISTT_VENDOR_AREA = 0xc000,
+ /* Standard area to allocate blobs used for Trusted Firmware */
+ BLOBLISTT_AREA_TF = 0x100,
+ BLOBLISTT_OPTEE_PAGABLE_PART = 0x100,
- /* Tags after this are not allocated for now */
- BLOBLISTT_EXPANSION = 0x10000,
+ /* Other standard area to allocate blobs */
+ BLOBLISTT_AREA_OTHER = 0x200,
+ BLOBLISTT_INTEL_VBT = 0x200, /* Intel Video-BIOS table */
+ BLOBLISTT_SMBIOS_TABLES = 0x201, /* SMBIOS tables for x86 */
+ BLOBLISTT_VBOOT_CTX = 0x202, /* Chromium OS verified boot context */
/*
* Tags from here are on reserved for private use within a single
* implementation, but cannot be used in upstream code. Allocate a
* tag in one of the areas above if you want that.
*
- * This area may move in future.
+ * Project-specific tags are permitted here. Projects can be open source
+ * or not, but the format of the data must be fuily documented in an
+ * open source project, including all fields, bits, etc. Naming should
+ * be: BLOBLISTT_<project>_<purpose_here>
+ *
+ * Vendor-specific tags are also permitted. Projects can be open source
+ * or not, but the format of the data must be fuily documented in an
+ * open source project, including all fields, bits, etc. Naming should
+ * be BLOBLISTT_<vendor>_<purpose_here>
*/
- BLOBLISTT_PRIVATE_AREA = 0xffff0000,
+ BLOBLISTT_PRIVATE_AREA = 0xfff000,
+ BLOBLISTT_U_BOOT_SPL_HANDOFF = 0xfff000, /* Hand-off info from SPL */
+ BLOBLISTT_VBE = 0xfff001, /* VBE per-phase state */
+ BLOBLISTT_U_BOOT_VIDEO = 0xfff002, /* Video info from SPL */
};
/**
* from the last.
*
* @magic: BLOBLIST_MAGIC
+ * @chksum: checksum for the entire bloblist allocated area. Since any of the
+ * blobs can be altered after being created, this checksum is only valid
+ * when the bloblist is finalized before jumping to the next stage of boot.
+ * This is the value needed to make all checksummed bytes sum to 0
* @version: BLOBLIST_VERSION
* @hdr_size: Size of this header, normally sizeof(struct bloblist_hdr). The
* first bloblist_rec starts at this offset from the start of the header
- * @flags: Space for BLOBLISTF... flags (none yet)
- * @size: Total size of the bloblist (non-zero if valid) including this header.
- * The bloblist extends for this many bytes from the start of this header.
- * When adding new records, the bloblist can grow up to this size.
- * @alloced: Total size allocated so far for this bloblist. This starts out as
+ * @align_log2: Power of two of the maximum alignment required by this list
+ * @used_size: Size allocated so far for this bloblist. This starts out as
* sizeof(bloblist_hdr) since we need at least that much space to store a
* valid bloblist
+ * @total_size: The number of total bytes that the bloblist can occupy.
+ * Any blob producer must check if there is sufficient space before adding
+ * a record to the bloblist.
+ * @flags: Space for BLOBLISTF... flags (none yet)
* @spare: Spare space (for future use)
- * @chksum: CRC32 for the entire bloblist allocated area. Since any of the
- * blobs can be altered after being created, this checksum is only valid
- * when the bloblist is finalised before jumping to the next stage of boot.
- * Note that chksum is last to make it easier to exclude it from the
- * checksum calculation.
*/
struct bloblist_hdr {
u32 magic;
- u32 version;
- u32 hdr_size;
+ u8 chksum;
+ u8 version;
+ u8 hdr_size;
+ u8 align_log2;
+ u32 used_size;
+ u32 total_size;
u32 flags;
-
- u32 size;
- u32 alloced;
u32 spare;
- u32 chksum;
};
/**
*
* NOTE: Only exported for testing purposes. Do not use this struct.
*
- * @tag: Tag indicating what the record contains
- * @hdr_size: Size of this header, normally sizeof(struct bloblist_rec). The
- * record's data starts at this offset from the start of the record
+ * @tag_and_hdr_size: Tag indicating what the record contains (bottom 24 bits), and
+ * size of this header (top 8 bits), normally sizeof(struct bloblist_rec).
+ * The record's data starts at this offset from the start of the record
* @size: Size of record in bytes, excluding the header size. This does not
* need to be aligned (e.g. 3 is OK).
- * @spare: Spare space for other things
*/
struct bloblist_rec {
- u32 tag;
- u32 hdr_size;
+ u32 tag_and_hdr_size;
u32 size;
- u32 spare;
+};
+
+enum {
+ BLOBLISTR_TAG_SHIFT = 0,
+ BLOBLISTR_TAG_MASK = 0xffffffU << BLOBLISTR_TAG_SHIFT,
+ BLOBLISTR_HDR_SIZE_SHIFT = 24,
+ BLOBLISTR_HDR_SIZE_MASK = 0xffU << BLOBLISTR_HDR_SIZE_SHIFT,
+
+ BLOBLIST_HDR_SIZE = sizeof(struct bloblist_hdr),
+ BLOBLIST_REC_HDR_SIZE = sizeof(struct bloblist_rec),
};
/**
*
* @tag: Tag to add (enum bloblist_tag_t)
* @size: Size of the blob
- * @align: Alignment of the blob (in bytes), 0 for default
+ * @align_log2: Alignment of the blob (in bytes log2), 0 for default
* Return: pointer to the newly added block, or NULL if there is not enough
* space for the blob
*/
-void *bloblist_add(uint tag, int size, int align);
+void *bloblist_add(uint tag, int size, int align_log2);
/**
* bloblist_ensure_size() - Find or add a blob
* @tag: Tag to add (enum bloblist_tag_t)
* @size: Size of the blob
* @blobp: Returns a pointer to blob on success
- * @align: Alignment of the blob (in bytes), 0 for default
+ * @align_log2: Alignment of the blob (in bytes log2), 0 for default
* Return: 0 if OK, -ENOSPC if it is missing and could not be added due to lack
* of space, or -ESPIPE it exists but has the wrong size
*/
-int bloblist_ensure_size(uint tag, int size, int align, void **blobp);
+int bloblist_ensure_size(uint tag, int size, int align_log2, void **blobp);
/**
* bloblist_ensure() - Find or add a blob
* @addr: Address of bloblist
* @size: Initial size for bloblist
* @flags: Flags to use for bloblist
+ * @align_log2: Log base 2 of maximum alignment provided by this bloblist
* Return: 0 if OK, -EFAULT if addr is not aligned correctly, -ENOSPC is the
* area is not large enough
*/
-int bloblist_new(ulong addr, uint size, uint flags);
+int bloblist_new(ulong addr, uint size, uint flags, uint align_log2);
/**
* bloblist_check() - Check if a bloblist exists
* This returns useful information about the bloblist
*
* @basep: Returns base address of bloblist
- * @sizep: Returns the number of bytes used in the bloblist
- * @allocedp: Returns the total space allocated to the bloblist
+ * @tsizep: Returns the total number of bytes of the bloblist
+ * @usizep: Returns the number of used bytes of the bloblist
*/
-void bloblist_get_stats(ulong *basep, ulong *sizep, ulong *allocedp);
+void bloblist_get_stats(ulong *basep, ulong *tsizep, ulong *usizep);
/**
* bloblist_get_base() - Get the base address of the bloblist
*/
ulong bloblist_get_size(void);
+/**
+ * bloblist_get_total_size() - Get the total size of the bloblist
+ *
+ * Return: the size in bytes
+ */
+ulong bloblist_get_total_size(void);
+
/**
* bloblist_show_stats() - Show information about the bloblist
*
#ifndef _BOOTCOUNT_H__
#define _BOOTCOUNT_H__
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#ifndef __bootdev_h
#define __bootdev_h
+#include <dm/uclass-id.h>
#include <linux/list.h>
struct bootflow;
* CONFIG_OF_HAS_PRIOR_STAGE is enabled
* @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather
* than being allocated by malloc().
+ * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT
*/
enum bootflow_flags_t {
BOOTFLOWF_USE_PRIOR_FDT = 1 << 0,
BOOTFLOWF_STATIC_BUF = 1 << 1,
+ BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2,
};
/**
#define BOOTM_ERR_OVERLAP (-2)
#define BOOTM_ERR_UNIMPLEMENTED (-3)
+/**
+ * struct bootm_info() - information used when processing images to boot
+ *
+ * These mirror the first three arguments of the bootm command. They are
+ * designed to handle any type of image, but typically it is a FIT.
+ *
+ * @addr_img: Address of image to bootm, as passed to
+ * genimg_get_kernel_addr_fit() for processing:
+ *
+ * NULL: Usees default load address, i.e. image_load_addr
+ * <addr>: Uses hex address
+ *
+ * For FIT:
+ * "[<addr>]#<conf>": Uses address (or image_load_addr) and also specifies
+ * the FIT configuration to use
+ * "[<addr>]:<subimage>": Uses address (or image_load_addr) and also
+ * specifies the subimage name containing the OS
+ *
+ * @conf_ramdisk: Address (or with FIT, the name) of the ramdisk image, as
+ * passed to boot_get_ramdisk() for processing, or NULL for none
+ * @conf_fdt: Address (or with FIT, the name) of the FDT image, as passed to
+ * boot_get_fdt() for processing, or NULL for none
+ * @boot_progress: true to show boot progress
+ * @images: images information
+ * @cmd_name: command which invoked this operation, e.g. "bootm"
+ * @argc: Number of arguments to the command (excluding the actual command).
+ * This is 0 if there are no arguments
+ * @argv: NULL-terminated list of arguments, or NULL if there are no arguments
+ */
+struct bootm_info {
+ const char *addr_img;
+ const char *conf_ramdisk;
+ const char *conf_fdt;
+ bool boot_progress;
+ struct bootm_headers *images;
+ const char *cmd_name;
+ int argc;
+ char *const *argv;
+};
+
+/**
+ * bootm_init() - Set up a bootm_info struct with useful defaults
+ *
+ * Set up the struct with default values for all members:
+ * @boot_progress is set to true and @images is set to the global images
+ * variable. Everything else is set to NULL except @argc which is 0
+ */
+void bootm_init(struct bootm_info *bmi);
+
/*
* Continue booting an OS image; caller already has:
* - copied image header to global variable `header'
* - disabled interrupts.
*
* @flag: Flags indicating what to do (BOOTM_STATE_...)
- * @argc: Number of arguments. Note that the arguments are shifted down
- * so that 0 is the first argument not processed by U-Boot, and
- * argc is adjusted accordingly. This avoids confusion as to how
- * many arguments are available for the OS.
- * @images: Pointers to os/initrd/fdt
+ * bmi: Bootm information
* Return: 1 on error. On success the OS boots so this function does
* not return.
*/
-typedef int boot_os_fn(int flag, int argc, char *const argv[],
- struct bootm_headers *images);
+typedef int boot_os_fn(int flag, struct bootm_info *bmi);
extern boot_os_fn do_bootm_linux;
extern boot_os_fn do_bootm_vxworks;
-int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_bootelf(struct cmd_tbl *cmdtp, int fglag, int argc, char *const argv[]);
boot_os_fn *bootm_os_get_boot_func(int os);
int bootm_host_load_images(const void *fit, int cfg_noffset);
#endif
-int boot_selected_os(int argc, char *const argv[], int state,
- struct bootm_headers *images, boot_os_fn *boot_fn);
+int boot_selected_os(int state, struct bootm_info *bmi, boot_os_fn *boot_fn);
ulong bootm_disable_interrupts(void);
-/* This is a special function used by booti/bootz */
-int bootm_find_images(int flag, int argc, char *const argv[], ulong start,
- ulong size);
+/**
+ * bootm_find_images() - find and locate various images
+ *
+ * @img_addr: Address of image being loaded
+ * @conf_ramdisk: Indicates the ramdisk to use (typically second arg of bootm)
+ * @conf_fdt: Indicates the FDT to use (typically third arg of bootm)
+ * @start: OS image start address
+ * @size: OS image size
+ *
+ * boot_find_images() will attempt to load an available ramdisk,
+ * flattened device tree, as well as specifically marked
+ * "loadable" images (loadables are FIT only)
+ *
+ * Note: bootm_find_images will skip an image if it is not found
+ *
+ * This is a special function used by booti/bootz
+ *
+ * Return:
+ * 0, if all existing images were loaded correctly
+ * 1, if an image is found but corrupted, or invalid
+ */
+int bootm_find_images(ulong img_addr, const char *conf_ramdisk,
+ const char *conf_fdt, ulong start, ulong size);
/*
* Measure the boot images. Measurement is the process of hashing some binary
*/
int bootm_measure(struct bootm_headers *images);
-int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], int states, struct bootm_headers *images,
- int boot_progress);
+/**
+ * bootm_run_states() - Execute selected states of the bootm command.
+ *
+ * Note that if states contains more than one flag it MUST contain
+ * BOOTM_STATE_START, since this handles the addr_fit, conf_ramdisk and conf_fit
+ * members of @bmi
+ *
+ * Also note that aside from boot_os_fn functions and bootm_load_os, no other
+ * functions store the return value of in 'ret' may use a negative return
+ * value, without special handling.
+ *
+ * @bmi: bootm information
+ * @states Mask containing states to run (BOOTM_STATE_...)
+ * Return: 0 if ok, something else on error. Some errors will cause this
+ * function to perform a reboot! If states contains BOOTM_STATE_OS_GO
+ * then the intent is to boot an OS, so this function will not return
+ * unless the image type is standalone.
+ */
+int bootm_run_states(struct bootm_info *bmi, int states);
+
+/**
+ * boot_run() - Run the entire bootm/booti/bootz process
+ *
+ * This runs through the boot process from start to finish, with a base set of
+ * states, along with the extra ones supplied.
+ *
+ * This uses bootm_run_states().
+ *
+ * Note that it is normally easier to use bootm_run(), etc. since they handle
+ * the extra states correctly.
+ *
+ * @bmi: bootm information
+ * @cmd: command being run, NULL if none
+ * @extra_states: Mask of extra states to use for the boot
+ * Return: 0 if ok, something else on error
+ */
+int boot_run(struct bootm_info *bmi, const char *cmd, int extra_states);
+
+/**
+ * bootm_run() - Run the entire bootm process
+ *
+ * This runs through the bootm process from start to finish, using the default
+ * set of states.
+ *
+ * This uses bootm_run_states().
+ *
+ * @bmi: bootm information
+ * Return: 0 if ok, something else on error
+ */
+int bootm_run(struct bootm_info *bmi);
+
+/**
+ * bootz_run() - Run the entire bootz process
+ *
+ * This runs through the bootz process from start to finish, using the default
+ * set of states.
+ *
+ * This uses bootm_run_states().
+ *
+ * @bmi: bootm information
+ * Return: 0 if ok, something else on error
+ */
+int bootz_run(struct bootm_info *bmi);
+
+/**
+ * booti_run() - Run the entire booti process
+ *
+ * This runs through the booti process from start to finish, using the default
+ * set of states.
+ *
+ * This uses bootm_run_states().
+ *
+ * @bmi: bootm information
+ * Return: 0 if ok, something else on error
+ */
+int booti_run(struct bootm_info *bmi);
void arch_preboot_os(void);
#define _BOOTSTAGE_H
#include <linux/types.h>
+#ifdef USE_HOSTCC
#include <linux/kconfig.h>
+#endif
/* Flags for each bootstage record */
enum bootstage_flags {
BOOTSTAGE_ID_FIT_CONFIG = 110,
BOOTSTAGE_ID_FIT_TYPE,
- BOOTSTAGE_ID_FIT_KERNEL_INFO,
BOOTSTAGE_ID_FIT_COMPRESSION,
BOOTSTAGE_ID_FIT_OS,
*/
void bootstd_clear_glob(void);
+/**
+ * bootstd_prog_boot() - Run standard boot in a fully programmatic mode
+ *
+ * Attempts to boot without making any use of U-Boot commands
+ *
+ * Returns: -ve error value (does not return except on failure to boot)
+ */
+int bootstd_prog_boot(void);
+
#endif
#define FLAG_REPARSING (1 << 2) /* >=2nd pass */
#define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */
+#if CONFIG_IS_ENABLED(HUSH_OLD_PARSER)
extern int u_boot_hush_start(void);
-extern int parse_string_outer(const char *, int);
+extern int parse_string_outer(const char *str, int flag);
extern int parse_file_outer(void);
-
int set_local_var(const char *s, int flg_export);
+#else
+static inline int u_boot_hush_start(void)
+{
+ return 0;
+}
+
+static inline int parse_string_outer(const char *str, int flag)
+{
+ return 1;
+}
+
+static inline int parse_file_outer(void)
+{
+ return 0;
+}
+
+static inline int set_local_var(const char *s, int flg_export)
+{
+ return 0;
+}
+#endif
+#if CONFIG_IS_ENABLED(HUSH_MODERN_PARSER)
+extern int u_boot_hush_start_modern(void);
+extern int parse_string_outer_modern(const char *str, int flag);
+extern void parse_and_run_file(void);
+int set_local_var_modern(char *s, int flg_export);
+#else
+static inline int u_boot_hush_start_modern(void)
+{
+ return 0;
+}
+
+static inline int parse_string_outer_modern(const char *str, int flag)
+{
+ return 1;
+}
+
+static inline void parse_and_run_file(void)
+{
+}
+
+static inline int set_local_var_modern(char *s, int flg_export)
+{
+ return 0;
+}
+#endif
+
void unset_local_var(const char *name);
char *get_local_var(const char *s);
* @set_parent: Set current clock parent
* @enable: Enable a clock.
* @disable: Disable a clock.
+ * @dump: Print clock information.
*
* The individual methods are described more fully below.
*/
int (*set_parent)(struct clk *clk, struct clk *parent);
int (*enable)(struct clk *clk);
int (*disable)(struct clk *clk);
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ void (*dump)(struct udevice *dev);
+#endif
};
#if 0 /* For documentation only */
* Return: zero on success, or -ve error code.
*/
int disable(struct clk *clk);
+
+/**
+ * dump() - Print clock information.
+ * @dev: The clock device to dump.
+ *
+ * If present, this function is called by "clk dump" command for each
+ * bound device.
+ */
+void dump(struct udevice *dev);
#endif
#endif
return clk && !!clk->dev;
}
-int soc_clk_dump(void);
-
#endif
#define clk_prepare_enable(clk) clk_enable(clk)
#endif
};
+/**
+ * cmd_arg_get() - Get a particular argument
+ *
+ * @argc: Number of arguments
+ * @argv: Argument vector of length @argc
+ * @argnum: Argument to get (0=first)
+ * Return: Pointer to argument @argnum if it exists, else NULL
+ */
+static inline const char *cmd_arg_get(int argc, char *const argv[], int argnum)
+{
+ return argc > argnum ? argv[argnum] : NULL;
+}
+
+static inline const char *cmd_arg0(int argc, char *const argv[])
+{
+ return cmd_arg_get(argc, argv, 0);
+}
+
+static inline const char *cmd_arg1(int argc, char *const argv[])
+{
+ return cmd_arg_get(argc, argv, 1);
+}
+
+static inline const char *cmd_arg2(int argc, char *const argv[])
+{
+ return cmd_arg_get(argc, argv, 2);
+}
+
+static inline const char *cmd_arg3(int argc, char *const argv[])
+{
+ return cmd_arg_get(argc, argv, 3);
+}
+
#if defined(CONFIG_CMD_RUN)
int do_run(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
ll_entry_declare(struct cmd_tbl, _name, cmd) = \
U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
- _usage, _help, _comp);
+ _usage, _help, _comp)
#define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage, \
_help, _comp) \
#include <env/ti/mmc.h>
#include <env/ti/k3_dfu.h>
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
#include <env/ti/k3_rproc.h>
#include <env/ti/k3_dfu.h>
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
#ifndef __AT91_SAMA5_COMMON_H
#define __AT91_SAMA5_COMMON_H
-#include <linux/kconfig.h>
-
/* ARM asynchronous clock */
#define CFG_SYS_AT91_SLOW_CLOCK 32768
#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
UBI_BOOTCMD
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
#define MODULE_EXTRA_ENV_SETTINGS \
- "variant=-emmc\0" \
EMMC_ANDROID_BOOTCMD
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * U-Boot file:/include/configs/am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef __CONFIG_DRACO_H
-#define __CONFIG_DRACO_H
-
-#include "siemens-am33x-common.h"
-
-#define DDR_PLL_FREQ 303
-
-#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
-#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
-
-#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \
- "button_dfu0=27\0" \
- "led0=103,1,0\0" \
- "led1=64,0,1\0"
-
- /* Physical Memory Map */
-#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-
-/* Default env settings */
-#define CFG_EXTRA_ENV_SETTINGS \
- "hostname=draco\0" \
- "ubi_off=2048\0"\
- "nand_img_size=0x400000\0" \
- "optargs=\0" \
- "preboot=draco_led 0\0" \
- CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \
- CFG_ENV_SETTINGS_V2 \
- CFG_ENV_SETTINGS_NAND_V2
-
-#endif /* ! __CONFIG_DRACO_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#ifndef __IMX8MP_DEBIX_MODEL_A_H
+#define __IMX8MP_DEBIX_MODEL_A_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR 1
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "image=Image\0" \
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "boot_fdt=try\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
+
+/* 2GB DDR */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+#ifndef __IMX93_VAR_SOM_H
+#define __IMX93_VAR_SOM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS BOOTENV
+
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define DEFAULT_SDRAM_SIZE (512 * SZ_1M) /* 512MB Minimum DDR4, see get_dram_size */
+#define VAR_EEPROM_DRAM_START (PHYS_SDRAM + (DEFAULT_SDRAM_SIZE >> 1))
+#define VAR_SOM_EEPROM_I2C_NAME "i2c@42530000"
+#define VAR_CARRIER_EEPROM_I2C_NAME "i2c@44340000"
+
+#define CFG_SYS_FSL_USDHC_NUM 2
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#if defined(CONFIG_CMD_NET)
+#define PHY_ANEG_TIMEOUT 20000
+#endif
+
+#endif
#include <linux/sizes.h>
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
#define CFG_SYS_FLASH_BASE 0x000000000
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1 0x880000000
-
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM)
#define CFG_SYS_UBOOT_BASE 0x50280000
"scriptaddr=0x80000000\0" \
"pxefile_addr_r=0x80100000\0" \
"kernel_addr_r=0x80800000\0" \
+ "kernel_comp_addr_r=0x90000000\0" \
+ "kernel_comp_size=0x08000000\0" \
"fdt_addr_r=0x84800000\0" \
"ramdisk_addr_r=0x85000000\0" \
"console=" CONSOLE ",115200\0" \
* MMC
*/
-/* SATA */
-#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
-#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
-#endif
-#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
- PCI_DEVICE_ID_FREESCALE_AHCI}
-
/* SPI */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
CSOR_NOR_TRHZ_80)
#endif
-/* SATA */
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-
/* Initial environment variables */
#ifndef SPL_NO_ENV
#undef CFG_EXTRA_ENV_SETTINGS
#endif
#endif
-/* SATA */
-#ifndef SPL_NO_SATA
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8365 based boards
+ *
+ * Copyright (C) 2023 BayLibre, SAS
+ * Author: Julien Masson <jmasson@baylibre.com>
+ */
+
+#ifndef __MT8365_H
+#define __MT8365_H
+
+#endif
#define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */
-#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CFG_DFU_ENV_SETTINGS \
"dfu_alt_info=" \
"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
"fastboot_partition_alias_system=rootfs\0" \
"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
+ "mmcautodetect=yes\0" \
PICO_BOOT_ENV
#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
"env_mmc_blknum=0xf80\0" \
"env_mmc_nblks=0x80\0" \
"kernel_addr_r=0x30000000\0" \
- "pxefile_addr_r=0x32000000\0" \
- "scriptaddr=0x32000000\0" \
- "fdt_addr_r=0x32200000\0" \
+ "pxefile_addr_r=0x33000000\0" \
+ "scriptaddr=0x33000000\0" \
+ "fdt_addr_r=0x33200000\0" \
"fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \
- "ramdisk_addr_r=0x32400000\0" \
+ "ramdisk_addr_r=0x33400000\0" \
BOOTENV
#endif /* _POPLAR_H_ */
#define CFG_SYS_SDRAM_BASE 0x80000000
-/* Environment options */
-
-#define BOOT_TARGET_DEVICES(func) \
- func(NVME, nvme, 0) \
- func(NVME, nvme, 1) \
- func(USB, usb, 0) \
- func(MMC, mmc, 0) \
- func(SCSI, scsi, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
-#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
-#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
-
-#define PARTS_DEFAULT \
- "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
- "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
- "name=system,size=-,bootable,type=${type_guid_gpt_system};"
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x80200000\0" \
- "kernel_comp_addr_r=0x88000000\0" \
- "kernel_comp_size=0x4000000\0" \
- "fdt_addr_r=0x8c000000\0" \
- "scriptaddr=0x8c100000\0" \
- "pxefile_addr_r=0x8c200000\0" \
- "ramdisk_addr_r=0x8c300000\0" \
- "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
- "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
- "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
- "partitions=" PARTS_DEFAULT "\0" \
- "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- BOOTENV
-
#endif /* __SIFIVE_UNMATCHED_H */
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
"fdt_addr_r=0x46000000\0" \
+ "fdtoverlay_addr_r=0x45800000\0" \
"scriptaddr=0x43900000\0" \
"pxefile_addr_r=0x45900000\0" \
"ramdisk_addr_r=0x46100000\0" \
"scriptaddr=0x00418000\0" \
"pxefile_addr_r=0x00428000\0" \
"ramdisk_addr_r=0x00438000\0" \
+ "splashimage=0x00448000\0" \
+ "splashpos=m,m\0" \
BOOTENV
#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP25x CPU
+ */
+
+#ifndef __CONFIG_STM32MP25_COMMMON_H
+#define __CONFIG_STM32MP25_COMMMON_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
+
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_SYS_BOOTMAPSZ SZ_256M
+
+#endif /* __CONFIG_STM32MP25_COMMMON_H */
*/
#define CFG_SYS_NS16550_CLK 166666666
-/*
- * Even though the board houses Realtek RTL8211E PHY
- * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
- * In particular "parse_status" reports link is down.
- *
- * Until Realtek PHY driver is fixed fall back to generic PHY driver
- * which implements all required functionality and behaves much more stable.
- *
- *
- */
-
-/*
- * Ethernet configuration
- */
-#define ETH0_BASE_ADDRESS 0xFE100000
-#define ETH1_BASE_ADDRESS 0xFE110000
-
-/*
- * Console configuration
- */
-
#endif /* _CONFIG_TB100_H_ */
#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H
-/* U-Boot Build Configuration */
-
-/* SoC Configuration */
-
/* Memory Configuration */
#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
-#else
-#define SPL_MALLOC_F_SIZE 0
-#endif
-
-/* SPL SPI Loader Configuration */
-#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
-
/* SRAM scratch space entries */
#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc
#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
-/* EEPROM definitions */
-
/* NAND Configuration */
#define CFG_SYS_NAND_MASK_CLE 0x4000
#define CFG_SYS_NAND_MASK_ALE 0x2000
#define CFG_SYS_NAND_LARGEPAGE
#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
-
-
-/* U-Boot general configuration */
-
-/* EDMA3 */
-
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
/* we may include files below only after all above definitions */
-#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <linux/kconfig.h>
#include <linux/stringify.h>
/* place code in last 4 MiB of RAM */
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
- "fdt_addr=0x43000000\0" \
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
func(USB, usb, 0) \
func(SATA, sata, 0) \
func(SATA, sata, 1) \
+ FUNC_VIRTIO(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na) \
func(AFS, afs, na)
#include "tegra30-common.h"
-#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
-
-#ifdef CONFIG_DEVICE_P880
/* High-level configuration options */
-#undef CFG_TEGRA_BOARD_STRING
-#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD"
-#endif
-
-#ifdef CONFIG_DEVICE_P895
-/* High-level configuration options */
-#undef CFG_TEGRA_BOARD_STRING
-#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu"
-#endif
+#define CFG_TEGRA_BOARD_STRING "LG X3 Board"
#define X3_FLASH_UBOOT \
"flash_uboot=echo Preparing RAM;" \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
*/
void console_puts_select_stderr(bool serial_only, const char *s);
+/**
+ * console_clear() - Clear the console
+ *
+ * Uses an ANSI sequence to clear the display, failing back to clearing the
+ * video display directly if !CONFIG_VIDEO_ANSI
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int console_clear(void);
+
/*
* CONSOLE multiplexing.
*/
#ifndef __DFU_ENTITY_H_
#define __DFU_ENTITY_H_
-#include <common.h>
#include <linux/list.h>
#include <mmc.h>
#include <spi_flash.h>
int dev_num;
};
+
+#if defined(CONFIG_DFU_NAME_MAX_SIZE)
+#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE
+#else
#define DFU_NAME_SIZE 32
+#endif
#ifndef DFU_DEFAULT_POLL_TIMEOUT
#define DFU_DEFAULT_POLL_TIMEOUT 0
#endif
#ifndef __DISPLAY_OPTIONS_H
#define __DISPLAY_OPTIONS_H
+#include <linux/types.h>
+
/**
* print_size() - Print a size with a suffix
*
* @size: Size to print
* @suffix String to print after the size
*/
-#include <display_options.h>
void print_size(uint64_t size, const char *suffix);
/**
#define IMX8MP_CLK_SAI1 123
#define IMX8MP_CLK_SAI2 124
#define IMX8MP_CLK_SAI3 125
-#define IMX8MP_CLK_SAI4 126
+/* #define IMX8MP_CLK_SAI4 126 */
#define IMX8MP_CLK_SAI5 127
#define IMX8MP_CLK_SAI6 128
#define IMX8MP_CLK_ENET_QOS 129
#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
-#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+ *
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8365_H
+#define _DT_BINDINGS_CLK_MT8365_H
+
+/* TOPCKGEN */
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_I2S0_BCK 1
+#define CLK_TOP_DSI0_LNTC_DSICK 2
+#define CLK_TOP_VPLL_DPIX 3
+#define CLK_TOP_LVDSTX_CLKDIG_CTS 4
+#define CLK_TOP_MFGPLL 5
+#define CLK_TOP_SYSPLL_D2 6
+#define CLK_TOP_SYSPLL1_D2 7
+#define CLK_TOP_SYSPLL1_D4 8
+#define CLK_TOP_SYSPLL1_D8 9
+#define CLK_TOP_SYSPLL1_D16 10
+#define CLK_TOP_SYSPLL_D3 11
+#define CLK_TOP_SYSPLL2_D2 12
+#define CLK_TOP_SYSPLL2_D4 13
+#define CLK_TOP_SYSPLL2_D8 14
+#define CLK_TOP_SYSPLL_D5 15
+#define CLK_TOP_SYSPLL3_D2 16
+#define CLK_TOP_SYSPLL3_D4 17
+#define CLK_TOP_SYSPLL_D7 18
+#define CLK_TOP_SYSPLL4_D2 19
+#define CLK_TOP_SYSPLL4_D4 20
+#define CLK_TOP_UNIVPLL 21
+#define CLK_TOP_UNIVPLL_D2 22
+#define CLK_TOP_UNIVPLL1_D2 23
+#define CLK_TOP_UNIVPLL1_D4 24
+#define CLK_TOP_UNIVPLL_D3 25
+#define CLK_TOP_UNIVPLL2_D2 26
+#define CLK_TOP_UNIVPLL2_D4 27
+#define CLK_TOP_UNIVPLL2_D8 28
+#define CLK_TOP_UNIVPLL2_D32 29
+#define CLK_TOP_UNIVPLL_D5 30
+#define CLK_TOP_UNIVPLL3_D2 31
+#define CLK_TOP_UNIVPLL3_D4 32
+#define CLK_TOP_MMPLL 33
+#define CLK_TOP_MMPLL_D2 34
+#define CLK_TOP_LVDSPLL_D2 35
+#define CLK_TOP_LVDSPLL_D4 36
+#define CLK_TOP_LVDSPLL_D8 37
+#define CLK_TOP_LVDSPLL_D16 38
+#define CLK_TOP_USB20_192M 39
+#define CLK_TOP_USB20_192M_D4 40
+#define CLK_TOP_USB20_192M_D8 41
+#define CLK_TOP_USB20_192M_D16 42
+#define CLK_TOP_USB20_192M_D32 43
+#define CLK_TOP_APLL1 44
+#define CLK_TOP_APLL1_D2 45
+#define CLK_TOP_APLL1_D4 46
+#define CLK_TOP_APLL1_D8 47
+#define CLK_TOP_APLL2 48
+#define CLK_TOP_APLL2_D2 49
+#define CLK_TOP_APLL2_D4 50
+#define CLK_TOP_APLL2_D8 51
+#define CLK_TOP_SYS_26M_D2 52
+#define CLK_TOP_MSDCPLL 53
+#define CLK_TOP_MSDCPLL_D2 54
+#define CLK_TOP_DSPPLL 55
+#define CLK_TOP_DSPPLL_D2 56
+#define CLK_TOP_DSPPLL_D4 57
+#define CLK_TOP_DSPPLL_D8 58
+#define CLK_TOP_APUPLL 59
+#define CLK_TOP_CLK26M_D52 60
+#define CLK_TOP_AXI_SEL 61
+#define CLK_TOP_MEM_SEL 62
+#define CLK_TOP_MM_SEL 63
+#define CLK_TOP_SCP_SEL 64
+#define CLK_TOP_MFG_SEL 65
+#define CLK_TOP_ATB_SEL 66
+#define CLK_TOP_CAMTG_SEL 67
+#define CLK_TOP_CAMTG1_SEL 68
+#define CLK_TOP_UART_SEL 69
+#define CLK_TOP_SPI_SEL 70
+#define CLK_TOP_MSDC50_0_HC_SEL 71
+#define CLK_TOP_MSDC2_2_HC_SEL 72
+#define CLK_TOP_MSDC50_0_SEL 73
+#define CLK_TOP_MSDC50_2_SEL 74
+#define CLK_TOP_MSDC30_1_SEL 75
+#define CLK_TOP_AUDIO_SEL 76
+#define CLK_TOP_AUD_INTBUS_SEL 77
+#define CLK_TOP_AUD_1_SEL 78
+#define CLK_TOP_AUD_2_SEL 79
+#define CLK_TOP_AUD_ENGEN1_SEL 80
+#define CLK_TOP_AUD_ENGEN2_SEL 81
+#define CLK_TOP_AUD_SPDIF_SEL 82
+#define CLK_TOP_DISP_PWM_SEL 83
+#define CLK_TOP_DXCC_SEL 84
+#define CLK_TOP_SSUSB_SYS_SEL 85
+#define CLK_TOP_SSUSB_XHCI_SEL 86
+#define CLK_TOP_SPM_SEL 87
+#define CLK_TOP_I2C_SEL 88
+#define CLK_TOP_PWM_SEL 89
+#define CLK_TOP_SENIF_SEL 90
+#define CLK_TOP_AES_FDE_SEL 91
+#define CLK_TOP_CAMTM_SEL 92
+#define CLK_TOP_DPI0_SEL 93
+#define CLK_TOP_DPI1_SEL 94
+#define CLK_TOP_DSP_SEL 95
+#define CLK_TOP_NFI2X_SEL 96
+#define CLK_TOP_NFIECC_SEL 97
+#define CLK_TOP_ECC_SEL 98
+#define CLK_TOP_ETH_SEL 99
+#define CLK_TOP_GCPU_SEL 100
+#define CLK_TOP_GCPU_CPM_SEL 101
+#define CLK_TOP_APU_SEL 102
+#define CLK_TOP_APU_IF_SEL 103
+#define CLK_TOP_MBIST_DIAG_SEL 104
+#define CLK_TOP_APLL_I2S0_SEL 105
+#define CLK_TOP_APLL_I2S1_SEL 106
+#define CLK_TOP_APLL_I2S2_SEL 107
+#define CLK_TOP_APLL_I2S3_SEL 108
+#define CLK_TOP_APLL_TDMOUT_SEL 109
+#define CLK_TOP_APLL_TDMIN_SEL 110
+#define CLK_TOP_APLL_SPDIF_SEL 111
+#define CLK_TOP_APLL12_CK_DIV0 112
+#define CLK_TOP_APLL12_CK_DIV1 113
+#define CLK_TOP_APLL12_CK_DIV2 114
+#define CLK_TOP_APLL12_CK_DIV3 115
+#define CLK_TOP_APLL12_CK_DIV4 116
+#define CLK_TOP_APLL12_CK_DIV4B 117
+#define CLK_TOP_APLL12_CK_DIV5 118
+#define CLK_TOP_APLL12_CK_DIV5B 119
+#define CLK_TOP_APLL12_CK_DIV6 120
+#define CLK_TOP_AUD_I2S0_M 121
+#define CLK_TOP_AUD_I2S1_M 122
+#define CLK_TOP_AUD_I2S2_M 123
+#define CLK_TOP_AUD_I2S3_M 124
+#define CLK_TOP_AUD_TDMOUT_M 125
+#define CLK_TOP_AUD_TDMOUT_B 126
+#define CLK_TOP_AUD_TDMIN_M 127
+#define CLK_TOP_AUD_TDMIN_B 128
+#define CLK_TOP_AUD_SPDIF_M 129
+#define CLK_TOP_USB20_48M_EN 130
+#define CLK_TOP_UNIVPLL_48M_EN 131
+#define CLK_TOP_LVDSTX_CLKDIG_EN 132
+#define CLK_TOP_VPLL_DPIX_EN 133
+#define CLK_TOP_SSUSB_TOP_CK_EN 134
+#define CLK_TOP_SSUSB_PHY_CK_EN 135
+#define CLK_TOP_CONN_32K 136
+#define CLK_TOP_CONN_26M 137
+#define CLK_TOP_DSP_32K 138
+#define CLK_TOP_DSP_26M 139
+#define CLK_TOP_NR_CLK 140
+#define CLK_TOP_CLK26M 141
+#define CLK_TOP_CLK32K 142
+
+/* INFRACFG */
+#define CLK_IFR_PMIC_TMR 0
+#define CLK_IFR_PMIC_AP 1
+#define CLK_IFR_PMIC_MD 2
+#define CLK_IFR_PMIC_CONN 3
+#define CLK_IFR_ICUSB 4
+#define CLK_IFR_GCE 5
+#define CLK_IFR_THERM 6
+#define CLK_IFR_PWM_HCLK 7
+#define CLK_IFR_PWM1 8
+#define CLK_IFR_PWM2 9
+#define CLK_IFR_PWM3 10
+#define CLK_IFR_PWM4 11
+#define CLK_IFR_PWM5 12
+#define CLK_IFR_PWM 13
+#define CLK_IFR_UART0 14
+#define CLK_IFR_UART1 15
+#define CLK_IFR_UART2 16
+#define CLK_IFR_DSP_UART 17
+#define CLK_IFR_GCE_26M 18
+#define CLK_IFR_CQ_DMA_FPC 19
+#define CLK_IFR_BTIF 20
+#define CLK_IFR_SPI0 21
+#define CLK_IFR_MSDC0_HCLK 22
+#define CLK_IFR_MSDC2_HCLK 23
+#define CLK_IFR_MSDC1_HCLK 24
+#define CLK_IFR_DVFSRC 25
+#define CLK_IFR_GCPU 26
+#define CLK_IFR_TRNG 27
+#define CLK_IFR_AUXADC 28
+#define CLK_IFR_CPUM 29
+#define CLK_IFR_AUXADC_MD 30
+#define CLK_IFR_AP_DMA 31
+#define CLK_IFR_DEBUGSYS 32
+#define CLK_IFR_AUDIO 33
+#define CLK_IFR_PWM_FBCLK6 34
+#define CLK_IFR_DISP_PWM 35
+#define CLK_IFR_AUD_26M_BK 36
+#define CLK_IFR_CQ_DMA 37
+#define CLK_IFR_MSDC0_SF 38
+#define CLK_IFR_MSDC1_SF 39
+#define CLK_IFR_MSDC2_SF 40
+#define CLK_IFR_AP_MSDC0 41
+#define CLK_IFR_MD_MSDC0 42
+#define CLK_IFR_MSDC0_SRC 43
+#define CLK_IFR_MSDC1_SRC 44
+#define CLK_IFR_MSDC2_SRC 45
+#define CLK_IFR_PWRAP_TMR 46
+#define CLK_IFR_PWRAP_SPI 47
+#define CLK_IFR_PWRAP_SYS 48
+#define CLK_IFR_MCU_PM_BK 49
+#define CLK_IFR_IRRX_26M 50
+#define CLK_IFR_IRRX_32K 51
+#define CLK_IFR_I2C0_AXI 52
+#define CLK_IFR_I2C1_AXI 53
+#define CLK_IFR_I2C2_AXI 54
+#define CLK_IFR_I2C3_AXI 55
+#define CLK_IFR_NIC_AXI 56
+#define CLK_IFR_NIC_SLV_AXI 57
+#define CLK_IFR_APU_AXI 58
+#define CLK_IFR_NFIECC 59
+#define CLK_IFR_NFIECC_BK 60
+#define CLK_IFR_NFI1X_BK 61
+#define CLK_IFR_NFI_BK 62
+#define CLK_IFR_MSDC2_AP_BK 63
+#define CLK_IFR_MSDC2_MD_BK 64
+#define CLK_IFR_MSDC2_BK 65
+#define CLK_IFR_SUSB_133_BK 66
+#define CLK_IFR_SUSB_66_BK 67
+#define CLK_IFR_SSUSB_SYS 68
+#define CLK_IFR_SSUSB_REF 69
+#define CLK_IFR_SSUSB_XHCI 70
+#define CLK_IFR_NR_CLK 71
+
+/* PERICFG */
+#define CLK_PERIAXI 0
+#define CLK_PERI_NR_CLK 1
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MFGPLL 3
+#define CLK_APMIXED_MSDCPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_APLL1 6
+#define CLK_APMIXED_APLL2 7
+#define CLK_APMIXED_LVDSPLL 8
+#define CLK_APMIXED_DSPPLL 9
+#define CLK_APMIXED_APUPLL 10
+#define CLK_APMIXED_UNIV_EN 11
+#define CLK_APMIXED_USB20_EN 12
+#define CLK_APMIXED_NR_CLK 13
+
+/* GCE */
+#define CLK_GCE_FAXI 0
+#define CLK_GCE_NR_CLK 1
+
+/* AUDIOTOP */
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_SPDF 7
+#define CLK_AUD_HDMI 8
+#define CLK_AUD_HDMI_IN 9
+#define CLK_AUD_ADC 10
+#define CLK_AUD_DAC 11
+#define CLK_AUD_DAC_PREDIS 12
+#define CLK_AUD_TML 13
+#define CLK_AUD_I2S1_BK 14
+#define CLK_AUD_I2S2_BK 15
+#define CLK_AUD_I2S3_BK 16
+#define CLK_AUD_I2S4_BK 17
+#define CLK_AUD_NR_CLK 18
+
+/* MIPI_CSI0A */
+#define CLK_MIPI0A_CSR_CSI_EN_0A 0
+#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
+
+/* MIPI_CSI0B */
+#define CLK_MIPI0B_CSR_CSI_EN_0B 0
+#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
+
+/* MIPI_CSI1A */
+#define CLK_MIPI1A_CSR_CSI_EN_1A 0
+#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
+
+/* MIPI_CSI1B */
+#define CLK_MIPI1B_CSR_CSI_EN_1B 0
+#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
+
+/* MIPI_CSI2A */
+#define CLK_MIPI2A_CSR_CSI_EN_2A 0
+#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
+
+/* MIPI_CSI2B */
+#define CLK_MIPI2B_CSR_CSI_EN_2B 0
+#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
+
+/* MCUCFG */
+#define CLK_MCU_BUS_SEL 0
+#define CLK_MCU_NR_CLK 1
+
+/* MFGCFG */
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_MBIST_DIAG 1
+#define CLK_MFG_NR_CLK 2
+
+/* MMSYS */
+#define CLK_MM_MM_MDP_RDMA0 0
+#define CLK_MM_MM_MDP_CCORR0 1
+#define CLK_MM_MM_MDP_RSZ0 2
+#define CLK_MM_MM_MDP_RSZ1 3
+#define CLK_MM_MM_MDP_TDSHP0 4
+#define CLK_MM_MM_MDP_WROT0 5
+#define CLK_MM_MM_MDP_WDMA0 6
+#define CLK_MM_MM_DISP_OVL0 7
+#define CLK_MM_MM_DISP_OVL0_2L 8
+#define CLK_MM_MM_DISP_RSZ0 9
+#define CLK_MM_MM_DISP_RDMA0 10
+#define CLK_MM_MM_DISP_WDMA0 11
+#define CLK_MM_MM_DISP_COLOR0 12
+#define CLK_MM_MM_DISP_CCORR0 13
+#define CLK_MM_MM_DISP_AAL0 14
+#define CLK_MM_MM_DISP_GAMMA0 15
+#define CLK_MM_MM_DISP_DITHER0 16
+#define CLK_MM_MM_DSI0 17
+#define CLK_MM_MM_DISP_RDMA1 18
+#define CLK_MM_MM_MDP_RDMA1 19
+#define CLK_MM_DPI0_DPI0 20
+#define CLK_MM_MM_FAKE 21
+#define CLK_MM_MM_SMI_COMMON 22
+#define CLK_MM_MM_SMI_LARB0 23
+#define CLK_MM_MM_SMI_COMM0 24
+#define CLK_MM_MM_SMI_COMM1 25
+#define CLK_MM_MM_CAM_MDP 26
+#define CLK_MM_MM_SMI_IMG 27
+#define CLK_MM_MM_SMI_CAM 28
+#define CLK_MM_IMG_IMG_DL_RELAY 29
+#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
+#define CLK_MM_DSI0_DIG_DSI 31
+#define CLK_MM_26M_HRTWT 32
+#define CLK_MM_MM_DPI0 33
+#define CLK_MM_LVDSTX_PXL 34
+#define CLK_MM_LVDSTX_CTS 35
+#define CLK_MM_NR_CLK 36
+
+/* IMGSYS */
+#define CLK_CAM_LARB2 0
+#define CLK_CAM 1
+#define CLK_CAMTG 2
+#define CLK_CAM_SENIF 3
+#define CLK_CAMSV0 4
+#define CLK_CAMSV1 5
+#define CLK_CAM_FDVT 6
+#define CLK_CAM_WPE 7
+#define CLK_CAM_NR_CLK 8
+
+/* VDECSYS */
+#define CLK_VDEC_VDEC 0
+#define CLK_VDEC_LARB1 1
+#define CLK_VDEC_NR_CLK 2
+
+/* VENCSYS */
+#define CLK_VENC 0
+#define CLK_VENC_JPGENC 1
+#define CLK_VENC_NR_CLK 2
+
+/* APUSYS */
+#define CLK_APU_IPU_CK 0
+#define CLK_APU_AXI 1
+#define CLK_APU_JTAG 2
+#define CLK_APU_IF_CK 3
+#define CLK_APU_EDMA 4
+#define CLK_APU_AHB 5
+#define CLK_APU_NR_CLK 6
+
+#endif /* _DT_BINDINGS_CLK_MT8365_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2023 Nuvoton Technology corporation.
+
+#ifndef _DT_BINDINGS_NPCM_USBPHY_H
+#define _DT_BINDINGS_NPCM_USBPHY_H
+
+#define NPCM_UDC0_7 0
+#define NPCM_UDC8 1
+#define NPCM_UDC9 2
+#define NPCM_USBH1 3
+#define NPCM_USBH2 4
+#define NPCM_MAX_USB_CTRL_ID 4
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+#ifndef __MT8365_PINFUNC_H
+#define __MT8365_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1)
+#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2)
+#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
+#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
+#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5)
+#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1)
+#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2)
+#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3)
+#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
+#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5)
+#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
+
+#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1)
+#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2)
+#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3)
+#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
+#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5)
+#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
+
+#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1)
+#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2)
+#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
+#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
+#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5)
+#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6)
+#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
+
+#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1)
+#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2)
+#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3)
+#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
+#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5)
+#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6)
+#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
+
+#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1)
+#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2)
+#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3)
+#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
+#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5)
+#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6)
+#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
+
+#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1)
+#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2)
+#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
+#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
+#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5)
+#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6)
+#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
+
+#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1)
+#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3)
+#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
+#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5)
+#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
+
+#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1)
+#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2)
+#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3)
+#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
+#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5)
+#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
+
+#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1)
+#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2)
+#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3)
+#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
+#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5)
+#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
+
+#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1)
+#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2)
+#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3)
+#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
+#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5)
+#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
+
+#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1)
+#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2)
+#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3)
+#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4)
+#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5)
+#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
+
+#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1)
+#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2)
+#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3)
+#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4)
+#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5)
+#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7)
+
+#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1)
+#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2)
+#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3)
+#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4)
+#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5)
+#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7)
+
+#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1)
+#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2)
+#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3)
+#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4)
+#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5)
+#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6)
+#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7)
+
+#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1)
+#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2)
+#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3)
+#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4)
+#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5)
+#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6)
+#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7)
+
+#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1)
+#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2)
+#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3)
+#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4)
+#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5)
+#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6)
+#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7)
+
+#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1)
+#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2)
+#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3)
+#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4)
+#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5)
+#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6)
+#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7)
+
+#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1)
+#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2)
+#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3)
+#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4)
+#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5)
+#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6)
+#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7)
+
+#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1)
+#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2)
+#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7)
+
+#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1)
+#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2)
+#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7)
+
+#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1)
+#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2)
+#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3)
+#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4)
+#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7)
+
+#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1)
+#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7)
+
+#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1)
+#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2)
+#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3)
+#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4)
+#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5)
+#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6)
+#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7)
+
+#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1)
+#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7)
+
+#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1)
+#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2)
+#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3)
+#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4)
+#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5)
+#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6)
+#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7)
+
+#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1)
+#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3)
+#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4)
+#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5)
+#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6)
+#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7)
+
+#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1)
+#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3)
+#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4)
+#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5)
+#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6)
+#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7)
+
+#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1)
+#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2)
+#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3)
+#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4)
+#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5)
+#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6)
+#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7)
+
+#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1)
+#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2)
+#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3)
+#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4)
+#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5)
+#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6)
+#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7)
+
+#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1)
+#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2)
+#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3)
+#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4)
+#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5)
+#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6)
+
+#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1)
+#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2)
+#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3)
+#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4)
+#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5)
+#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6)
+
+#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1)
+#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2)
+#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3)
+#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4)
+#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5)
+
+#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1)
+#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2)
+#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3)
+#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4)
+#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5)
+
+#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1)
+#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2)
+#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3)
+#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4)
+#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5)
+
+#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1)
+#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2)
+#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7)
+
+#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1)
+#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2)
+#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7)
+
+#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1)
+#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2)
+#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3)
+#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4)
+#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5)
+#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6)
+#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7)
+
+#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1)
+#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2)
+#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3)
+#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4)
+#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5)
+#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6)
+#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7)
+
+#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1)
+#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2)
+#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3)
+#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4)
+#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5)
+#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6)
+#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7)
+
+#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1)
+#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2)
+#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3)
+#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4)
+#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5)
+#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6)
+#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7)
+
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1)
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2)
+
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1)
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2)
+
+#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1)
+
+#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1)
+
+#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1)
+
+#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1)
+
+#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1)
+#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2)
+
+#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1)
+
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3)
+
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3)
+
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3)
+
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3)
+
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3)
+
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3)
+
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3)
+
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3)
+
+#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1)
+
+#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1)
+
+#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1)
+#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6)
+#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7)
+
+#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1)
+#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6)
+#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7)
+
+#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1)
+
+#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1)
+
+#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1)
+
+#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1)
+
+#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1)
+#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2)
+#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7)
+
+#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1)
+#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2)
+#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7)
+
+#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1)
+#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2)
+#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4)
+#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5)
+#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7)
+
+#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1)
+#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2)
+#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4)
+#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5)
+#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7)
+
+#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1)
+#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2)
+#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3)
+#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4)
+#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5)
+#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7)
+
+#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1)
+#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2)
+#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4)
+#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5)
+#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7)
+
+#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1)
+#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2)
+#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7)
+
+#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1)
+#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2)
+#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5)
+#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7)
+
+#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1)
+#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2)
+#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5)
+#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7)
+
+#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1)
+#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2)
+#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5)
+#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7)
+
+#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1)
+#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5)
+#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7)
+
+#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1)
+#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5)
+#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7)
+
+#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1)
+#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5)
+#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7)
+
+#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1)
+#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5)
+#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7)
+
+#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1)
+#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5)
+#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7)
+
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6)
+
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6)
+
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6)
+
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6)
+
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6)
+
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5)
+
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3)
+
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7)
+
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7)
+
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7)
+
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7)
+
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7)
+
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3)
+
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1)
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2)
+
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1)
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2)
+
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1)
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2)
+
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1)
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2)
+
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1)
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2)
+
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1)
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2)
+
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1)
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2)
+
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1)
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2)
+
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1)
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2)
+
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1)
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2)
+
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1)
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2)
+
+#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1)
+
+#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1)
+#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2)
+#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7)
+
+#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1)
+#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2)
+#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7)
+
+#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1)
+#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2)
+#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7)
+
+#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1)
+#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2)
+#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7)
+
+#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1)
+#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2)
+#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7)
+
+#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1)
+#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2)
+#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3)
+#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4)
+#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5)
+
+#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5)
+
+#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1)
+#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2)
+#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3)
+#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4)
+#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5)
+
+#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1)
+#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2)
+#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3)
+#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4)
+#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5)
+
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7)
+
+#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7)
+
+#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4)
+#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5)
+#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6)
+#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7)
+
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7)
+
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7)
+
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7)
+
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7)
+
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7)
+
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7)
+
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7)
+
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7)
+
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7)
+
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1)
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2)
+
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1)
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2)
+
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3)
+
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3)
+
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3)
+
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3)
+
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7)
+
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1)
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7)
+
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1)
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7)
+
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1)
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7)
+
+#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1)
+
+#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1)
+
+#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1)
+
+#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1)
+
+#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1)
+
+#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1)
+
+#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1)
+
+#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1)
+
+#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1)
+
+#endif /* __MT8365_PINFUNC_H */
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
+#define STM32MP_PKG_AI 0x100
+#define STM32MP_PKG_AK 0x400
+#define STM32MP_PKG_AL 0x800
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_MAX77663_H_
+#define _DT_BINDINGS_MAX77663_H_
+
+/*
+ * MAX77663 has 8 GPIO (0 to 7) and 3 KEYS
+ * KEYS are appended after GPIOs
+ */
+
+#define EN0 10
+#define ACOK 9
+#define LID 8
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
+#define _DT_BINDINGS_POWER_MT8365_POWER_H
+
+#define MT8365_POWER_DOMAIN_MM 0
+#define MT8365_POWER_DOMAIN_CONN 1
+#define MT8365_POWER_DOMAIN_MFG 2
+#define MT8365_POWER_DOMAIN_AUDIO 3
+#define MT8365_POWER_DOMAIN_CAM 4
+#define MT8365_POWER_DOMAIN_DSP 5
+#define MT8365_POWER_DOMAIN_VDEC 6
+#define MT8365_POWER_DOMAIN_VENC 7
+#define MT8365_POWER_DOMAIN_APU 8
+
+#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
struct efi_event *event,
void *context),
void *notify_context,
- efi_guid_t *event_group,
+ const efi_guid_t *event_group,
struct efi_event **event);
};
#define EFI_EVENT_GROUP_RESET_SYSTEM \
EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \
0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b)
+#define EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR \
+ EFI_GUID(0xb4a40fe6, 0x9149, 0x4f29, 0x94, 0x47, \
+ 0x49, 0x38, 0x7a, 0x7f, 0xab, 0x87)
/* EFI Configuration Table and GUID definitions */
#define NULL_GUID \
EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \
0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+#define SMBIOS3_TABLE_GUID \
+ EFI_GUID(0xf2fd1544, 0x9794, 0x4a2c, \
+ 0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94)
+
#define EFI_LOAD_FILE_PROTOCOL_GUID \
EFI_GUID(0x56ec3091, 0x954c, 0x11d2, \
0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
#ifndef _EFI_LOADER_H
#define _EFI_LOADER_H 1
-#include <common.h>
#include <blk.h>
#include <event.h>
#include <log.h>
* back to u-boot world
*/
void efi_restore_gd(void);
+/* Call this to unset the current device name */
+void efi_clear_bootdev(void);
/* Call this to set the current device name */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
void *buffer, size_t buffer_size);
/* No loader configured, stub out EFI_ENTRY */
static inline void efi_restore_gd(void) { }
+static inline void efi_clear_bootdev(void) { }
static inline void efi_set_bootdev(const char *dev, const char *devnr,
const char *path, void *buffer,
size_t buffer_size) { }
extern const efi_guid_t efi_guid_event_group_ready_to_boot;
/* event group ResetSystem() invoked (before ExitBootServices) */
extern const efi_guid_t efi_guid_event_group_reset_system;
+/* event group return to efibootmgr */
+extern const efi_guid_t efi_guid_event_group_return_to_efibootmgr;
/* GUID of the device tree table */
extern const efi_guid_t efi_guid_fdt;
extern const efi_guid_t efi_guid_loaded_image;
efi_status_t efi_bootmgr_update_media_device_boot_option(void);
/* Delete selected boot option */
efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index);
+/* Invoke EFI boot manager */
+efi_status_t efi_bootmgr_run(void *fdt);
/* search the boot option index in BootOrder */
bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index);
/* Set up console modes */
void efi_setup_console_size(void);
+/* Set up load options from environment variable */
+efi_status_t efi_env_set_load_options(efi_handle_t handle, const char *env_var,
+ u16 **load_options);
/* Install device tree */
efi_status_t efi_install_fdt(void *fdt);
/* Run loaded UEFI image */
efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size);
+/* Run loaded UEFI image with given fdt */
+efi_status_t efi_binary_run(void *image, size_t size, void *fdt);
/* Initialize variable services */
efi_status_t efi_init_variables(void);
/* Notify ExitBootServices() is called */
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, efi_guid_t *group,
+ void *notify_context, const efi_guid_t *group,
struct efi_event **event);
/* Call this to set a timer */
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time);
-#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
/*
* Entry point for the tests of the EFI API.
* It is called by 'bootefi selftest'
*/
efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle,
struct efi_system_table *systab);
-#endif
efi_status_t EFIAPI efi_get_variable(u16 *variable_name,
const efi_guid_t *vendor, u32 *attributes,
#ifndef _EFI_SELFTEST_H
#define _EFI_SELFTEST_H
-#include <common.h>
#include <efi.h>
#include <efi_api.h>
#include <efi_loader.h>
*/
int env_get_id(void);
+/**
+ * env_inc_id() - Increase the sequence number for the environment
+ *
+ * Increment the value that is used by env_get_id() to inform callers
+ * if the environment has changed since they last checked.
+ */
+void env_inc_id(void);
+
/**
* env_init() - Set up the pre-relocation environment
*
bootcmd_ti_mmc=
run findfdt; run init_${boot};
#if CONFIG_CMD_REMOTEPROC
- run main_cpsw0_qsgmii_phyinit; run boot_rprocs;
+ if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
+ then run main_cpsw0_qsgmii_phyinit;
+ fi
+ run boot_rprocs;
#endif
if test ${boot_fit} -eq 1;
then run get_fit_${boot}; run get_fit_overlaystring; run run_fit;
#ifndef _ENV_INTERNAL_H_
#define _ENV_INTERNAL_H_
-#include <linux/kconfig.h>
/**************************************************************************
*
extern struct hsearch_data env_htab;
+/**
+ * env_do_env_set() - Perform the actual setting of an environment variable
+ *
+ * Due to the number of places we may need to set an environmental variable
+ * from we have an exposed internal function that performs the real work and
+ * then call this from both the command line function as well as other
+ * locations.
+ *
+ * Return: 0 on success or 1 on failure
+ */
+int env_do_env_set(int flag, int argc, char *const argv[], int env_flag);
+
/**
* env_ext4_get_intf() - Provide the interface for env in EXT4
*
struct ext_filesystem *get_fs(void);
int ext4fs_open(const char *filename, loff_t *len);
int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
-int ext4fs_mount(unsigned part_length);
+int ext4fs_mount(void);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
/* Maximum number of entry for long file name according to spec */
#define MAX_LFN_SLOT 20
-/* Filesystem identifiers */
-#define FAT12_SIGN "FAT12 "
-#define FAT16_SIGN "FAT16 "
-#define FAT32_SIGN "FAT32 "
-#define SIGNLEN 8
-
/* File attributes */
#define ATTR_RO 1
#define ATTR_HIDDEN 2
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
-#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \
- !defined(USE_HOSTCC)
+#if !defined(USE_HOSTCC)
#include <asm/u-boot.h>
#include <linux/libfdt.h>
/**
* Add initrd information to the FDT before booting the OS.
*
- * @param fdt FDT address in memory
+ * Adds linux,initrd-start and linux,initrd-end properties to the /chosen node,
+ * creating it if necessary.
+ *
+ * A memory reservation for the ramdisk is added to the FDT, or an existing one
+ * (with matching @initrd_start) updated.
+ *
+ * If @initrd_start == @initrd_end this function does nothing and returns 0.
+ *
+ * @fdt: Pointer to FDT in memory
+ * @initrd_start: Start of ramdisk
+ * @initrd_end: End of ramdisk
* Return: 0 if ok, or -FDT_ERR_... on error
*/
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end);
void set_working_fdt_addr(ulong addr);
/**
- * shrink down the given blob to minimum size + some extrasize if required
+ * fdt_shrink_to_minimum() - shrink FDT while allowing for some margin
+ *
+ * Shrink down the given blob to 'minimum' size + some extrasize.
+ *
+ * The new size is enough to hold the existing contents plus @extrasize bytes,
+ * plus 5 memory reservations. Also, the end of the FDT is aligned to a 4KB
+ * boundary, so it might end up up to 4KB larger than needed.
+ *
+ * If there is an existing memory reservation for @blob in the FDT, it is
+ * updated for the new size.
*
* @param blob FDT blob to update
* @param extrasize additional bytes needed
* Return: 0 if ok, or -FDT_ERR_... on error
*/
int fdt_shrink_to_minimum(void *blob, uint extrasize);
+
int fdt_increase_size(void *fdt, int add_len);
int fdt_delete_disabled_nodes(void *blob);
*/
int fdt_get_cells_len(const void *blob, char *nr_cells_name);
-#endif /* ifdef CONFIG_OF_LIBFDT */
+#endif /* !USE_HOSTCC */
#ifdef USE_HOSTCC
int fdtdec_get_int(const void *blob, int node, const char *prop_name,
* U-Boot is packaged as an ELF file, e.g. for debugging purposes
* @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should
* be used for debugging/development only
- * @FDTSRC_NONE: No devicetree at all
+ * @FDTSRC_BLOBLIST: Provided by a bloblist from an earlier phase
*/
enum fdt_source_t {
FDTSRC_SEPARATE,
FDTSRC_BOARD,
FDTSRC_EMBED,
FDTSRC_ENV,
+ FDTSRC_BLOBLIST,
};
/*
*
* The existing devicetree is available at gd->fdt_blob
*
- * @err internal error code if we fail to setup a DTB
+ * @err: 0 on success, -EEXIST if the devicetree is already correct, or other
+ * internal error code if we fail to setup a DTB
* @returns new devicetree blob pointer
*/
void *board_fdt_blob_setup(int *err);
#ifndef __FM_ETH_H__
#define __FM_ETH_H__
-#include <common.h>
#include <phy.h>
#include <asm/types.h>
#ifndef _FS_H
#define _FS_H
-#include <common.h>
#include <rtc.h>
struct cmd_tbl;
#ifndef __FSL_MC_H__
#define __FSL_MC_H__
-#include <common.h>
#include <linux/bitops.h>
+struct bd_info;
+
#define MC_CCSR_BASE_ADDR \
((struct mc_ccsr_registers __iomem *)0x8340000)
#ifndef _FSL_ERRATA_H
#define _FSL_ERRATA_H
-#include <common.h>
#if defined(CONFIG_PPC)
#include <asm/processor.h>
#elif defined(CONFIG_ARCH_LS1021A)
#ifdef CONFIG_FSL_IFC
#include <config.h>
-#include <common.h>
#include <part.h>
#ifdef CONFIG_ARM
#include <asm/arch/soc.h>
#ifndef __QE_H__
#define __QE_H__
-#include "common.h"
#ifdef CONFIG_U_QE
#include <linux/immap_qe.h>
#endif
#ifndef __FSL_SEC_H
#define __FSL_SEC_H
-#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_LE
#ifndef __FSL_SEC_MON_H
#define __FSL_SEC_MON_H
-#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_MON_LE
#ifndef _FSL_SFP_SNVS_
#define _FSL_SFP_SNVS_
-#include <common.h>
#include <config.h>
#include <asm/io.h>
#ifndef __GETOPT_H
#define __GETOPT_H
+#include <stdbool.h>
+
/**
* struct getopt_state - Saved state across getopt() calls
*/
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
-ulong genimg_get_kernel_addr_fit(char * const img_addr,
- const char **fit_uname_config,
- const char **fit_uname_kernel);
+/**
+ * genimg_get_kernel_addr_fit() - Parse FIT specifier
+ *
+ * Get the real kernel start address from a string which is normally the first
+ * argv of bootm/bootz
+ *
+ * These cases are dealt with, based on the value of @img_addr:
+ * NULL: Returns image_load_addr, does not set last two args
+ * "<addr>": Returns address
+ *
+ * For FIT:
+ * "[<addr>]#<conf>": Returns address (or image_load_addr),
+ * sets fit_uname_config to config name
+ * "[<addr>]:<subimage>": Returns address (or image_load_addr) and sets
+ * fit_uname_kernel to the subimage name
+ *
+ * @img_addr: a string might contain real image address (or NULL)
+ * @fit_uname_config: Returns configuration unit name
+ * @fit_uname_kernel: Returns subimage name
+ *
+ * Returns: kernel start address
+ */
+ulong genimg_get_kernel_addr_fit(const char *const img_addr,
+ const char **fit_uname_config,
+ const char **fit_uname_kernel);
+
ulong genimg_get_kernel_addr(char * const img_addr);
int genimg_get_format(const void *img_addr);
int genimg_has_config(struct bootm_headers *images);
-int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len);
-int boot_get_ramdisk(int argc, char *const argv[], struct bootm_headers *images,
- uint8_t arch, ulong *rd_start, ulong *rd_end);
+/**
+ * boot_get_fpga() - Locate the FPGA image
+ *
+ * @images: Information about images being loaded
+ * Return 0 if OK, non-zero on failure
+ */
+int boot_get_fpga(struct bootm_headers *images);
+
+/**
+ * boot_get_ramdisk() - Locate the ramdisk
+ *
+ * @select: address or name of ramdisk to use, or NULL for default
+ * @images: pointer to the bootm images structure
+ * @arch: expected ramdisk architecture
+ * @rd_start: pointer to a ulong variable, will hold ramdisk start address
+ * @rd_end: pointer to a ulong variable, will hold ramdisk end
+ *
+ * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if ramdisk image was found and valid, or skiped
+ * rd_start and rd_end are set to ramdisk start/end addresses if
+ * ramdisk image is found and valid
+ *
+ * 1, if ramdisk image is found but corrupted, or invalid
+ * rd_start and rd_end are set to 0 if no ramdisk exists
+ */
+int boot_get_ramdisk(char const *select, struct bootm_headers *images,
+ uint arch, ulong *rd_start, ulong *rd_end);
/**
- * boot_get_loadable - routine to load a list of binaries to memory
- * @argc: Ignored Argument
- * @argv: Ignored Argument
+ * boot_get_loadable() - load a list of binaries to memory
+ *
* @images: pointer to the bootm images structure
- * @arch: expected architecture for the image
- * @ld_start: Ignored Argument
- * @ld_len: Ignored Argument
*
- * boot_get_loadable() will take the given FIT configuration, and look
- * for a field named "loadables". Loadables, is a list of elements in
- * the FIT given as strings. exe:
+ * Takes the given FIT configuration, then looks for a field named
+ * "loadables", a list of elements in the FIT given as strings, e.g.:
* loadables = "linux_kernel", "fdt-2";
- * this function will attempt to parse each string, and load the
- * corresponding element from the FIT into memory. Once placed,
- * no aditional actions are taken.
*
- * @return:
+ * Each string is parsed, loading the corresponding element from the FIT into
+ * memory. Once placed, no additional actions are taken.
+ *
+ * Return:
* 0, if only valid images or no images are found
* error code, if an error occurs during fit_image_load
*/
-int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images,
- uint8_t arch, const ulong *ld_start, ulong *const ld_len);
+int boot_get_loadable(struct bootm_headers *images);
int boot_get_setup_fit(struct bootm_headers *images, uint8_t arch,
ulong *setup_start, ulong *setup_len);
* @param load_op Decribes what to do with the load address
* @param datap Returns address of loaded image
* @param lenp Returns length of loaded image
- * Return: node offset of image, or -ve error code on error
+ * Return: node offset of image, or -ve error code on error:
+ * -ENOEXEC - unsupported architecture
+ * -ENOENT - could not find image / subimage
+ * -EACCES - hash, signature or decryptions failure
+ * -EBADF - invalid OS or image type, or cannot get image load-address
+ * -EXDEV - memory overwritten / overlap
+ * -NOEXEC - image decompression error, or invalid FDT
*/
int fit_image_load(struct bootm_headers *images, ulong addr,
const char **fit_unamep, const char **fit_uname_configp,
int fit_get_node_from_config(struct bootm_headers *images,
const char *prop_name, ulong addr);
-int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
- struct bootm_headers *images,
- char **of_flat_tree, ulong *of_size);
+/**
+ * boot_get_fdt() - locate FDT devicetree to use for booting
+ *
+ * @buf: Pointer to image
+ * @select: FDT to select (this is normally argv[2] of the bootm command)
+ * @arch: architecture (IH_ARCH_...)
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Currently supported are the following FDT sources:
+ * - multicomponent kernel/ramdisk/FDT image,
+ * - commandline provided address of decicated FDT image.
+ *
+ * Return:
+ * 0, if fdt image was found and valid, or skipped
+ * of_flat_tree and of_size are set to fdt start address and length if
+ * fdt image is found and valid
+ *
+ * 1, if fdt image is found but corrupted
+ * of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(void *buf, const char *select, uint arch,
+ struct bootm_headers *images, char **of_flat_tree,
+ ulong *of_size);
+
void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
* @load: Destination load address in U-Boot memory
* @image_start Image start address (where we are decompressing from)
* @type: OS type (IH_OS_...)
- * @load_bug: Place to decompress to
+ * @load_buf: Place to decompress to
* @image_buf: Address to decompress from
* @image_len: Number of bytes in @image_buf to decompress
* @unc_len: Available space for decompression
*
* @images: Images information
* @blob: FDT to update
- * @of_size: Size of the FDT
* @lmb: Points to logical memory block structure
* Return: 0 if ok, <0 on failure
*/
int image_setup_libfdt(struct bootm_headers *images, void *blob,
- int of_size, struct lmb *lmb);
+ struct lmb *lmb);
/**
* Set up the FDT to use for booting a kernel
/* common/board_info.c */
int checkboard(void);
+
+/**
+ * show_board_info() - Show board information
+ *
+ * Check sysinfo for board information. Failing that if the root node of the DTB
+ * has a "model" property, show it.
+ *
+ * Then call checkboard().
+ *
+ * Return 0 if OK, -ve on error
+ */
int show_board_info(void);
/**
struct udevice;
struct iommu_ops {
+ /**
+ * init() - Connect a device to it's IOMMU, called before probe()
+ * The iommu device can be fetched through dev->iommu
+ *
+ * @iommu_dev: IOMMU device
+ * @dev: Device to connect
+ * @return 0 if OK, -errno on error
+ */
+ int (*connect)(struct udevice *dev);
/**
* map() - map DMA memory
*
#ifndef __IOTRACE_H
#define __IOTRACE_H
-//#include <common.h>
#include <linux/types.h>
/* Support up to the machine word length for now */
#ifdef CONFIG_UNIT_TEST
TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
struct k210_pll_config *best);
-#ifndef nop
-#define nop()
-#endif
#endif
#endif /* K210_PLL_H */
#ifndef _KEY_MATRIX_H
#define _KEY_MATRIX_H
-#include <common.h>
/* Information about a matrix keyboard */
struct key_matrix {
*/
int led_set_period(struct udevice *dev, int period_ms);
+/**
+ * led_bind_generic() - bind children of parent to given driver
+ *
+ * @parent: Top-level LED device
+ * @driver_name: Driver for handling individual child nodes
+ */
+int led_bind_generic(struct udevice *parent, const char *driver_name);
+
#endif
#ifndef __LIBATA_H__
#define __LIBATA_H__
-#include <common.h>
enum {
/* various global constants */
#ifndef __IMMAP_QE_H__
#define __IMMAP_QE_H__
+#include <config.h>
+
#ifdef CONFIG_MPC83xx
#if defined(CONFIG_ARCH_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#ifndef __LINUX_MII_H__
#define __LINUX_MII_H__
+#include <linux/types.h>
+
/* Generic MII registers. */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#ifdef __UBOOT__
/* drivers/mtd/mtdcore.h */
+#if CONFIG_IS_ENABLED(MTD)
int add_mtd_device(struct mtd_info *mtd);
int del_mtd_device(struct mtd_info *mtd);
+#else
+static inline int add_mtd_device(struct mtd_info *mtd)
+{
+ return -ENOSYS;
+}
+
+static inline int del_mtd_device(struct mtd_info *mtd)
+{
+ return -ENOSYS;
+}
+#endif
#ifdef CONFIG_MTD_PARTITIONS
int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#else
-#include <common.h>
#include <spi.h>
#include <spi-mem.h>
#include <linux/mtd/nand.h>
extern const struct spinand_manufacturer paragon_spinand_manufacturer;
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
+extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
/**
* struct spinand_op_variants - SPI NAND operation variants
#define _REENT_ONLY
+#define MSEC_PER_SEC 1000L
+#define USEC_PER_MSEC 1000L
+#define NSEC_PER_USEC 1000L
+#define NSEC_PER_MSEC 1000000L
+#define USEC_PER_SEC 1000000L
+#define NSEC_PER_SEC 1000000000L
+#define PSEC_PER_SEC 1000000000000LL
+#define FSEC_PER_SEC 1000000000000000LL
+
#define SECSPERMIN 60L
#define MINSPERHOUR 60L
#define HOURSPERDAY 24L
* the composite model the host can use both functions at the same time.
*/
-#include <common.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/bitmap.h>
# ifdef CONFIG_ARCH_MAP_SYSMEM
#include <asm/io.h>
# else
+#include <linux/types.h>
+
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
{
return (void *)(uintptr_t)paddr;
{
return (phys_addr_t)(uintptr_t)ptr;
}
+
+/**
+ * nomap_sysmem() - pass through an address unchanged
+ *
+ * This is used to indicate an address which should NOT be mapped, e.g. in
+ * SMBIOS tables. Using this function instead of a case shows that the sandbox
+ * conversion has been done
+ */
+static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t nomap_to_sysmem(const void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
+
# endif
#endif /* __MAPMEM_H */
* is used to align DMA buffers.
*/
#ifndef __ASSEMBLY__
+#include <linux/kernel.h>
#include <asm/cache.h>
#include <malloc.h>
#ifndef _miiphy_h_
#define _miiphy_h_
-#include <common.h>
#include <linux/mii.h>
#include <linux/list.h>
#include <net.h>
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
-#include <config.h>
-#include <asm/fsl_lbc.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
/* map to cfi_flash_num_flash_banks only when supported */
#if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \
- (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT))
+ (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD))
#define CFI_FLASH_BANKS (cfi_flash_num_flash_banks)
/* board code can update this variable before CFI detection */
extern int cfi_flash_num_flash_banks;
#ifndef __MV886352_H
#define __MV886352_H
-#include <common.h>
/* PHY registers */
#define PHY(itf) (itf)
#include <config.h>
extern void nand_init(void);
+void nand_reinit(void);
unsigned long nand_size(void);
+unsigned int nand_page_size(void);
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
void board_nand_init(void);
int nand_register(int devnum, struct mtd_info *mtd);
+void nand_unregister(struct mtd_info *mtd);
#else
struct nand_chip;
static inline void eth_set_enable_bootdevs(bool enable) {}
#endif
+/**
+ * wget_with_dns() - runs dns host IP address resulution before wget
+ *
+ * @dst_addr: destination address to download the file
+ * @uri: uri string of target file of wget
+ * Return: downloaded file size, negative if failed
+ */
+int wget_with_dns(ulong dst_addr, char *uri);
+
+/**
+ * wget_validate_uri() - varidate the uri
+ *
+ * @uri: uri string of target file of wget
+ * Return: true if uri is valid, false if uri is invalid
+ */
+bool wget_validate_uri(char *uri);
+
#endif /* __NET_H__ */
* Copyright (C) 2019, IBM Corporation.
*/
-#include <common.h>
#include <phy.h>
bool ncsi_active(void);
};
#define DEBUG_WGET 0 /* Set to 1 for debug messages */
-#define SERVER_PORT 80
#define WGET_RETRY_COUNT 30
#define WGET_TIMEOUT 2000UL
#include <net.h>
#include <linux/ctype.h>
+#include <linux/errno.h>
/* struct in6_addr - 128 bits long IPv6 address */
struct in6_addr {
*/
int os_persistent_file(char *buf, int maxsize, const char *fname);
+/**
+ * os_mktemp() - Create a temporary file
+ * @fname: The template to use for the file name. This must end with 6 Xs. It
+ * will be modified to the opened filename on success.
+ * @size: The size of the file
+ *
+ * Create a temporary file using @fname as a template, unlink it, and truncate
+ * it to @size.
+ *
+ * Return: A file descriptor, or negative errno on error
+ */
+int os_mktemp(char *fname, off_t size);
+
/**
* os_exit() - access to the OS exit() system call
*
#ifndef PALMAS_H
#define PALMAS_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses, TW6035/37 */
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
+/* Per https://www.qemu.org/docs/master/specs/pci-ids.html */
+#define PCI_VENDOR_ID_REDHAT 0x1b36
+#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
+#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
+#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
+#define PCI_DEVICE_ID_REDHAT_UFS 0x0013
+
#define PCI_VENDOR_ID_INIT 0x1101
#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */
#define _POST_H
#ifndef __ASSEMBLY__
-#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_POST)
#define MAX77663_LDO_DRIVER "max77663_ldo"
#define MAX77663_SD_DRIVER "max77663_sd"
#define MAX77663_RST_DRIVER "max77663_rst"
+#define MAX77663_GPIO_DRIVER "max77663_gpio"
/* Step-Down (SD) Regulator calculations */
#define SD_STATUS_MASK 0x30
#define PALMAS_LDO_DRIVER "palmas_ldo"
#define PALMAS_SMPS_DRIVER "palmas_smps"
#define PALMAS_RST_DRIVER "palmas_rst"
+#define PALMAS_GPIO_DRIVER "palmas_gpio"
#define PALMAS_SMPS_VOLT_MASK 0x7F
#define PALMAS_SMPS_RANGE_MASK 0x80
#define DEV_OFF 0x00
#define PALMAS_INT3_MASK 0x1B
#define MASK_VBUS BIT(7)
+
+/* second chip */
+#define PALMAS_GPIO_DATA_IN 0x80
+#define PALMAS_GPIO_DATA_DIR 0x81
+#define PALMAS_GPIO_DATA_OUT 0x82
+#define PALMAS_GPIO_DEBOUNCE_EN 0x83
+#define PALMAS_GPIO_CLEAR_DATA_OUT 0x84
+#define PALMAS_GPIO_SET_DATA_OUT 0x85
+#define PALMAS_PU_PD_GPIO_CTRL1 0x86
+#define PALMAS_PU_PD_GPIO_CTRL2 0x87
+#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88
#include <bcd.h>
#include <rtc_def.h>
#include <linux/errno.h>
+#include <linux/types.h>
typedef int64_t time64_t;
struct udevice;
#define __SATA_H__
#include <part.h>
-#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
-int init_sata(int dev);
-int reset_sata(int dev);
-int scan_sata(int dev);
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
-
-int sata_initialize(void);
-int __sata_initialize(void);
-int sata_stop(void);
-int __sata_stop(void);
-int sata_port_status(int dev, int port);
-
-extern struct blk_desc sata_dev_desc[];
-#endif
-
int sata_probe(int devnum);
int sata_remove(int devnum);
#include <bouncebuf.h>
#include <linux/dma-direction.h>
-/* Fix this to the maximum */
-#define SCSI_MAX_DEVICE \
- (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-
struct udevice;
/**
*/
int scsi_scan_dev(struct udevice *dev, bool verbose);
-#ifndef CONFIG_DM_SCSI
-void scsi_low_level_init(int busdevfunc);
-void scsi_init(void);
-#endif
-
#define SCSI_IDENTIFY 0xC0 /* not used */
/* Hardware errors */
/* SMBIOS spec version implemented */
#define SMBIOS_MAJOR_VER 3
-#define SMBIOS_MINOR_VER 0
+#define SMBIOS_MINOR_VER 7
enum {
SMBIOS_STR_MAX = 64, /* Maximum length allowed for a string */
u8 bcd_rev;
};
+/**
+ * struct smbios3_entry - SMBIOS 3.0 (64-bit) Entry Point structure
+ */
+struct __packed smbios3_entry {
+ /** @anchor: anchor string */
+ u8 anchor[5];
+ /** @checksum: checksum of the entry point structure */
+ u8 checksum;
+ /** @length: length of the entry point structure */
+ u8 length;
+ /** @major_ver: major version of the SMBIOS specification */
+ u8 major_ver;
+ /** @minor_ver: minor version of the SMBIOS specification */
+ u8 minor_ver;
+ /** @docrev: revision of the SMBIOS specification */
+ u8 doc_rev;
+ /** @entry_point_rev: revision of the entry point structure */
+ u8 entry_point_rev;
+ /** @reserved: reserved */
+ u8 reserved;
+ /** maximum size of SMBIOS table */
+ u32 max_struct_size;
+ /** @struct_table_address: 64-bit physical starting address */
+ u64 struct_table_address;
+};
+
+/* These two structures should use the same amount of 16-byte-aligned space */
+static_assert(ALIGN(16, sizeof(struct smbios_entry)) ==
+ ALIGN(16, sizeof(struct smbios3_entry)));
+
/* BIOS characteristics */
#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11)
*
* This writes SMBIOS table at a given address.
*
- * @addr: start address to write SMBIOS table. If this is not
- * 16-byte-aligned then it will be aligned before the table is
- * written.
+ * @addr: start address to write SMBIOS table, 16-byte-alignment
+ * recommended. Note that while the SMBIOS tables themself have no alignment
+ * requirement, some systems may requires alignment. For example x86 systems
+ * which put tables at f0000 require 16-byte alignment
+ *
* Return: end address of SMBIOS table (and start address for next entry)
* or NULL in case of an error
- *
*/
ulong write_smbios_table(ulong addr);
#ifndef _SPI_H_
#define _SPI_H_
-#include <common.h>
#include <linux/bitops.h>
/* SPI mode flags */
/**
* Information required to load data from a device
*
- * @dev: Pointer to the device, e.g. struct mmc *
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
- * @filename: Name of the fit image file.
* @read: Function to call to read from the device
*/
struct spl_load_info {
- void *dev;
void *priv;
- int bl_len;
- const char *filename;
/**
* read() - Read from device
*
* @load: Information about the load state
- * @sector: Sector number to read from (each @load->bl_len bytes)
- * @count: Number of sectors to read
+ * @offset: Offset to read from in bytes. This must be a multiple of
+ * @load->bl_len.
+ * @count: Number of bytes to read. This must be a multiple of
+ * @load->bl_len.
* @buf: Buffer to read into
- * @return number of sectors read, 0 on error
+ * @return number of bytes read, 0 on error
*/
ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
void *buf);
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
+ int bl_len;
+};
+
+static inline int spl_get_bl_len(struct spl_load_info *info)
+{
+ return info->bl_len;
+}
+
+static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+{
+ info->bl_len = bl_len;
+}
+#else
};
+static inline int spl_get_bl_len(struct spl_load_info *info)
+{
+ return 1;
+}
+
+static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+{
+ if (bl_len != 1)
+ panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+}
+#endif
+
/*
* We need to know the position of U-Boot in memory so we can jump to it. We
* allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
- * @sector: Sector number where FIT image is located in the device
+ * @offset: Offset where FIT image is located in the device. Must be aligned
+ * to the device's bl_len.
* @fdt: Pointer to the copied FIT header.
*
* Reads the FIT image @sector in the device. Loads u-boot image to
* Returns 0 on success.
*/
int spl_load_simple_fit(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector, void *fdt);
+ struct spl_load_info *info, ulong offset, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
#define SPL_FIT_FOUND 2
+/**
+ * spl_load_legacy_lzma() - Load an LZMA-compressed legacy image
+ * @spl_image: Image description (already set up)
+ * @load: Structure containing the information required to load data.
+ * @offset: Pointer to image
+ *
+ * Load/decompress an LZMA-compressed legacy image from the device.
+ *
+ * Return: 0 on success, or a negative error on failure
+ */
+int spl_load_legacy_lzma(struct spl_image_info *spl_image,
+ struct spl_load_info *load, ulong offset);
+
/**
* spl_load_legacy_img() - Loads a legacy image from a device.
* @spl_image: Image description to set up
* spl_load_imx_container() - Loads a imx container image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
- * @sector: Sector number where container image is located in the device
+ * @sector: Offset where container image is located in the device. Must be
+ * aligned to the device block size.
*
* Reads the container image @sector in the device. Loads u-boot image to
* specified load address.
*/
int spl_load_imx_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector);
+ struct spl_load_info *info, ulong offset);
/* SPL common functions */
void preloader_console_init(void);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef _SPL_LOAD_H_
+#define _SPL_LOAD_H_
+
+#include <image.h>
+#include <imx_container.h>
+#include <mapmem.h>
+#include <spl.h>
+
+static inline int _spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev,
+ struct spl_load_info *info, size_t size,
+ size_t offset)
+{
+ struct legacy_img_hdr *header =
+ spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ ulong base_offset, image_offset, overhead;
+ int read, ret;
+
+ read = info->read(info, offset, ALIGN(sizeof(*header),
+ spl_get_bl_len(info)), header);
+ if (read < sizeof(*header))
+ return -EIO;
+
+ if (image_get_magic(header) == FDT_MAGIC) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+ void *buf;
+
+ /*
+ * In order to support verifying images in the FIT, we
+ * need to load the whole FIT into memory. Try and
+ * guess how much we need to load by using the total
+ * size. This will fail for FITs with external data,
+ * but there's not much we can do about that.
+ */
+ if (!size)
+ size = round_up(fdt_totalsize(header), 4);
+ buf = map_sysmem(CONFIG_SYS_LOAD_ADDR, size);
+ read = info->read(info, offset,
+ ALIGN(size, spl_get_bl_len(info)),
+ buf);
+ if (read < size)
+ return -EIO;
+
+ return spl_parse_image_header(spl_image, bootdev, buf);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
+ return spl_load_simple_fit(spl_image, info, offset,
+ header);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header))
+ return spl_load_imx_container(spl_image, info, offset);
+
+ if (IS_ENABLED(CONFIG_SPL_LZMA) &&
+ image_get_magic(header) == IH_MAGIC &&
+ image_get_comp(header) == IH_COMP_LZMA) {
+ spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
+ ret = spl_parse_image_header(spl_image, bootdev, header);
+ if (ret)
+ return ret;
+
+ return spl_load_legacy_lzma(spl_image, info, offset);
+ }
+
+ ret = spl_parse_image_header(spl_image, bootdev, header);
+ if (ret)
+ return ret;
+
+ base_offset = spl_image->offset;
+ /* Only NOR sets this flag. */
+ if (IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) &&
+ spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
+ base_offset += sizeof(*header);
+ image_offset = ALIGN_DOWN(base_offset, spl_get_bl_len(info));
+ overhead = base_offset - image_offset;
+ size = ALIGN(spl_image->size + overhead, spl_get_bl_len(info));
+
+ read = info->read(info, offset + image_offset, size,
+ map_sysmem(spl_image->load_addr - overhead, size));
+ return read < spl_image->size ? -EIO : 0;
+}
+
+/*
+ * Although spl_load results in size reduction for callers, this is generally
+ * not enough to counteract the bloat if there is only one caller. The core
+ * problem is that the compiler can't optimize across translation units. The
+ * general solution to this is CONFIG_LTO, but that is not available on all
+ * architectures. Perform a pseudo-LTO just for this function by declaring it
+ * inline if there is one caller, and extern otherwise.
+ */
+#define SPL_LOAD_USERS \
+ IS_ENABLED(CONFIG_SPL_BLK_FS) + \
+ IS_ENABLED(CONFIG_SPL_FS_EXT4) + \
+ IS_ENABLED(CONFIG_SPL_FS_FAT) + \
+ IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \
+ (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \
+ IS_ENABLED(CONFIG_SPL_NET) + \
+ IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \
+ IS_ENABLED(CONFIG_SPL_SEMIHOSTING) + \
+ IS_ENABLED(CONFIG_SPL_SPI_LOAD) + \
+ 0
+
+#if SPL_LOAD_USERS > 1
+/**
+ * spl_load() - Parse a header and load the image
+ * @spl_image: Image data which will be filled in by this function
+ * @bootdev: The device to load from
+ * @info: Describes how to load additional information from @bootdev. At the
+ * minimum, read() and bl_len must be populated.
+ * @size: The size of the image, in bytes, if it is known in advance. Some boot
+ * devices (such as filesystems) know how big an image is before parsing
+ * the header. If 0, then the size will be determined from the header.
+ * @offset: The offset from the start of @bootdev, in bytes. This should have
+ * the offset @header was loaded from. It will be added to any offsets
+ * passed to @info->read().
+ *
+ * This function determines the image type (FIT, legacy, i.MX, raw, etc), calls
+ * the appropriate parsing function, determines the load address, and the loads
+ * the image from storage. It is designed to replace ad-hoc image loading which
+ * may not support all image types (especially when config options are
+ * involved).
+ *
+ * Return: 0 on success, or a negative error on failure
+ */
+int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev, struct spl_load_info *info,
+ size_t size, size_t offset);
+#else
+static inline int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev,
+ struct spl_load_info *info, size_t size,
+ size_t offset)
+{
+ return _spl_load(spl_image, bootdev, info, size, offset);
+}
+#endif
+
+#endif /* _SPL_LOAD_H_ */
/* For show_board_info() */
SYSINFO_ID_BOARD_MODEL,
+ SYSINFO_ID_BOARD_MANUFACTURER,
+ SYSINFO_ID_PRIOR_STAGE_VERSION,
+ SYSINFO_ID_PRIOR_STAGE_DATE,
/* First value available for downstream/board used */
SYSINFO_ID_USER = 0x1000,
#ifndef __SYSTEM_CONSTANTS_H__
#define __SYSTEM_CONSTANTS_H__
+#include <config.h>
+
/*
* The most common case for our initial stack pointer address is to
* say that we have defined a static intiial ram address location and
#define SPL_PAYLOAD_ARGS_ADDR 0
#endif
+/* Number of pages per block */
+#define SYS_NAND_BLOCK_PAGES \
+ (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
+
#endif
#ifndef __include_tegra_kbc_h__
#define __include_tegra_kbc_h__
-#include <common.h>
#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __TEST_CMD_H__
+#define __TEST_CMD_H__
+
+#include <test/test.h>
+
+/* Declare a new command test */
+#define CMD_TEST(_name, _flags) UNIT_TEST(_name, _flags, cmd_test)
+
+#endif /* __TEST_CMD_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#ifndef __TEST_HUSH_H__
+#define __TEST_HUSH_H__
+
+#include <test/test.h>
+
+/* Declare a new environment test */
+#define HUSH_TEST(_name, _flags) UNIT_TEST(_name, _flags, hush_test)
+
+#endif /* __TEST_HUSH_H__ */
int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1,
struct spl_image_info *info2);
+/* Some compressed data and it size */
+extern const char lzma_compressed[];
+extern const size_t lzma_compressed_size;
+
/**
* typedef write_image_t - Callback for writing an image
* @uts: Current unit test state
char *const argv[]);
int do_ut_bloblist(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
+int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_common(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
int do_ut_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_font(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_ut_hush(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
*/
int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...);
+/**
+ * ut_check_skip_to_linen() - skip output until a partial line is found
+ *
+ * This creates a string and then checks it against the following lines of
+ * console output obtained with console_record_readline() until it is found.
+ * Only the characters up to the length of the string are checked, so the line
+ * may extend further
+ *
+ * After the function returns, uts->expect_str holds the expected string and
+ * uts->actual_str holds the actual string read from the console.
+ *
+ * @uts: Test state
+ * @fmt: printf() format string to look for, followed by args
+ * Return: 0 if OK, -ENOENT if not found, other value on error
+ */
+int ut_check_skip_to_linen(struct unit_test_state *uts, const char *fmt, ...);
+
/**
* ut_check_console_end() - Check there is no more console output
*
__ret; \
})
+/* Assert that a following console output line matches */
+#define ut_assert_skip_to_linen(fmt, args...) ({ \
+ int __ret = 0; \
+ \
+ if (ut_check_skip_to_linen(uts, fmt, ##args)) { \
+ ut_failf(uts, __FILE__, __LINE__, __func__, \
+ "console", "\nExpected '%s',\n got to '%s'", \
+ uts->expect_str, uts->actual_str); \
+ return CMD_RET_FAILURE; \
+ } \
+ __ret; \
+})
+
/* Assert that there is no more console output */
#define ut_assert_console_end() ({ \
int __ret = 0; \
#ifndef TWL4030_H
#define TWL4030_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
#ifndef TWL6030_H
#define TWL6030_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
#include <errno.h>
#include <image.h>
-#include <linux/kconfig.h>
/**
* crypto_algo API impementation for ECDSA;
#ifndef __UBOOT_UBI_H
#define __UBOOT_UBI_H
-#include <common.h>
#include <compiler.h>
#include <linux/compat.h>
#include <malloc.h>
#ifndef __USBDCORE_H__
#define __USBDCORE_H__
-#include <common.h>
#include "usbdescriptors.h"
config LIB_UUID
bool
+config RANDOM_UUID
+ bool "GPT Random UUID generation"
+ select LIB_UUID
+ help
+ Enable the generation of partitions with random UUIDs if none
+ are provided.
+
config SPL_LIB_UUID
depends on SPL
bool
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && (ARM64 || RISCV)
+ depends on SEMIHOSTING
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+ depends on SPL_SEMIHOSTING
select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
default y
help
Check http://www.dmtf.org/standards/smbios for details.
- See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
+ See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in
the devicetree.
endmenu
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <malloc.h>
#include <mapmem.h>
#include <string.h>
obj-y += acpi_writer.o
# With QEMU the ACPI tables come from there, not from U-Boot
-ifndef CONFIG_QEMU
+ifndef CONFIG_QFW_ACPI
obj-y += base.o
obj-y += csrt.o
obj-y += mcfg.o
* Copyright 2023 Google LLC
*/
-#include <common.h>
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/global_data.h>
{
struct acpi_rsdp *rsdp;
struct acpi_rsdt *rsdt;
+ struct acpi_xsdt *xsdt;
int len, i, count;
rsdp = map_sysmem(gd_acpi_start(), 0);
if (!rsdp)
return NULL;
- rsdt = map_sysmem(rsdp->rsdt_address, 0);
- len = rsdt->header.length - sizeof(rsdt->header);
- count = len / sizeof(u32);
+ if (rsdp->xsdt_address) {
+ xsdt = nomap_sysmem(rsdp->xsdt_address, 0);
+ len = xsdt->header.length - sizeof(xsdt->header);
+ count = len / sizeof(u64);
+ } else {
+ if (!rsdp->rsdt_address)
+ return NULL;
+ rsdt = nomap_sysmem(rsdp->rsdt_address, 0);
+ len = rsdt->header.length - sizeof(rsdt->header);
+ count = len / sizeof(u32);
+ }
for (i = 0; i < count; i++) {
struct acpi_table_header *hdr;
- hdr = map_sysmem(rsdt->entry[i], 0);
+ if (rsdp->xsdt_address)
+ hdr = nomap_sysmem(xsdt->entry[i], 0);
+ else
+ hdr = nomap_sysmem(rsdt->entry[i], 0);
if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN))
return hdr;
if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) {
struct acpi_fadt *fadt = (struct acpi_fadt *)hdr;
- if (!memcmp(sig, "DSDT", ACPI_NAME_LEN) && fadt->dsdt)
- return map_sysmem(fadt->dsdt, 0);
- if (!memcmp(sig, "FACS", ACPI_NAME_LEN) &&
- fadt->firmware_ctrl)
- return map_sysmem(fadt->firmware_ctrl, 0);
+ if (!memcmp(sig, "DSDT", ACPI_NAME_LEN)) {
+ void *dsdt;
+
+ if (fadt->header.revision >= 3 && fadt->x_dsdt)
+ dsdt = nomap_sysmem(fadt->x_dsdt, 0);
+ else if (fadt->dsdt)
+ dsdt = nomap_sysmem(fadt->dsdt, 0);
+ else
+ dsdt = NULL;
+ return dsdt;
+ }
+
+ if (!memcmp(sig, "FACS", ACPI_NAME_LEN)) {
+ void *facs;
+
+ if (fadt->header.revision >= 3 &&
+ fadt->x_firmware_ctrl)
+ facs = nomap_sysmem(fadt->x_firmware_ctrl, 0);
+ else if (fadt->firmware_ctrl)
+ facs = nomap_sysmem(fadt->firmware_ctrl, 0);
+ else
+ facs = NULL;
+ return facs;
+ }
}
}
* Mostly taken from coreboot file of the same name
*/
-#include <common.h>
#include <dm.h>
#include <irq.h>
#include <log.h>
* Mostly taken from coreboot file acpi_device.c
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
* Copyright 2019 Google LLC
*/
-#include <common.h>
#include <dm.h>
#include <cpu.h>
#include <log.h>
}
/* Add table to the RSDT */
- rsdt->entry[i] = map_to_sysmem(table);
+ rsdt->entry[i] = nomap_to_sysmem(table);
/* Fix RSDT length or the kernel will assume invalid entries */
rsdt->header.length = sizeof(struct acpi_table_header) +
xsdt = ctx->xsdt;
/* Add table to the XSDT */
- xsdt->entry[i] = map_to_sysmem(table);
+ xsdt->entry[i] = nomap_to_sysmem(table);
/* Fix XSDT length */
xsdt->header.length = sizeof(struct acpi_table_header) +
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/global_data.h>
#include <dm/acpi.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-#ifndef CONFIG_QEMU
+#ifndef CONFIG_QFW_ACPI
static int acpi_write_all(struct acpi_ctx *ctx)
{
const struct acpi_writer *writer =
return map_to_sysmem(gd->acpi_ctx->rsdp);
}
-#endif /* QEMU */
+#endif /* QFW_ACPI */
void acpi_setup_ctx(struct acpi_ctx *ctx, ulong start)
{
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <uuid.h>
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
#include <mapmem.h>
#include <tables_csum.h>
+#include <linux/sizes.h>
+#include <linux/errno.h>
+#include <linux/string.h>
void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
struct acpi_xsdt *xsdt)
memcpy(rsdp->signature, RSDP_SIG, 8);
memcpy(rsdp->oem_id, OEM_ID, 6);
- rsdp->length = sizeof(struct acpi_rsdp);
- rsdp->rsdt_address = map_to_sysmem(rsdt);
+ if (rsdt)
+ rsdp->rsdt_address = nomap_to_sysmem(rsdt);
+
+ if (xsdt)
+ rsdp->xsdt_address = nomap_to_sysmem(xsdt);
- rsdp->xsdt_address = map_to_sysmem(xsdt);
+ rsdp->length = sizeof(struct acpi_rsdp);
rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
/* Calculate checksums */
static int acpi_write_base(struct acpi_ctx *ctx,
const struct acpi_writer *entry)
{
- /* We need at least an RSDP and an RSDT Table */
+ /* We need at least an RSDP and an XSDT Table */
ctx->rsdp = ctx->current;
acpi_inc_align(ctx, sizeof(struct acpi_rsdp));
- ctx->rsdt = ctx->current;
- acpi_inc_align(ctx, sizeof(struct acpi_rsdt));
+ if (map_to_sysmem(ctx->current) < SZ_4G - SZ_64K) {
+ ctx->rsdt = ctx->current;
+ acpi_inc_align(ctx, sizeof(struct acpi_rsdt));
+ } else {
+ ctx->rsdt = 0;
+ }
ctx->xsdt = ctx->current;
acpi_inc_align(ctx, sizeof(struct acpi_xsdt));
memset(ctx->base, '\0', ctx->current - ctx->base);
acpi_write_rsdp(ctx->rsdp, ctx->rsdt, ctx->xsdt);
- acpi_write_rsdt(ctx->rsdt);
+ if (ctx->rsdt)
+ acpi_write_rsdt(ctx->rsdt);
acpi_write_xsdt(ctx->xsdt);
return 0;
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <mapmem.h>
#include <tables_csum.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
+#include <linux/string.h>
__weak int acpi_fill_csrt(struct acpi_ctx *ctx)
{
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
#include <tables_csum.h>
+#include <linux/string.h>
/*
* IASL compiles the dsdt entries and writes the hex values
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
+#include <linux/string.h>
int acpi_write_facs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
{
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <mapmem.h>
#include <tables_csum.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
u16 seg_nr, u8 start, u8 end)
#define LOG_CATEGORY LOGC_ACPI
-#include <common.h>
#include <acpi/acpi_table.h>
#include <dm/acpi.h>
#include <tables_csum.h>
+#include <linux/errno.h>
+#include <linux/string.h>
int acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
{
int ret;
ssdt = ctx->current;
- memset((void *)ssdt, '\0', sizeof(struct acpi_table_header));
+ memset(ssdt, '\0', sizeof(struct acpi_table_header));
acpi_fill_header(ssdt, "SSDT");
- memcpy(ssdt->oem_table_id, OEM_TABLE_ID, sizeof(ssdt->oem_table_id));
ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT);
ssdt->aslc_revision = 1;
ssdt->length = sizeof(struct acpi_table_header);
* Copyright 2008 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <addr_map.h>
#include <mapmem.h>
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <display_options.h>
#include <log.h>
+#include <linux/string.h>
#else
#include <string.h>
#endif
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <malloc.h>
#endif
#include <image.h>
* #defines from the assembly-language output.
*/
-#include <common.h>
#include <asm-offsets.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
#include <linux/kbuild.h>
* Wenyou.Yang <wenyou.yang@microchip.com>
*/
-#include <common.h>
#include <atmel_lcd.h>
#include "atmel_logo_8bpp.h"
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <log.h>
#include <malloc.h>
#include <ubi_uboot.h>
* Written by Simon Glass <sjg@chromium.org>
*/
-#include <common.h>
#include <binman.h>
#include <dm.h>
#include <log.h>
-#include <config.h>
-#include <common.h>
#include <malloc.h>
#include <watchdog.h>
+#include <stdio.h>
/*
* This file is a modified version of bzlib.c from the bzip2-1.0.2
#include <config.h>
-#include <common.h>
#include <watchdog.h>
/*-------------------------------------------------------------*/
* Copyright (c) 2017 Rob Clark
*/
-#include <common.h>
#include <charset.h>
#include <capitalization.h>
#include <cp437.h>
* Gerry Hamel, geh@ti.com, Texas Instruments
*/
-#include <common.h>
#include <log.h>
#include <malloc.h>
#ifdef USE_HOSTCC
#include <arpa/inet.h>
-#else
-#include <common.h>
#endif
#include <u-boot/crc.h>
#ifdef USE_HOSTCC
#include <arpa/inet.h>
#else
-#include <common.h>
#include <efi_loader.h>
#endif
#include <compiler.h>
* any later version.
*/
-#include <common.h>
#include <compiler.h>
uint32_t crc32c_cal(uint32_t crc, const char *data, int length,
#ifdef USE_HOSTCC
#include <arpa/inet.h>
-#else
-#include <common.h>
#endif
#include <u-boot/crc.h>
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2020 Steffen Jaeckel <jaeckel-floss@eyet-services.de> */
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
#include <linux/types.h>
#include <vsprintf.h>
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2020 Steffen Jaeckel <jaeckel-floss@eyet-services.de> */
-#include <common.h>
#include <crypt.h>
#include "crypt-port.h"
#define pr_fmt(fmt) "X.509: "fmt
#ifdef __UBOOT__
-#include <common.h>
#include <image.h>
#include <dm/devres.h>
#include <linux/compat.h>
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <command.h>
#include <errno.h>
#include <rtc.h>
* (C) Copyright 2015 Google, Inc
*/
-#include <common.h>
#include <command.h>
#include <div64.h>
+#include <time.h>
+#include <vsprintf.h>
#include "dhry.h"
static int do_dhry(struct cmd_tbl *cmdtp, int flag, int argc,
***************************************************************************/
char SCCSid[] = "@(#) @(#)dhry_1.c:3.4 -- 5/15/91 19:30:21";
-#include <common.h>
#include <malloc.h>
+#include <stdio.h>
#include "dhry.h"
****************************************************************************/
/* SCCSid is defined in dhry_1.c */
-#include <common.h>
+#include <linux/string.h>
#include "dhry.h"
#ifndef REG
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <compiler.h>
#include <console.h>
#include <display_options.h>
#include <div64.h>
#include <version_string.h>
#include <linux/ctype.h>
+#include <linux/kernel.h>
#include <asm/io.h>
+#include <vsprintf.h>
char *display_options_get_banner_priv(bool newlines, const char *build_tag,
char *buf, int size)
* Common EFI functions
*/
-#include <common.h>
#include <debug_uart.h>
#include <errno.h>
#include <malloc.h>
* This file implements U-Boot running as an EFI application.
*/
-#include <common.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <dm.h>
+#include <efi.h>
+#include <efi_api.h>
#include <errno.h>
#include <init.h>
#include <malloc.h>
+#include <sysreset.h>
+#include <uuid.h>
#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
-#include <efi.h>
-#include <efi_api.h>
-#include <sysreset.h>
+#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/root.h>
+#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+static void scan_tables(struct efi_system_table *sys_table)
+{
+ efi_guid_t acpi = EFI_ACPI_TABLE_GUID;
+ uint i;
+
+ for (i = 0; i < sys_table->nr_tables; i++) {
+ struct efi_configuration_table *tab = &sys_table->tables[i];
+
+ if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t)))
+ gd_set_acpi_start(map_to_sysmem(tab->table));
+ }
+}
+
/**
* efi_main() - Start an EFI image
*
return ret;
}
+ scan_tables(priv->sys_table);
+
/*
* We could store the EFI memory map here, but it changes all the time,
* so this is only useful for debugging.
* Access to the EFI information table
*/
-#include <common.h>
#include <efi.h>
#include <errno.h>
#include <mapmem.h>
* EFI application. It can be built either in 32-bit or 64-bit mode.
*/
-#include <common.h>
#include <debug_uart.h>
#include <efi.h>
#include <efi_api.h>
* iPXE uses the simple file protocol to load Grub or the Linux Kernel.
*/
-#include <common.h>
#include <blk.h>
#include <dm.h>
#include <efi_driver.h>
* controllers.
*/
-#include <common.h>
#include <dm.h>
#include <efi_driver.h>
#include <log.h>
if EFI_LOADER
-config CMD_BOOTEFI_BOOTMGR
+config BOOTEFI_BOOTMGR
bool "UEFI Boot Manager"
default y
select BOOTMETH_GLOBAL if BOOTSTD
help
Select this option if you want to select the UEFI binary to be booted
- via UEFI variables Boot####, BootOrder, and BootNext. This enables the
- 'bootefi bootmgr' command.
+ via UEFI variables Boot####, BootOrder, and BootNext. You should also
+ normally enable CMD_BOOTEFI_BOOTMGR so that the command is available.
choice
prompt "Store for non-volatile UEFI variables"
replace the transfer via the device-tree. The latter is not
possible on systems using ACPI.
+config EFI_HTTP_BOOT
+ bool "EFI HTTP Boot support"
+ select CMD_DNS
+ select CMD_WGET
+ select BLKMAP
+ help
+ Enabling this option adds EFI HTTP Boot support. It allows to
+ directly boot from network.
+
endif
endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
-obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o
+obj-$(CONFIG_BOOTEFI_BOOTMGR) += efi_bootmgr.o
obj-y += efi_boottime.o
obj-y += efi_helper.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o
-ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
obj-y += efi_dt_fixup.o
-endif
obj-y += efi_file.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
obj-y += efi_image_loader.o
* to a file.
*/
-#include <common.h>
#include <efi_api.h>
#include <efi_dt_fixup.h>
#include <part.h>
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
#include <efi_loader.h>
#include <log.h>
#include <mapmem.h>
* EFI boot manager
*
* Copyright (c) 2017 Rob Clark
+ * For the code moved from cmd/bootefi.c
+ * Copyright (c) 2016 Alexander Graf
*/
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
+#include <blk.h>
+#include <blkmap.h>
#include <charset.h>
+#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <net.h>
#include <efi_default_filename.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <asm/unaligned.h>
+/* TODO: temporarily added here; clean up later */
+#include <bootm.h>
+#include <efi_selftest.h>
+#include <env.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <linux/libfdt_env.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
static const struct efi_boot_services *bs;
static const struct efi_runtime_services *rs;
+/**
+ * struct uridp_context - uri device path resource
+ *
+ * @image_size: image size
+ * @image_addr: image address
+ * @loaded_dp: pointer to loaded device path
+ * @ramdisk_blk_dev: pointer to the ramdisk blk device
+ * @mem_handle: efi_handle to the loaded PE-COFF image
+ */
+struct uridp_context {
+ ulong image_size;
+ ulong image_addr;
+ struct efi_device_path *loaded_dp;
+ struct udevice *ramdisk_blk_dev;
+ efi_handle_t mem_handle;
+};
+
const efi_guid_t efi_guid_bootmenu_auto_generated =
EFICONFIG_AUTO_GENERATED_ENTRY_GUID;
return ret;
}
+/**
+ * mount_image() - mount the image with blkmap
+ *
+ * @lo_label: u16 label string of load option
+ * @addr: image address
+ * @size: image size
+ * Return: pointer to the UCLASS_BLK udevice, NULL if failed
+ */
+static struct udevice *mount_image(u16 *lo_label, ulong addr, ulong size)
+{
+ int err;
+ struct blkmap *bm;
+ struct udevice *bm_dev;
+ char *label = NULL, *p;
+
+ label = efi_alloc(utf16_utf8_strlen(lo_label) + 1);
+ if (!label)
+ return NULL;
+
+ p = label;
+ utf16_utf8_strcpy(&p, lo_label);
+ err = blkmap_create_ramdisk(label, addr, size, &bm_dev);
+ if (err) {
+ efi_free_pool(label);
+ return NULL;
+ }
+ bm = dev_get_plat(bm_dev);
+
+ efi_free_pool(label);
+
+ return bm->blk;
+}
+
+/**
+ * search_default_file() - search default file
+ *
+ * @dev: pointer to the UCLASS_BLK or UCLASS_PARTITION udevice
+ * @loaded_dp: pointer to default file device path
+ * Return: status code
+ */
+static efi_status_t search_default_file(struct udevice *dev,
+ struct efi_device_path **loaded_dp)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+ u16 *default_file_name = NULL;
+ struct efi_file_handle *root, *f;
+ struct efi_device_path *dp = NULL, *fp = NULL;
+ struct efi_simple_file_system_protocol *file_system;
+ struct efi_device_path *device_path, *full_path = NULL;
+
+ if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **)&handle)) {
+ log_warning("DM_TAG_EFI not found\n");
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ret = EFI_CALL(bs->open_protocol(handle, &efi_guid_device_path,
+ (void **)&device_path, efi_root, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(bs->open_protocol(handle, &efi_simple_file_system_protocol_guid,
+ (void **)&file_system, efi_root, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(file_system->open_volume(file_system, &root));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ full_path = expand_media_path(device_path);
+ ret = efi_dp_split_file_path(full_path, &dp, &fp);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ default_file_name = efi_dp_str(fp);
+ efi_free_pool(dp);
+ efi_free_pool(fp);
+ if (!default_file_name) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto err;
+ }
+
+ ret = EFI_CALL(root->open(root, &f, default_file_name,
+ EFI_FILE_MODE_READ, 0));
+ efi_free_pool(default_file_name);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ EFI_CALL(f->close(f));
+ EFI_CALL(root->close(root));
+
+ *loaded_dp = full_path;
+
+ return EFI_SUCCESS;
+
+err:
+ EFI_CALL(root->close(root));
+ efi_free_pool(full_path);
+
+ return ret;
+}
+
+/**
+ * check_disk_has_default_file() - load the default file
+ *
+ * @blk: pointer to the UCLASS_BLK udevice
+ * @dp: pointer to default file device path
+ * Return: status code
+ */
+static efi_status_t check_disk_has_default_file(struct udevice *blk,
+ struct efi_device_path **dp)
+{
+ efi_status_t ret;
+ struct udevice *partition;
+
+ /* image that has no partition table but a file system */
+ ret = search_default_file(blk, dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ /* try the partitions */
+ device_foreach_child(partition, blk) {
+ enum uclass_id id;
+
+ id = device_get_uclass_id(partition);
+ if (id != UCLASS_PARTITION)
+ continue;
+
+ ret = search_default_file(partition, dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ * prepare_loaded_image() - prepare ramdisk for downloaded image
+ *
+ * @label: label of load option
+ * @addr: image address
+ * @size: image size
+ * @dp: pointer to default file device path
+ * @blk: pointer to created blk udevice
+ * Return: status code
+ */
+static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
+ struct efi_device_path **dp,
+ struct udevice **blk)
+{
+ efi_status_t ret;
+ struct udevice *ramdisk_blk;
+
+ ramdisk_blk = mount_image(label, addr, size);
+ if (!ramdisk_blk)
+ return EFI_LOAD_ERROR;
+
+ ret = check_disk_has_default_file(ramdisk_blk, dp);
+ if (ret != EFI_SUCCESS) {
+ log_info("Cannot boot from downloaded image\n");
+ goto err;
+ }
+
+ /*
+ * TODO: expose the ramdisk to OS.
+ * Need to pass the ramdisk information by the architecture-specific
+ * methods such as 'pmem' device-tree node.
+ */
+ ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE);
+ if (ret != EFI_SUCCESS) {
+ log_err("Memory reservation failed\n");
+ goto err;
+ }
+
+ *blk = ramdisk_blk;
+
+ return EFI_SUCCESS;
+
+err:
+ if (blkmap_destroy(ramdisk_blk->parent))
+ log_err("Destroying blkmap failed\n");
+
+ return ret;
+}
+
+/**
+ * efi_bootmgr_release_uridp_resource() - cleanup uri device path resource
+ *
+ * @ctx: event context
+ * Return: status code
+ */
+efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (!ctx)
+ return ret;
+
+ /* cleanup for iso or img image */
+ if (ctx->ramdisk_blk_dev) {
+ ret = efi_add_memory_map(ctx->image_addr, ctx->image_size,
+ EFI_CONVENTIONAL_MEMORY);
+ if (ret != EFI_SUCCESS)
+ log_err("Reclaiming memory failed\n");
+
+ if (blkmap_destroy(ctx->ramdisk_blk_dev->parent)) {
+ log_err("Destroying blkmap failed\n");
+ ret = EFI_DEVICE_ERROR;
+ }
+ }
+
+ /* cleanup for PE-COFF image */
+ if (ctx->mem_handle) {
+ ret = efi_uninstall_multiple_protocol_interfaces(
+ ctx->mem_handle, &efi_guid_device_path, ctx->loaded_dp,
+ NULL);
+ if (ret != EFI_SUCCESS)
+ log_err("Uninstall device_path protocol failed\n");
+ }
+
+ efi_free_pool(ctx->loaded_dp);
+ free(ctx);
+
+ return ret;
+}
+
+/**
+ * efi_bootmgr_image_return_notify() - return to efibootmgr callback
+ *
+ * @event: the event for which this notification function is registered
+ * @context: event context
+ */
+static void EFIAPI efi_bootmgr_image_return_notify(struct efi_event *event,
+ void *context)
+{
+ efi_status_t ret;
+
+ EFI_ENTRY("%p, %p", event, context);
+ ret = efi_bootmgr_release_uridp_resource(context);
+ EFI_EXIT(ret);
+}
+
+/**
+ * try_load_from_uri_path() - Handle the URI device path
+ *
+ * @uridp: uri device path
+ * @lo_label: label of load option
+ * @handle: pointer to handle for newly installed image
+ * Return: status code
+ */
+static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp,
+ u16 *lo_label,
+ efi_handle_t *handle)
+{
+ char *s;
+ int err;
+ int uri_len;
+ efi_status_t ret;
+ void *source_buffer;
+ efi_uintn_t source_size;
+ struct uridp_context *ctx;
+ struct udevice *blk = NULL;
+ struct efi_event *event = NULL;
+ efi_handle_t mem_handle = NULL;
+ struct efi_device_path *loaded_dp;
+ static ulong image_size, image_addr;
+
+ ctx = calloc(1, sizeof(struct uridp_context));
+ if (!ctx)
+ return EFI_OUT_OF_RESOURCES;
+
+ s = env_get("loadaddr");
+ if (!s) {
+ log_err("Error: loadaddr is not set\n");
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ image_addr = hextoul(s, NULL);
+ err = wget_with_dns(image_addr, uridp->uri);
+ if (err < 0) {
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ image_size = env_get_hex("filesize", 0);
+ if (!image_size) {
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ /*
+ * If the file extension is ".iso" or ".img", mount it and try to load
+ * the default file.
+ * If the file is PE-COFF image, load the downloaded file.
+ */
+ uri_len = strlen(uridp->uri);
+ if (!strncmp(&uridp->uri[uri_len - 4], ".iso", 4) ||
+ !strncmp(&uridp->uri[uri_len - 4], ".img", 4)) {
+ ret = prepare_loaded_image(lo_label, image_addr, image_size,
+ &loaded_dp, &blk);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ source_buffer = NULL;
+ source_size = 0;
+ } else if (efi_check_pe((void *)image_addr, image_size, NULL) == EFI_SUCCESS) {
+ /*
+ * loaded_dp must exist until efi application returns,
+ * will be freed in return_to_efibootmgr event callback.
+ */
+ loaded_dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+ (uintptr_t)image_addr, image_size);
+ ret = efi_install_multiple_protocol_interfaces(
+ &mem_handle, &efi_guid_device_path, loaded_dp, NULL);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ source_buffer = (void *)image_addr;
+ source_size = image_size;
+ } else {
+ log_err("Error: file type is not supported\n");
+ ret = EFI_UNSUPPORTED;
+ goto err;
+ }
+
+ ctx->image_size = image_size;
+ ctx->image_addr = image_addr;
+ ctx->loaded_dp = loaded_dp;
+ ctx->ramdisk_blk_dev = blk;
+ ctx->mem_handle = mem_handle;
+
+ ret = EFI_CALL(efi_load_image(false, efi_root, loaded_dp, source_buffer,
+ source_size, handle));
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ /* create event for cleanup when the image returns or error occurs */
+ ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
+ efi_bootmgr_image_return_notify, ctx,
+ &efi_guid_event_group_return_to_efibootmgr,
+ &event);
+ if (ret != EFI_SUCCESS) {
+ log_err("Creating event failed\n");
+ goto err;
+ }
+
+ return ret;
+
+err:
+ efi_bootmgr_release_uridp_resource(ctx);
+
+ return ret;
+}
+
/**
* try_load_entry() - try to load image for boot option
*
if (EFI_DP_TYPE(lo.file_path, MEDIA_DEVICE, FILE_PATH)) {
/* file_path doesn't contain a device path */
ret = try_load_from_short_path(lo.file_path, handle);
+ } else if (EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, MSG_URI)) {
+ if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
+ ret = try_load_from_uri_path(
+ (struct efi_device_path_uri *)lo.file_path,
+ lo.label, handle);
+ else
+ ret = EFI_LOAD_ERROR;
} else {
file_path = expand_media_path(lo.file_path);
ret = EFI_CALL(efi_load_image(true, efi_root, file_path,
return EFI_SUCCESS;
return ret;
}
+
+static struct efi_device_path *bootefi_image_path;
+static struct efi_device_path *bootefi_device_path;
+static void *image_addr;
+static size_t image_size;
+
+/**
+ * efi_get_image_parameters() - return image parameters
+ *
+ * @img_addr: address of loaded image in memory
+ * @img_size: size of loaded image
+ */
+void efi_get_image_parameters(void **img_addr, size_t *img_size)
+{
+ *img_addr = image_addr;
+ *img_size = image_size;
+}
+
+/**
+ * efi_clear_bootdev() - clear boot device
+ */
+void efi_clear_bootdev(void)
+{
+ efi_free_pool(bootefi_device_path);
+ efi_free_pool(bootefi_image_path);
+ bootefi_device_path = NULL;
+ bootefi_image_path = NULL;
+ image_addr = NULL;
+ image_size = 0;
+}
+
+/**
+ * efi_set_bootdev() - set boot device
+ *
+ * This function is called when a file is loaded, e.g. via the 'load' command.
+ * We use the path to this file to inform the UEFI binary about the boot device.
+ *
+ * @dev: device, e.g. "MMC"
+ * @devnr: number of the device, e.g. "1:2"
+ * @path: path to file loaded
+ * @buffer: buffer with file loaded
+ * @buffer_size: size of file loaded
+ */
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
+ void *buffer, size_t buffer_size)
+{
+ struct efi_device_path *device, *image;
+ efi_status_t ret;
+
+ log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev,
+ devnr, path, buffer, buffer_size);
+
+ /* Forget overwritten image */
+ if (buffer + buffer_size >= image_addr &&
+ image_addr + image_size >= buffer)
+ efi_clear_bootdev();
+
+ /* Remember only PE-COFF and FIT images */
+ if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
+ if (IS_ENABLED(CONFIG_FIT) &&
+ !fit_check_format(buffer, IMAGE_SIZE_INVAL)) {
+ /*
+ * FIT images of type EFI_OS are started via command
+ * bootm. We should not use their boot device with the
+ * bootefi command.
+ */
+ buffer = 0;
+ buffer_size = 0;
+ } else {
+ log_debug("- not remembering image\n");
+ return;
+ }
+ }
+
+ /* efi_set_bootdev() is typically called repeatedly, recover memory */
+ efi_clear_bootdev();
+
+ image_addr = buffer;
+ image_size = buffer_size;
+
+ ret = efi_dp_from_name(dev, devnr, path, &device, &image);
+ if (ret == EFI_SUCCESS) {
+ bootefi_device_path = device;
+ if (image) {
+ /* FIXME: image should not contain device */
+ struct efi_device_path *image_tmp = image;
+
+ efi_dp_split_file_path(image, &device, &image);
+ efi_free_pool(image_tmp);
+ }
+ bootefi_image_path = image;
+ log_debug("- boot device %pD\n", device);
+ if (image)
+ log_debug("- image %pD\n", image);
+ } else {
+ log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
+ efi_clear_bootdev();
+ }
+}
+
+/**
+ * efi_env_set_load_options() - set load options from environment variable
+ *
+ * @handle: the image handle
+ * @env_var: name of the environment variable
+ * @load_options: pointer to load options (output)
+ * Return: status code
+ */
+efi_status_t efi_env_set_load_options(efi_handle_t handle,
+ const char *env_var,
+ u16 **load_options)
+{
+ const char *env = env_get(env_var);
+ size_t size;
+ u16 *pos;
+ efi_status_t ret;
+
+ *load_options = NULL;
+ if (!env)
+ return EFI_SUCCESS;
+ size = sizeof(u16) * (utf8_utf16_strlen(env) + 1);
+ pos = calloc(size, 1);
+ if (!pos)
+ return EFI_OUT_OF_RESOURCES;
+ *load_options = pos;
+ utf8_utf16_strcpy(&pos, env);
+ ret = efi_set_load_options(handle, size, *load_options);
+ if (ret != EFI_SUCCESS) {
+ free(*load_options);
+ *load_options = NULL;
+ }
+ return ret;
+}
+
+/**
+ * copy_fdt() - Copy the device tree to a new location available to EFI
+ *
+ * The FDT is copied to a suitable location within the EFI memory map.
+ * Additional 12 KiB are added to the space in case the device tree needs to be
+ * expanded later with fdt_open_into().
+ *
+ * @fdtp: On entry a pointer to the flattened device tree.
+ * On exit a pointer to the copy of the flattened device tree.
+ * FDT start
+ * Return: status code
+ */
+static efi_status_t copy_fdt(void **fdtp)
+{
+ unsigned long fdt_ram_start = -1L, fdt_pages;
+ efi_status_t ret = 0;
+ void *fdt, *new_fdt;
+ u64 new_fdt_addr;
+ uint fdt_size;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ u64 ram_start = gd->bd->bi_dram[i].start;
+ u64 ram_size = gd->bd->bi_dram[i].size;
+
+ if (!ram_size)
+ continue;
+
+ if (ram_start < fdt_ram_start)
+ fdt_ram_start = ram_start;
+ }
+
+ /*
+ * Give us at least 12 KiB of breathing room in case the device tree
+ * needs to be expanded later.
+ */
+ fdt = *fdtp;
+ fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000);
+ fdt_size = fdt_pages << EFI_PAGE_SHIFT;
+
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_ACPI_RECLAIM_MEMORY, fdt_pages,
+ &new_fdt_addr);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: Failed to reserve space for FDT\n");
+ goto done;
+ }
+ new_fdt = (void *)(uintptr_t)new_fdt_addr;
+ memcpy(new_fdt, fdt, fdt_totalsize(fdt));
+ fdt_set_totalsize(new_fdt, fdt_size);
+
+ *fdtp = (void *)(uintptr_t)new_fdt_addr;
+done:
+ return ret;
+}
+
+/**
+ * get_config_table() - get configuration table
+ *
+ * @guid: GUID of the configuration table
+ * Return: pointer to configuration table or NULL
+ */
+static void *get_config_table(const efi_guid_t *guid)
+{
+ size_t i;
+
+ for (i = 0; i < systab.nr_tables; i++) {
+ if (!guidcmp(guid, &systab.tables[i].guid))
+ return systab.tables[i].table;
+ }
+ return NULL;
+}
+
+/**
+ * efi_install_fdt() - install device tree
+ *
+ * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory
+ * address will be installed as configuration table, otherwise the device
+ * tree located at the address indicated by environment variable fdt_addr or as
+ * fallback fdtcontroladdr will be used.
+ *
+ * On architectures using ACPI tables device trees shall not be installed as
+ * configuration table.
+ *
+ * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use
+ * the hardware device tree as indicated by environment variable
+ * fdt_addr or as fallback the internal device tree as indicated by
+ * the environment variable fdtcontroladdr
+ * Return: status code
+ */
+efi_status_t efi_install_fdt(void *fdt)
+{
+ struct bootm_headers img = { 0 };
+ efi_status_t ret;
+
+ /*
+ * The EBBR spec requires that we have either an FDT or an ACPI table
+ * but not both.
+ */
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
+ log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
+
+ if (fdt == EFI_FDT_USE_INTERNAL) {
+ const char *fdt_opt;
+ uintptr_t fdt_addr;
+
+ /* Look for device tree that is already installed */
+ if (get_config_table(&efi_guid_fdt))
+ return EFI_SUCCESS;
+ /* Check if there is a hardware device tree */
+ fdt_opt = env_get("fdt_addr");
+ /* Use our own device tree as fallback */
+ if (!fdt_opt) {
+ fdt_opt = env_get("fdtcontroladdr");
+ if (!fdt_opt) {
+ log_err("ERROR: need device tree\n");
+ return EFI_NOT_FOUND;
+ }
+ }
+ fdt_addr = hextoul(fdt_opt, NULL);
+ if (!fdt_addr) {
+ log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n");
+ return EFI_LOAD_ERROR;
+ }
+ fdt = map_sysmem(fdt_addr, 0);
+ }
+
+ /* Install device tree */
+ if (fdt_check_header(fdt)) {
+ log_err("ERROR: invalid device tree\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ return EFI_SUCCESS;
+
+ /* Prepare device tree for payload */
+ ret = copy_fdt(&fdt);
+ if (ret) {
+ log_err("ERROR: out of memory\n");
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (image_setup_libfdt(&img, fdt, NULL)) {
+ log_err("ERROR: failed to process device tree\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ efi_try_purge_kaslr_seed(fdt);
+
+ if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
+ ret = efi_tcg2_measure_dtb(fdt);
+ if (ret == EFI_SECURITY_VIOLATION) {
+ log_err("ERROR: failed to measure DTB\n");
+ return ret;
+ }
+ }
+
+ /* Install device tree as UEFI table */
+ ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: failed to install device tree\n");
+ return ret;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * do_bootefi_exec() - execute EFI binary
+ *
+ * The image indicated by @handle is started. When it returns the allocated
+ * memory for the @load_options is freed.
+ *
+ * @handle: handle of loaded image
+ * @load_options: load options
+ * Return: status code
+ *
+ * Load the EFI binary into a newly assigned memory unwinding the relocation
+ * information, install the loaded image protocol, and call the binary.
+ */
+static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options)
+{
+ efi_status_t ret;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
+ struct efi_event *evt;
+
+ /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
+ switch_to_non_secure_mode();
+
+ /*
+ * The UEFI standard requires that the watchdog timer is set to five
+ * minutes when invoking an EFI boot option.
+ *
+ * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
+ * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
+ */
+ ret = efi_set_watchdog(300);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: Failed to set watchdog timer\n");
+ goto out;
+ }
+
+ /* Call our payload! */
+ ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
+ if (ret != EFI_SUCCESS) {
+ log_err("## Application failed, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ if (exit_data) {
+ log_err("## %ls\n", exit_data);
+ efi_free_pool(exit_data);
+ }
+ }
+
+ efi_restore_gd();
+
+out:
+ free(load_options);
+
+ if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
+ if (efi_initrd_deregister() != EFI_SUCCESS)
+ log_err("Failed to remove loadfile2 for initrd\n");
+ }
+
+ /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_return_to_efibootmgr)) {
+ efi_signal_event(evt);
+ EFI_CALL(systab.boottime->close_event(evt));
+ break;
+ }
+ }
+
+ /* Control is returned to U-Boot, disable EFI watchdog */
+ efi_set_watchdog(0);
+
+ return ret;
+}
+
+/**
+ * efi_bootmgr_run() - execute EFI boot manager
+ * @fdt: Flat device tree
+ *
+ * Invoke EFI boot manager and execute a binary depending on
+ * boot options. If @fdt is not NULL, it will be passed to
+ * the executed binary.
+ *
+ * Return: status code
+ */
+efi_status_t efi_bootmgr_run(void *fdt)
+{
+ efi_handle_t handle;
+ void *load_options;
+ efi_status_t ret;
+
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = efi_install_fdt(fdt);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = efi_bootmgr_load(&handle, &load_options);
+ if (ret != EFI_SUCCESS) {
+ log_notice("EFI boot manager: Cannot load any image\n");
+ return ret;
+ }
+
+ return do_bootefi_exec(handle, load_options);
+}
+
+/**
+ * efi_run_image() - run loaded UEFI image
+ *
+ * @source_buffer: memory address of the UEFI image
+ * @source_size: size of the UEFI image
+ * Return: status code
+ */
+efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size)
+{
+ efi_handle_t mem_handle = NULL, handle;
+ struct efi_device_path *file_path = NULL;
+ struct efi_device_path *msg_path;
+ efi_status_t ret, ret2;
+ u16 *load_options;
+
+ if (!bootefi_device_path || !bootefi_image_path) {
+ log_debug("Not loaded from disk\n");
+ /*
+ * Special case for efi payload not loaded from disk,
+ * such as 'bootefi hello' or for example payload
+ * loaded directly into memory via JTAG, etc:
+ */
+ file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+ (uintptr_t)source_buffer,
+ source_size);
+ /*
+ * Make sure that device for device_path exist
+ * in load_image(). Otherwise, shell and grub will fail.
+ */
+ ret = efi_install_multiple_protocol_interfaces(&mem_handle,
+ &efi_guid_device_path,
+ file_path, NULL);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ msg_path = file_path;
+ } else {
+ file_path = efi_dp_append(bootefi_device_path,
+ bootefi_image_path);
+ msg_path = bootefi_image_path;
+ log_debug("Loaded from disk\n");
+ }
+
+ log_info("Booting %pD\n", msg_path);
+
+ ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer,
+ source_size, &handle));
+ if (ret != EFI_SUCCESS) {
+ log_err("Loading image failed\n");
+ goto out;
+ }
+
+ /* Transfer environment variable as load options */
+ ret = efi_env_set_load_options(handle, "bootargs", &load_options);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ ret = do_bootefi_exec(handle, load_options);
+
+out:
+ ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle,
+ &efi_guid_device_path,
+ file_path, NULL);
+ efi_free_pool(file_path);
+ return (ret != EFI_SUCCESS) ? ret : ret2;
+}
+
+/**
+ * efi_binary_run() - run loaded UEFI image
+ *
+ * @image: memory address of the UEFI image
+ * @size: size of the UEFI image
+ * @fdt: device-tree
+ *
+ * Execute an EFI binary image loaded at @image.
+ * @size may be zero if the binary is loaded with U-Boot load command.
+ *
+ * Return: status code
+ */
+efi_status_t efi_binary_run(void *image, size_t size, void *fdt)
+{
+ efi_status_t ret;
+
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return -1;
+ }
+
+ ret = efi_install_fdt(fdt);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ return efi_run_image(image, size);
+}
* Copyright (c) 2016 Alexander Graf
*/
-#include <common.h>
#include <bootm.h>
#include <div64.h>
#include <dm/device.h>
/* event group ResetSystem() invoked (before ExitBootServices) */
const efi_guid_t efi_guid_event_group_reset_system =
EFI_EVENT_GROUP_RESET_SYSTEM;
+/* event group return to efibootmgr */
+const efi_guid_t efi_guid_event_group_return_to_efibootmgr =
+ EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR;
/* GUIDs of the Load File and Load File2 protocols */
const efi_guid_t efi_guid_load_file_protocol = EFI_LOAD_FILE_PROTOCOL_GUID;
const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID;
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, efi_guid_t *group,
+ void *notify_context, const efi_guid_t *group,
struct efi_event **event)
{
struct efi_event *evt;
struct efi_event *event,
void *context),
void *notify_context,
- efi_guid_t *event_group,
+ const efi_guid_t *event_group,
struct efi_event **event)
{
efi_status_t ret;
const efi_guid_t *protocol,
efi_handle_t child_handle)
{
- efi_uintn_t number_of_drivers, tmp;
+ efi_uintn_t number_of_drivers;
efi_handle_t *driver_handle_buffer;
efi_status_t r, ret;
if (!number_of_drivers)
return EFI_SUCCESS;
- tmp = number_of_drivers;
while (number_of_drivers) {
- ret = EFI_CALL(efi_disconnect_controller(
+ r = EFI_CALL(efi_disconnect_controller(
handle,
driver_handle_buffer[--number_of_drivers],
child_handle));
- if (ret != EFI_SUCCESS)
- goto reconnect;
- }
-
- free(driver_handle_buffer);
- return ret;
-
-reconnect:
- /* Reconnect all disconnected drivers */
- for (; number_of_drivers < tmp; number_of_drivers++) {
- r = EFI_CALL(efi_connect_controller(handle,
- &driver_handle_buffer[number_of_drivers],
- NULL, true));
if (r != EFI_SUCCESS)
- EFI_PRINT("Failed to reconnect controller\n");
+ ret = r;
}
free(driver_handle_buffer);
r = efi_disconnect_all_drivers(handle, protocol, NULL);
if (r != EFI_SUCCESS) {
r = EFI_ACCESS_DENIED;
+ /*
+ * This will reconnect all controllers of the handle, even ones
+ * that were not connected before. This can be done better
+ * but we are following the EDKII implementation on this for
+ * now
+ */
+ EFI_CALL(efi_connect_controller(handle, NULL, NULL, true));
goto out;
}
/* Close protocol */
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <env.h>
* Copyright (C) 2022 Arm Ltd.
*/
-#include <common.h>
#include <efi_loader.h>
#include <log.h>
#include <efi_api.h>
#define LOG_CATEGORY LOGC_EFI
#include <ansi.h>
-#include <common.h>
#include <charset.h>
#include <malloc.h>
#include <time.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <blk.h>
#include <dm.h>
#include <dm/root.h>
* Copyright (c) 2017 Heinrich Schuchardt
*/
-#include <common.h>
#include <blk.h>
#include <efi_loader.h>
#include <malloc.h>
* Copyright (c) 2017 Leif Lindholm
*/
-#include <common.h>
#include <efi_loader.h>
const efi_guid_t efi_guid_device_path_utilities_protocol =
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <blk.h>
#include <dm.h>
#include <dm/device-internal.h>
return -1;
}
+ /* only do the boot option management when UEFI sub-system is initialized */
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && efi_obj_list_initialized == EFI_SUCCESS) {
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS)
+ return -1;
+ }
+
return 0;
}
dev_tag_del(dev, DM_TAG_EFI);
return 0;
+
+ /*
+ * TODO A flag to distinguish below 2 different scenarios of this
+ * function call is needed:
+ * a) Unplugging of a removable media under U-Boot
+ * b) U-Boot exiting and booting an OS
+ * In case of scenario a), efi_bootmgr_update_media_device_boot_option()
+ * needs to be invoked here to update the boot options and remove the
+ * unnecessary ones.
+ */
+
}
/**
* Copyright (c) 2020 Heinrich Schuchardt
*/
-#include <common.h>
#include <efi_dt_fixup.h>
#include <efi_loader.h>
#include <efi_rng.h>
}
fdt_set_totalsize(dtb, *buffer_size);
- if (image_setup_libfdt(&img, dtb, 0, NULL)) {
+ if (image_setup_libfdt(&img, dtb, NULL)) {
log_err("failed to process device tree\n");
ret = EFI_INVALID_PARAMETER;
goto out;
* Copyright (C) 2021 Arm Ltd.
*/
-#include <common.h>
#include <efi_loader.h>
#include <log.h>
#include <efi_api.h>
* Copyright (c) 2017 Rob Clark
*/
-#include <common.h>
#include <charset.h>
#include <efi_loader.h>
#include <log.h>
* Author: AKASHI Takahiro
*/
-#include <common.h>
#include <charset.h>
#include <dfu.h>
#include <efi_loader.h>
* memset(), and memcmp().
*/
-#include <common.h>
+#include <linux/types.h>
/**
* memcmp() - compare memory areas
* Copyright (c) 2016 Alexander Graf
*/
-#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <log.h>
*/
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <env.h>
#include <malloc.h>
#include <dm.h>
* Copyright (c) 2018 AKASHI Takahiro, Linaro Limited
*/
-#include <common.h>
#include <efi_loader.h>
#include <malloc.h>
#include <asm/unaligned.h>
* the Makefile.
*/
-#include <common.h>
#include <efi_loader.h>
const efi_guid_t efi_guid_hii_config_routing_protocol
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <cpu_func.h>
#include <efi_loader.h>
#include <log.h>
*/
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <efi_load_initrd.h>
#include <efi_variable.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <charset.h>
#include <log.h>
#include <malloc.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <init.h>
#include <log.h>
* Reset(): EfiSimpleNetworkInitialized -> EfiSimpleNetworkInitialized
*/
-#include <common.h>
#include <efi_loader.h>
#include <malloc.h>
#include <net.h>
*/
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <log.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <efi_rng.h>
* Copyright (c) 2018 Heinrich Schuchardt
*/
-#include <common.h>
#include <malloc.h>
#include <efi_dt_fixup.h>
#include <efi_loader.h>
* Copyright (c) 2016 Alexander Graf
*/
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <log.h>
if (ret != EFI_SUCCESS)
goto out;
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
+ /* update boot option after variable service initialized */
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+
/* Define supported languages */
ret = efi_init_platform_lang();
if (ret != EFI_SUCCESS)
* Copyright (c) 2019 Linaro Limited, Author: AKASHI Takahiro
*/
-#include <common.h>
#include <charset.h>
#include <efi_loader.h>
#include <efi_variable.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <log.h>
#include <malloc.h>
#include <smbios.h>
#include <linux/sizes.h>
+const efi_guid_t smbios3_guid = SMBIOS3_TABLE_GUID;
+
enum {
TABLE_SIZE = SZ_4K,
};
{
ulong addr;
efi_status_t ret;
+ void *buf;
- addr = gd->arch.smbios_start;
+ addr = gd_smbios_start();
if (!addr) {
log_err("No SMBIOS tables to install\n");
return EFI_NOT_FOUND;
log_debug("EFI using SMBIOS tables at %lx\n", addr);
/* Install SMBIOS information as configuration table */
- return efi_install_configuration_table(&smbios_guid,
- map_sysmem(addr, 0));
+ buf = map_sysmem(addr, 0);
+ ret = efi_install_configuration_table(&smbios3_guid, buf);
+ unmap_sysmem(buf);
+
+ return ret;
}
static int install_smbios_table(void)
{
- u64 addr;
- efi_status_t ret;
+ ulong addr;
+ void *buf;
if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) || IS_ENABLED(CONFIG_X86))
return 0;
- addr = SZ_4G;
- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA,
- efi_size_in_pages(TABLE_SIZE), &addr);
- if (ret != EFI_SUCCESS)
+ /* Align the table to a 4KB boundary to keep EFI happy */
+ buf = memalign(SZ_4K, TABLE_SIZE);
+ if (!buf)
return log_msg_ret("mem", -ENOMEM);
- addr = map_to_sysmem((void *)(uintptr_t)addr);
+ addr = map_to_sysmem(buf);
if (!write_smbios_table(addr)) {
log_err("Failed to write SMBIOS table\n");
return log_msg_ret("smbios", -EINVAL);
}
/* Make a note of where we put it */
- log_debug("SMBIOS tables written to %llx\n", addr);
+ log_debug("SMBIOS tables written to %lx\n", addr);
gd->arch.smbios_start = addr;
return 0;
* Copyright (c) 2020 AKASHI Takahiro, Linaro Limited
*/
-#include <common.h>
#include <charset.h>
#include <efi_loader.h>
#include <malloc.h>
*/
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <efi_variable.h>
* Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
*/
-#include <common.h>
#include <charset.h>
#include <cp1250.h>
#include <cp437.h>
* Copyright (c) 2020 Linaro Limited, Author: AKASHI Takahiro
*/
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <stdlib.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <charset.h>
#include <fs.h>
#include <log.h>
* Copyright (c) 2020, Heinrich Schuchardt
*/
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <u-boot/crc.h>
#define LOG_CATEGORY LOGC_EFI
-#include <common.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <env.h>
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
-#include <common.h>
#if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT)
#include <arm_ffa.h>
#endif
* Copyright (c) 2017 Heinrich Schuchardt
*/
-#include <common.h>
#include <efi_loader.h>
/* Conversion factor from seconds to multiples of 100ns */
* clearing of the screen.
*/
-#include <common.h>
#include <efi_api.h>
#include <efi_load_initrd.h>
*
* Copyright (C) 2021 Arm Ltd.
*/
-#include <common.h>
#include <efi_loader.h>
#include <efi_selftest.h>
* This EFI application triggers an exception.
*/
-#include <common.h>
#include <efi_api.h>
#include <host_arch.h>
* It uses the Exit boot service to return.
*/
-#include <common.h>
#include <efi_selftest.h>
static efi_guid_t loaded_image_protocol_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
* It returns directly without calling the Exit boot service.
*/
-#include <common.h>
#include <efi_api.h>
/*
Copyright (c) 2001 William L. Pitts
*/
-#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <elf.h>
*
* SDPX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <errno.h>
+#include <linux/kernel.h>
#define ERRNO_MSG(errno, msg) msg
#define SAME_AS(x) (const char *)&errno_message[x]
*/
#ifndef USE_HOSTCC
-#include <common.h>
+
+#define LOG_CATEGORY LOGC_DT
+
+#include <bloblist.h>
#include <boot_fit.h>
#include <display_options.h>
#include <dm.h>
[FDTSRC_BOARD] = "board",
[FDTSRC_EMBED] = "embed",
[FDTSRC_ENV] = "env",
+ [FDTSRC_BLOBLIST] = "bloblist",
};
const char *fdtdec_get_srcname(void)
int fdtdec_setup(void)
{
- int ret;
+ int ret = -ENOENT;
+
+ /* If allowing a bloblist, check that first */
+ if (CONFIG_IS_ENABLED(BLOBLIST)) {
+ ret = bloblist_maybe_init();
+ if (!ret) {
+ gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0);
+ if (gd->fdt_blob) {
+ gd->fdt_src = FDTSRC_BLOBLIST;
+ log_debug("Devicetree is in bloblist at %p\n",
+ gd->fdt_blob);
+ } else {
+ log_debug("No FDT found in bloblist\n");
+ ret = -ENOENT;
+ }
+ }
+ }
- /* The devicetree is typically appended to U-Boot */
- if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
- gd->fdt_blob = fdt_find_separate();
- gd->fdt_src = FDTSRC_SEPARATE;
- } else { /* embed dtb in ELF file for testing / development */
- gd->fdt_blob = dtb_dt_embedded();
- gd->fdt_src = FDTSRC_EMBED;
+ /* Otherwise, the devicetree is typically appended to U-Boot */
+ if (ret) {
+ if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
+ gd->fdt_blob = fdt_find_separate();
+ gd->fdt_src = FDTSRC_SEPARATE;
+ } else { /* embed dtb in ELF file for testing / development */
+ gd->fdt_blob = dtb_dt_embedded();
+ gd->fdt_src = FDTSRC_EMBED;
+ }
}
/* Allow the board to override the fdt address. */
if (IS_ENABLED(CONFIG_OF_BOARD)) {
gd->fdt_blob = board_fdt_blob_setup(&ret);
- if (ret)
+ if (!ret)
+ gd->fdt_src = FDTSRC_BOARD;
+ else if (ret != -EEXIST)
return ret;
- gd->fdt_src = FDTSRC_BOARD;
}
/* Allow the early environment to override the fdt address */
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <log.h>
#include <linux/libfdt.h>
#include <fdtdec.h>
* Copyright (c) 2011 The Chromium OS Authors.
*/
-#include <common.h>
#include <command.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
#define LOG_CATEGORY LOGC_CORE
-#include <common.h>
#include <getopt.h>
#include <log.h>
+#include <linux/string.h>
void getopt_init_state(struct getopt_state *gs)
{
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <blk.h>
#include <command.h>
#include <console.h>
* Lei Wen <leiwen@marvell.com>, Marvell Inc.
*/
-#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <gzip.h>
* u-boot.
*/
-#include <common.h>
#include <bootstage.h>
#include <hang.h>
+#include <stdio.h>
#include <os.h>
/**
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <fdtdec.h>
#include <asm/byteorder.h>
#include <linux/errno.h>
# endif
# endif
#else /* U-Boot build */
-# include <common.h>
# include <linux/string.h>
# include <linux/ctype.h>
#endif
* more details.
*/
-#include <common.h>
#include <hexdump.h>
#include <mapmem.h>
+#include <vsprintf.h>
#include <linux/ctype.h>
#include <linux/compat.h>
#include <linux/log2.h>
*/
#include <config.h>
-#include <common.h>
#include <blk.h>
#include <image-sparse.h>
#include <div64.h>
* Copyright (c) 2013 The Chromium OS Authors.
*/
-#include <common.h>
#include <efi.h>
#include <initcall.h>
#include <log.h>
* like uint8_t, uint64_t, and bool (with |false|, |true| keywords)
* must be present.
*/
-#include <common.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <linux/types.h>
/* If you don't have gcc or clang, these attribute macros may need to
* be adjusted.
-#include <common.h>
#include <malloc.h>
#include <memalign.h>
#include <asm/cache.h>
#include <linux/slab.h>
#else
#include <linux/compat.h>
-#include <common.h>
#include <malloc.h>
#include <linux/printk.h>
#endif
* Copyright (C) 2001 Peter Bergner.
*/
-#include <common.h>
#include <efi_loader.h>
#include <image.h>
#include <mapmem.h>
* - LZ4 homepage : http://www.lz4.org
* - LZ4 source repository : https://github.com/lz4/lz4
*/
-#include <common.h>
#include <compiler.h>
#include <linux/kernel.h>
#include <linux/types.h>
* Copyright 2015 Google Inc.
*/
-#include <common.h>
#include <compiler.h>
#include <image.h>
#include <linux/kernel.h>
2009-09-20 : Igor Pavlov : Public domain */
#include <config.h>
-#include <common.h>
#include <watchdog.h>
#include "LzmaDec.h"
*/
#include <config.h>
-#include <common.h>
#include <log.h>
#include <watchdog.h>
* Richard Purdie <rpurdie@openedhand.com>
*/
-#include <common.h>
+#include <linux/kernel.h>
#include <linux/lzo.h>
+#include <linux/string.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include "lzodefs.h"
#include "compiler.h"
#ifndef USE_HOSTCC
-#include <common.h>
#include <watchdog.h>
#endif /* USE_HOSTCC */
#include <u-boot/md5.h>
* Copyright (c) 1992 Simon Glass
*/
-#include <common.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
* Copyright 2009 Dirk Behme, dirk.behme@googlemail.com
*/
-#include <common.h>
#include <net.h>
#include <net6.h>
+#include <vsprintf.h>
struct in_addr string_to_ip(const char *s)
{
#define LOG_CATEGORY LOGC_DT
-#include <common.h>
#include <abuf.h>
#include <log.h>
#include <linux/libfdt.h>
* Bryan O'Donoghue <bryan.odonoghue@linaro.org>
*/
-#include <common.h>
#include <fdtdec.h>
#include <image.h>
#include <log.h>
* Wirzenius wrote this portably, Torvalds fucked it up :-)
*/
-#include <common.h>
#include <hang.h>
#if !defined(CONFIG_PANIC_HANG)
#include <command.h>
* Software Foundation.
*/
-#include <common.h>
#include <log.h>
#include <mapmem.h>
#include <physmem.h>
#include <linux/compiler.h>
+#include <linux/string.h>
phys_addr_t __weak arch_phys_memset(phys_addr_t s, int c, phys_size_t n)
{
#include <log.h>
#include <linux/types.h>
-#include <common.h>
#include <exports.h>
#include <sort.h>
* Michael Walle <michael@walle.cc>
*/
-#include <common.h>
#include <rand.h>
static unsigned int y = 1U;
* Rivest Cipher 4 (RC4) implementation
*/
-#ifndef USE_HOSTCC
-#include <common.h>
-#endif
#include <rc4.h>
void rc4_encode(unsigned char *buf, unsigned int len, const unsigned char key[16])
* Copyright (c) 2016 Thomas Pornin <pornin@bolet.org>
*/
-#include <common.h>
#include <image.h>
#include <malloc.h>
#include <crypto/internal/rsa.h>
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/types.h>
if (keydir)
if (strstr(keydir, "object="))
snprintf(key_id, sizeof(key_id),
- "pkcs11:%s;type=public",
+ "%s;type=public",
keydir);
else
snprintf(key_id, sizeof(key_id),
- "pkcs11:%s;object=%s;type=public",
+ "%s;object=%s;type=public",
keydir, name);
else
snprintf(key_id, sizeof(key_id),
- "pkcs11:object=%s;type=public",
+ "object=%s;type=public",
name);
} else if (engine_id) {
if (keydir)
if (keydir)
if (strstr(keydir, "object="))
snprintf(key_id, sizeof(key_id),
- "pkcs11:%s;type=private",
+ "%s;type=private",
keydir);
else
snprintf(key_id, sizeof(key_id),
- "pkcs11:%s;object=%s;type=private",
+ "%s;object=%s;type=private",
keydir, name);
else
snprintf(key_id, sizeof(key_id),
- "pkcs11:object=%s;type=private",
+ "object=%s;type=private",
name);
} else if (engine_id) {
if (keydir && name)
e = ENGINE_by_id(engine_id);
if (!e) {
- fprintf(stderr, "Engine isn't available\n");
+ fprintf(stderr, "Engine '%s' isn't available\n", engine_id);
+ ERR_print_errors_fp(stderr);
return -1;
}
*/
#ifndef USE_HOSTCC
-#include <common.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
#else
#include "fdt_host.h"
#include "mkimage.h"
+#include <linux/kconfig.h>
#include <fdt_support.h>
#endif
-#include <linux/kconfig.h>
#include <u-boot/rsa-mod-exp.h>
#include <u-boot/rsa.h>
* - January is month 1.
*/
-#include <common.h>
#include <rtc.h>
#include <linux/math64.h>
* Copyright 2014 Broadcom Corporation
*/
-#include <common.h>
#include <log.h>
#include <semihosting.h>
+#include <linux/errno.h>
+#include <linux/string.h>
#define SYSOPEN 0x01
#define SYSCLOSE 0x02
#endif
#ifndef USE_HOSTCC
-#include <common.h>
-#include <linux/string.h>
-#else
-#include <string.h>
+#include <cyclic.h>
#endif /* USE_HOSTCC */
-#include <watchdog.h>
+#include <string.h>
#include <u-boot/sha1.h>
#include <linux/compiler_attributes.h>
*/
#ifndef USE_HOSTCC
-#include <common.h>
-#include <linux/string.h>
-#else
-#include <string.h>
+#include <cyclic.h>
#endif /* USE_HOSTCC */
-#include <watchdog.h>
+#include <string.h>
#include <u-boot/sha256.h>
#include <linux/compiler_attributes.h>
*/
#ifndef USE_HOSTCC
-#include <common.h>
-#include <linux/string.h>
-#else
-#include <string.h>
+#include <cyclic.h>
#endif /* USE_HOSTCC */
#include <compiler.h>
-#include <watchdog.h>
#include <u-boot/sha512.h>
const uint8_t sha384_der_prefix[SHA384_DER_LEN] = {
#include <string.h>
#else
#include <log.h>
-#include <common.h>
#include <linux/ctype.h>
+#include <linux/string.h>
#endif /* SLRE_TEST */
#include <errno.h>
}
if (!slre_compile(&slre, argv[1])) {
+ (void) fclose(fp);
fprintf(stderr, "Error compiling slre: %s\n", slre.err_str);
return 1;
}
#define LOG_CATEGORY LOGC_BOOT
-#include <common.h>
#include <smbios.h>
static inline int verify_checksum(const struct smbios_entry *e)
* Adapted from coreboot src/arch/x86/smbios.c
*/
-#include <common.h>
#include <dm.h>
#include <env.h>
#include <linux/stringify.h>
+#include <linux/string.h>
#include <mapmem.h>
#include <smbios.h>
#include <sysinfo.h>
#include <tables_csum.h>
#include <version.h>
+#include <malloc.h>
+#include <dm/ofnode.h>
#ifdef CONFIG_CPU
#include <cpu.h>
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * struct map_sysinfo - Mapping of sysinfo strings to DT
+ *
+ * @sysinfo_str: sysinfo string
+ * @dt_str: DT string
+ * @max: Max index of the tokenized string to pick. Counting starts from 0
+ *
+ */
+struct map_sysinfo {
+ const char *sysinfo_str;
+ const char *dt_str;
+ int max;
+};
+
+static const struct map_sysinfo sysinfo_to_dt[] = {
+ { .sysinfo_str = "product", .dt_str = "model", 2 },
+ { .sysinfo_str = "manufacturer", .dt_str = "compatible", 1 },
+};
+
/**
* struct smbios_ctx - context for writing SMBIOS tables
*
const char *subnode_name;
};
+static const struct map_sysinfo *convert_sysinfo_to_dt(const char *sysinfo_str)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sysinfo_to_dt); i++) {
+ if (!strcmp(sysinfo_str, sysinfo_to_dt[i].sysinfo_str))
+ return &sysinfo_to_dt[i];
+ }
+
+ return NULL;
+}
+
/**
* smbios_add_string() - add a string to the string area
*
int i = 1;
char *p = ctx->eos;
- if (!*str)
- str = "Unknown";
-
for (;;) {
if (!*p) {
ctx->last_str = p;
}
}
+/**
+ * get_str_from_dt - Get a substring from a DT property.
+ * After finding the property in the DT, the function
+ * will parse comma-separated values and return the value.
+ * If nprop->max exceeds the number of comma-separated
+ * elements, the last non NULL value will be returned.
+ * Counting starts from zero.
+ *
+ * @nprop: sysinfo property to use
+ * @str: pointer to fill with data
+ * @size: str buffer length
+ */
+static
+void get_str_from_dt(const struct map_sysinfo *nprop, char *str, size_t size)
+{
+ const char *dt_str;
+ int cnt = 0;
+ char *token;
+
+ memset(str, 0, size);
+ if (!nprop || !nprop->max)
+ return;
+
+ dt_str = ofnode_read_string(ofnode_root(), nprop->dt_str);
+ if (!dt_str)
+ return;
+
+ memcpy(str, dt_str, size);
+ token = strtok(str, ",");
+ while (token && cnt < nprop->max) {
+ strlcpy(str, token, strlen(token) + 1);
+ token = strtok(NULL, ",");
+ cnt++;
+ }
+}
+
/**
* smbios_add_prop_si() - Add a property from the devicetree or sysinfo
*
*
* @ctx: context for writing the tables
* @prop: property to write
+ * @dval: Default value to use if the string is not found or is empty
* Return: 0 if not found, else SMBIOS string number (1 or more)
*/
static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop,
- int sysinfo_id)
+ int sysinfo_id, const char *dval)
{
+ int ret;
+
+ if (!dval || !*dval)
+ dval = "Unknown";
+
+ if (!prop)
+ return smbios_add_string(ctx, dval);
+
if (sysinfo_id && ctx->dev) {
char val[SMBIOS_STR_MAX];
- int ret;
ret = sysinfo_get_str(ctx->dev, sysinfo_id, sizeof(val), val);
if (!ret)
return smbios_add_string(ctx, val);
}
if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- const char *str;
+ const char *str = NULL;
+ char str_dt[128] = { 0 };
+ /*
+ * If the node is not valid fallback and try the entire DT
+ * so we can at least fill in manufacturer and board type
+ */
+ if (ofnode_valid(ctx->node)) {
+ str = ofnode_read_string(ctx->node, prop);
+ } else {
+ const struct map_sysinfo *nprop;
+
+ nprop = convert_sysinfo_to_dt(prop);
+ get_str_from_dt(nprop, str_dt, sizeof(str_dt));
+ str = (const char *)str_dt;
+ }
- str = ofnode_read_string(ctx->node, prop);
- if (str)
- return smbios_add_string(ctx, str);
+ ret = smbios_add_string(ctx, str && *str ? str : dval);
+ return ret;
}
return 0;
/**
* smbios_add_prop() - Add a property from the devicetree
*
- * @prop: property to write
+ * @prop: property to write. The default string will be written if
+ * prop is NULL
+ * @dval: Default value to use if the string is not found or is empty
* Return: 0 if not found, else SMBIOS string number (1 or more)
*/
-static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop)
+static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop,
+ const char *dval)
{
- return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE);
+ return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval);
}
static void smbios_set_eos(struct smbios_ctx *ctx, char *eos)
memset(t, 0, sizeof(struct smbios_type0));
fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
- t->vendor = smbios_add_string(ctx, "U-Boot");
+ t->vendor = smbios_add_prop(ctx, NULL, "U-Boot");
- t->bios_ver = smbios_add_prop(ctx, "version");
- if (!t->bios_ver)
- t->bios_ver = smbios_add_string(ctx, PLAIN_VERSION);
+ t->bios_ver = smbios_add_prop(ctx, "version", PLAIN_VERSION);
if (t->bios_ver)
gd->smbios_version = ctx->last_str;
log_debug("smbios_version = %p: '%s'\n", gd->smbios_version,
print_buffer((ulong)gd->smbios_version, gd->smbios_version,
1, strlen(gd->smbios_version) + 1, 0);
#endif
- t->bios_release_date = smbios_add_string(ctx, U_BOOT_DMI_DATE);
+ t->bios_release_date = smbios_add_prop(ctx, NULL, U_BOOT_DMI_DATE);
#ifdef CONFIG_ROM_SIZE
t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1;
#endif
memset(t, 0, sizeof(struct smbios_type1));
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
- t->manufacturer = smbios_add_prop(ctx, "manufacturer");
- if (!t->manufacturer)
- t->manufacturer = smbios_add_string(ctx, "Unknown");
- t->product_name = smbios_add_prop(ctx, "product");
- if (!t->product_name)
- t->product_name = smbios_add_string(ctx, "Unknown Product");
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown");
+ t->product_name = smbios_add_prop(ctx, "product", "Unknown");
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_SYSTEM_VERSION);
+ SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
+ "Unknown");
if (serial_str) {
- t->serial_number = smbios_add_string(ctx, serial_str);
+ t->serial_number = smbios_add_prop(ctx, NULL, serial_str);
strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
} else {
- t->serial_number = smbios_add_prop(ctx, "serial");
+ t->serial_number = smbios_add_prop(ctx, "serial", "Unknown");
}
- t->sku_number = smbios_add_prop(ctx, "sku");
- t->family = smbios_add_prop(ctx, "family");
+ t->sku_number = smbios_add_prop(ctx, "sku", "Unknown");
+ t->family = smbios_add_prop(ctx, "family", "Unknown");
len = t->length + smbios_string_table_len(ctx);
*current += len;
memset(t, 0, sizeof(struct smbios_type2));
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
- t->manufacturer = smbios_add_prop(ctx, "manufacturer");
- if (!t->manufacturer)
- t->manufacturer = smbios_add_string(ctx, "Unknown");
- t->product_name = smbios_add_prop(ctx, "product");
- if (!t->product_name)
- t->product_name = smbios_add_string(ctx, "Unknown Product");
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown");
+ t->product_name = smbios_add_prop(ctx, "product", "Unknown");
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_BASEBOARD_VERSION);
- t->asset_tag_number = smbios_add_prop(ctx, "asset-tag");
+ SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
+ "Unknown");
+ t->asset_tag_number = smbios_add_prop(ctx, "asset-tag", "Unknown");
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
memset(t, 0, sizeof(struct smbios_type3));
fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
smbios_set_eos(ctx, t->eos);
- t->manufacturer = smbios_add_prop(ctx, "manufacturer");
- if (!t->manufacturer)
- t->manufacturer = smbios_add_string(ctx, "Unknown");
+ t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown");
t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
t->bootup_state = SMBIOS_STATE_SAFE;
t->power_supply_state = SMBIOS_STATE_SAFE;
#endif
t->processor_family = processor_family;
- t->processor_manufacturer = smbios_add_string(ctx, vendor);
- t->processor_version = smbios_add_string(ctx, name);
+ t->processor_manufacturer = smbios_add_prop(ctx, NULL, vendor);
+ t->processor_version = smbios_add_prop(ctx, NULL, name);
}
static int smbios_write_type4(ulong *current, int handle,
ulong write_smbios_table(ulong addr)
{
ofnode parent_node = ofnode_null();
- struct smbios_entry *se;
+ ulong table_addr, start_addr;
+ struct smbios3_entry *se;
struct smbios_ctx ctx;
- ulong table_addr;
ulong tables;
int len = 0;
int max_struct_size = 0;
int handle = 0;
- char *istart;
- int isize;
int i;
ctx.node = ofnode_null();
ctx.dev = NULL;
}
- /* 16 byte align the table address */
- addr = ALIGN(addr, 16);
+ start_addr = addr;
- se = map_sysmem(addr, sizeof(struct smbios_entry));
- memset(se, 0, sizeof(struct smbios_entry));
-
- addr += sizeof(struct smbios_entry);
- addr = ALIGN(addr, 16);
+ /* move past the (so-far-unwritten) header to start writing structs */
+ addr = ALIGN(addr + sizeof(struct smbios3_entry), 16);
tables = addr;
/* populate minimum required tables */
len += tmp;
}
- memcpy(se->anchor, "_SM_", 4);
- se->length = sizeof(struct smbios_entry);
- se->major_ver = SMBIOS_MAJOR_VER;
- se->minor_ver = SMBIOS_MINOR_VER;
- se->max_struct_size = max_struct_size;
- memcpy(se->intermediate_anchor, "_DMI_", 5);
- se->struct_table_length = len;
-
/*
* We must use a pointer here so things work correctly on sandbox. The
* user of this table is not aware of the mapping of addresses to
* sandbox's DRAM buffer.
*/
table_addr = (ulong)map_sysmem(tables, 0);
- if (sizeof(table_addr) > sizeof(u32) && table_addr > (ulong)UINT_MAX) {
- /*
- * We need to put this >32-bit pointer into the table but the
- * field is only 32 bits wide.
- */
- printf("WARNING: SMBIOS table_address overflow %llx\n",
- (unsigned long long)table_addr);
- addr = 0;
- goto out;
- }
- se->struct_table_address = table_addr;
-
- se->struct_count = handle;
- /* calculate checksums */
- istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET;
- isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET;
- se->intermediate_checksum = table_compute_checksum(istart, isize);
- se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry));
-out:
+ /* now go back and write the SMBIOS3 header */
+ se = map_sysmem(start_addr, sizeof(struct smbios_entry));
+ memset(se, '\0', sizeof(struct smbios_entry));
+ memcpy(se->anchor, "_SM3_", 5);
+ se->length = sizeof(struct smbios3_entry);
+ se->major_ver = SMBIOS_MAJOR_VER;
+ se->minor_ver = SMBIOS_MINOR_VER;
+ se->doc_rev = 0;
+ se->entry_point_rev = 1;
+ se->max_struct_size = len;
+ se->struct_table_address = table_addr;
+ se->checksum = table_compute_checksum(se, sizeof(struct smbios3_entry));
unmap_sysmem(se);
return addr;
* Wirzenius wrote this portably, Torvalds fucked it up :-)
*/
-#include <common.h>
#include <errno.h>
#include <malloc.h>
+#include <vsprintf.h>
#include <linux/ctype.h>
/* from lib/kstrtox.c */
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
-#include <common.h>
-#include <linux/ctype.h>
+#include <linux/types.h>
u8 table_compute_checksum(void *v, int len)
{
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <clock_legacy.h>
#include <bootstage.h>
#include <dm.h>
* Copyright (C) 2004,2008 Kustaa Nyholm
*/
-#include <common.h>
#include <log.h>
#include <serial.h>
#include <stdarg.h>
#define LOG_CATEGORY UCLASS_TPM
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/unaligned.h>
#define LOG_CATEGORY UCLASS_TPM
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/unaligned.h>
* Author: Miquel Raynal <miquel.raynal@bootlin.com>
*/
-#include <common.h>
#include <dm.h>
#include <dm/of_access.h>
#include <tpm_api.h>
* Copyright 2019 Google LLC
*/
-#include <common.h>
#include <dm.h>
#include <log.h>
#include <tpm_api.h>
* Copyright (c) 2012 The Chromium OS Authors.
*/
-#include <common.h>
#include <mapmem.h>
#include <time.h>
#include <trace.h>
+#include <linux/errno.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
#define LOG_CATEGOT LOGC_CORE
-#include <common.h>
#include <command.h>
#include <efi_api.h>
#include <env.h>
#include <uuid.h>
#include <linux/ctype.h>
#include <errno.h>
-#include <common.h>
#include <asm/io.h>
#include <part_efi.h>
#include <malloc.h>
* from hush: simple_itoa() was lifted from boa-0.93.15
*/
-#include <common.h>
#include <charset.h>
#include <efi_loader.h>
#include <div64.h>
#ifndef __GLUE_ZLIB_H__
#define __GLUE_ZLIB_H__
-#include <common.h>
#include <linux/compiler.h>
#include <asm/unaligned.h>
#include <watchdog.h>
#define LOG_CATEGORY LOGC_BOOT
-#include <common.h>
#include <abuf.h>
#include <log.h>
#include <malloc.h>
+#include <linux/errno.h>
#include <linux/zstd.h>
int zstd_decompress(struct abuf *in, struct abuf *out)
menuconfig NET
bool "Networking support"
default y
+ imply NETDEVICES
if NET
bool "NetConsole support"
help
Support the 'nc' input/output device for networked console.
- See README.NetConsole for details.
+ See doc/usage/netconsole.rst for details.
config IP_DEFRAG
bool "Support IP datagram reassembly"
#ifndef __ARP_H__
#define __ARP_H__
-#include <common.h>
-
extern struct in_addr net_arp_wait_packet_ip;
/* MAC address of waiting packet's destination */
extern uchar *arp_wait_packet_ethaddr;
* Licensed under the GPL v2 or later
*/
-#if defined(CONFIG_CMD_LINK_LOCAL)
-
#ifndef __LINK_LOCAL_H__
#define __LINK_LOCAL_H__
-#include <common.h>
+struct arp_hdr;
void link_local_receive_arp(struct arp_hdr *arp, int len);
void link_local_start(void);
#endif /* __LINK_LOCAL_H__ */
-#endif
#ifndef __NET_RAND_H__
#define __NET_RAND_H__
-#include <common.h>
#include <dm/uclass.h>
#include <rng.h>
#ifndef __PING_H__
#define __PING_H__
-#include <common.h>
#include <net.h>
/*
* Copyright Duncan Hare <dh@synoia.com> 2017
*/
+#include <asm/global_data.h>
#include <command.h>
#include <common.h>
#include <display_options.h>
#include <env.h>
#include <image.h>
+#include <lmb.h>
#include <mapmem.h>
#include <net.h>
#include <net/tcp.h>
#include <net/wget.h>
+#include <stdlib.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The default, change with environment variable 'httpdstp' */
+#define SERVER_PORT 80
static const char bootfile1[] = "GET ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */
static int retry_len; /* TCP retry length */
+static ulong wget_load_size;
+
+/**
+ * wget_init_max_size() - initialize maximum load size
+ *
+ * Return: 0 if success, -1 if fails
+ */
+static int wget_init_load_size(void)
+{
+ struct lmb lmb;
+ phys_size_t max_size;
+
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
+ max_size = lmb_get_free_size(&lmb, image_load_addr);
+ if (!max_size)
+ return -1;
+
+ wget_load_size = max_size;
+
+ return 0;
+}
+
/**
* store_block() - store block in memory
* @src: source of data
*/
static inline int store_block(uchar *src, unsigned int offset, unsigned int len)
{
+ ulong store_addr = image_load_addr + offset;
ulong newsize = offset + len;
uchar *ptr;
- ptr = map_sysmem(image_load_addr + offset, len);
+ if (IS_ENABLED(CONFIG_LMB)) {
+ ulong end_addr = image_load_addr + wget_load_size;
+
+ if (!end_addr)
+ end_addr = ULONG_MAX;
+
+ if (store_addr < image_load_addr ||
+ store_addr + len > end_addr) {
+ printf("\nwget error: ");
+ printf("trying to overwrite reserved memory...\n");
+ return -1;
+ }
+ }
+
+ ptr = map_sysmem(store_addr, len);
memcpy(ptr, src, len);
unmap_sysmem(ptr);
int len = retry_len;
unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len);
unsigned int tcp_seq_num = retry_tcp_ack_num;
+ unsigned int server_port;
uchar *ptr, *offset;
+ server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff;
+
switch (current_wget_state) {
case WGET_CLOSED:
debug_cond(DEBUG_WGET, "wget: send SYN\n");
current_wget_state = WGET_CONNECTING;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
packets = 0;
break;
case WGET_CONNECTING:
pkt_q_idx = 0;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
ptr = net_tx_packet + net_eth_hdr_size() +
memcpy(offset, &bootfile3, strlen(bootfile3));
offset += strlen(bootfile3);
- net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port,
+ net_send_tcp_packet((offset - ptr), server_port, our_port,
TCP_PUSH, tcp_seq_num, tcp_ack_num);
current_wget_state = WGET_CONNECTED;
break;
case WGET_CONNECTED:
case WGET_TRANSFERRING:
case WGET_TRANSFERRED:
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
break;
}
net_boot_file_size = 0;
- if (len > hlen)
- store_block(pkt + hlen, 0, len - hlen);
+ if (len > hlen) {
+ if (store_block(pkt + hlen, 0, len - hlen) != 0) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ }
debug_cond(DEBUG_WGET,
"wget: Connected Pkt %p hlen %x\n",
pkt, hlen);
for (i = 0; i < pkt_q_idx; i++) {
+ int err;
+
ptr1 = map_sysmem(
(phys_addr_t)(pkt_q[i].pkt),
pkt_q[i].len);
- store_block(ptr1,
- pkt_q[i].tcp_seq_num -
- initial_data_seq_num,
- pkt_q[i].len);
+ err = store_block(ptr1,
+ pkt_q[i].tcp_seq_num -
+ initial_data_seq_num,
+ pkt_q[i].len);
unmap_sysmem(ptr1);
debug_cond(DEBUG_WGET,
"wget: Connctd pkt Q %p len %x\n",
pkt_q[i].pkt, pkt_q[i].len);
+ if (err) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
}
}
}
len) != 0) {
wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
return;
}
debug_cond(DEBUG_WGET,
"\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr);
+ if (IS_ENABLED(CONFIG_LMB)) {
+ if (wget_init_load_size()) {
+ printf("\nwget error: ");
+ printf("trying to overwrite reserved memory...\n");
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ }
+
net_set_timeout_handler(wget_timeout, wget_timeout_handler);
tcp_set_tcp_handler(wget_handler);
wget_send(TCP_SYN, 0, 0, 0);
}
+
+#if (IS_ENABLED(CONFIG_CMD_DNS))
+int wget_with_dns(ulong dst_addr, char *uri)
+{
+ int ret;
+ char *s, *host_name, *file_name, *str_copy;
+
+ /*
+ * Download file using wget.
+ *
+ * U-Boot wget takes the target uri in this format.
+ * "<http server ip>:<file path>" e.g.) 192.168.1.1:/sample/test.iso
+ * Need to resolve the http server ip address before starting wget.
+ */
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return -ENOMEM;
+
+ s = str_copy + strlen("http://");
+ host_name = strsep(&s, "/");
+ if (!s) {
+ log_err("Error: invalied uri, no file path\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ file_name = s;
+
+ /* TODO: If the given uri has ip address for the http server, skip dns */
+ net_dns_resolve = host_name;
+ net_dns_env_var = "httpserverip";
+ if (net_loop(DNS) < 0) {
+ log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve);
+ ret = -EINVAL;
+ goto out;
+ }
+ s = env_get("httpserverip");
+ if (!s) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name));
+ strlcat(net_boot_file_name, ":/", sizeof(net_boot_file_name)); /* append '/' which is removed by strsep() */
+ strlcat(net_boot_file_name, file_name, sizeof(net_boot_file_name));
+ image_load_addr = dst_addr;
+ ret = net_loop(WGET);
+
+out:
+ free(str_copy);
+
+ return ret;
+}
+#endif
+
+/**
+ * wget_validate_uri() - validate the uri for wget
+ *
+ * @uri: uri string
+ *
+ * This function follows the current U-Boot wget implementation.
+ * scheme: only "http:" is supported
+ * authority:
+ * - user information: not supported
+ * - host: supported
+ * - port: not supported(always use the default port)
+ *
+ * Uri is expected to be correctly percent encoded.
+ * This is the minimum check, control codes(0x1-0x19, 0x7F, except '\0')
+ * and space character(0x20) are not allowed.
+ *
+ * TODO: stricter uri conformance check
+ *
+ * Return: true on success, false on failure
+ */
+bool wget_validate_uri(char *uri)
+{
+ char c;
+ bool ret = true;
+ char *str_copy, *s, *authority;
+
+ for (c = 0x1; c < 0x21; c++) {
+ if (strchr(uri, c)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+ }
+ if (strchr(uri, 0x7f)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+
+ if (strncmp(uri, "http://", 7)) {
+ log_err("only http:// is supported\n");
+ return false;
+ }
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return false;
+
+ s = str_copy + strlen("http://");
+ authority = strsep(&s, "/");
+ if (!s) {
+ log_err("invalid uri, no file path\n");
+ ret = false;
+ goto out;
+ }
+ s = strchr(authority, '@');
+ if (s) {
+ log_err("user information is not supported\n");
+ ret = false;
+ goto out;
+ }
+ s = strchr(authority, ':');
+ if (s) {
+ log_err("user defined port is not supported\n");
+ ret = false;
+ goto out;
+ }
+
+out:
+ free(str_copy);
+
+ return ret;
+}
$(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@)
$(obj)/.capsule_esl.dtsi: FORCE
+ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"")
+ $(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \
+ public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled")
+else
$(call cmd_capsule_esl_gen)
+endif
capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in
capsule_esl_dtsi = .capsule_esl.dtsi
fdtgrep_props := -b bootph-all -b bootph-pre-ram $(migrate_spl)
endif
endif
+
+# This rule produces the .dtb for an SPL build.
+#
+# The first fdtgrep keeps nodes with the above properties (with -u ensuring that
+# the properties are implied in all parents of a matching node). The root node
+# is always included, along with /chosen and /config nodes. Referenced aliases
+# (i.e. properties in /aliases which point to an incldued node) are also
+# included.
+#
+# The second fdtgrep removes all bootph properties along with unused strings
+# and any properties in CONFIG_OF_SPL_REMOVE_PROPS
quiet_cmd_fdtgrep = FDTGREP $@
- cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \
+ cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -u -RT $< \
-n /chosen -n /config -O dtb | \
$(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
-P bootph-all -P bootph-pre-ram -P bootph-pre-sram \
# - we have either OF_SEPARATE or OF_HOSTFILE
build_dtb :=
ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),)
-ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_SANDBOX),y)
+ifneq ($(CONFIG_OF_SEPARATE)$(CONFIG_SANDBOX),)
build_dtb := y
endif
endif
# Non-empty to do the actual upload
upload=1
+# Non-empty to delete files used for testing
+delete_testfiles=1
+
tool="$1"
shift
flags="$*"
if [[ "${tool}" =~ ^(patman|buildman|dtoc|binman|u_boot_pylib)$ ]]; then
echo "Building dist package for tool ${tool}"
else
- echo "Unknown tool ${tool}: use patman, buildman, dtoc or binman"
+ echo "Unknown tool ${tool}: use u_boot_pylib, patman, buildman, dtoc or binman"
exit 1
fi
fi
fi
+if [[ "${tool}" =~ ^(patman|u_boot_pylib)$ ]]; then
+ # Leave test_util.py and patman test files alone
+ delete_testfiles=
+fi
+
# Create a temp dir to work in
dir=$(mktemp -d)
find ${dest} -depth -name __pycache__ -exec rmdir 112 \;
# Remove test files
-rm -rf ${dest}/*test*
+if [ -n "${delete_testfiles}" ]; then
+ rm -rfv ${dest}/*test*
+fi
mkdir ${dir}/tests
cd ${dir}
config UNIT_TEST
bool "Unit tests"
+ depends on CMDLINE
help
Select this to compile in unit tests for various parts of
U-Boot. Test suites will be subcommands of the "ut" command.
config UT_LIB_ASN1
bool "Unit test for asn1 compiler and decoder function"
+ depends on SANDBOX
default y
imply ASYMMETRIC_KEY_TYPE
imply ASYMMETRIC_PUBLIC_KEY_SUBTYPE
endif
+config UT_BOOTSTD
+ bool "Unit tests for standard boot"
+ depends on UNIT_TEST && SANDBOX
+ default y
+
config UT_COMPRESSION
bool "Unit test for compression"
depends on UNIT_TEST
ifndef CONFIG_SANDBOX_VPL
obj-$(CONFIG_UNIT_TEST) += lib/
endif
+ifneq ($(CONFIG_HUSH_PARSER),)
+obj-$(CONFIG_$(SPL_)CMDLINE) += hush/
+endif
obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o
obj-$(CONFIG_UT_TIME) += time_ut.o
obj-y += ut.o
ifeq ($(CONFIG_SPL_BUILD),)
-obj-$(CONFIG_UNIT_TEST) += boot/
+obj-$(CONFIG_$(SPL_)UT_BOOTSTD) += boot/
obj-$(CONFIG_UNIT_TEST) += common/
obj-y += log/
obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o
hdr = clear_bloblist();
ut_asserteq(-ENOENT, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
ut_asserteq_ptr(NULL, bloblist_check_magic(TEST_ADDR));
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
ut_asserteq_ptr(hdr, bloblist_check_magic(TEST_ADDR));
hdr->version++;
ut_asserteq(-EPROTONOSUPPORT, bloblist_check(TEST_ADDR,
TEST_BLOBLIST_SIZE));
- ut_asserteq(-ENOSPC, bloblist_new(TEST_ADDR, 0x10, 0));
- ut_asserteq(-EFAULT, bloblist_new(1, TEST_BLOBLIST_SIZE, 0));
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_asserteq(-ENOSPC, bloblist_new(TEST_ADDR, 0xc, 0, 0));
+ ut_asserteq(-EFAULT, bloblist_new(1, TEST_BLOBLIST_SIZE, 0, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
ut_assertok(bloblist_finish());
/* At the start there should be no records */
hdr = clear_bloblist();
ut_assertnull(bloblist_find(TEST_TAG, TEST_BLOBLIST_SIZE));
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
- ut_asserteq(TEST_BLOBLIST_SIZE, bloblist_get_size());
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
+ ut_asserteq(sizeof(struct bloblist_hdr), bloblist_get_size());
+ ut_asserteq(TEST_BLOBLIST_SIZE, bloblist_get_total_size());
ut_asserteq(TEST_ADDR, bloblist_get_base());
ut_asserteq(map_to_sysmem(hdr), TEST_ADDR);
/* At the start there should be no records */
clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
/* Test with an empty bloblist */
size = TEST_SIZE;
void *data;
hdr = clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
data = hdr + 1;
data += sizeof(struct bloblist_rec);
ut_asserteq_addr(data, bloblist_ensure(TEST_TAG, TEST_SIZE));
char *data, *data2;
hdr = clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
ut_assertok(bloblist_finish());
ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
hdr->flags++;
- hdr->size--;
+ hdr->total_size--;
ut_asserteq(-EFBIG, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
- hdr->size++;
+ hdr->total_size++;
hdr->spare++;
ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
hdr->chksum--;
+ hdr->align_log2++;
+ ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
+ hdr->align_log2--;
+
/* Make sure the checksum changes when we add blobs */
data = bloblist_add(TEST_TAG, TEST_SIZE, 0);
ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
*data2 -= 1;
/*
- * Changing data outside the range of valid data should not affect
- * the checksum.
+ * Changing data outside the range of valid data should affect the
+ * checksum.
*/
ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
data[TEST_SIZE]++;
+ ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
+ data[TEST_SIZE]--;
+ ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
+
data2[TEST_SIZE2]++;
+ ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
+ data[TEST_SIZE]--;
ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE));
return 0;
char *data, *data2;
hdr = clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
ut_silence_console(uts);
console_record_reset();
run_command("bloblist info", 0);
- ut_assert_nextline("base: %lx", (ulong)map_to_sysmem(hdr));
- ut_assert_nextline("size: 400 1 KiB");
- ut_assert_nextline("alloced: 70 112 Bytes");
- ut_assert_nextline("free: 390 912 Bytes");
+ ut_assert_nextline("base: %lx", (ulong)map_to_sysmem(hdr));
+ ut_assert_nextline("total size: 400 1 KiB");
+ ut_assert_nextline("used size: 50 80 Bytes");
+ ut_assert_nextline("free: 3b0 944 Bytes");
ut_assert_console_end();
ut_unsilence_console(uts);
char *data, *data2;
hdr = clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
console_record_reset();
run_command("bloblist list", 0);
ut_assert_nextline("Address Size Tag Name");
- ut_assert_nextline("%08lx %8x 8000 SPL hand-off",
+ ut_assert_nextline("%08lx %8x fff000 SPL hand-off",
(ulong)map_to_sysmem(data), TEST_SIZE);
- ut_assert_nextline("%08lx %8x 106 Chrome OS vboot context",
+ ut_assert_nextline("%08lx %8x 202 Chrome OS vboot context",
(ulong)map_to_sysmem(data2), TEST_SIZE2);
ut_assert_console_end();
ut_unsilence_console(uts);
/* At the start there should be no records */
hdr = clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
ut_assertnull(bloblist_find(TEST_TAG, TEST_BLOBLIST_SIZE));
/* Check the default alignment */
data = bloblist_add(i, size, 0);
ut_assertnonnull(data);
addr = map_to_sysmem(data);
- ut_asserteq(0, addr & (BLOBLIST_ALIGN - 1));
+ ut_asserteq(0, addr & (BLOBLIST_BLOB_ALIGN - 1));
/* Only the bytes in the blob data should be zeroed */
for (j = 0; j < size; j++)
ut_asserteq(0, data[j]);
- for (; j < BLOBLIST_ALIGN; j++)
+ for (; j < BLOBLIST_BLOB_ALIGN; j++)
ut_asserteq(ERASE_BYTE, data[j]);
}
/* Check larger alignment */
for (i = 0; i < 3; i++) {
- int align = 32 << i;
+ int align = 5 - i;
data = bloblist_add(3 + i, i * 4, align);
ut_assertnonnull(data);
}
/* Check alignment with an bloblist starting on a smaller alignment */
- hdr = map_sysmem(TEST_ADDR + BLOBLIST_ALIGN, TEST_BLOBLIST_SIZE);
+ hdr = map_sysmem(TEST_ADDR + BLOBLIST_BLOB_ALIGN, TEST_BLOBLIST_SIZE);
memset(hdr, ERASE_BYTE, TEST_BLOBLIST_SIZE);
memset(hdr, '\0', sizeof(*hdr));
ut_assertok(bloblist_new(TEST_ADDR + BLOBLIST_ALIGN, TEST_BLOBLIST_SIZE,
- 0));
+ 0, 0));
- data = bloblist_add(1, 5, BLOBLIST_ALIGN * 2);
+ data = bloblist_add(1, 5, BLOBLIST_ALIGN_LOG2 + 1);
ut_assertnonnull(data);
addr = map_to_sysmem(data);
- ut_asserteq(0, addr & (BLOBLIST_ALIGN * 2 - 1));
+ ut_asserteq(0, addr & (BLOBLIST_BLOB_ALIGN * 2 - 1));
return 0;
}
ulong new_addr;
ulong new_size;
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
old_ptr = map_sysmem(TEST_ADDR, TEST_BLOBLIST_SIZE);
/* Add one blob and then one that won't fit */
memset(hdr, ERASE_BYTE, TEST_BLOBLIST_SIZE);
/* Create two blobs */
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
blob1 = bloblist_add(TEST_TAG, small_size, 0);
ut_assertnonnull(blob1);
ut_assertok(check_zero(blob1, small_size));
ut_asserteq(sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2,
- hdr->alloced);
+ hdr->used_size);
/* Resize the first one */
ut_assertok(bloblist_resize(TEST_TAG, small_size + 4));
hdr = ptr;
ut_asserteq(sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2 +
- BLOBLIST_ALIGN,
- hdr->alloced);
+ BLOBLIST_BLOB_ALIGN,
+ hdr->used_size);
return 0;
}
ptr = map_sysmem(TEST_ADDR, TEST_BLOBLIST_SIZE);
/* Create two blobs */
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
blob1 = bloblist_add(TEST_TAG, small_size, 0);
ut_assertnonnull(blob1);
strcpy(blob1, test1_str);
hdr = ptr;
ut_asserteq(sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2,
- hdr->alloced);
+ hdr->used_size);
/* Resize the first one */
new_size = small_size - BLOBLIST_ALIGN - 4;
ut_asserteq(sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2 -
BLOBLIST_ALIGN,
- hdr->alloced);
+ hdr->used_size);
return 0;
}
ptr = map_sysmem(TEST_ADDR, TEST_BLOBLIST_SIZE);
/* Create two blobs */
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
blob1 = bloblist_add(TEST_TAG, small_size, 0);
ut_assertnonnull(blob1);
hdr = ptr;
ut_asserteq(sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2,
- hdr->alloced);
+ hdr->used_size);
/* Resize the first one, to check the boundary conditions */
ut_asserteq(-EINVAL, bloblist_resize(TEST_TAG, -1));
- new_size = small_size + (hdr->size - hdr->alloced);
+ new_size = small_size + (hdr->total_size - hdr->used_size);
ut_asserteq(-ENOSPC, bloblist_resize(TEST_TAG, new_size + 1));
ut_assertok(bloblist_resize(TEST_TAG, new_size));
hdr = ptr;
/* Create two blobs */
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
blob1 = bloblist_add(TEST_TAG, small_size, 0);
ut_assertnonnull(blob1);
/* Check the byte after the last blob */
alloced_val = sizeof(struct bloblist_hdr) +
sizeof(struct bloblist_rec) * 2 + small_size * 2;
- ut_asserteq(alloced_val, hdr->alloced);
+ ut_asserteq(alloced_val, hdr->used_size);
ut_asserteq_ptr((void *)hdr + alloced_val, blob2 + small_size);
- ut_asserteq((u8)ERASE_BYTE, *((u8 *)hdr + hdr->alloced));
+ ut_asserteq((u8)ERASE_BYTE, *((u8 *)hdr + hdr->used_size));
/* Resize the second one, checking nothing changes */
ut_asserteq(0, bloblist_resize(TEST_TAG2, small_size + 4));
ut_asserteq((u8)ERASE_BYTE, *((u8 *)hdr + alloced_val + 4));
/* Check that the new top of the allocated blobs has not been touched */
- alloced_val += BLOBLIST_ALIGN;
- ut_asserteq(alloced_val, hdr->alloced);
- ut_asserteq((u8)ERASE_BYTE, *((u8 *)hdr + hdr->alloced));
+ alloced_val += BLOBLIST_BLOB_ALIGN;
+ ut_asserteq(alloced_val, hdr->used_size);
+ ut_asserteq((u8)ERASE_BYTE, *((u8 *)hdr + hdr->used_size));
return 0;
}
/* At the start there should be no records */
clear_bloblist();
- ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0));
+ ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0));
/* Add a blob that takes up all space */
size = TEST_BLOBLIST_SIZE - sizeof(struct bloblist_hdr) -
{
struct udevice *bootstd, *dev;
- if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR))
+ if (!IS_ENABLED(CONFIG_BOOTEFI_BOOTMGR))
return -EAGAIN;
ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr),
}
BOOTSTD_TEST(bootflow_cmd_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+/* Check 'bootflow scan -m' to select a bootflow using a menu */
+static int bootflow_scan_menu(struct unit_test_state *uts)
+{
+ struct bootstd_priv *std;
+ const char **old_order, **new_order;
+ char prev[3];
+
+ /* get access to the current bootflow */
+ ut_assertok(bootstd_get_priv(&std));
+
+ ut_assertok(prep_mmc_bootdev(uts, "mmc4", false, &old_order));
+
+ /* Add keypresses to move to and select the second one in the list */
+ prev[0] = CTL_CH('n');
+ prev[1] = '\r';
+ prev[2] = '\0';
+ ut_asserteq(2, console_in_puts(prev));
+
+ ut_assertok(run_command("bootflow scan -lm", 0));
+ new_order = std->bootdev_order;
+ std->bootdev_order = old_order;
+
+ ut_assert_skip_to_line("No more bootdevs");
+ ut_assert_nextlinen("--");
+ ut_assert_nextline("(2 bootflows, 2 valid)");
+
+ ut_assert_nextline("Selected: Armbian");
+ ut_assertnonnull(std->cur_bootflow);
+ ut_assert_console_end();
+
+ /* Check not selecting anything */
+ prev[0] = '\e';
+ prev[1] = '\0';
+ ut_asserteq(1, console_in_puts(prev));
+
+ std->bootdev_order = new_order; /* Blue Monday */
+ ut_assertok(run_command("bootflow scan -lm", 0));
+ std->bootdev_order = old_order;
+
+ ut_assertnull(std->cur_bootflow);
+ ut_assert_skip_to_line("(2 bootflows, 2 valid)");
+ ut_assert_nextline("Nothing chosen");
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_scan_menu,
+ UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+
+/* Check 'bootflow scan -mb' to select and boot a bootflow using a menu */
+static int bootflow_scan_menu_boot(struct unit_test_state *uts)
+{
+ struct bootstd_priv *std;
+ const char **old_order;
+ char prev[3];
+
+ /* get access to the current bootflow */
+ ut_assertok(bootstd_get_priv(&std));
+
+ ut_assertok(prep_mmc_bootdev(uts, "mmc4", false, &old_order));
+
+ /* Add keypresses to move to and select the second one in the list */
+ prev[0] = CTL_CH('n');
+ prev[1] = '\r';
+ prev[2] = '\0';
+ ut_asserteq(2, console_in_puts(prev));
+
+ ut_assertok(run_command("bootflow scan -lmb", 0));
+ std->bootdev_order = old_order;
+
+ ut_assert_skip_to_line("(2 bootflows, 2 valid)");
+
+ ut_assert_nextline("Selected: Armbian");
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ /*
+ * With old hush, despite booti failing to boot, i.e. returning
+ * CMD_RET_FAILURE, run_command() returns 0 which leads bootflow_boot(), as
+ * we are using bootmeth_script here, to return -EFAULT.
+ */
+ ut_assert_skip_to_line("Boot failed (err=-14)");
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * While with modern one, run_command() propagates CMD_RET_FAILURE returned
+ * by booti, so we get 1 here.
+ */
+ ut_assert_skip_to_line("Boot failed (err=1)");
+ }
+ ut_assertnonnull(std->cur_bootflow);
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_scan_menu_boot,
+ UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+
/* Check searching for a single bootdev using the hunters */
static int bootflow_cmd_hunt_single(struct unit_test_state *uts)
{
ut_asserteq(0, run_command("bootflow cmdline get mary", 0));
ut_assert_nextline_empty();
+ ut_asserteq(0, run_command("bootflow cmdline set mary abc", 0));
+ ut_asserteq(0, run_command("bootflow cmdline set mary", 0));
+ ut_assert_nextline_empty();
+
ut_assert_console_end();
return 0;
# Copyright (c) 2013 Google, Inc
# Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+obj-y += cmd_ut_cmd.o
+
ifdef CONFIG_HUSH_PARSER
obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
endif
end = base + size - 1;
flags = rgn->region[i].flags;
+ /*
+ * this entry includes the stack (get_sp()) on many platforms
+ * so will different each time lmb_init_and_reserve() is called.
+ * We could instead have the bdinfo command put its lmb region
+ * in a known location, so we can check it directly, rather than
+ * calling lmb_init_and_reserve() to create a new (and hopefully
+ * identical one). But for now this seems good enough.
+ */
+ if (!IS_ENABLED(CONFIG_SANDBOX) && i == 3) {
+ ut_assert_nextlinen(" %s[%d]\t[", name, i);
+ continue;
+ }
ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x",
name, i, base, end, size, flags);
}
static int lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb)
{
ut_assert_nextline("lmb_dump_all:");
- lmb_test_dump_region(uts, &lmb->memory, "memory");
- lmb_test_dump_region(uts, &lmb->reserved, "reserved");
+ ut_assertok(lmb_test_dump_region(uts, &lmb->memory, "memory"));
+ ut_assertok(lmb_test_dump_region(uts, &lmb->reserved, "reserved"));
return 0;
}
-static int bdinfo_test_move(struct unit_test_state *uts)
+static int bdinfo_check_mem(struct unit_test_state *uts)
{
struct bd_info *bd = gd->bd;
int i;
- /* Test moving the working BDINFO to a new location */
- ut_assertok(console_record_reset_enable());
- ut_assertok(run_commandf("bdinfo"));
-
- ut_assertok(test_num_l(uts, "boot_params", 0));
-
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
ut_assertok(test_num_l(uts, "DRAM bank", i));
}
}
+ return 0;
+}
+
+static int bdinfo_test_all(struct unit_test_state *uts)
+{
+ ut_assertok(test_num_l(uts, "boot_params", 0));
+
+ ut_assertok(bdinfo_check_mem(uts));
+
/* CONFIG_SYS_HAS_SRAM testing not supported */
ut_assertok(test_num_l(uts, "flashstart", 0));
ut_assertok(test_num_l(uts, "flashsize", 0));
ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size));
if (IS_ENABLED(CONFIG_VIDEO))
- test_video_info(uts);
+ ut_assertok(test_video_info(uts));
/* The gd->multi_dtb_fit may not be available, hence, #if below. */
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
struct lmb lmb;
lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
- lmb_test_dump_all(uts, &lmb);
+ ut_assertok(lmb_test_dump_all(uts, &lmb));
if (IS_ENABLED(CONFIG_OF_REAL))
ut_assert_nextline("devicetree = %s", fdtdec_get_srcname());
}
ut_assertok(test_num_l(uts, "malloc base", gd_malloc_start()));
}
+ if (IS_ENABLED(CONFIG_X86))
+ ut_check_skip_to_linen(uts, " high end =");
+
+ return 0;
+}
+
+static int bdinfo_test_full(struct unit_test_state *uts)
+{
+ /* Test BDINFO full print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo"));
+ ut_assertok(bdinfo_test_all(uts));
+ ut_assertok(run_commandf("bdinfo -a"));
+ ut_assertok(bdinfo_test_all(uts));
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_full, UT_TESTF_CONSOLE_REC);
+
+static int bdinfo_test_help(struct unit_test_state *uts)
+{
+ /* Test BDINFO unknown option help text print */
+ ut_assertok(console_record_reset_enable());
+ if (!CONFIG_IS_ENABLED(GETOPT)) {
+ ut_asserteq(0, run_commandf("bdinfo -h"));
+ ut_assertok(bdinfo_test_all(uts));
+ } else {
+ ut_asserteq(1, run_commandf("bdinfo -h"));
+ ut_assert_nextlinen("bdinfo: invalid option -- h");
+ ut_assert_nextlinen("bdinfo - print Board Info structure");
+ ut_assert_nextline_empty();
+ ut_assert_nextlinen("Usage:");
+ ut_assert_nextlinen("bdinfo");
+ }
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_help, UT_TESTF_CONSOLE_REC);
+
+static int bdinfo_test_memory(struct unit_test_state *uts)
+{
+ /* Test BDINFO memory layout only print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo -m"));
+ if (!CONFIG_IS_ENABLED(GETOPT))
+ ut_assertok(bdinfo_test_all(uts));
+ else
+ ut_assertok(bdinfo_check_mem(uts));
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_memory, UT_TESTF_CONSOLE_REC);
+
+static int bdinfo_test_eth(struct unit_test_state *uts)
+{
+ /* Test BDINFO ethernet settings only print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo -e"));
+ if (!CONFIG_IS_ENABLED(GETOPT))
+ ut_assertok(bdinfo_test_all(uts));
+ else if (IS_ENABLED(CONFIG_CMD_NET))
+ ut_assertok(test_eth(uts));
ut_assertok(ut_check_console_end(uts));
return 0;
}
-BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_eth, UT_TESTF_CONSOLE_REC);
int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Unit tests for command functions
+ */
+
+#include <command.h>
+#include <test/cmd.h>
+#include <test/suites.h>
+#include <test/ut.h>
+
+int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(cmd_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(cmd_test);
+
+ return cmd_ut_category("cmd", "cmd_test_", tests, n_ents, argc, argv);
+}
set_working_fdt_addr(0);
ut_assert_nextline("Working FDT set to 0");
ut_asserteq(CMD_RET_FAILURE, run_command("fdt addr", 0));
- ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
+
+ /*
+ * sandbox fails the check for !blob since the 0 pointer is mapped to
+ * memory somewhere other than at 0x0
+ */
+ if (IS_ENABLED(CONFIG_SANDBOX))
+ ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
ut_assertok(ut_check_console_end(uts));
/* Set up a working FDT and try again */
ut_assertok(console_record_reset_enable());
ut_assertok(run_command("font list", 0));
ut_assert_nextline("nimbus_sans_l_regular");
- ut_assert_nextline("cantoraone_regular");
+ if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
+ ut_assert_nextline("cantoraone_regular");
ut_assertok(ut_check_console_end(uts));
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("nimbus_sans_l_regular", name);
ut_asserteq(18, size);
+ if (!IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
+ return 0;
+
max_metrics = 1;
if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE))
max_metrics = IF_ENABLED_INT(CONFIG_CONSOLE_TRUETYPE,
}
ret = ut_run_list(name, prefix, tests, n_ents,
- argc > 1 ? argv[1] : NULL, runs_per_text, force_run,
+ cmd_arg1(argc, argv), runs_per_text, force_run,
test_insert);
return ret ? CMD_RET_FAILURE : 0;
#ifdef CONFIG_CMD_BDI
U_BOOT_CMD_MKENT(bdinfo, CONFIG_SYS_MAXARGS, 1, do_ut_bdinfo, "", ""),
#endif
-#ifdef CONFIG_BOOTSTD
+#ifdef CONFIG_UT_BOOTSTD
U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd,
"", ""),
+#endif
+#ifdef CONFIG_CMDLINE
+ U_BOOT_CMD_MKENT(cmd, CONFIG_SYS_MAXARGS, 1, do_ut_cmd, "", ""),
#endif
U_BOOT_CMD_MKENT(common, CONFIG_SYS_MAXARGS, 1, do_ut_common, "", ""),
#if defined(CONFIG_UT_DM)
#ifdef CONFIG_CMD_ADDRMAP
U_BOOT_CMD_MKENT(addrmap, CONFIG_SYS_MAXARGS, 1, do_ut_addrmap, "", ""),
#endif
+#if CONFIG_IS_ENABLED(HUSH_PARSER)
+ U_BOOT_CMD_MKENT(hush, CONFIG_SYS_MAXARGS, 1, do_ut_hush, "", ""),
+#endif
#ifdef CONFIG_CMD_LOADM
U_BOOT_CMD_MKENT(loadm, CONFIG_SYS_MAXARGS, 1, do_ut_loadm, "", ""),
#endif
#ifdef CONFIG_BOOTSTD
"\nbootstd - standard boot implementation"
#endif
+#ifdef CONFIG_CMDLINE
+ "\ncmd - test various commands"
+#endif
#ifdef CONFIG_SANDBOX
"\ncompression - compressors and bootm decompression"
#endif
#ifdef CONFIG_CONSOLE_TRUETYPE
"\nfont - font command"
#endif
+#if CONFIG_IS_ENABLED(HUSH_PARSER)
+ "\nhush - Test hush behavior"
+#endif
#ifdef CONFIG_CMD_LOADM
"\nloadm - loadm command parameters and loading memory blob"
#endif
struct test_state state;
struct udevice *dev;
+ if (!IS_ENABLED(SANDBOX))
+ return -EAGAIN;
+
state.val = 0;
ut_assertok(event_register("pre", EVT_DM_PRE_PROBE, h_probe, &state));
ut_assertok(event_register("post", EVT_DM_POST_PROBE, h_probe, &state));
obj-$(CONFIG_MULTIPLEXER) += mux-emul.o
obj-$(CONFIG_MUX_MMIO) += mux-mmio.o
obj-y += fdtdec.o
+obj-$(CONFIG_MTD_RAW_NAND) += nand.o
obj-$(CONFIG_UT_DM) += nop.o
obj-y += ofnode.o
obj-y += ofread.o
/* Check that the pointers were added correctly */
for (i = 0; i < 3; i++) {
- ut_asserteq(map_to_sysmem(dmar + i), ctx.rsdt->entry[i]);
- ut_asserteq(map_to_sysmem(dmar + i), ctx.xsdt->entry[i]);
+ ut_asserteq(nomap_to_sysmem(dmar + i), ctx.rsdt->entry[i]);
+ ut_asserteq(nomap_to_sysmem(dmar + i), ctx.xsdt->entry[i]);
}
ut_asserteq(0, ctx.rsdt->entry[3]);
ut_asserteq(0, ctx.xsdt->entry[3]);
DM_TEST(dm_test_acpi_basic, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/* Test setup_ctx_and_base_tables */
-static int dm_test_setup_ctx_and_base_tables(struct unit_test_state *uts)
+static int dm_test_acpi_ctx_and_base_tables(struct unit_test_state *uts)
{
struct acpi_rsdp *rsdp;
struct acpi_rsdt *rsdt;
end = PTR_ALIGN((void *)xsdt + sizeof(*xsdt), 64);
ut_asserteq_ptr(end, ctx.current);
- ut_asserteq(map_to_sysmem(rsdt), rsdp->rsdt_address);
- ut_asserteq(map_to_sysmem(xsdt), rsdp->xsdt_address);
+ ut_asserteq(nomap_to_sysmem(rsdt), rsdp->rsdt_address);
+ ut_asserteq(nomap_to_sysmem(xsdt), rsdp->xsdt_address);
return 0;
}
-DM_TEST(dm_test_setup_ctx_and_base_tables,
+DM_TEST(dm_test_acpi_ctx_and_base_tables,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/* Test 'acpi list' command */
console_record_reset();
run_command("acpi list", 0);
- ut_assert_nextline("Name Base Size Detail");
- ut_assert_nextline("---- -------- ----- ------");
- ut_assert_nextline("RSDP %08lx %5zx v02 U-BOOT", addr,
+ ut_assert_nextline("Name Base Size Detail");
+ ut_assert_nextline("---- ---------------- ----- ----------------------------");
+ ut_assert_nextline("RSDP %16lx %5zx v02 U-BOOT", addr,
sizeof(struct acpi_rsdp));
addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16);
- ut_assert_nextline("RSDT %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
+ ut_assert_nextline("RSDT %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
addr, sizeof(struct acpi_table_header) +
3 * sizeof(u32), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16);
- ut_assert_nextline("XSDT %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
+ ut_assert_nextline("XSDT %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
addr, sizeof(struct acpi_table_header) +
3 * sizeof(u64), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64);
- ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
+ ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
addr, sizeof(struct acpi_dmar), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
- ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
+ ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
addr, sizeof(struct acpi_dmar), OEM_REVISION);
addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
- ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
+ ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0",
addr, sizeof(struct acpi_dmar), OEM_REVISION);
ut_assert_console_end();
/* Now a real table */
console_record_reset();
run_command("acpi dump dmar", 0);
- addr = ALIGN(map_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64);
- ut_assert_nextline("DMAR @ %08lx", addr);
+ addr = ALIGN(nomap_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64);
+ ut_assert_nextline("DMAR @ %16lx", addr);
ut_assert_nextlines_are_dump(0x30);
ut_assert_console_end();
return 0;
}
DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/**
+ * dm_test_write_test_table() - create test ACPI table
+ *
+ * Create an ACPI table TSTn, where n is given by @index.
+ *
+ * @ctx: ACPI table writing context
+ * @index: table index
+ * Return: generated table
+ */
+static struct acpi_table_header
+*dm_test_write_test_table(struct acpi_ctx *ctx, int index)
+{
+ struct acpi_table_header *tbl = ctx->current;
+ char signature[5];
+
+ snprintf(signature, sizeof(signature), "TST%1d", index);
+ memset(tbl, 0, sizeof(*tbl));
+ acpi_fill_header(tbl, signature);
+ acpi_inc(ctx, sizeof(struct acpi_table_header));
+ tbl->length = (u8 *)ctx->current - (u8 *)tbl;
+ tbl->checksum = table_compute_checksum(tbl, tbl->length);
+ acpi_add_table(ctx, tbl);
+
+ return tbl;
+}
+
+/* Test acpi_find_table() */
+static int dm_test_acpi_find_table(struct unit_test_state *uts)
+{
+ struct acpi_ctx ctx;
+ ulong acpi_start, addr;
+ void *buf;
+ struct acpi_table_header *table, *table1, *table2, *table3;
+ struct acpi_rsdp *rsdp;
+ ulong rsdt;
+ ulong xsdt;
+
+ /* Keep reference to original ACPI tables */
+ acpi_start = gd_acpi_start();
+
+ /* Setup new ACPI tables */
+ buf = memalign(16, BUF_SIZE);
+ ut_assertnonnull(buf);
+ addr = map_to_sysmem(buf);
+ ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr));
+ table3 = dm_test_write_test_table(&ctx, 3);
+ table1 = dm_test_write_test_table(&ctx, 1);
+ table2 = dm_test_write_test_table(&ctx, 2);
+
+ /* Retrieve RSDP, RSDT, XSDT */
+ rsdp = map_sysmem(gd_acpi_start(), 0);
+ ut_assertnonnull(rsdp);
+ rsdt = rsdp->rsdt_address;
+ ut_assert(rsdt);
+ xsdt = rsdp->xsdt_address;
+ ut_assert(xsdt);
+
+ /* Find with both RSDT and XSDT */
+ table = acpi_find_table("TST1");
+ ut_asserteq_ptr(table1, table);
+ ut_asserteq_strn("TST1", table->signature);
+ table = acpi_find_table("TST2");
+ ut_asserteq_ptr(table2, table);
+ ut_asserteq_strn("TST2", table->signature);
+ table = acpi_find_table("TST3");
+ ut_asserteq_ptr(table3, table);
+ ut_asserteq_strn("TST3", table->signature);
+
+ /* Find with XSDT only */
+ rsdp->rsdt_address = 0;
+ table = acpi_find_table("TST1");
+ ut_asserteq_ptr(table1, table);
+ table = acpi_find_table("TST2");
+ ut_asserteq_ptr(table2, table);
+ table = acpi_find_table("TST3");
+ ut_asserteq_ptr(table3, table);
+ rsdp->rsdt_address = rsdt;
+
+ /* Find with RSDT only */
+ rsdp->xsdt_address = 0;
+ table = acpi_find_table("TST1");
+ ut_asserteq_ptr(table1, table);
+ table = acpi_find_table("TST2");
+ ut_asserteq_ptr(table2, table);
+ table = acpi_find_table("TST3");
+ ut_asserteq_ptr(table3, table);
+ rsdp->xsdt_address = xsdt;
+
+ /* Restore previous ACPI tables */
+ gd_set_acpi_start(acpi_start);
+ free(buf);
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_find_table, 0);
+
+/* Test offsets in RSDT, XSDT */
+static int dm_test_acpi_offsets(struct unit_test_state *uts)
+{
+ ut_asserteq(36, offsetof(struct acpi_rsdt, entry));
+ ut_asserteq(36, offsetof(struct acpi_xsdt, entry));
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_offsets, 0);
static int dm_test_clk_ccf(struct unit_test_state *uts)
{
struct clk *clk, *pclk;
- struct udevice *dev;
+ struct udevice *dev, *test_dev;
long long rate;
int ret;
#if CONFIG_IS_ENABLED(CLK_CCF)
+ struct clk clk_ccf;
const char *clkname;
int clkid, i;
#endif
/* Get the device using the clk device */
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev));
/* Test for clk_get_by_id() */
ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 60000000);
+ rate = clk_set_rate(clk, 60000000);
+ ut_asserteq(rate, -ENOSYS);
+
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
ut_asserteq_str("pll3_80m", pclk->dev->name);
ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
+ rate = clk_set_rate(clk, 80000000);
+ ut_asserteq(rate, -ENOSYS);
+
rate = clk_get_rate(clk);
ut_asserteq(rate, 80000000);
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
+ rate = clk_set_rate(clk, 60000000);
+ ut_asserteq(rate, 60000000);
+
#if CONFIG_IS_ENABLED(CLK_CCF)
/* Test clk tree enable/disable */
+
+ ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf);
+ ut_assertok(ret);
+ ut_asserteq_str("clk-ccf", clk_ccf.dev->name);
+ ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT);
+
ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
ut_assertok(ret);
ut_asserteq_str("i2c_root", clk->dev->name);
+ ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT);
- ret = clk_enable(clk);
+ ret = clk_enable(&clk_ccf);
ut_assertok(ret);
ret = sandbox_clk_enable_count(clk);
/* Prepare the test scenario */
for (i = 0; i < DM_TEST_ETH_NUM; i++) {
+ char *addr;
+
ut_assertok(uclass_find_device_by_name(UCLASS_ETH,
ethname[i], &dev[i]));
ut_assertok(device_remove(dev[i], DM_REMOVE_NORMAL));
/* Invalidate MAC address */
- strncpy(ethaddr[i], env_get(addrname[i]), 17);
+ addr = env_get(addrname[i]);
+ ut_assertnonnull(addr);
+ strncpy(ethaddr[i], addr, 17);
/* Must disable access protection for ethaddr before clearing */
env_set(".flags", addrname[i]);
env_set(addrname[i], NULL);
for (i = 0; i < ARRAY_SIZE(addr); i++) {
char addrname[10];
+ char *env_addr;
if (i)
snprintf(addrname, sizeof(addrname), "eth%daddr", i + 1);
else
strcpy(addrname, "ethaddr");
- ut_asserteq_str(addr[i], env_get(addrname));
+
+ env_addr = env_get(addrname);
+ ut_assertnonnull(env_addr);
+ ut_asserteq_str(addr[i], env_addr);
}
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <nand.h>
+#include <part.h>
+#include <rand.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+static int dm_test_nand(struct unit_test_state *uts, int dev, bool end)
+{
+ nand_erase_options_t opts = { };
+ struct mtd_info *mtd;
+ size_t length;
+ loff_t size;
+ char *buf;
+ int *gold;
+ u8 oob[NAND_MAX_OOBSIZE];
+ int i;
+ loff_t off = 0;
+ mtd_oob_ops_t ops = { };
+
+ /* Seed RNG for bit errors */
+ srand((off >> 32) ^ off ^ ~dev);
+
+ mtd = get_nand_dev_by_index(dev);
+ ut_assertnonnull(mtd);
+ size = mtd->erasesize * 4;
+ length = size;
+
+ buf = malloc(size);
+ ut_assertnonnull(buf);
+ gold = malloc(size);
+ ut_assertnonnull(gold);
+
+ /* Mark a block as bad */
+ ut_assertok(mtd_block_markbad(mtd, off + mtd->erasesize));
+
+ /* Erase some stuff */
+ if (end)
+ off = mtd->size - size - mtd->erasesize;
+ opts.offset = off;
+ opts.length = size;
+ opts.spread = 1;
+ opts.lim = U32_MAX;
+ ut_assertok(nand_erase_opts(mtd, &opts));
+
+ /* Make sure everything is erased */
+ memset(gold, 0xff, size);
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ /* ...but our bad block marker is still there */
+ ops.oobbuf = oob;
+ ops.ooblen = mtd->oobsize;
+ ut_assertok(mtd_read_oob(mtd, mtd->erasesize, &ops));
+ ut_asserteq(0, oob[mtd_to_nand(mtd)->badblockpos]);
+
+ /* Generate some data and write it */
+ for (i = 0; i < size / sizeof(int); i++)
+ gold[i] = rand();
+ ut_assertok(nand_write_skip_bad(mtd, off, &length, NULL, U64_MAX,
+ (void *)gold, 0));
+ ut_asserteq(size, length);
+
+ /* Verify */
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ /* Erase some blocks */
+ memset(((char *)gold) + mtd->erasesize, 0xff, mtd->erasesize * 2);
+ opts.offset = off + mtd->erasesize;
+ opts.length = mtd->erasesize * 2;
+ ut_assertok(nand_erase_opts(mtd, &opts));
+
+ /* Verify */
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ return 0;
+}
+
+#define DM_NAND_TEST(dev) \
+static int dm_test_nand##dev##_start(struct unit_test_state *uts) \
+{ \
+ return dm_test_nand(uts, dev, false); \
+} \
+DM_TEST(dm_test_nand##dev##_start, UT_TESTF_SCAN_FDT); \
+static int dm_test_nand##dev##_end(struct unit_test_state *uts) \
+{ \
+ return dm_test_nand(uts, dev, true); \
+} \
+DM_TEST(dm_test_nand##dev##_end, UT_TESTF_SCAN_FDT)
+
+DM_NAND_TEST(0);
+DM_NAND_TEST(1);
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
+#include <vsprintf.h>
#include <asm/scmi_test.h>
#include <dm/device-internal.h>
#include <dm/test.h>
-#include <linux/kconfig.h>
#include <power/regulator.h>
#include <test/ut.h>
DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT);
+static int dm_test_scmi_cmd(struct unit_test_state *uts)
+{
+ struct udevice *agent_dev;
+ int num_proto = 0;
+ char cmd_out[30];
+
+ if (!CONFIG_IS_ENABLED(CMD_SCMI))
+ return -EAGAIN;
+
+ /* preparation */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+
+ /*
+ * Estimate the number of provided protocols.
+ * This estimation is correct as far as a corresponding
+ * protocol support is added to sandbox fake serer.
+ */
+ if (CONFIG_IS_ENABLED(POWER_DOMAIN))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ num_proto++;
+
+ /* scmi info */
+ ut_assertok(run_command("scmi info", 0));
+
+ ut_assert_nextline("SCMI device: scmi");
+ snprintf(cmd_out, 30, " protocol version: 0x%x",
+ SCMI_BASE_PROTOCOL_VERSION);
+ ut_assert_nextline(cmd_out);
+ ut_assert_nextline(" # of agents: 2");
+ ut_assert_nextline(" 0: platform");
+ ut_assert_nextline(" > 1: OSPM");
+ snprintf(cmd_out, 30, " # of protocols: %d", num_proto);
+ ut_assert_nextline(cmd_out);
+ if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ ut_assert_nextline(" Power domain management");
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
+ ut_assert_nextline(" Clock management");
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ ut_assert_nextline(" Reset domain management");
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ ut_assert_nextline(" Voltage domain management");
+ ut_assert_nextline(" vendor: U-Boot");
+ ut_assert_nextline(" sub vendor: Sandbox");
+ ut_assert_nextline(" impl version: 0x1");
+
+ ut_assert_console_end();
+
+ /* scmi perm_dev */
+ ut_assertok(run_command("scmi perm_dev 1 0 1", 0));
+ ut_assert_console_end();
+
+ ut_assert(run_command("scmi perm_dev 1 0 0", 0));
+ ut_assert_nextline("Denying access to device:0 failed (-13)");
+ ut_assert_console_end();
+
+ /* scmi perm_proto */
+ ut_assertok(run_command("scmi perm_proto 1 0 14 1", 0));
+ ut_assert_console_end();
+
+ ut_assert(run_command("scmi perm_proto 1 0 14 0", 0));
+ ut_assert_nextline("Denying access to protocol:0x14 on device:0 failed (-13)");
+ ut_assert_console_end();
+
+ /* scmi reset */
+ ut_assert(run_command("scmi reset 1 1", 0));
+ ut_assert_nextline("Reset failed (-13)");
+ ut_assert_console_end();
+
+ return 0;
+}
+
+DM_TEST(dm_test_scmi_cmd, UT_TESTF_SCAN_FDT);
+
static int dm_test_scmi_power_domains(struct unit_test_state *uts)
{
struct sandbox_scmi_agent *agent;
u8 *name;
int ret;
+ if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ return -EAGAIN;
+
/* preparation */
ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
ut_assertnonnull(agent);
int ret_dev;
int ret;
+ if (!CONFIG_IS_ENABLED(CLK_SCMI))
+ return -EAGAIN;
+
ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
struct udevice *agent_dev, *reset_dev, *dev = NULL;
int ret;
+ if (!CONFIG_IS_ENABLED(RESET_SCMI))
+ return -EAGAIN;
+
ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
struct udevice *dev;
struct udevice *regul0_dev;
+ if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ return -EAGAIN;
+
ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
scmi_devices = sandbox_scmi_devices_ctx(dev);
/* Device 1 is the warm sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_POWER));
state->sysreset_allowed[SYSRESET_WARM] = true;
ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
/* Device 2 is the cold sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_WARM));
state->sysreset_allowed[SYSRESET_COLD] = false;
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
state->sysreset_allowed[SYSRESET_COLD] = true;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021
+# Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+
+obj-y += cmd_ut_hush.o
+obj-y += if.o
+obj-y += dollar.o
+obj-y += list.o
+obj-y += loop.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#include <command.h>
+#include <test/hush.h>
+#include <test/suites.h>
+#include <test/ut.h>
+
+int do_ut_hush(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(hush_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(hush_test);
+
+ return cmd_ut_category("hush", "hush_test_",
+ tests, n_ents, argc, argv);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#include <command.h>
+#include <env_attr.h>
+#include <test/hush.h>
+#include <test/ut.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int hush_test_simple_dollar(struct unit_test_state *uts)
+{
+ console_record_reset_enable();
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline_empty();
+ ut_assert_console_end();
+
+ ut_assertok(run_command("echo ${dollar_foo}", 0));
+ ut_assert_nextline_empty();
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_foo=bar", 0));
+
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("echo ${dollar_foo}", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_foo=\\$bar", 0));
+
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline("$bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_foo='$bar'", 0));
+
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline("$bar");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("dollar_foo=bar quux", 0));
+ /* Next line contains error message */
+ ut_assert_skipline();
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("dollar_foo='bar quux", 0));
+ /* Next line contains error message */
+ ut_assert_skipline();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * For some strange reasons, the console is not empty after
+ * running above command.
+ * So, we reset it to not have side effects for other tests.
+ */
+ console_record_reset_enable();
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assert_console_end();
+ }
+
+ ut_asserteq(1, run_command("dollar_foo=bar quux\"", 0));
+ /* Two next lines contain error message */
+ ut_assert_skipline();
+ ut_assert_skipline();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* See above comments. */
+ console_record_reset_enable();
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assert_console_end();
+ }
+
+ ut_assertok(run_command("dollar_foo='bar \"quux'", 0));
+
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ /*
+ * This one is buggy.
+ * ut_assert_nextline("bar \"quux");
+ * ut_assert_console_end();
+ *
+ * So, let's reset output:
+ */
+ console_record_reset_enable();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * Old parser returns an error because it waits for closing
+ * '\'', but this behavior is wrong as the '\'' is surrounded by
+ * '"', so no need to wait for a closing one.
+ */
+ ut_assertok(run_command("dollar_foo=\"bar 'quux\"", 0));
+
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline("bar 'quux");
+ ut_assert_console_end();
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_asserteq(1, run_command("dollar_foo=\"bar 'quux\"", 0));
+ /* Next line contains error message */
+ ut_assert_skipline();
+ ut_assert_console_end();
+ }
+
+ ut_assertok(run_command("dollar_foo='bar quux'", 0));
+ ut_assertok(run_command("echo $dollar_foo", 0));
+ ut_assert_nextline("bar quux");
+ ut_assert_console_end();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* Reset local variable. */
+ ut_assertok(run_command("dollar_foo=", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ puts("Beware: this test set local variable dollar_foo and it cannot be unset!");
+ }
+
+ return 0;
+}
+HUSH_TEST(hush_test_simple_dollar, 0);
+
+static int hush_test_env_dollar(struct unit_test_state *uts)
+{
+ env_set("env_foo", "bar");
+ console_record_reset_enable();
+
+ ut_assertok(run_command("echo $env_foo", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("echo ${env_foo}", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ /* Environment variables have priority over local variable */
+ ut_assertok(run_command("env_foo=quux", 0));
+ ut_assertok(run_command("echo ${env_foo}", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ /* Clean up setting the variable */
+ env_set("env_foo", NULL);
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* Reset local variable. */
+ ut_assertok(run_command("env_foo=", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ puts("Beware: this test set local variable env_foo and it cannot be unset!");
+ }
+
+ return 0;
+}
+HUSH_TEST(hush_test_env_dollar, 0);
+
+static int hush_test_command_dollar(struct unit_test_state *uts)
+{
+ console_record_reset_enable();
+
+ ut_assertok(run_command("dollar_bar=\"echo bar\"", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("${dollar_bar}", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_bar=\"echo\nbar\"", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_bar='echo bar\n'", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_bar='echo bar\\n'", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * This difference seems to come from a bug solved in Busybox
+ * hush.
+ * Behavior of hush 2021 is coherent with bash and other shells.
+ */
+ ut_assert_nextline("bar\\n");
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assert_nextline("barn");
+ }
+
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_bar='echo $bar'", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+ ut_assert_nextline("$bar");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("dollar_quux=quux", 0));
+ ut_assertok(run_command("dollar_bar=\"echo $dollar_quux\"", 0));
+
+ ut_assertok(run_command("$dollar_bar", 0));
+ ut_assert_nextline("quux");
+ ut_assert_console_end();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* Reset local variables. */
+ ut_assertok(run_command("dollar_bar=", 0));
+ ut_assertok(run_command("dollar_quux=", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ puts("Beware: this test sets local variable dollar_bar and dollar_quux and they cannot be unset!");
+ }
+
+ return 0;
+}
+HUSH_TEST(hush_test_command_dollar, 0);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#include <command.h>
+#include <env_attr.h>
+#include <vsprintf.h>
+#include <test/hush.h>
+#include <test/ut.h>
+
+/*
+ * All tests will execute the following:
+ * if condition_to_test; then
+ * true
+ * else
+ * false
+ * fi
+ * If condition is true, command returns 1, 0 otherwise.
+ */
+const char *if_format = "if %s; then true; else false; fi";
+
+static int hush_test_if_base(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "true");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "false");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_base, 0);
+
+static int hush_test_if_basic_operators(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test aaa = aaa");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa = bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa != bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa != aaa");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa < bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test bbb < aaa");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test bbb > aaa");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa > bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -eq 123");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -eq 456");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -ne 456");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -ne 123");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -lt 456");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -lt 123");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 456 -lt 123");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -le 456");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -le 123");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 456 -le 123");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 456 -gt 123");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -gt 123");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -gt 456");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 456 -ge 123");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -ge 123");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 123 -ge 456");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_basic_operators, 0);
+
+static int hush_test_if_octal(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test 010 -eq 010");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 010 -eq 011");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 010 -ne 011");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 010 -ne 010");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_octal, 0);
+
+static int hush_test_if_hexadecimal(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -gt 0x2000001");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -gt 0x2000000");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -gt 0x1ffffff");
+ ut_assertok(run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_hexadecimal, 0);
+
+static int hush_test_if_mixed(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test 010 -eq 10");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 010 -ne 10");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0xa -eq 10");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0xa -eq 012");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 2000000 -gt 0x1ffffff");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -gt 1ffffff");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -lt 1ffffff");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -eq 2000000");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test 0x2000000 -ne 2000000");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -z \"\"");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -z \"aaa\"");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -n \"aaa\"");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -n \"\"");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_mixed, 0);
+
+static int hush_test_if_inverted(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test ! aaa = aaa");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! aaa = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! ! aaa = aaa");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! ! aaa = bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_inverted, 0);
+
+static int hush_test_if_binary(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test aaa != aaa -o bbb != bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa != aaa -o bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa = aaa -o bbb != bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa = aaa -o bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa != aaa -a bbb != bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa != aaa -a bbb = bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa = aaa -a bbb != bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test aaa = aaa -a bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_binary, 0);
+
+static int hush_test_if_inverted_binary(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ sprintf(if_formatted, if_format, "test ! aaa != aaa -o ! bbb != bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! aaa != aaa -o ! bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! aaa = aaa -o ! bbb != bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! aaa = aaa -o ! bbb = bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format,
+ "test ! ! aaa != aaa -o ! ! bbb != bbb");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format,
+ "test ! ! aaa != aaa -o ! ! bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format,
+ "test ! ! aaa = aaa -o ! ! bbb != bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test ! ! aaa = aaa -o ! ! bbb = bbb");
+ ut_assertok(run_command(if_formatted, 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_inverted_binary, 0);
+
+static int hush_test_if_z_operator(struct unit_test_state *uts)
+{
+ char if_formatted[128];
+
+ /* Deal with environment variable used during test. */
+ env_set("ut_var_nonexistent", NULL);
+ env_set("ut_var_exists", "1");
+ env_set("ut_var_unset", "1");
+
+ sprintf(if_formatted, if_format, "test -z \"$ut_var_nonexistent\"");
+ ut_assertok(run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -z \"$ut_var_exists\"");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ sprintf(if_formatted, if_format, "test -z \"$ut_var_unset\"");
+ ut_asserteq(1, run_command(if_formatted, 0));
+
+ env_set("ut_var_unset", NULL);
+ sprintf(if_formatted, if_format, "test -z \"$ut_var_unset\"");
+ ut_assertok(run_command(if_formatted, 0));
+
+ /* Clear the set environment variable. */
+ env_set("ut_var_exists", NULL);
+
+ return 0;
+}
+HUSH_TEST(hush_test_if_z_operator, 0);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#include <command.h>
+#include <env_attr.h>
+#include <test/hush.h>
+#include <test/ut.h>
+#include <asm/global_data.h>
+
+static int hush_test_semicolon(struct unit_test_state *uts)
+{
+ /* A; B = B truth table. */
+ ut_asserteq(1, run_command("false; false", 0));
+ ut_assertok(run_command("false; true", 0));
+ ut_assertok(run_command("true; true", 0));
+ ut_asserteq(1, run_command("true; false", 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_semicolon, 0);
+
+static int hush_test_and(struct unit_test_state *uts)
+{
+ /* A && B truth table. */
+ ut_asserteq(1, run_command("false && false", 0));
+ ut_asserteq(1, run_command("false && true", 0));
+ ut_assertok(run_command("true && true", 0));
+ ut_asserteq(1, run_command("true && false", 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_and, 0);
+
+static int hush_test_or(struct unit_test_state *uts)
+{
+ /* A || B truth table. */
+ ut_asserteq(1, run_command("false || false", 0));
+ ut_assertok(run_command("false || true", 0));
+ ut_assertok(run_command("true || true", 0));
+ ut_assertok(run_command("true || false", 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_or, 0);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int hush_test_and_or(struct unit_test_state *uts)
+{
+ /* A && B || C truth table. */
+ ut_asserteq(1, run_command("false && false || false", 0));
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_asserteq(1, run_command("false && false || true", 0));
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * This difference seems to come from a bug solved in Busybox
+ * hush.
+ *
+ * Indeed, the following expression can be seen like this:
+ * (false && false) || true
+ * So, (false && false) returns 1, the second false is not
+ * executed, and true is executed because of ||.
+ */
+ ut_assertok(run_command("false && false || true", 0));
+ }
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_asserteq(1, run_command("false && true || true", 0));
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * This difference seems to come from a bug solved in Busybox
+ * hush.
+ *
+ * Indeed, the following expression can be seen like this:
+ * (false && true) || true
+ * So, (false && true) returns 1, the true is not executed, and
+ * true is executed because of ||.
+ */
+ ut_assertok(run_command("false && true || true", 0));
+ }
+
+ ut_asserteq(1, run_command("false && true || false", 0));
+ ut_assertok(run_command("true && true || false", 0));
+ ut_asserteq(1, run_command("true && false || false", 0));
+ ut_assertok(run_command("true && false || true", 0));
+ ut_assertok(run_command("true && true || true", 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_and_or, 0);
+
+static int hush_test_or_and(struct unit_test_state *uts)
+{
+ /* A || B && C truth table. */
+ ut_asserteq(1, run_command("false || false && false", 0));
+ ut_asserteq(1, run_command("false || false && true", 0));
+ ut_assertok(run_command("false || true && true", 0));
+ ut_asserteq(1, run_command("false || true && false", 0));
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assertok(run_command("true || true && false", 0));
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * This difference seems to come from a bug solved in Busybox
+ * hush.
+ *
+ * Indeed, the following expression can be seen like this:
+ * (true || true) && false
+ * So, (true || true) returns 0, the second true is not
+ * executed, and then false is executed because of &&.
+ */
+ ut_asserteq(1, run_command("true || true && false", 0));
+ }
+
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assertok(run_command("true || false && false", 0));
+ } else if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * This difference seems to come from a bug solved in Busybox
+ * hush.
+ *
+ * Indeed, the following expression can be seen like this:
+ * (true || false) && false
+ * So, (true || false) returns 0, the false is not executed, and
+ * then false is executed because of &&.
+ */
+ ut_asserteq(1, run_command("true || false && false", 0));
+ }
+
+ ut_assertok(run_command("true || false && true", 0));
+ ut_assertok(run_command("true || true && true", 0));
+
+ return 0;
+}
+HUSH_TEST(hush_test_or_and, 0);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021
+ * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com
+ */
+
+#include <command.h>
+#include <env_attr.h>
+#include <test/hush.h>
+#include <test/ut.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int hush_test_for(struct unit_test_state *uts)
+{
+ console_record_reset_enable();
+
+ ut_assertok(run_command("for loop_i in foo bar quux quux; do echo $loop_i; done", 0));
+ ut_assert_nextline("foo");
+ ut_assert_nextline("bar");
+ ut_assert_nextline("quux");
+ ut_assert_nextline("quux");
+ ut_assert_console_end();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* Reset local variable. */
+ ut_assertok(run_command("loop_i=", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ puts("Beware: this test set local variable loop_i and it cannot be unset!");
+ }
+
+ return 0;
+}
+HUSH_TEST(hush_test_for, 0);
+
+static int hush_test_while(struct unit_test_state *uts)
+{
+ console_record_reset_enable();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /*
+ * Hush 2021 always returns 0 from while loop...
+ * You can see code snippet near this line to have a better
+ * understanding:
+ * debug_printf_exec(": while expr is false: breaking (exitcode:EXIT_SUCCESS)\n");
+ */
+ ut_assertok(run_command("while test -z \"$loop_foo\"; do echo bar; loop_foo=quux; done", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ /*
+ * Exit status is that of test, so 1 since test is false to quit
+ * the loop.
+ */
+ ut_asserteq(1, run_command("while test -z \"$loop_foo\"; do echo bar; loop_foo=quux; done", 0));
+ }
+ ut_assert_nextline("bar");
+ ut_assert_console_end();
+
+ if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
+ /* Reset local variable. */
+ ut_assertok(run_command("loop_foo=", 0));
+ } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ puts("Beware: this test set local variable loop_foo and it cannot be unset!");
+ }
+
+ return 0;
+}
+HUSH_TEST(hush_test_while, 0);
+
+static int hush_test_until(struct unit_test_state *uts)
+{
+ console_record_reset_enable();
+ env_set("loop_bar", "bar");
+
+ /*
+ * WARNING We have to use environment variable because it is not possible
+ * resetting local variable.
+ */
+ ut_assertok(run_command("until test -z \"$loop_bar\"; do echo quux; setenv loop_bar; done", 0));
+ ut_assert_nextline("quux");
+ ut_assert_console_end();
+
+ /*
+ * Loop normally resets foo environment variable, but we reset it here in
+ * case the test failed.
+ */
+ env_set("loop_bar", NULL);
+ return 0;
+}
+HUSH_TEST(hush_test_until, 0);
help
Test filesystems and the various load methods which use them.
+config SPL_UT_LOAD_NAND
+ bool "Test loading from NAND flash"
+ depends on SANDBOX && SPL_OF_REAL
+ depends on SPL_NAND_SUPPORT
+ depends on SPL_MTD
+ default y
+ help
+ Test the NAND flash load method.
+
config SPL_UT_LOAD_NET
bool "Test loading over TFTP"
depends on SANDBOX && SPL_OF_REAL
config SPL_UT_LOAD_OS
bool "Test loading from the host OS"
depends on SANDBOX && SPL_LOAD_FIT
+ select SPL_LOAD_BLOCK
default y
help
Smoke test to ensure that loading U-boot works in sandbox.
obj-y += spl_load.o
obj-$(CONFIG_SPL_UT_LOAD_FS) += spl_load_fs.o
+obj-$(CONFIG_SPL_UT_LOAD_NAND) += spl_load_nand.o
obj-$(CONFIG_SPL_UT_LOAD_NET) += spl_load_net.o
obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_load_nor.o
obj-$(CONFIG_SPL_UT_LOAD_OS) += spl_load_os.o
if (check_image_info(uts, &info_write, &info_read))
return CMD_RET_FAILURE;
} else {
- struct spl_load_info load = {
- .bl_len = 1,
- .priv = img,
- .read = spl_test_read,
- };
+ struct spl_load_info load;
+ spl_set_bl_len(&load, 1);
+ load.priv = img;
+ load.read = spl_test_read;
if (type == IMX8)
ut_assertok(spl_load_imx_container(&info_read, &load,
0));
* LZMA is too complex to generate on the fly, so let's use some data I put in
* the oven^H^H^H^H compressed earlier
*/
-static const char lzma_compressed[] = {
+const char lzma_compressed[] = {
0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0x00, 0x02, 0x05, 0x55, 0x4e, 0x82, 0xbc, 0xc2, 0x42, 0xf6, 0x88,
0x6c, 0x99, 0xd6, 0x82, 0x48, 0xa6, 0x06, 0x67, 0xf8, 0x46, 0x7c, 0xe9,
0x1e, 0xff, 0xff, 0x80, 0x8e, 0x00, 0x00
};
+const size_t lzma_compressed_size = sizeof(lzma_compressed);
+
int do_spl_test_load(struct unit_test_state *uts, const char *test_name,
enum spl_test_image type, struct spl_image_loader *loader,
int (*write_image)(struct unit_test_state *, void *, size_t))
bs->root_cluster = cpu_to_le32(root_sector);
vi->ext_boot_sign = 0x29;
- memcpy(vi->fs_type, FAT32_SIGN, sizeof(vi->fs_type));
+ memcpy(vi->fs_type, "FAT32 ", sizeof(vi->fs_type));
memcpy(dst + 0x1fe, "\x55\xAA", 2);
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
struct blk_desc *dev_desc;
size_t fs_size, fs_data, img_size, img_data,
- data_size = SPL_TEST_DATA_SIZE;
+ plain_size = SPL_TEST_DATA_SIZE;
struct spl_image_info info_write = {
.name = test_name,
- .size = data_size,
+ .size = type == LEGACY_LZMA ? lzma_compressed_size :
+ plain_size,
}, info_read = { };
struct disk_partition part = {
.start = 1,
.boot_device = loader->boot_device,
};
void *fs;
- char *data;
+ char *data, *plain;
img_size = create_image(NULL, type, &info_write, &img_data);
ut_assert(img_size);
ut_assertnonnull(fs);
data = fs + fs_data + img_data;
- generate_data(data, data_size, test_name);
+ if (type == LEGACY_LZMA) {
+ plain = malloc(plain_size);
+ ut_assertnonnull(plain);
+ generate_data(plain, plain_size, "lzma");
+ memcpy(data, lzma_compressed, lzma_compressed_size);
+ } else {
+ plain = data;
+ generate_data(plain, plain_size, test_name);
+ }
ut_asserteq(img_size, create_image(fs + fs_data, type, &info_write,
NULL));
ut_asserteq(fs_size, create_fs(fs, img_size, filename, NULL));
ut_assertok(loader->load_image(&info_read, &bootdev));
if (check_image_info(uts, &info_write, &info_read))
return CMD_RET_FAILURE;
- ut_asserteq_mem(data, phys_to_virt(info_write.load_addr), data_size);
+ if (type == LEGACY_LZMA)
+ ut_asserteq(plain_size, info_read.size);
+ ut_asserteq_mem(plain, phys_to_virt(info_write.load_addr), plain_size);
+ if (type == LEGACY_LZMA)
+ free(plain);
free(fs);
return 0;
}
return spl_test_mmc_fs(uts, test_name, type, create_ext2, true);
}
SPL_IMG_TEST(spl_test_blk, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_blk, FIT_EXTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_blk, FIT_INTERNAL, DM_FLAGS);
spl_mmc_clear_cache();
spl_fat_force_reregister();
- if (type == LEGACY &&
- spl_test_mmc_fs(uts, test_name, type, create_ext2, false))
+ if (spl_test_mmc_fs(uts, test_name, type, create_ext2, false))
return CMD_RET_FAILURE;
- if (type != IMX8 &&
- spl_test_mmc_fs(uts, test_name, type, create_fat, false))
+ if (spl_test_mmc_fs(uts, test_name, type, create_fat, false))
return CMD_RET_FAILURE;
return do_spl_test_load(uts, test_name, type,
spl_test_mmc_write_image);
}
SPL_IMG_TEST(spl_test_mmc, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_mmc, LEGACY_LZMA, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, FIT_EXTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, FIT_INTERNAL, DM_FLAGS);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <nand.h>
+#include <spl.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+uint32_t spl_nand_get_uboot_raw_page(void);
+
+static int spl_test_nand_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ uint32_t off = spl_nand_get_uboot_raw_page();
+ struct mtd_info *mtd;
+ struct erase_info erase = { };
+ size_t length;
+
+ nand_reinit();
+ mtd = get_nand_dev_by_index(0);
+ ut_assertnonnull(mtd);
+
+ /* Mark the first block as bad to test that it gets skipped */
+ ut_assertok(mtd_block_markbad(mtd, off & ~mtd->erasesize_mask));
+ off += mtd->erasesize;
+
+ erase.mtd = mtd;
+ erase.len = img_size + (off & mtd->erasesize_mask);
+ erase.len += mtd->erasesize_mask;
+ erase.len &= ~mtd->erasesize_mask;
+ erase.addr = off & ~mtd->erasesize_mask;
+ erase.scrub = 1;
+ ut_assertok(mtd_erase(mtd, &erase));
+
+ ut_assertok(mtd_write(mtd, off, img_size, &length, img));
+
+ return 0;
+}
+
+static int spl_test_nand(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ return do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(1, BOOT_DEVICE_NAND,
+ spl_nand_load_image),
+ spl_test_nand_write_image);
+}
+SPL_IMG_TEST(spl_test_nand, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, IMX8, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, FIT_INTERNAL, DM_FLAGS);
+#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
+SPL_IMG_TEST(spl_test_nand, FIT_EXTERNAL, DM_FLAGS);
+#endif
return ret;
}
SPL_IMG_TEST(spl_test_net, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_net, FIT_INTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_net, FIT_EXTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_nor, LEGACY_LZMA, 0);
SPL_IMG_TEST(spl_test_nor, IMX8, 0);
SPL_IMG_TEST(spl_test_nor, FIT_INTERNAL, 0);
+#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
SPL_IMG_TEST(spl_test_nor, FIT_EXTERNAL, 0);
+#endif
int fd;
};
-static ulong read_fit_image(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
+static ulong read_fit_image(struct spl_load_info *load, ulong offset,
+ ulong size, void *buf)
{
struct text_ctx *text_ctx = load->priv;
- off_t offset, ret;
+ off_t ret;
ssize_t res;
- offset = sector * load->bl_len;
ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
if (ret != offset) {
printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
return 0;
}
- res = os_read(text_ctx->fd, buf, count * load->bl_len);
+ res = os_read(text_ctx->fd, buf, size);
if (res == -1) {
printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
- count * load->bl_len, res, errno);
+ size, res, errno);
return 0;
}
- return count;
+ return size;
}
static int spl_test_load(struct unit_test_state *uts)
int fd;
memset(&load, '\0', sizeof(load));
- load.bl_len = 512;
+ spl_set_bl_len(&load, 512);
load.read = read_fit_image;
ret = sandbox_find_next_phase(fname, sizeof(fname), true);
if (ret)
ut_assertf(0, "%s not found, error %d\n", fname, ret);
- load.filename = fname;
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
spl_test_spi_write_image);
}
SPL_IMG_TEST(spl_test_spi, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_spi, LEGACY_LZMA, DM_FLAGS);
SPL_IMG_TEST(spl_test_spi, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_spi, FIT_INTERNAL, DM_FLAGS);
#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
#include <log.h>
#include <malloc.h>
#include <dm/test.h>
+#include <test/lib.h>
#include <test/test.h>
#include <test/ut.h>
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_multi_alloc_512mb(uts, 0xE0000000);
}
-
-DM_TEST(lib_test_lmb_simple, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_simple, 0);
/* Create two memory regions with one reserved region and allocate */
static int lib_test_lmb_simple_x2(struct unit_test_state *uts)
/* simulate 512 MiB RAM beginning at 3.5GiB and 1 GiB */
return test_multi_alloc_512mb_x2(uts, 0xE0000000, 0x40000000);
}
-
-DM_TEST(lib_test_lmb_simple_x2, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_simple_x2, 0);
/* Simulate 512 MiB RAM, allocate some blocks that fit/don't fit */
static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram)
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_bigblock(uts, 0xE0000000);
}
-
-DM_TEST(lib_test_lmb_big, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_big, 0);
/* Simulate 512 MiB RAM, allocate a block without previous reservation */
static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram,
return test_noreserved(uts, 0xE0000000, 4, 1);
}
-DM_TEST(lib_test_lmb_noreserved, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_noreserved, 0);
static int lib_test_lmb_unaligned_size(struct unit_test_state *uts)
{
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_noreserved(uts, 0xE0000000, 5, 8);
}
+LIB_TEST(lib_test_lmb_unaligned_size, 0);
-DM_TEST(lib_test_lmb_unaligned_size, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/*
* Simulate a RAM that starts at 0 and allocate down to address 0, which must
* fail as '0' means failure for the lmb_alloc functions.
return 0;
}
-
-DM_TEST(lib_test_lmb_at_0, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_at_0, 0);
/* Check that calling lmb_reserve with overlapping regions fails. */
static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts)
0, 0, 0, 0);
return 0;
}
-
-DM_TEST(lib_test_lmb_overlapping_reserve,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_overlapping_reserve, 0);
/*
* Simulate 512 MiB RAM, reserve 3 blocks, allocate addresses in between.
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_alloc_addr(uts, 0xE0000000);
}
-
-DM_TEST(lib_test_lmb_alloc_addr, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_alloc_addr, 0);
/* Simulate 512 MiB RAM, reserve 3 blocks, check addresses in between */
static int test_get_unreserved_size(struct unit_test_state *uts,
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_get_unreserved_size(uts, 0xE0000000);
}
-
-DM_TEST(lib_test_lmb_get_free_size,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_get_free_size, 0);
#ifdef CONFIG_LMB_USE_MAX_REGIONS
static int lib_test_lmb_max_regions(struct unit_test_state *uts)
return 0;
}
+LIB_TEST(lib_test_lmb_max_regions, 0);
#endif
-DM_TEST(lib_test_lmb_max_regions,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-
static int lib_test_lmb_flags(struct unit_test_state *uts)
{
const phys_addr_t ram = 0x40000000;
return 0;
}
-
-DM_TEST(lib_test_lmb_flags,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_lmb_flags, 0);
u8 *buf;
int i;
+ /* This test requires writable memory at zero */
+ if (IS_ENABLED(CONFIG_X86))
+ return -EAGAIN;
+
buf = map_sysmem(0, BUF_SIZE);
memset(buf, '\0', BUF_SIZE);
for (i = 0; i < 0x11; i++)
u8 *buf;
int i;
+ /* This test requires writable memory at zero */
+ if (IS_ENABLED(CONFIG_X86))
+ return -EAGAIN;
+
buf = map_sysmem(0, BUF_SIZE);
memset(buf, '\0', BUF_SIZE);
for (i = 0; i < 0x11; i++)
import os
from subprocess import call, check_call, check_output, CalledProcessError
-def mk_fs(config, fs_type, size, prefix):
+def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000):
"""Create a file system volume
Args:
fs_type (str): File system type, e.g. 'ext4'
size (int): Size of file system in bytes
prefix (str): Prefix string of volume's file name
+ size_gran (int): Size granularity of file system image in bytes
Raises:
CalledProcessError: if any error occurs when creating the filesystem
fs_img = f'{prefix}.{fs_type}.img'
fs_img = os.path.join(config.persistent_data_dir, fs_img)
- if fs_type == 'fat16':
+ if fs_type == 'fat12':
+ mkfs_opt = '-F 12'
+ elif fs_type == 'fat16':
mkfs_opt = '-F 16'
elif fs_type == 'fat32':
mkfs_opt = '-F 32'
else:
fs_lnxtype = fs_type
- count = (size + 0x100000 - 1) // 0x100000
+ count = (size + size_gran - 1) // size_gran
# Some distributions do not add /sbin to the default PATH, where mkfs lives
if '/sbin' not in os.environ["PATH"].split(os.pathsep):
try:
check_call(f'rm -f {fs_img}', shell=True)
- check_call(f'dd if=/dev/zero of={fs_img} bs=1M count={count}',
+ check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}',
shell=True)
check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
if fs_type == 'ext4':
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
# Test Case 1b, run unsigned image if no PK
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert('\'HELLO1\' failed' in ''.join(output))
assert('efi_start_image() returned: 26' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld_forged.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert('hELLO, world!' in ''.join(output))
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert(not 'hELLO, world!' in ''.join(output))
assert('\'HELLO1\' failed' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_a host 0:1 /helloworld.efi.signed_a -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_a\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
# Test Case 1b, signed and authenticated by root CA
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO_ab host 0:1 /helloworld.efi.signed_ab -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db_b.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
# Or,
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 dbx_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
'U-Boot loaded FDT from offset %#x, FDT is actually at %#x' %
(fit_offset, real_fit_offset))
+ # Check if bootargs strings substitution works
+ output = cons.run_command_list([
+ 'env set bootargs \\\"\'my_boot_var=${foo}\'\\\"',
+ 'env set foo bar',
+ 'bootm prep',
+ 'env print bootargs'])
+ assert 'bootargs="my_boot_var=bar"' in output, "Bootargs strings not substituted"
+
# Now a kernel and an FDT
with cons.log.section('Kernel + FDT load'):
params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr']
cons = u_boot_console
+ # We need to use our own device tree file. Remember to restore it
+ # afterwards.
+ old_dtb = cons.config.dtb
try:
- # We need to use our own device tree file. Remember to restore it
- # afterwards.
- old_dtb = cons.config.dtb
mkimage = cons.config.build_dir + '/tools/mkimage'
run_fit_test(mkimage)
finally:
from subprocess import call, check_call, check_output, CalledProcessError
from fstest_defs import *
import u_boot_utils as util
+# pylint: disable=E0611
from tests import fs_helper
supported_fs_basic = ['fat16', 'fat32', 'ext4']
-supported_fs_ext = ['fat16', 'fat32']
-supported_fs_mkdir = ['fat16', 'fat32']
-supported_fs_unlink = ['fat16', 'fat32']
+supported_fs_ext = ['fat12', 'fat16', 'fat32']
+supported_fs_fat = ['fat12', 'fat16']
+supported_fs_mkdir = ['fat12', 'fat16', 'fat32']
+supported_fs_unlink = ['fat12', 'fat16', 'fat32']
supported_fs_symlink = ['ext4']
#
"""
global supported_fs_basic
global supported_fs_ext
+ global supported_fs_fat
global supported_fs_mkdir
global supported_fs_unlink
global supported_fs_symlink
print('*** FS TYPE modified: %s' % supported_fs)
supported_fs_basic = intersect(supported_fs, supported_fs_basic)
supported_fs_ext = intersect(supported_fs, supported_fs_ext)
+ supported_fs_fat = intersect(supported_fs, supported_fs_fat)
supported_fs_mkdir = intersect(supported_fs, supported_fs_mkdir)
supported_fs_unlink = intersect(supported_fs, supported_fs_unlink)
supported_fs_symlink = intersect(supported_fs, supported_fs_symlink)
if 'fs_obj_ext' in metafunc.fixturenames:
metafunc.parametrize('fs_obj_ext', supported_fs_ext,
indirect=True, scope='module')
+ if 'fs_obj_fat' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_fat', supported_fs_fat,
+ indirect=True, scope='module')
if 'fs_obj_mkdir' in metafunc.fixturenames:
metafunc.parametrize('fs_obj_mkdir', supported_fs_mkdir,
indirect=True, scope='module')
finally:
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
+
+#
+# Fixture for fat test
+#
+@pytest.fixture()
+def fs_obj_fat(request, u_boot_config):
+ """Set up a file system to be used in fat test.
+
+ Args:
+ request: Pytest request object.
+ u_boot_config: U-Boot configuration.
+
+ Return:
+ A fixture for fat test, i.e. a duplet of file system type and
+ volume file name.
+ """
+
+ # the maximum size of a FAT12 filesystem resulting in 4084 clusters
+ MAX_FAT12_SIZE = 261695 * 1024
+
+ # the minimum size of a FAT16 filesystem that can be created with
+ # mkfs.vfat resulting in 4087 clusters
+ MIN_FAT16_SIZE = 8208 * 1024
+
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ fs_size = MAX_FAT12_SIZE if fs_type == 'fat12' else MIN_FAT16_SIZE
+
+ try:
+ # the volume size depends on the filesystem
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', 1024)
+ except:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ return
+ else:
+ yield [fs_ubtype, fs_img]
+ call('rm -f %s' % fs_img, shell=True)
"""
build_dir = u_boot_console.config.build_dir
+ # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
+ # add EFI boot option when the new disk is detected. If there is no EFI
+ # System Partition exists, EFI subsystem outputs error messages and
+ # it ends up with test failure.
+ # Restart U-Boot to clear the previous state.
+ # TODO: Ideally EFI test cases need to be fixed, but it will
+ # increase the number of system reset.
+ u_boot_console.restart_uboot()
+
try:
# setup test environment
make_erofs_image(build_dir)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Weidmüller Interface GmbH & Co. KG
+# Author: Christian Taedcke <christian.taedcke@weidmueller.com>
+#
+# U-Boot File System: FAT Test
+
+"""
+This test verifies fat specific file system behaviour.
+"""
+
+import pytest
+import re
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.slow
+class TestFsFat(object):
+ def test_fs_fat1(self, u_boot_console, fs_obj_fat):
+ """Test that `fstypes` prints a result which includes `sandbox`."""
+ fs_type,fs_img = fs_obj_fat
+ with u_boot_console.log.section('Test Case 1 - fatinfo'):
+ # Test Case 1 - ls
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ 'fatinfo host 0:0'])
+ assert(re.search('Filesystem: %s' % fs_type.upper(), ''.join(output)))
"""
build_dir = u_boot_console.config.build_dir
+ # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
+ # add EFI boot option when the new disk is detected. If there is no EFI
+ # System Partition exists, EFI subsystem outputs error messages and
+ # it ends up with test failure.
+ # Restart U-Boot to clear the previous state.
+ # TODO: Ideally EFI test cases need to be fixed, but it will
+ # increase the number of system reset.
+ u_boot_console.restart_uboot()
+
# setup test environment
check_mksquashfs_version()
generate_sqfs_src_dir(build_dir)
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
-
-# Test operation of the "if" shell command.
-
-import os
-import os.path
-import pytest
-
-# TODO: These tests should be converted to a C test.
-# For more information please take a look at the thread
-# https://lists.denx.de/pipermail/u-boot/2019-October/388732.html
-
-pytestmark = pytest.mark.buildconfigspec('hush_parser')
-
-# The list of "if test" conditions to test.
-subtests = (
- # Base if functionality.
-
- ('true', True),
- ('false', False),
-
- # Basic operators.
-
- ('test aaa = aaa', True),
- ('test aaa = bbb', False),
-
- ('test aaa != bbb', True),
- ('test aaa != aaa', False),
-
- ('test aaa < bbb', True),
- ('test bbb < aaa', False),
-
- ('test bbb > aaa', True),
- ('test aaa > bbb', False),
-
- ('test 123 -eq 123', True),
- ('test 123 -eq 456', False),
-
- ('test 123 -ne 456', True),
- ('test 123 -ne 123', False),
-
- ('test 123 -lt 456', True),
- ('test 123 -lt 123', False),
- ('test 456 -lt 123', False),
-
- ('test 123 -le 456', True),
- ('test 123 -le 123', True),
- ('test 456 -le 123', False),
-
- ('test 456 -gt 123', True),
- ('test 123 -gt 123', False),
- ('test 123 -gt 456', False),
-
- ('test 456 -ge 123', True),
- ('test 123 -ge 123', True),
- ('test 123 -ge 456', False),
-
- # Octal tests
-
- ('test 010 -eq 010', True),
- ('test 010 -eq 011', False),
-
- ('test 010 -ne 011', True),
- ('test 010 -ne 010', False),
-
- # Hexadecimal tests
-
- ('test 0x2000000 -gt 0x2000001', False),
- ('test 0x2000000 -gt 0x2000000', False),
- ('test 0x2000000 -gt 0x1ffffff', True),
-
- # Mixed tests
-
- ('test 010 -eq 10', False),
- ('test 010 -ne 10', True),
- ('test 0xa -eq 10', True),
- ('test 0xa -eq 012', True),
-
- ('test 2000000 -gt 0x1ffffff', False),
- ('test 0x2000000 -gt 1ffffff', True),
- ('test 0x2000000 -lt 1ffffff', False),
- ('test 0x2000000 -eq 2000000', False),
- ('test 0x2000000 -ne 2000000', True),
-
- ('test -z ""', True),
- ('test -z "aaa"', False),
-
- ('test -n "aaa"', True),
- ('test -n ""', False),
-
- # Inversion of simple tests.
-
- ('test ! aaa = aaa', False),
- ('test ! aaa = bbb', True),
- ('test ! ! aaa = aaa', True),
- ('test ! ! aaa = bbb', False),
-
- # Binary operators.
-
- ('test aaa != aaa -o bbb != bbb', False),
- ('test aaa != aaa -o bbb = bbb', True),
- ('test aaa = aaa -o bbb != bbb', True),
- ('test aaa = aaa -o bbb = bbb', True),
-
- ('test aaa != aaa -a bbb != bbb', False),
- ('test aaa != aaa -a bbb = bbb', False),
- ('test aaa = aaa -a bbb != bbb', False),
- ('test aaa = aaa -a bbb = bbb', True),
-
- # Inversion within binary operators.
-
- ('test ! aaa != aaa -o ! bbb != bbb', True),
- ('test ! aaa != aaa -o ! bbb = bbb', True),
- ('test ! aaa = aaa -o ! bbb != bbb', True),
- ('test ! aaa = aaa -o ! bbb = bbb', False),
-
- ('test ! ! aaa != aaa -o ! ! bbb != bbb', False),
- ('test ! ! aaa != aaa -o ! ! bbb = bbb', True),
- ('test ! ! aaa = aaa -o ! ! bbb != bbb', True),
- ('test ! ! aaa = aaa -o ! ! bbb = bbb', True),
-)
-
-def exec_hush_if(u_boot_console, expr, result):
- """Execute a shell "if" command, and validate its result."""
-
- config = u_boot_console.config.buildconfig
- maxargs = int(config.get('config_sys_maxargs', '0'))
- args = len(expr.split(' ')) - 1
- if args > maxargs:
- u_boot_console.log.warning('CONFIG_SYS_MAXARGS too low; need ' +
- str(args))
- pytest.skip()
-
- cmd = 'if ' + expr + '; then echo true; else echo false; fi'
- response = u_boot_console.run_command(cmd)
- assert response.strip() == str(result).lower()
-
-@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.parametrize('expr,result', subtests)
-def test_hush_if_test(u_boot_console, expr, result):
- """Test a single "if test" condition."""
-
- exec_hush_if(u_boot_console, expr, result)
-
-def test_hush_z(u_boot_console):
- """Test the -z operator"""
- u_boot_console.run_command('setenv ut_var_nonexistent')
- u_boot_console.run_command('setenv ut_var_exists 1')
- exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True)
- exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False)
- u_boot_console.run_command('setenv ut_var_exists')
-
-# We might test this on real filesystems via UMS, DFU, 'save', etc.
-# Of those, only UMS currently allows file removal though.
-@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.boardspec('sandbox')
-def test_hush_if_test_host_file_exists(u_boot_console):
- """Test the "if test -e" shell command."""
-
- test_file = u_boot_console.config.result_dir + \
- '/creating_this_file_breaks_u_boot_tests'
-
- try:
- os.unlink(test_file)
- except:
- pass
- assert not os.path.exists(test_file)
-
- expr = 'test -e hostfs - ' + test_file
- exec_hush_if(u_boot_console, expr, False)
-
- try:
- with open(test_file, 'wb'):
- pass
- assert os.path.exists(test_file)
-
- expr = 'test -e hostfs - ' + test_file
- exec_hush_if(u_boot_console, expr, True)
- finally:
- os.unlink(test_file)
-
- expr = 'test -e hostfs - ' + test_file
- exec_hush_if(u_boot_console, expr, False)
-
-def test_hush_var(u_boot_console):
- """Test the set and unset of variables"""
- u_boot_console.run_command('ut_var_nonexistent=')
- u_boot_console.run_command('ut_var_exists=1')
- u_boot_console.run_command('ut_var_unset=1')
- exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True)
- exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False)
- exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', False)
- exec_hush_if(u_boot_console, 'ut_var_unset=', True)
- exec_hush_if(u_boot_console, 'test -z "$ut_var_unset"', True)
- u_boot_console.run_command('ut_var_exists=')
- u_boot_console.run_command('ut_var_unset=')
import pytest
import u_boot_utils
import uuid
+import datetime
"""
Note: This test relies on boardenv_* containing configuration values to define
'addr': 0x10000000,
'size': 5058624,
'crc32': 'c2244b26',
+ 'timeout': 50000,
+ 'fnu': 'ubtest-upload.bin',
}
# Details regarding a file that may be read from a NFS server. This variable
assert expected_text_default in output
assert "Config file 'default.boot' found" in output
+
+@pytest.mark.buildconfigspec("cmd_crc32")
+@pytest.mark.buildconfigspec("cmd_net")
+@pytest.mark.buildconfigspec("cmd_tftpput")
+def test_net_tftpput(u_boot_console):
+ """Test the tftpput command.
+
+ A file is downloaded from the TFTP server and then uploaded to the TFTP
+ server, its size and its CRC32 are validated.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+
+ if not net_set_up:
+ pytest.skip("Network not initialized")
+
+ f = u_boot_console.config.env.get("env__net_tftp_readable_file", None)
+ if not f:
+ pytest.skip("No TFTP readable file to read")
+
+ addr = f.get("addr", None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
+ sz = f.get("size", None)
+ timeout = f.get("timeout", u_boot_console.p.timeout)
+ fn = f["fn"]
+ fnu = f.get("fnu", "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn]))
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn))
+
+ assert "TIMEOUT" not in output
+ assert expected_text in output
+
+ expected_tftpb_crc = f.get("crc32", None)
+
+ output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ assert expected_tftpb_crc in output
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ "tftpput $fileaddr $filesize $serverip:%s" % (fnu)
+ )
+
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+ addr = addr + sz
+ assert "TIMEOUT" not in output
+ assert "Access violation" not in output
+ assert expected_text in output
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu))
+
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+ assert "TIMEOUT" not in output
+ assert expected_text in output
+
+ output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ assert expected_tftpb_crc in output
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright 2022 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+import pytest
+
+import u_boot_utils as util
+
+# This is needed for Azure, since the default '..' directory is not writeable
+TMPDIR = '/tmp/test_cmdline'
+
+@pytest.mark.slow
+@pytest.mark.boardspec('sandbox')
+def test_sandbox_cmdline(u_boot_console):
+ """Test building sandbox without CONFIG_CMDLINE"""
+ cons = u_boot_console
+
+ out = util.run_and_log(
+ cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ '-a', '~CMDLINE', '-o', TMPDIR])
+
+@pytest.mark.slow
+@pytest.mark.boardspec('sandbox')
+def test_sandbox_lto(u_boot_console):
+ """Test building sandbox without CONFIG_LTO"""
+ cons = u_boot_console
+
+ out = util.run_and_log(
+ cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ '-a', '~LTO', '-o', TMPDIR])
import pytest
import u_boot_utils
+# pylint: disable=E0611
from tests import fs_helper
def mkdir_cond(dirname):
execute command 'ut foo bar'
"""
- output = u_boot_console.run_command('ut ' + ut_subtest)
+ if ut_subtest == 'hush hush_test_simple_dollar':
+ # ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
+ with u_boot_console.disable_check('unknown_command'):
+ output = u_boot_console.run_command('ut ' + ut_subtest)
+ assert('Unknown command \'quux\' - try \'help\'' in output)
+ else:
+ output = u_boot_console.run_command('ut ' + ut_subtest)
assert output.endswith('Failures: 0')
with open(evil_kernel, 'wb') as fd:
fd.write(500 * b'\x01')
+ # We need to use our own device tree file. Remember to restore it
+ # afterwards.
+ old_dtb = cons.config.dtb
try:
- # We need to use our own device tree file. Remember to restore it
- # afterwards.
- old_dtb = cons.config.dtb
cons.config.dtb = dtb
if global_sign:
test_global_sign(sha_algo, padding, sign_options)
return 0;
}
+int ut_check_skip_to_linen(struct unit_test_state *uts, const char *fmt, ...)
+{
+ va_list args;
+ int len;
+ int ret;
+
+ va_start(args, fmt);
+ len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
+ va_end(args);
+ if (len >= sizeof(uts->expect_str)) {
+ ut_fail(uts, __FILE__, __LINE__, __func__,
+ "unit_test_state->expect_str too small");
+ return -EOVERFLOW;
+ }
+ while (1) {
+ if (!console_record_avail())
+ return -ENOENT;
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
+
+ if (!strncmp(uts->expect_str, uts->actual_str,
+ strlen(uts->expect_str)))
+ return 0;
+ }
+}
+
int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...)
{
va_list args;
If the blobs are in a different directory, you can specify this with the `-I`
option.
-For U-Boot, you can use set the BINMAN_INDIRS environment variable to provide a
+For U-Boot, you can set the BINMAN_INDIRS environment variable to provide a
space-separated list of directories to search for binary blobs::
BINMAN_INDIRS="odroid-c4/fip/g12a \
return self.run_cmd(*args)
def x509_cert_sysfw(self, cert_fname, input_fname, key_fname, sw_rev,
- config_fname, req_dist_name_dict):
+ config_fname, req_dist_name_dict, firewall_cert_data):
"""Create a certificate to be booted by system firmware
Args:
req_dist_name_dict (dict): Dictionary containing key-value pairs of
req_distinguished_name section extensions, must contain extensions for
C, ST, L, O, OU, CN and emailAddress
+ firewall_cert_data (dict):
+ - auth_in_place (int): The Priv ID for copying as the
+ specific host in firewall protected region
+ - num_firewalls (int): The number of firewalls in the
+ extended certificate
+ - certificate (str): Extended firewall certificate with
+ the information for the firewall configurations.
Returns:
str: Tool output
1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
1.3.6.1.4.1.294.1.34 = ASN1:SEQUENCE:sysfw_image_integrity
1.3.6.1.4.1.294.1.35 = ASN1:SEQUENCE:sysfw_image_load
+1.3.6.1.4.1.294.1.37 = ASN1:SEQUENCE:firewall
[ swrv ]
swrv = INTEGER:{sw_rev}
[ sysfw_image_load ]
destAddr = FORMAT:HEX,OCT:00000000
-authInPlace = INTEGER:2
+authInPlace = INTEGER:{hex(firewall_cert_data['auth_in_place'])}
+
+[ firewall ]
+numFirewallRegions = INTEGER:{firewall_cert_data['num_firewalls']}
+{firewall_cert_data['certificate']}
''', file=outf)
args = ['req', '-new', '-x509', '-key', key_fname, '-nodes',
'-outform', 'DER', '-out', cert_fname, '-config', config_fname,
def testEmbedFail(self):
"""Test calling GetSymbolFileOffset() without elftools"""
+ old_val = elf.ELF_TOOLS
try:
- old_val = elf.ELF_TOOLS
elf.ELF_TOOLS = False
fname = self.ElfTestFile('embed_data')
with self.assertRaises(ValueError) as e:
def test_read_segments_fail(self):
"""Test for read_loadable_segments() without elftools"""
+ old_val = elf.ELF_TOOLS
try:
- old_val = elf.ELF_TOOLS
elf.ELF_TOOLS = False
fname = self.ElfTestFile('embed_data')
with self.assertRaises(ValueError) as e:
def test_get_file_offset_fail(self):
"""Test calling GetFileOffset() without elftools"""
+ old_val = elf.ELF_TOOLS
try:
- old_val = elf.ELF_TOOLS
elf.ELF_TOOLS = False
fname = self.ElfTestFile('embed_data')
with self.assertRaises(ValueError) as e:
def test_get_symbol_from_address_fail(self):
"""Test calling GetSymbolFromAddress() without elftools"""
+ old_val = elf.ELF_TOOLS
try:
- old_val = elf.ELF_TOOLS
elf.ELF_TOOLS = False
fname = self.ElfTestFile('embed_data')
with self.assertRaises(ValueError) as e:
+.. _etype_ti_dm:
+
+Entry: ti-dm: TI Device Manager (DM) blob
+-----------------------------------------
+
+Properties / Entry arguments:
+ - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin
+
+This entry holds the device manager responsible for resource and power management
+in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information
+about TI DM.
+
+
+
.. _etype_ti_secure:
Entry: ti-secure: Entry containing a TI x509 certificate binary
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis <n-francis@ti.com>
+#
+# Entry-type module for TI Device Manager (DM)
+#
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+
+class Entry_ti_dm(Entry_blob_named_by_arg):
+ """TI Device Manager (DM) blob
+
+ Properties / Entry arguments:
+ - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin
+
+ This entry holds the device manager responsible for resource and power management
+ in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information
+ about TI DM.
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node, 'ti-dm')
+ self.external = True
from binman.entry import EntryArg
from binman.etype.x509_cert import Entry_x509_cert
+from dataclasses import dataclass
from dtoc import fdt_util
+@dataclass
+class Firewall():
+ id: int
+ region: int
+ control : int
+ permissions: list
+ start_address: str
+ end_address: str
+
+ def ensure_props(self, etype, name):
+ missing_props = []
+ for key, val in self.__dict__.items():
+ if val is None:
+ missing_props += [key]
+
+ if len(missing_props):
+ etype.Raise(f"Subnode '{name}' is missing properties: {','.join(missing_props)}")
+
+ def get_certificate(self) -> str:
+ unique_identifier = f"{self.id}{self.region}"
+ cert = f"""
+firewallID{unique_identifier} = INTEGER:{self.id}
+region{unique_identifier} = INTEGER:{self.region}
+control{unique_identifier} = INTEGER:{hex(self.control)}
+nPermissionRegs{unique_identifier} = INTEGER:{len(self.permissions)}
+"""
+ for index, permission in enumerate(self.permissions):
+ cert += f"""permissions{unique_identifier}{index} = INTEGER:{hex(permission)}
+"""
+ cert += f"""startAddress{unique_identifier} = FORMAT:HEX,OCT:{self.start_address:02x}
+endAddress{unique_identifier} = FORMAT:HEX,OCT:{self.end_address:02x}
+"""
+ return cert
+
class Entry_ti_secure(Entry_x509_cert):
"""Entry containing a TI x509 certificate binary
- content: List of phandles to entries to sign
- keyfile: Filename of file containing key to sign binary with
- sha: Hash function to be used for signing
+ - auth-in-place: This is an integer field that contains two pieces
+ of information
+ Lower Byte - Remains 0x02 as per our use case
+ ( 0x02: Move the authenticated binary back to the header )
+ Upper Byte - The Host ID of the core owning the firewall
Output files:
- input.<unique_name> - input file passed to openssl
- cert.<unique_name> - output file generated by openssl (which is
used as the entry contents)
+ Depending on auth-in-place information in the inputs, we read the
+ firewall nodes that describe the configurations of firewall that TIFS
+ will be doing after reading the certificate.
+
+ The syntax of the firewall nodes are as such:
+
+ firewall-257-0 {
+ id = <257>; /* The ID of the firewall being configured */
+ region = <0>; /* Region number to configure */
+
+ control = /* The control register */
+ <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>;
+
+ permissions = /* The permission registers */
+ <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>;
+
+ /* More defines can be found in k3-security.h */
+
+ start_address = /* The Start Address of the firewall */
+ <0x0 0x0>;
+ end_address = /* The End Address of the firewall */
+ <0xff 0xffffffff>;
+ };
+
+
openssl signs the provided data, using the TI templated config file and
writes the signature in this entry. This allows verification that the
data is genuine.
def __init__(self, section, etype, node):
super().__init__(section, etype, node)
self.openssl = None
+ self.firewall_cert_data: dict = {
+ 'auth_in_place': 0x02,
+ 'num_firewalls': 0,
+ 'certificate': '',
+ }
def ReadNode(self):
super().ReadNode()
self.key_fname = self.GetEntryArgsOrProps([
EntryArg('keyfile', str)], required=True)[0]
+ auth_in_place = fdt_util.GetInt(self._node, 'auth-in-place')
+ if auth_in_place:
+ self.firewall_cert_data['auth_in_place'] = auth_in_place
+ self.ReadFirewallNode()
self.sha = fdt_util.GetInt(self._node, 'sha', 512)
self.req_dist_name = {'C': 'US',
'ST': 'TX',
'CN': 'TI Support',
'emailAddress': 'support@ti.com'}
+ def ReadFirewallNode(self):
+ self.firewall_cert_data['certificate'] = ""
+ self.firewall_cert_data['num_firewalls'] = 0
+ for node in self._node.subnodes:
+ if 'firewall' in node.name:
+ firewall = Firewall(
+ fdt_util.GetInt(node, 'id'),
+ fdt_util.GetInt(node, 'region'),
+ fdt_util.GetInt(node, 'control'),
+ fdt_util.GetPhandleList(node, 'permissions'),
+ fdt_util.GetInt64(node, 'start_address'),
+ fdt_util.GetInt64(node, 'end_address'),
+ )
+ firewall.ensure_props(self, node.name)
+ self.firewall_cert_data['num_firewalls'] += 1
+ self.firewall_cert_data['certificate'] += firewall.get_certificate()
+
def GetCertificate(self, required):
"""Get the contents of this entry
self.hashval_sysfw_data = None
self.sysfw_inner_cert_ext_boot_block = None
self.dm_data_ext_boot_block = None
+ self.firewall_cert_data = None
def ReadNode(self):
super().ReadNode()
key_fname=self.key_fname,
config_fname=config_fname,
sw_rev=self.sw_rev,
- req_dist_name_dict=self.req_dist_name)
+ req_dist_name_dict=self.req_dist_name,
+ firewall_cert_data=self.firewall_cert_data)
elif type == 'rom':
stdout = self.openssl.x509_cert_rom(
cert_fname=output_fname,
FSP_T_DATA = b'fsp_t'
ATF_BL31_DATA = b'bl31'
TEE_OS_DATA = b'this is some tee OS data'
+TI_DM_DATA = b'tidmtidm'
ATF_BL2U_DATA = b'bl2u'
OPENSBI_DATA = b'opensbi'
SCP_DATA = b'scp'
TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA)
+ TestFunctional._MakeInputFile('dm.bin', TI_DM_DATA)
TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA)
TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
fdt_size = entries['section'].GetEntries()['u-boot-dtb'].size
fdtmap_offset = entries['fdtmap'].offset
+ tmpdir = None
try:
tmpdir, updated_fname = self._SetupImageInTmpdir()
with test_util.capture_sys_output() as (stdout, stderr):
self._DoBinman('ls', '-i', updated_fname)
finally:
- shutil.rmtree(tmpdir)
+ if tmpdir:
+ shutil.rmtree(tmpdir)
lines = stdout.getvalue().splitlines()
expected = [
'Name Image-pos Size Entry-type Offset Uncomp-size',
def testListCmdFail(self):
"""Test failing to list an image"""
self._DoReadFile('005_simple.dts')
+ tmpdir = None
try:
tmpdir, updated_fname = self._SetupImageInTmpdir()
with self.assertRaises(ValueError) as e:
self._DoBinman('ls', '-i', updated_fname)
finally:
- shutil.rmtree(tmpdir)
+ if tmpdir:
+ shutil.rmtree(tmpdir)
self.assertIn("Cannot find FDT map in image", str(e.exception))
def _RunListCmd(self, paths, expected):
self._CheckLz4()
self._DoReadFileRealDtb('130_list_fdtmap.dts')
fname = os.path.join(self._indir, 'output.extact')
+ tmpdir = None
try:
tmpdir, updated_fname = self._SetupImageInTmpdir()
with test_util.capture_sys_output() as (stdout, stderr):
self._DoBinman('extract', '-i', updated_fname, 'u-boot',
'-f', fname)
finally:
- shutil.rmtree(tmpdir)
+ if tmpdir:
+ shutil.rmtree(tmpdir)
data = tools.read_file(fname)
self.assertEqual(U_BOOT_DATA, data)
data = self._DoReadFileRealDtb('207_fip_ls.dts')
hdr, fents = fip_util.decode_fip(data)
+ tmpdir = None
try:
tmpdir, updated_fname = self._SetupImageInTmpdir()
with test_util.capture_sys_output() as (stdout, stderr):
self._DoBinman('ls', '-i', updated_fname)
finally:
- shutil.rmtree(tmpdir)
+ if tmpdir:
+ shutil.rmtree(tmpdir)
lines = stdout.getvalue().splitlines()
expected = [
'Name Image-pos Size Entry-type Offset Uncomp-size',
use_real_dtb=True,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])
+ tmpdir = None
try:
tmpdir, updated_fname = self._SetupImageInTmpdir()
with test_util.capture_sys_output() as (stdout, stderr):
self._RunBinman('ls', '-i', updated_fname)
finally:
- shutil.rmtree(tmpdir)
+ if tmpdir:
+ shutil.rmtree(tmpdir)
def testFitSubentryUsesBintool(self):
"""Test that binman FIT subentries can use bintools"""
data = self._DoReadFile('222_tee_os.dts')
self.assertEqual(TEE_OS_DATA, data[:len(TEE_OS_DATA)])
+ def testPackTiDm(self):
+ """Test that an image with a TI DM binary can be created"""
+ data = self._DoReadFile('225_ti_dm.dts')
+ self.assertEqual(TI_DM_DATA, data[:len(TI_DM_DATA)])
+
def testFitFdtOper(self):
"""Check handling of a specified FIT operation"""
entry_args = {
entry_args=entry_args)[0]
self.assertGreater(len(data), len(TI_UNSECURE_DATA))
+ def testPackTiSecureFirewall(self):
+ """Test that an image with a TI secured binary can be created"""
+ keyfile = self.TestFile('key.key')
+ entry_args = {
+ 'keyfile': keyfile,
+ }
+ data_no_firewall = self._DoReadFileDtb('296_ti_secure.dts',
+ entry_args=entry_args)[0]
+ data_firewall = self._DoReadFileDtb('324_ti_secure_firewall.dts',
+ entry_args=entry_args)[0]
+ self.assertGreater(len(data_firewall),len(data_no_firewall))
+
+ def testPackTiSecureFirewallMissingProperty(self):
+ """Test that an image with a TI secured binary can be created"""
+ keyfile = self.TestFile('key.key')
+ entry_args = {
+ 'keyfile': keyfile,
+ }
+ with self.assertRaises(ValueError) as e:
+ data_firewall = self._DoReadFileDtb('325_ti_secure_firewall_missing_property.dts',
+ entry_args=entry_args)[0]
+ self.assertRegex(str(e.exception), "Node '/binman/ti-secure': Subnode 'firewall-0-2' is missing properties: id,region")
+
def testPackTiSecureMissingTool(self):
"""Test that an image with a TI secured binary (non-functional) can be created
when openssl is missing"""
[project]
name = "binary-manager"
-version = "0.0.2"
+version = "0.0.6"
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
-dependencies = ["pylibfdt", "u_boot_pylib", "dtoc"]
+dependencies = ["pylibfdt", "u_boot_pylib >= 0.0.6", "dtoc >= 0.0.6"]
description = "Binman firmware-packaging tool"
readme = "README.rst"
requires-python = ">=3.7"
]
[project.urls]
-"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/package/index.html"
+"Homepage" = "https://docs.u-boot.org/en/latest/develop/package/index.html"
"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
[project.scripts]
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ binman {
+ ti-dm {
+ filename = "dm.bin";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ ti-secure {
+ content = <&unsecure_binary>;
+ auth-in-place = <0xa02>;
+
+ firewall-0-2 {
+ id = <0>;
+ region = <2>;
+ control = <0x31a>;
+ permissions = <0xc3ffff>;
+ start_address = <0x0 0x9e800000>;
+ end_address = <0x0 0x9fffffff>;
+ };
+
+ };
+ unsecure_binary: blob-ext {
+ filename = "ti_unsecure.bin";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ ti-secure {
+ content = <&unsecure_binary>;
+ auth-in-place = <0xa02>;
+
+ firewall-0-2 {
+ // id = <0>;
+ // region = <2>;
+ control = <0x31a>;
+ permissions = <0xc3ffff>;
+ start_address = <0x0 0x9e800000>;
+ end_address = <0x0 0x9fffffff>;
+ };
+
+ };
+ unsecure_binary: blob-ext {
+ filename = "ti_unsecure.bin";
+ };
+ };
+};
"""Set up a new Expr object.
Args:
- expr (str): String cotaining regular expression to store
+ expr (str): String containing regular expression to store
"""
self._expr = expr
self._re = re.compile(expr)
Args:
commit: Commit object that is being built
brd: Board object that is being built
- stage: Stage that we are at (mrproper, config, build)
+ stage: Stage that we are at (mrproper, config, oldconfig, build)
cwd: Directory where make should be run
args: Arguments to pass to make
kwargs: Arguments to pass to command.run_pipe()
# Now do the build, if everything looks OK
if result.return_code == 0:
+ if adjust_cfg:
+ oldc_args = list(args) + ['oldconfig']
+ oldc_result = self.make(commit, brd, 'oldconfig', cwd,
+ *oldc_args, env=env)
+ if oldc_result.return_code:
+ return oldc_result
result = self._build(commit, brd, cwd, args, env, cmd_list,
config_only)
if adjust_cfg:
tools.write_file(fname, b'CONFIG_SOMETHING=1')
return command.CommandResult(return_code=0,
combined='Test configuration complete')
+ elif stage == 'oldconfig':
+ return command.CommandResult(return_code=0)
elif stage == 'build':
stderr = ''
fname = os.path.join(cwd or '', out_dir, 'u-boot')
return command.CommandResult(return_code=0)
# Not handled, so abort
- print('make', stage)
+ print('_HandleMake failure: make', stage)
sys.exit(1)
# Example function to print output lines
[project]
name = "buildman"
-version = "0.0.2"
+version = "0.0.6"
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
-dependencies = ["u_boot_pylib", "patch-manager"]
+dependencies = ["u_boot_pylib >= 0.0.6", "patch-manager >= 0.0.6"]
description = "Buildman build tool for U-Boot"
readme = "README.rst"
requires-python = ">=3.7"
]
[project.urls]
-"Homepage" = "https://u-boot.readthedocs.io/en/latest/build/buildman.html"
+"Homepage" = "https://docs.u-boot.org/en/latest/build/buildman.html"
"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
[project.scripts]
for node in parent.subnodes.__reversed__():
dst = self.copy_node(node)
- tout.debug(f'merge props from {parent.path} to {dst.path}')
+ tout.debug(f'merge props from {parent.path} to {self.path}')
self.merge_props(parent, False)
[project]
name = "dtoc"
-version = "0.0.2"
+version = "0.0.6"
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
-dependencies = ["pylibfdt", "u_boot_pylib"]
+dependencies = ["pylibfdt", "u_boot_pylib >= 0.0.6"]
description = "Devicetree-to-C generator"
readme = "README.rst"
requires-python = ">=3.7"
]
[project.urls]
-"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/driver-model/of-plat.html"
+"Homepage" = "https://docs.u-boot.org/en/latest/develop/driver-model/of-plat.html"
"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
[project.scripts]
this environment instance. On NAND this is used to limit the range
within which bad blocks are skipped, on NOR it is not used.
+If DEVICEx_ESIZE and DEVICEx_ENVSECTORS are both zero, then a runtime
+detection is attempted for NOR and NAND mtd types.
+
To prevent losing changes to the environment and to prevent confusing the MTD
drivers, a lock file at /run/fw_printenv.lock is used to serialize access
to the environment.
*/
lseek(fd, blockstart + block_seek, SEEK_SET);
- rc = read(fd, buf + processed, readlen);
- if (rc == -1) {
- fprintf(stderr, "Read error on %s: %s\n",
- DEVNAME(dev), strerror(errno));
- return -1;
- }
+ while (readlen) {
+ rc = read(fd, buf + processed, readlen);
+ if (rc == -1) {
+ fprintf(stderr, "Read error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
+ return -1;
+ }
#ifdef DEBUG
- fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
- rc, (unsigned long long)blockstart + block_seek,
- DEVNAME(dev));
+ fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
+ rc, (unsigned long long)blockstart + block_seek,
+ DEVNAME(dev));
#endif
- processed += rc;
- if (rc != readlen) {
- fprintf(stderr,
- "Warning on %s: Attempted to read %zd bytes but got %d\n",
- DEVNAME(dev), readlen, rc);
+ processed += rc;
readlen -= rc;
- block_seek += rc;
- } else {
- blockstart += blocklen;
- readlen = min(blocklen, count - processed);
- block_seek = 0;
}
+
+ blockstart += blocklen;
+ readlen = min(blocklen, count - processed);
+ block_seek = 0;
}
return processed;
{
int crc0, crc0_ok;
unsigned char flag0;
- void *addr0 = NULL;
+ void *buf0 = NULL;
int crc1, crc1_ok;
unsigned char flag1;
- void *addr1 = NULL;
+ void *buf1 = NULL;
int ret;
if (parse_config(opts)) /* should fill envdevices */
return -EINVAL;
- addr0 = calloc(1, CUR_ENVSIZE);
- if (addr0 == NULL) {
+ buf0 = calloc(1, CUR_ENVSIZE);
+ if (buf0 == NULL) {
fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
CUR_ENVSIZE);
}
dev_current = 0;
- if (flash_io(O_RDONLY, addr0, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, buf0, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
if (!have_redund_env) {
- struct env_image_single *single = addr0;
+ struct env_image_single *single = buf0;
crc0 = crc32(0, (uint8_t *)single->data, ENV_SIZE);
crc0_ok = (crc0 == single->crc);
environment.dirty = 1;
}
- environment.image = addr0;
+ environment.image = buf0;
environment.crc = &single->crc;
environment.flags = NULL;
environment.data = single->data;
} else {
- struct env_image_redundant *redundant0 = addr0;
+ struct env_image_redundant *redundant0 = buf0;
struct env_image_redundant *redundant1;
crc0 = crc32(0, (uint8_t *)redundant0->data, ENV_SIZE);
flag0 = redundant0->flags;
dev_current = 1;
- addr1 = calloc(1, CUR_ENVSIZE);
- if (addr1 == NULL) {
+ buf1 = calloc(1, CUR_ENVSIZE);
+ if (buf1 == NULL) {
fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
CUR_ENVSIZE);
ret = -ENOMEM;
goto open_cleanup;
}
- redundant1 = addr1;
+ redundant1 = buf1;
- if (flash_io(O_RDONLY, addr1, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, buf1, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
* flags before writing out
*/
if (dev_current) {
- environment.image = addr1;
+ environment.image = buf1;
environment.crc = &redundant1->crc;
environment.flags = &redundant1->flags;
environment.data = redundant1->data;
- free(addr0);
+ free(buf0);
} else {
- environment.image = addr0;
+ environment.image = buf0;
environment.crc = &redundant0->crc;
environment.flags = &redundant0->flags;
environment.data = redundant0->data;
- free(addr1);
+ free(buf1);
}
#ifdef DEBUG
fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
return 0;
open_cleanup:
- if (addr0)
- free(addr0);
-
- if (addr1)
- free(addr1);
+ free(buf0);
+ free(buf1);
return ret;
}
}
DEVTYPE(dev) = mtdinfo.type;
if (DEVESIZE(dev) == 0 && ENVSECTORS(dev) == 0 &&
- mtdinfo.type == MTD_NORFLASH)
- DEVESIZE(dev) = mtdinfo.erasesize;
+ mtdinfo.erasesize > 0) {
+ if (mtdinfo.type == MTD_NORFLASH)
+ DEVESIZE(dev) = mtdinfo.erasesize;
+ else if (mtdinfo.type == MTD_NANDFLASH) {
+ DEVESIZE(dev) = mtdinfo.erasesize;
+ ENVSECTORS(dev) =
+ mtdinfo.size / mtdinfo.erasesize;
+ }
+ }
if (DEVESIZE(dev) == 0)
/* Assume the erase size is the same as the env-size */
DEVESIZE(dev) = ENVSIZE(dev);
}
while (!nvmem && (dent = readdir(dir))) {
+ struct stat s;
FILE *fp;
size_t size;
continue;
}
- size = fread(buf, sizeof(buf), 1, fp);
+ if (fstat(fileno(fp), &s)) {
+ fprintf(stderr, "Failed to fstat %s\n", comp);
+ goto next;
+ }
+
+ if (s.st_size >= sizeof(buf)) {
+ goto next;
+ }
+
+ size = fread(buf, s.st_size, 1, fp);
if (size != 1) {
fprintf(stderr,
"read failed about %s\n", comp);
- fclose(fp);
- return -EIO;
+ goto next;
}
-
+ buf[s.st_size] = '\0';
if (!strcmp(buf, "u-boot,env")) {
bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name);
}
}
+next:
fclose(fp);
}
int types_inc; /* Mask of types that we include (FDT_IS...) */
int types_exc; /* Mask of types that we exclude (FDT_IS...) */
int invert; /* Invert polarity of match */
+ int props_up; /* Imply properties up to supernodes */
struct value_node *value_head; /* List of values to match */
const char *output_fname; /* Output filename */
FILE *fout; /* File to write dts/dtb output */
const char *str;
int str_base = fdt_off_dt_strings(blob);
- for (offset = 0; offset < fdt_size_dt_strings(blob);
- offset += strlen(str) + 1) {
+ for (offset = 0;
+ offset < (int)fdt_size_dt_strings(blob);
+ offset += strlen(str) + 1) {
str = fdt_string(blob, offset);
int len = strlen(str) + 1;
int show;
{
struct fdt_header *fdt;
int size, struct_start;
- int ptr;
+ unsigned int ptr;
int i;
/* Set up a basic header (even if we don't actually write it) */
}
/**
- * h_include() - Include handler function for fdt_find_regions()
+ * check_props() - Check if a node has properties that we want to include
+ *
+ * Calls check_type_include() for each property in the nodn, returning 1 if
+ * that function returns 1 for any of them
+ *
+ * @disp: Display structure, holding info about our options
+ * @fdt: Devicetree blob to check
+ * @node: Node offset to check
+ * @inc: Current value of the 'include' variable (see h_include())
+ * Return: 0 to exclude, 1 to include, -1 if no information is available
+ */
+static int check_props(struct display_info *disp, const void *fdt, int node,
+ int inc)
+{
+ int offset;
+
+ for (offset = fdt_first_property_offset(fdt, node);
+ offset > 0 && inc != 1;
+ offset = fdt_next_property_offset(fdt, offset)) {
+ const struct fdt_property *prop;
+ const char *str;
+
+ prop = fdt_get_property_by_offset(fdt, offset, NULL);
+ if (!prop)
+ continue;
+ str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+ inc = check_type_include(disp, FDT_NODE_HAS_PROP, str,
+ strlen(str));
+ }
+
+ /* if requested, check all subnodes for this property too */
+ if (inc != 1 && disp->props_up) {
+ int subnode;
+
+ for (subnode = fdt_first_subnode(fdt, node);
+ subnode > 0 && inc != 1;
+ subnode = fdt_next_subnode(fdt, subnode))
+ inc = check_props(disp, fdt, subnode, inc);
+ }
+
+ return inc;
+}
+
+/**
+ * h_include() - Include handler function for fdt_first_region()
*
* This function decides whether to include or exclude a node, property or
- * compatible string. The function is defined by fdt_find_regions().
+ * compatible string. The function is defined by fdt_first_region().
*
* The algorithm is documented in the code - disp->invert is 0 for normal
* operation, and 1 to invert the sense of all matches.
*
- * See
+ * @priv: Private pointer as passed to fdtgrep_find_regions()
+ * @fdt: Pointer to FDT blob
+ * @offset: Offset of this node / property
+ * @type: Type of this part, FDT_IS_...
+ * @data: Pointer to data (node name, property name, compatible string)
+ * @size: Size of data, or 0 if none
+ * Return: 0 to exclude, 1 to include, -1 if no information is available
*/
static int h_include(void *priv, const void *fdt, int offset, int type,
const char *data, int size)
(disp->types_inc & FDT_NODE_HAS_PROP)) {
debug(" - checking node '%s'\n",
fdt_get_name(fdt, offset, NULL));
- for (offset = fdt_first_property_offset(fdt, offset);
- offset > 0 && inc != 1;
- offset = fdt_next_property_offset(fdt, offset)) {
- const struct fdt_property *prop;
- const char *str;
-
- prop = fdt_get_property_by_offset(fdt, offset, NULL);
- if (!prop)
- continue;
- str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
- inc = check_type_include(priv, FDT_NODE_HAS_PROP, str,
- strlen(str));
- }
+ inc = check_props(disp, fdt, offset, inc);
if (inc == -1)
inc = 0;
}
- switch (inc) {
- case 1:
- inc = !disp->invert;
- break;
- case 0:
- inc = disp->invert;
- break;
- }
+ if (inc != -1 && disp->invert)
+ inc = !inc;
debug(" - returning %d\n", inc);
return inc;
return new_count;
} else if (new_count <= max_regions) {
/*
- * The alias regions will now be at the end of the list.
- * Sort the regions by offset to get things into the
- * right order
- */
+ * The alias regions will now be at the end of the list.
+ * Sort the regions by offset to get things into the
+ * right order
+ */
count = new_count;
qsort(region, count, sizeof(struct fdt_region),
h_cmp_region);
region, max_regions, path, sizeof(path),
disp->flags);
if (count < 0) {
- report_error("fdt_find_regions", count);
+ report_error("fdtgrep_find_regions", count);
free(region);
return -1;
}
size = fdt_totalsize(fdt);
}
- if (size != fwrite(fdt, 1, size, disp->fout)) {
+ if ((size_t)size != fwrite(fdt, 1, size, disp->fout)) {
fprintf(stderr, "Write failure, %d bytes\n", size);
free(fdt);
ret = 1;
case '?': usage("unknown option");
static const char usage_short_opts[] =
- "haAc:b:C:defg:G:HIlLmn:N:o:O:p:P:rRsStTv"
+ "haAc:b:C:defg:G:HIlLmn:N:o:O:p:P:rRsStTuv"
USAGE_COMMON_SHORT_OPTS;
-static struct option const usage_long_opts[] = {
+static const struct option usage_long_opts[] = {
{"show-address", no_argument, NULL, 'a'},
{"colour", no_argument, NULL, 'A'},
{"include-node-with-prop", a_argument, NULL, 'b'},
{"include-mem", no_argument, NULL, 'm'},
{"include-node", a_argument, NULL, 'n'},
{"exclude-node", a_argument, NULL, 'N'},
+ {"out", a_argument, NULL, 'o'},
+ {"out-format", a_argument, NULL, 'O'},
{"include-prop", a_argument, NULL, 'p'},
{"exclude-prop", a_argument, NULL, 'P'},
{"remove-strings", no_argument, NULL, 'r'},
{"skip-supernodes", no_argument, NULL, 'S'},
{"show-stringtab", no_argument, NULL, 't'},
{"show-aliases", no_argument, NULL, 'T'},
- {"out", a_argument, NULL, 'o'},
- {"out-format", a_argument, NULL, 'O'},
+ {"props-up-to-supernode", no_argument, NULL, 'u'},
{"invert-match", no_argument, NULL, 'v'},
USAGE_COMMON_LONG_OPTS,
};
"Include mem_rsvmap section in binary output",
"Node to include in grep",
"Node to exclude in grep",
+ "-o <output file>",
+ "-O <output format>",
"Property to include in grep",
"Property to exclude in grep",
"Remove unused strings from string table",
"Don't include supernodes of matching nodes",
"Include string table in binary output",
"Include matching aliases in output",
- "-o <output file>",
- "-O <output format>",
+ "Add -p properties to supernodes too",
"Invert the sense of matching (select non-matching lines)",
USAGE_COMMON_OPTS_HELP
};
case 'H':
disp->header = 1;
break;
+ case 'I':
+ disp->show_dts_version = 1;
+ break;
case 'l':
disp->region_list = 1;
break;
case 'T':
disp->add_aliases = 1;
break;
+ case 'u':
+ disp->props_up = 1;
+ break;
case 'v':
disp->invert = 1;
break;
- case 'I':
- disp->show_dts_version = 1;
- break;
}
if (type && value_add(disp, &disp->value_head, type, inc,
--- /dev/null
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Script to check whether the file exists in mkimage cfg files for the i.MX9.
+#
+# usage: $0 <file.cfg>
+
+file=$1
+
+blobs=`awk '/^APPEND/ {print $2} /^IMAGE/ || /^DATA/ {print $3}' $file`
+for f in $blobs; do
+ tmp=$srctree/$f
+ if [ $f = "u-boot-spl-ddr.bin" ]; then
+ continue
+ fi
+
+ if [ -f $f ]; then
+ continue
+ fi
+
+ if [ ! -f $tmp ]; then
+ echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2
+
+ # Comment-out the lines for un-existing files. This way,
+ # mkimage can keep working. This allows CI tests to pass even
+ # if the resulting binary won't boot.
+ sed -in "/$f/ s/./#&/" $file
+ fi
+done
+
+exit 0
#include <sys/stat.h>
#include <sys/types.h>
#include <uuid/uuid.h>
-#include <linux/kconfig.h>
#include <gnutls/gnutls.h>
#include <gnutls/pkcs7.h>
goto err0;
}
- memset(buf, 0, size);
+ memset(buf, 0xff, size);
fcb = mx28_nand_get_fcb(MAX_BOOTSTREAM_SIZE);
if (!fcb) {
[project]
name = "patch-manager"
-version = "0.0.2"
+version = "0.0.6"
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
-dependencies = ["u_boot_pylib"]
+dependencies = ["u_boot_pylib >= 0.0.6"]
description = "Patman patch manager"
readme = "README.rst"
requires-python = ">=3.7"
]
[project.urls]
-"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/patman.html"
+"Homepage" = "https://docs.u-boot.org/en/latest/develop/patman.html"
"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
[project.scripts]
-patman = "patman.__main__"
+patman = "patman.__main__:run_patman"
[tool.setuptools.package-data]
patman = ["*.rst"]
.. SPDX-License-Identifier: GPL-2.0+
# U-Boot Python Library
-=====================
+=======================
This is a Python library used by various U-Boot tools, including patman,
buildman and binman.
[project]
name = "u_boot_pylib"
-version = "0.0.2"
+version = "0.0.6"
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
]
[project.urls]
-"Homepage" = "https://u-boot.readthedocs.io"
+"Homepage" = "https://docs.u-boot.org"
"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues"
-[tool.setuptools.packages.find]
-where = [".."]
-include = ["u_boot_pylib*"]
+[tool.setuptools.package-data]
+u_boot_pylib = ["*.rst"]
projects / thirdparty / u-boot.git / commitdiff
