--- /dev/null
+From 5ef4bac02189bee0b7c170e352d7a38e13fe9678 Mon Sep 17 00:00:00 2001
+From: Mahesh Vaidya <mahesh.vaidya@altera.com>
+Date: Thu, 30 Apr 2026 13:43:29 -0700
+Subject: PCI: altera: Do not dispose parent IRQ mapping
+
+From: Mahesh Vaidya <mahesh.vaidya@altera.com>
+
+commit 5ef4bac02189bee0b7c170e352d7a38e13fe9678 upstream.
+
+altera_pcie_irq_teardown() calls irq_dispose_mapping() on pcie->irq.
+However, pcie->irq is the parent IRQ returned by platform_get_irq(), not
+the mapping created by Altera INTx irq_domain.
+
+The Altera driver only sets the chained handler on the parent IRQ. It
+should detach that handler during teardown, but it should not dispose the
+parent IRQ mapping, which belongs to the parent interrupt controller's
+irq_domain.
+
+Drop irq_dispose_mapping(pcie->irq) from the teardown path.
+
+Note that during irqchip remove(), the child IRQs should've disposed. But
+since the chained handler itself is removed, there is no way the stale
+child IRQs (if exists) could fire. So it is safe here.
+
+Fixes: ec15c4d0d5d2 ("PCI: altera: Allow building as module")
+Signed-off-by: Mahesh Vaidya <mahesh.vaidya@altera.com>
+[mani: added a note about IRQ disposal]
+Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
+Reviewed-by: Subhransu S. Prusty <subhransu.sekhar.prusty@altera.com>
+Cc: stable@vger.kernel.org
+Link: https://patch.msgid.link/20260430204330.3121003-2-mahesh.vaidya@altera.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/pcie-altera.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-altera.c
++++ b/drivers/pci/controller/pcie-altera.c
+@@ -868,7 +868,6 @@ static void altera_pcie_irq_teardown(str
+ {
+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
+ irq_domain_remove(pcie->irq_domain);
+- irq_dispose_mapping(pcie->irq);
+ }
+
+ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
--- /dev/null
+From 7a94138caeb27f3c49c1dbd93bf422098925bb28 Mon Sep 17 00:00:00 2001
+From: Mahesh Vaidya <mahesh.vaidya@altera.com>
+Date: Thu, 30 Apr 2026 13:43:30 -0700
+Subject: PCI: altera: Fix resource leaks on probe failure
+
+From: Mahesh Vaidya <mahesh.vaidya@altera.com>
+
+commit 7a94138caeb27f3c49c1dbd93bf422098925bb28 upstream.
+
+The chained IRQ handler is set during probe, but is only removed during the
+driver remove(). If pci_host_probe() fails, the handler and INTx IRQ
+domain remain set even though the devm-managed host bridge storage
+containing struct altera_pcie will be released, leaving the handler with
+a stale data pointer.
+
+Interrupts are also enabled before pci_host_probe() is called. If probe
+fails after that point, the controller interrupt source should be disabled
+before the chained handler and INTx domain are removed.
+
+So set the chained handler only after the INTx domain has been created.
+Disable controller interrupts during IRQ teardown, and tear the IRQ setup
+down if pci_host_probe() fails.
+
+Fixes: c63aed7334c2 ("PCI: altera: Use pci_host_probe() to register host")
+Signed-off-by: Mahesh Vaidya <mahesh.vaidya@altera.com>
+[mani: commit log]
+Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
+Reviewed-by: Subhransu S. Prusty <subhransu.sekhar.prusty@altera.com>
+Cc: stable@vger.kernel.org
+Link: https://patch.msgid.link/20260430204330.3121003-3-mahesh.vaidya@altera.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/pcie-altera.c | 35 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 33 insertions(+), 2 deletions(-)
+
+--- a/drivers/pci/controller/pcie-altera.c
++++ b/drivers/pci/controller/pcie-altera.c
+@@ -864,8 +864,23 @@ static int altera_pcie_init_irq_domain(s
+ return 0;
+ }
+
++static void altera_pcie_disable_irq(struct altera_pcie *pcie)
++{
++ if (pcie->pcie_data->version == ALTERA_PCIE_V1 ||
++ pcie->pcie_data->version == ALTERA_PCIE_V2) {
++ /* Disable all P2A interrupts */
++ cra_writel(pcie, 0, P2A_INT_ENABLE);
++ } else if (pcie->pcie_data->version == ALTERA_PCIE_V3) {
++ /* Disable port-level interrupts (CFG_AER, etc.) */
++ writel(0, pcie->hip_base +
++ pcie->pcie_data->port_conf_offset +
++ pcie->pcie_data->port_irq_enable_offset);
++ }
++}
++
+ static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
+ {
++ altera_pcie_disable_irq(pcie);
+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
+ irq_domain_remove(pcie->irq_domain);
+ }
+@@ -890,7 +905,6 @@ static int altera_pcie_parse_dt(struct a
+ if (pcie->irq < 0)
+ return pcie->irq;
+
+- irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr, pcie);
+ return 0;
+ }
+
+@@ -1019,6 +1033,14 @@ static int altera_pcie_probe(struct plat
+ return ret;
+ }
+
++ /*
++ * The chained handler uses pcie->irq_domain, so set it only after the
++ * INTx domain has been created.
++ */
++ irq_set_chained_handler_and_data(pcie->irq,
++ pcie->pcie_data->ops->rp_isr,
++ pcie);
++
+ if (pcie->pcie_data->version == ALTERA_PCIE_V1 ||
+ pcie->pcie_data->version == ALTERA_PCIE_V2) {
+ /* clear all interrupts */
+@@ -1036,7 +1058,16 @@ static int altera_pcie_probe(struct plat
+ bridge->busnr = pcie->root_bus_nr;
+ bridge->ops = &altera_pcie_ops;
+
+- return pci_host_probe(bridge);
++ ret = pci_host_probe(bridge);
++ if (ret)
++ goto err_teardown_irq;
++
++ return 0;
++
++err_teardown_irq:
++ altera_pcie_irq_teardown(pcie);
++
++ return ret;
+ }
+
+ static void altera_pcie_remove(struct platform_device *pdev)
--- /dev/null
+From e373c789bac0ad73b472d8b44714df3bd18a4edf Mon Sep 17 00:00:00 2001
+From: Ziyao Li <liziyao@uniontech.com>
+Date: Sun, 12 Apr 2026 18:17:31 +0800
+Subject: PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series
+
+From: Ziyao Li <liziyao@uniontech.com>
+
+commit e373c789bac0ad73b472d8b44714df3bd18a4edf upstream.
+
+Older steppings of the Loongson-3C6000 series incorrectly report the
+supported link speeds on their PCIe bridges (device IDs 0x3c19, 0x3c29)
+as only 2.5 GT/s, despite the upstream bus supporting speeds from
+2.5 GT/s up to 16 GT/s.
+
+As a result, since commit 774c71c52aa4 ("PCI/bwctrl: Enable only if more
+than one speed is supported"), bwctrl will be disabled if there's only
+one 2.5 GT/s value in vector 'supported_speeds'.
+
+Manually override the 'supported_speeds' field for affected PCIe bridges
+with those found on the upstream bus to correctly reflect the supported
+link speeds. Updating the speeds to reflect what the hardware actually
+supports avoids quirks in drivers consuming the speed information.
+
+This commit was originally found from AOSC OS[1].
+
+Fixes: cd89edda4002 ("PCI: loongson: Add ACPI init support")
+Signed-off-by: Ayden Meng <aydenmeng@yeah.net>
+Signed-off-by: Mingcong Bai <jeffbai@aosc.io>
+[Ziyao Li: move from drivers/pci/quirks.c to drivers/pci/controller/pci-loongson.c]
+Signed-off-by: Ziyao Li <liziyao@uniontech.com>
+[Xi Ruoyao: Fixed falling through logic, added debug log, Fixes tag and rebased to 7.0-rc7]
+Signed-off-by: Xi Ruoyao <xry111@xry111.site>
+Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
+[bhelgaas: commit log, https://lore.kernel.org/all/9d815df3b33a63223112b97440c01247935363c1.camel@xry111.site]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Tested-by: Lain Fearyncess Yang <fsf@live.com>
+Tested-by: Ayden Meng <aydenmeng@yeah.net>
+Tested-by: Mingcong Bai <jeffbai@aosc.io>
+Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
+Cc: stable@vger.kernel.org
+Link: https://github.com/AOSC-Tracking/linux/commit/4392f441363abdf6fa0a0433d73175a17f493454
+Link: https://github.com/AOSC-Tracking/linux/pull/2 #1
+Link: https://patch.msgid.link/20260412101731.107059-1-xry111@xry111.site
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/pci-loongson.c | 36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/drivers/pci/controller/pci-loongson.c
++++ b/drivers/pci/controller/pci-loongson.c
+@@ -176,6 +176,42 @@ static void loongson_pci_msi_quirk(struc
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk);
+
++/*
++ * Older steppings of the Loongson-3C6000 series incorrectly report the
++ * supported link speeds on their PCIe bridges (device IDs 0x3c19,
++ * 0x3c29) as only 2.5 GT/s, despite the upstream bus supporting speeds
++ * from 2.5 GT/s up to 16 GT/s.
++ */
++static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)
++{
++ u8 old_supported_speeds = pdev->supported_speeds;
++
++ switch (pdev->bus->max_bus_speed) {
++ case PCIE_SPEED_16_0GT:
++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;
++ fallthrough;
++ case PCIE_SPEED_8_0GT:
++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;
++ fallthrough;
++ case PCIE_SPEED_5_0GT:
++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
++ fallthrough;
++ case PCIE_SPEED_2_5GT:
++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;
++ break;
++ default:
++ pci_warn(pdev, "unexpected max bus speed");
++
++ return;
++ }
++
++ if (pdev->supported_speeds != old_supported_speeds)
++ pci_info(pdev, "fixed up supported link speeds: 0x%x => 0x%x",
++ old_supported_speeds, pdev->supported_speeds);
++}
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);
++
+ static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
+ {
+ struct pci_config_window *cfg;
usb-xhci-fix-sleep-in-atomic-context-in-xhci_free_streams.patch
xhci-sideband-fix-ring-sg-table-pages-leak.patch
usb-typec-tcpci_rt1711h-unregister-tcpci-port-with-devres.patch
+pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch
+pci-altera-do-not-dispose-parent-irq-mapping.patch
+pci-altera-fix-resource-leaks-on-probe-failure.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
