Transactional and non-transactional stores to the same cache line cause
transactions to abort on newer generations. Add sufficient padding to make
sure another cache line is used.
Tested on s390.
gcc/testsuite/ChangeLog:
* gcc.target/s390/htm-builtins-1.c: Fix.
* gcc.target/s390/htm-builtins-2.c: Fix.
Signed-off-by: Juergen Christ <jchrist@linux.ibm.com>
__attribute__ ((aligned(256))) struct
{
volatile uint64_t c1;
+ char pad1[256 - sizeof(uint64_t)];
volatile uint64_t c2;
+ char pad2[256 - sizeof(uint64_t)];
volatile uint64_t c3;
-} counters = { 0, 0, 0 };
+} counters = { 0 };
/* ---------------------------- local helper functions --------------------- */
__attribute__ ((aligned(256))) struct
{
volatile uint64_t c1;
+ char pad1[256 - sizeof(uint64_t)];
volatile uint64_t c2;
+ char pad2[256 - sizeof(uint64_t)];
volatile uint64_t c3;
-} counters = { 0, 0, 0 };
+} counters = { 0 };
/* ---------------------------- local helper functions --------------------- */