clk: renesas: r9a09g056: Add clock and reset entries for ISP

Add entries detailing the clocks and resets for the ISP in the
RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 9c536f7706ff23e2b7b5569da3a988e82c04b19c..e4a6dfd2bec93d32ac3995fb653ec0f1d53dfedd 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -53,6 +53,7 @@ enum clk_ids {
        CLK_PLLDTY_DIV16,
        CLK_PLLVDO_CRU0,
        CLK_PLLVDO_CRU1,
+       CLK_PLLVDO_ISP,
        CLK_PLLETH_DIV_250_FIX,
        CLK_PLLETH_DIV_125_FIX,
        CLK_CSDIV_PLLETH_GBE0,
@@ -186,6 +187,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
 
        DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
        DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
+       DEF_DDIV(".pllvdo_isp",  CLK_PLLVDO_ISP,  CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
 
        DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
        DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -359,6 +361,14 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(5))),
        DEF_MOD("cru_1_pclk",                   CLK_PLLDTY_DIV16, 13, 7, 6, 23,
                                                BUS_MSTOP(9, BIT(5))),
+       DEF_MOD("isp_0_reg_aclk",               CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
+                                               BUS_MSTOP(9, BIT(8))),
+       DEF_MOD("isp_0_pclk",                   CLK_PLLDTY_DIV16, 14, 3, 7, 3,
+                                               BUS_MSTOP(9, BIT(8))),
+       DEF_MOD("isp_0_vin_aclk",               CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
+                                               BUS_MSTOP(9, BIT(9))),
+       DEF_MOD("isp_0_isp_sclk",               CLK_PLLVDO_ISP, 14, 5, 7, 5,
+                                               BUS_MSTOP(9, BIT(9))),
        DEF_MOD("dsi_0_pclk",                   CLK_PLLDTY_DIV16, 14, 8, 7, 8,
                                                BUS_MSTOP(9, BIT(14) | BIT(15))),
        DEF_MOD("dsi_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
@@ -427,6 +437,10 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(12, 8, 5, 25),          /* CRU_1_PRESETN */
        DEF_RST(12, 9, 5, 26),          /* CRU_1_ARESETN */
        DEF_RST(12, 10, 5, 27),         /* CRU_1_S_RESETN */
+       DEF_RST(13, 1, 6, 2),           /* ISP_0_VIN_ARESETN */
+       DEF_RST(13, 2, 6, 3),           /* ISP_0_REG_ARESETN */
+       DEF_RST(13, 3, 6, 4),           /* ISP_0_ISP_SRESETN */
+       DEF_RST(13, 4, 6, 5),           /* ISP_0_PRESETN */
        DEF_RST(13, 7, 6, 8),           /* DSI_0_PRESETN */
        DEF_RST(13, 8, 6, 9),           /* DSI_0_ARESETN */
        DEF_RST(13, 12, 6, 13),         /* LCDC_0_RESET_N */