[APX EGPR] Add backend hook for base_reg_class/index_reg_class.

Add backend helper functions to verify if a rtx_insn can adopt EGPR to
its base/index reg of memory operand. The verification rule goes like
  1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32.
  2. Disable EGPR for unrecognized insn.
  3. If which_alternative is not decided, loop through enabled alternatives
  and check its attr_gpr32. Only enable EGPR when all enabled
  alternatives has attr_gpr32 = 1.
  4. If which_alternative is decided, enable/disable EGPR by its corresponding
  attr_gpr32.

gcc/ChangeLog:

	* config/i386/i386-protos.h (ix86_insn_base_reg_class): New
	prototype.
	(ix86_regno_ok_for_insn_base_p): Likewise.
	(ix86_insn_index_reg_class): Likewise.
	* config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
	New helper function to scan the insn.
	(ix86_insn_base_reg_class): New function to choose BASE_REG_CLASS.
	(ix86_regno_ok_for_insn_base_p): Likewise for base regno.
	(ix86_insn_index_reg_class): Likewise for INDEX_REG_CLASS.
	* config/i386/i386.h (INSN_BASE_REG_CLASS): Define.
	(REGNO_OK_FOR_INSN_BASE_P): Likewise.
	(INSN_INDEX_REG_CLASS): Likewise.
	(enum reg_class): Add INDEX_GPR16.
	(GENERAL_GPR16_REGNO_P): Define.
	* config/i386/i386.md (gpr32): New attribute.

Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>

diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index bd4782800c441475ff1d2d22cd12129c8ab645b5..a54e3f6b1dc9dc9340e5e0a4442df216b50f2171 100644 (file)
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -79,6 +79,9 @@ extern bool ix86_expand_set_or_cpymem (rtx, rtx, rtx, rtx, rtx, rtx,
                                       rtx, rtx, rtx, rtx, bool);
 extern bool ix86_expand_cmpstrn_or_cmpmem (rtx, rtx, rtx, rtx, rtx, bool);
 
+extern enum reg_class ix86_insn_base_reg_class (rtx_insn *);
+extern bool ix86_regno_ok_for_insn_base_p (int, rtx_insn *);
+extern enum reg_class ix86_insn_index_reg_class (rtx_insn *);
 extern bool constant_address_p (rtx);
 extern bool legitimate_pic_operand_p (rtx);
 extern bool legitimate_pic_address_disp_p (rtx);

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index c66c011b757caa2214963a891b964cfee98fd809..ada9ac8f1f610311eb86408f8579312e971b7ec9 100644 (file)
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -11062,6 +11062,95 @@ ix86_validate_address_register (rtx op)
   return NULL_RTX;
 }
 
+/* Return true if insn memory address can use any available reg
+   in BASE_REG_CLASS or INDEX_REG_CLASS, otherwise false.
+   For APX, some instruction can't be encoded with gpr32
+   which is BASE_REG_CLASS or INDEX_REG_CLASS, for that case
+   returns false.  */
+static bool
+ix86_memory_address_use_extended_reg_class_p (rtx_insn* insn)
+{
+  /* LRA will do some initialization with insn == NULL,
+     return the maximum reg class for that.
+     For other cases, real insn will be passed and checked.  */
+  bool ret = true;
+  if (TARGET_APX_EGPR && insn)
+    {
+      if (asm_noperands (PATTERN (insn)) >= 0
+         || GET_CODE (PATTERN (insn)) == ASM_INPUT)
+       return ix86_apx_inline_asm_use_gpr32;
+
+      if (INSN_CODE (insn) < 0)
+       return false;
+
+      /* Try recog the insn before calling get_attr_gpr32. Save
+        the current recog_data first.  */
+      /* Also save which_alternative for current recog.  */
+
+      struct recog_data_d recog_data_save = recog_data;
+      int which_alternative_saved = which_alternative;
+
+      /* Update the recog_data for alternative check. */
+      if (recog_data.insn != insn)
+       extract_insn_cached (insn);
+
+      /* If alternative is not set, loop throught each alternative
+        of insn and get gpr32 attr for all enabled alternatives.
+        If any enabled alternatives has 0 value for gpr32, disallow
+        gpr32 for addressing.  */
+      if (which_alternative_saved == -1)
+       {
+         alternative_mask enabled = get_enabled_alternatives (insn);
+         bool curr_insn_gpr32 = false;
+         for (int i = 0; i < recog_data.n_alternatives; i++)
+           {
+             if (!TEST_BIT (enabled, i))
+               continue;
+             which_alternative = i;
+             curr_insn_gpr32 = get_attr_gpr32 (insn);
+             if (!curr_insn_gpr32)
+               ret = false;
+           }
+       }
+      else
+       {
+         which_alternative = which_alternative_saved;
+         ret = get_attr_gpr32 (insn);
+       }
+
+      recog_data = recog_data_save;
+      which_alternative = which_alternative_saved;
+    }
+
+  return ret;
+}
+
+/* For APX, some instructions can't be encoded with gpr32.  */
+enum reg_class
+ix86_insn_base_reg_class (rtx_insn* insn)
+{
+  if (ix86_memory_address_use_extended_reg_class_p (insn))
+    return BASE_REG_CLASS;
+  return GENERAL_GPR16;
+}
+
+bool
+ix86_regno_ok_for_insn_base_p (int regno, rtx_insn* insn)
+{
+
+  if (ix86_memory_address_use_extended_reg_class_p (insn))
+    return GENERAL_REGNO_P (regno);
+  return GENERAL_GPR16_REGNO_P (regno);
+}
+
+enum reg_class
+ix86_insn_index_reg_class (rtx_insn* insn)
+{
+  if (ix86_memory_address_use_extended_reg_class_p (insn))
+    return INDEX_REG_CLASS;
+  return INDEX_GPR16;
+}
+
 /* Recognizes RTL expressions that are valid memory addresses for an
    instruction.  The MODE argument is the machine mode for the MEM
    expression that wants to use this address.

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 66b8764e82b0ae921f4d4e64fa9b1c75848e66ac..7fa7585e058d9dec3172c97273b50160abed6d37 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1018,6 +1018,14 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 
 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
 
+#define INSN_BASE_REG_CLASS(INSN) \
+  ix86_insn_base_reg_class (INSN)
+
+#define REGNO_OK_FOR_INSN_BASE_P(NUM, INSN) \
+  ix86_regno_ok_for_insn_base_p (NUM, INSN)
+
+#define INSN_INDEX_REG_CLASS(INSN) \
+  ix86_insn_index_reg_class (INSN)
 
 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
 
@@ -1297,6 +1305,8 @@ enum reg_class
                                   %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
   GENERAL_GPR16,               /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
                                   %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
+  INDEX_GPR16,                 /* %eax %ebx %ecx %edx %esi %edi %ebp
+                                  %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
   FP_TOP_REG, FP_SECOND_REG,   /* %st(0) %st(1) */
   FLOAT_REGS,
   SSE_FIRST_REG,
@@ -1360,6 +1370,7 @@ enum reg_class
    "LEGACY_REGS",                      \
    "GENERAL_REGS",                     \
    "GENERAL_GPR16",                    \
+   "INDEX_GPR16",                      \
    "FP_TOP_REG", "FP_SECOND_REG",      \
    "FLOAT_REGS",                       \
    "SSE_FIRST_REG",                    \
@@ -1395,10 +1406,11 @@ enum reg_class
       { 0x0f,        0x0,   0x0 },     /* Q_REGS */                    \
    { 0x900f0,        0x0,   0x0 },     /* NON_Q_REGS */                \
       { 0x7e,      0xff0,   0x0 },     /* TLS_GOTBASE_REGS */          \
-      { 0x7f,      0xff0,   0x0 },     /* INDEX_REGS */                \
+      { 0x7f,      0xff0,   0xffff000 },       /* INDEX_REGS */                \
    { 0x900ff,        0x0,   0x0 },     /* LEGACY_REGS */               \
    { 0x900ff,      0xff0,   0xffff000 },       /* GENERAL_REGS */              \
    { 0x900ff,      0xff0,   0x0 },     /* GENERAL_GPR16 */             \
+   { 0x0007f,      0xff0,   0x0 },     /* INDEX_GPR16 */               \
      { 0x100,        0x0,   0x0 },     /* FP_TOP_REG */                \
      { 0x200,        0x0,   0x0 },     /* FP_SECOND_REG */             \
     { 0xff00,        0x0,   0x0 },     /* FLOAT_REGS */                \
@@ -1456,6 +1468,9 @@ enum reg_class
 #define INDEX_REGNO_P(N) \
   (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
 
+#define GENERAL_GPR16_REGNO_P(N) \
+  (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
+
 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
 #define ANY_QI_REGNO_P(N) \
   (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index bf296632acd94804069eeccd691f776db4ca5477..144fccdf9628b5389df24273116b2bf153d0dbda 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -873,6 +873,9 @@
 ;; Define attribute to indicate unaligned ssemov insns
 (define_attr "movu" "0,1" (const_string "0"))
 
+;; Define attribute to indicate gpr32 insns.
+(define_attr "gpr32" "0, 1" (const_string "1"))
+
 ;; Define instruction set of MMX instructions
 (define_attr "mmx_isa" "base,native,sse,sse_noavx,avx"
   (const_string "base"))