+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2013-01-15 Alan Modra <amodra@gmail.com>
+ * elf64-ppc.c (ppc64_elf_size_stubs): Default shared libs to
+ plt-thread-safe.
+
+ 2013-01-14 Alan Modra <amodra@gmail.com>
+ PR binutils/14813
+ * bfdio.c (struct bfd_iovec <bclose>): Revert 2012-11-06.
+ (memory_bclose): Likewise. Return 0 on success.
+ * cache.c (cache_bclose): Likewise.
+ * opncls.c (opncls_bclose, bfd_close): Likewise.
+ * vms-lib.c (vms_lib_bclose): Likewise.
+ * libbfd.h: Regenerate.
+
+ 2013-01-13 Alan Modra <amodra@gmail.com>
+ * elf-bfd.h (struct elf_link_hash_entry): Delete dynamic_weak.
+ Add ref_dynamic_nonweak.
+ * elflink.c (_bfd_elf_mark_dynamic_def_weak): Delete.
+ (_bfd_elf_merge_symbol): Don't call above function. Move
+ setting of ref_dynamic_nonweak and dynamic_def earlier. Don't
+ clear dynamic_def.
+ (elf_link_add_object_symbols): Delete redundant "override" test.
+ Don't set dynamic_def here.
+ (elf_link_output_extsym): Update.
+
+ 2013-01-12 Alan Modra <amodra@gmail.com>
+ * elf-bfd.h (_bfd_elf_strtab_refcount): Declare.
+ * elf-strtab.c (_bfd_elf_strtab_refcount): New function.
+ * elflink.c (elf_add_dt_needed_tag): Use _bfd_elf_strtab_refcount.
+
+ 2013-01-12 Alan Modra <amodra@gmail.com>
+ PR ld/12549
+ * elf-bfd.h (_bfd_elf_strtab_clear_refs): Declare.
+ (_bfd_elf_strtab_clear_all_refs): Define.
+ * elf-strtab.c (_bfd_elf_strtab_clear_refs): New function.
+ (_bfd_elf_strtab_clear_all_refs): Delete.
+ * elflink.c (elf_link_add_object_symbols): Clear out added
+ strtab refs. Correct handling of warning common symbols.
+
+ 2012-12-19 H.J. Lu <hongjiu.lu@intel.com>
+ * elf32-i386.c (elf_i386_relocate_section): Replace
+ bfd_elf32_swap_reloc_out with elf_append_rel.
+ (elf_i386_finish_dynamic_symbol): Likewise.
+ * elflink.c (elf_append_rel): Call swap_reloc_out instead of
+ swap_reloca_out.
+
+ 2012-12-18 Alan Modra <amodra@gmail.com>
+ * elf.c (swap_out_syms): Set shndx to SHN_ABS when not one of
+ the special MAP_* values.
+
+ 2012-12-07 Alan Modra <amodra@gmail.com>
+ PR ld/14926
+ * elf.c (_bfd_elf_map_sections_to_segments): Include elf header
+ size when determining phdr_in_segment.
+
+ 2012-12-05 Alan Modra <amodra@gmail.com>
+ * elf64-ppc.c (build_plt_stub): Fix off by one error in branch
+ to glink.
+
+ 2012-11-21 H.J. Lu <hongjiu.lu@intel.com>
+ PR binutils/14493
+ * elf.c (copy_elf_program_header): When rewriting program
+ header, set the output maxpagesize to the maximum alignment
+ of input PT_LOAD segments.
+
+ 2012-11-13 Joe Seymour <jseymour@codesourcery.com>
+ * elf.c (rewrite_elf_program_header): Allocate elf_segment_map
+ with bfd_zalloc, instead of bfd_alloc.
+
+ 2012-11-06 H.J. Lu <hongjiu.lu@intel.com>
+ PR binutils/14813
+ * bfdio.c (bfd_iovec): Change return type of bclose to
+ bfd_boolean.
+ (memory_bclose): Change return type to bfd_boolean.
+ * cache.c (cache_bclose): Likewise.
+ * opncls.c (opncls_bclose): Likewise. Return TRUE on success.
+ * vms-lib.c (vms_lib_bclose): Likewise. Return TRUE.
+ * libbfd.h: Regenerated.
+
+ 2012-11-06 Alan Modra <amodra@gmail.com>
+ PR binutils/14567
+ * opncls.c (opncls_iovec): Forward declare.
+ (_bfd_new_bfd_contained_in): If using opncls_iovec, copy iostream
+ to new bfd.
+
+ 2012-11-06 Alan Modra <amodra@gmail.com>
+ * elf64-ppc.c (maybe_strip_output): Heed SEC_KEEP.
+
+ 2012-11-05 Alan Modra <amodra@gmail.com>
+ * elf64-ppc.c (ppc64_elf_edit_toc): Clear "repeat" inside
+ loop. Really mark toc entry referring to another toc entry
+ only if the first is used.
+
+ 2012-10-29 Alan Modra <amodra@gmail.com>
+ * elf32-ppc.c (ppc_elf_howto_raw): Correct dst_mask in
+ R_PPC_VLE_LO16A, R_PPC_VLE_HI16A, R_PPC_VLE_HA16A,
+ R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_HI16A,
+ R_PPC_VLE_SDAREL_HA16A reloc howtos.
+
+ 2012-10-26 Alan Modra <amodra@gmail.com>
+ PR gas/14758
+ * elf32-ppc.c (ppc_elf_reloc_type_lookup): Decode ppc64 _DS
+ bfd_reloc values. Map to corresponding D-form relocs.
+ (is_insn_ds_form, is_insn_qs_form): New functions.
+ (ppc_elf_relocate_section): Validate insn with DS-form or DQ-form
+ fields using D-form reloc.
+
+ 2012-10-21 Hans-Peter Nilsson <hp@bitrange.com>
+ * linker.c (_bfd_generic_link_output_symbols): Handle a
+ no-longer-global symbol entered as a BFD_PLUGIN.
+
+ 2012-10-08 Alan Modra <amodra@gmail.com>
+ PR binutils/14662
+ * elf.c (_bfd_elf_make_section_from_shdr): Treat .gdb_index as
+ SEC_DEBUGGING.
+
+ 2012-09-04 H.J. Lu <hongjiu.lu@intel.com>
+ PR binutils/14493
+ * elf.c (ignore_section_sym): Also ignore section symbols without
+ a BFD section.
+
2012-12-21 H.J. Lu <hongjiu.lu@intel.com>
* elf64-x86-64.c (elf_x86_64_relocate_section): Check
free (bim);
abfd->iostream = NULL;
- return TRUE;
+ return 0;
}
static int
static int
cache_bclose (struct bfd *abfd)
{
- return bfd_cache_close (abfd);
+ return bfd_cache_close (abfd) - 1;
}
static int
FIXME: There is no real need for this field if def_dynamic is never
cleared and all places that test def_dynamic also test def_regular. */
unsigned int dynamic_def : 1;
- /* Symbol is weak in all shared objects. */
- unsigned int dynamic_weak : 1;
+ /* Symbol has a non-weak reference from a shared object. */
+ unsigned int ref_dynamic_nonweak : 1;
/* Symbol is referenced with a relocation where C/C++ pointer equality
matters. */
unsigned int pointer_equality_needed : 1;
(struct elf_strtab_hash *, bfd_size_type);
extern void _bfd_elf_strtab_delref
(struct elf_strtab_hash *, bfd_size_type);
-extern void _bfd_elf_strtab_clear_all_refs
- (struct elf_strtab_hash *);
+extern unsigned int _bfd_elf_strtab_refcount
+ (struct elf_strtab_hash *, bfd_size_type);
+extern void _bfd_elf_strtab_clear_refs
+ (struct elf_strtab_hash *, bfd_size_type);
+#define _bfd_elf_strtab_clear_all_refs(tab) \
+ do { _bfd_elf_strtab_clear_refs (tab, 1); } while (0)
extern bfd_size_type _bfd_elf_strtab_size
(struct elf_strtab_hash *);
extern bfd_size_type _bfd_elf_strtab_offset
--tab->array[idx]->refcount;
}
-void
-_bfd_elf_strtab_clear_all_refs (struct elf_strtab_hash *tab)
+unsigned int
+_bfd_elf_strtab_refcount (struct elf_strtab_hash *tab, bfd_size_type idx)
{
- bfd_size_type idx;
+ return tab->array[idx]->refcount;
+}
- for (idx = 1; idx < tab->size; ++idx)
- tab->array[idx]->refcount = 0;
+void
+_bfd_elf_strtab_clear_refs (struct elf_strtab_hash *tab, bfd_size_type idx)
+{
+ while (idx < tab->size)
+ tab->array[idx++]->refcount = 0;
}
bfd_size_type
{
/* The debugging sections appear to be recognized only by name,
not any sort of flag. Their SEC_ALLOC bits are cleared. */
- static const struct
- {
- const char *name;
- int len;
- } debug_sections [] =
- {
- { STRING_COMMA_LEN ("debug") }, /* 'd' */
- { NULL, 0 }, /* 'e' */
- { NULL, 0 }, /* 'f' */
- { STRING_COMMA_LEN ("gnu.linkonce.wi.") }, /* 'g' */
- { NULL, 0 }, /* 'h' */
- { NULL, 0 }, /* 'i' */
- { NULL, 0 }, /* 'j' */
- { NULL, 0 }, /* 'k' */
- { STRING_COMMA_LEN ("line") }, /* 'l' */
- { NULL, 0 }, /* 'm' */
- { NULL, 0 }, /* 'n' */
- { NULL, 0 }, /* 'o' */
- { NULL, 0 }, /* 'p' */
- { NULL, 0 }, /* 'q' */
- { NULL, 0 }, /* 'r' */
- { STRING_COMMA_LEN ("stab") }, /* 's' */
- { NULL, 0 }, /* 't' */
- { NULL, 0 }, /* 'u' */
- { NULL, 0 }, /* 'v' */
- { NULL, 0 }, /* 'w' */
- { NULL, 0 }, /* 'x' */
- { NULL, 0 }, /* 'y' */
- { STRING_COMMA_LEN ("zdebug") } /* 'z' */
- };
-
if (name [0] == '.')
{
- int i = name [1] - 'd';
- if (i >= 0
- && i < (int) ARRAY_SIZE (debug_sections)
- && debug_sections [i].name != NULL
- && strncmp (&name [1], debug_sections [i].name,
- debug_sections [i].len) == 0)
+ const char *p;
+ int n;
+ if (name[1] == 'd')
+ p = ".debug", n = 6;
+ else if (name[1] == 'g' && name[2] == 'n')
+ p = ".gnu.linkonce.wi.", n = 17;
+ else if (name[1] == 'g' && name[2] == 'd')
+ p = ".gdb_index", n = 11; /* yes we really do mean 11. */
+ else if (name[1] == 'l')
+ p = ".line", n = 5;
+ else if (name[1] == 's')
+ p = ".stab", n = 5;
+ else if (name[1] == 'z')
+ p = ".zdebug", n = 7;
+ else
+ p = NULL, n = 0;
+ if (p != NULL && strncmp (name, p, n) == 0)
flags |= SEC_DEBUGGING;
}
}
}
/* Don't output section symbols for sections that are not going to be
- output, or that are duplicates. */
+ output, that are duplicates or there is no BFD section. */
static bfd_boolean
ignore_section_sym (bfd *abfd, asymbol *sym)
{
- return ((sym->flags & BSF_SECTION_SYM) != 0
- && !(sym->section->owner == abfd
+ elf_symbol_type *type_ptr;
+
+ if ((sym->flags & BSF_SECTION_SYM) == 0)
+ return FALSE;
+
+ type_ptr = elf_symbol_from (abfd, sym);
+ return ((type_ptr != NULL
+ && type_ptr->internal_elf_sym.st_shndx != 0
+ && bfd_is_abs_section (sym->section))
+ || !(sym->section->owner == abfd
|| (sym->section->output_section->owner == abfd
&& sym->section->output_offset == 0)
|| bfd_is_abs_section (sym->section)));
if (phdr_size == (bfd_size_type) -1)
phdr_size = get_program_header_size (abfd, info);
+ phdr_size += bed->s->sizeof_ehdr;
if ((abfd->flags & D_PAGED) == 0
|| (sections[0]->lma & addr_mask) < phdr_size
|| ((sections[0]->lma & addr_mask) % maxpagesize
and carry on looping. */
amt = sizeof (struct elf_segment_map);
amt += ((bfd_size_type) section_count - 1) * sizeof (asection *);
- map = (struct elf_segment_map *) bfd_alloc (obfd, amt);
+ map = (struct elf_segment_map *) bfd_zalloc (obfd, amt);
if (map == NULL)
{
free (sections);
}
rewrite:
+ if (ibfd->xvec == obfd->xvec)
+ {
+ /* When rewriting program header, set the output maxpagesize to
+ the maximum alignment of input PT_LOAD segments. */
+ Elf_Internal_Phdr *segment;
+ unsigned int i;
+ unsigned int num_segments = elf_elfheader (ibfd)->e_phnum;
+ bfd_vma maxpagesize = 0;
+
+ for (i = 0, segment = elf_tdata (ibfd)->phdr;
+ i < num_segments;
+ i++, segment++)
+ if (segment->p_type == PT_LOAD
+ && maxpagesize < segment->p_align)
+ maxpagesize = segment->p_align;
+
+ if (maxpagesize != get_elf_backend_data (obfd)->maxpagesize)
+ bfd_emul_set_maxpagesize (bfd_get_target (obfd), maxpagesize);
+ }
+
return rewrite_elf_program_header (ibfd, obfd);
}
shndx = elf_tdata (abfd)->symtab_shndx_section;
break;
default:
+ shndx = SHN_ABS;
break;
}
}
if (info->shared && h->non_got_ref)
{
Elf_Internal_Rela outrel;
- bfd_byte *loc;
asection *sreloc;
bfd_vma offset;
outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
sreloc = htab->elf.irelifunc;
- loc = sreloc->contents;
- loc += (sreloc->reloc_count++
- * sizeof (Elf32_External_Rel));
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
/* If this reloc is against an external symbol, we
do not want to fiddle with the addend. Otherwise,
{
asection *s;
Elf_Internal_Rela outrel;
- bfd_byte *loc;
s = htab->elf.srelgot;
if (s == NULL)
+ htab->elf.sgot->output_offset
+ off);
outrel.r_info = ELF32_R_INFO (0, R_386_RELATIVE);
- loc = s->contents;
- loc += s->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, s, &outrel);
}
local_got_offsets[r_symndx] |= 1;
|| h->root.type == bfd_link_hash_undefined)))
{
Elf_Internal_Rela outrel;
- bfd_byte *loc;
bfd_boolean skip, relocate;
asection *sreloc;
goto check_relocation_error;
}
- loc = sreloc->contents;
- loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rel);
-
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
/* If this reloc is against an external symbol, we do
not want to fiddle with the addend. Otherwise, we
if (!info->executable)
{
Elf_Internal_Rela outrel;
- bfd_byte *loc;
asection *sreloc;
outrel.r_offset = rel->r_offset
sreloc = elf_section_data (input_section)->sreloc;
if (sreloc == NULL)
abort ();
- loc = sreloc->contents;
- loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
}
/* Fall through */
else
{
Elf_Internal_Rela outrel;
- bfd_byte *loc;
int dr_type;
asection *sreloc;
if (GOT_TLS_GDESC_P (tls_type))
{
+ bfd_byte *loc;
outrel.r_info = ELF32_R_INFO (indx, R_386_TLS_DESC);
BFD_ASSERT (htab->sgotplt_jump_table_size + offplt + 8
<= htab->elf.sgotplt->size);
loc += (htab->next_tls_desc_index++
* sizeof (Elf32_External_Rel));
BFD_ASSERT (loc + sizeof (Elf32_External_Rel)
- <= sreloc->contents + sreloc->size);
+ <= sreloc->contents + sreloc->size);
bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
if (indx == 0)
{
htab->elf.sgot->contents + off);
outrel.r_info = ELF32_R_INFO (indx, dr_type);
- loc = sreloc->contents;
- loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rel);
- BFD_ASSERT (loc + sizeof (Elf32_External_Rel)
- <= sreloc->contents + sreloc->size);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
if (GOT_TLS_GD_P (tls_type))
{
outrel.r_info = ELF32_R_INFO (indx,
R_386_TLS_DTPOFF32);
outrel.r_offset += 4;
- sreloc->reloc_count++;
- loc += sizeof (Elf32_External_Rel);
- BFD_ASSERT (loc + sizeof (Elf32_External_Rel)
- <= sreloc->contents + sreloc->size);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
}
}
else if (tls_type == GOT_TLS_IE_BOTH)
htab->elf.sgot->contents + off + 4);
outrel.r_info = ELF32_R_INFO (indx, R_386_TLS_TPOFF);
outrel.r_offset += 4;
- sreloc->reloc_count++;
- loc += sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
}
dr_done:
else
{
Elf_Internal_Rela outrel;
- bfd_byte *loc;
if (htab->elf.srelgot == NULL)
abort ();
bfd_put_32 (output_bfd, 0,
htab->elf.sgot->contents + off + 4);
outrel.r_info = ELF32_R_INFO (0, R_386_TLS_DTPMOD32);
- loc = htab->elf.srelgot->contents;
- loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, htab->elf.srelgot, &outrel);
htab->tls_ldm_got.offset |= 1;
}
relocation = htab->elf.sgot->output_section->vma
{
Elf_Internal_Rela outrel;
asection *sreloc;
- bfd_byte *loc;
outrel.r_offset = rel->r_offset
+ input_section->output_section->vma
sreloc = elf_section_data (input_section)->sreloc;
if (sreloc == NULL)
abort ();
- loc = sreloc->contents;
- loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+ elf_append_rel (output_bfd, sreloc, &outrel);
if (indx)
continue;
else if (r_type == R_386_TLS_LE_32)
&& (elf_i386_hash_entry(h)->tls_type & GOT_TLS_IE) == 0)
{
Elf_Internal_Rela rel;
- bfd_byte *loc;
/* This symbol has an entry in the global offset table. Set it
up. */
rel.r_info = ELF32_R_INFO (h->dynindx, R_386_GLOB_DAT);
}
- loc = htab->elf.srelgot->contents;
- loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+ elf_append_rel (output_bfd, htab->elf.srelgot, &rel);
}
if (h->needs_copy)
{
Elf_Internal_Rela rel;
- bfd_byte *loc;
/* This symbol needs a copy reloc. Set it up. */
+ h->root.u.def.section->output_section->vma
+ h->root.u.def.section->output_offset);
rel.r_info = ELF32_R_INFO (h->dynindx, R_386_COPY);
- loc = htab->srelbss->contents;
- loc += htab->srelbss->reloc_count++ * sizeof (Elf32_External_Rel);
- bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+ elf_append_rel (output_bfd, htab->srelbss, &rel);
}
return TRUE;
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
- FALSE, /* pc_relative */ /* FIXME: Does this apply to split relocs? */
+ FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_LO16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The 16 LSBS in split16d format. */
"R_PPC_VLE_HI16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 split16d format. */
"R_PPC_VLE_HA16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (High Adjusted) in split16d format. */
"R_PPC_VLE_SDAREL_LO16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The 16 LSBS relative to _SDA_BASE_ in split16d format. */
"R_PPC_VLE_SDAREL_HI16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 relative to _SDA_BASE_ in split16d format. */
"R_PPC_VLE_SDAREL_HA16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
- 0x1f00fff, /* dst_mask */
+ 0x1f007ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (HA) relative to _SDA_BASE split16d format. */
case BFD_RELOC_NONE: r = R_PPC_NONE; break;
case BFD_RELOC_32: r = R_PPC_ADDR32; break;
case BFD_RELOC_PPC_BA26: r = R_PPC_ADDR24; break;
+ case BFD_RELOC_PPC64_ADDR16_DS:
case BFD_RELOC_16: r = R_PPC_ADDR16; break;
+ case BFD_RELOC_PPC64_ADDR16_LO_DS:
case BFD_RELOC_LO16: r = R_PPC_ADDR16_LO; break;
case BFD_RELOC_HI16: r = R_PPC_ADDR16_HI; break;
case BFD_RELOC_HI16_S: r = R_PPC_ADDR16_HA; break;
case BFD_RELOC_PPC_B16: r = R_PPC_REL14; break;
case BFD_RELOC_PPC_B16_BRTAKEN: r = R_PPC_REL14_BRTAKEN; break;
case BFD_RELOC_PPC_B16_BRNTAKEN: r = R_PPC_REL14_BRNTAKEN; break;
+ case BFD_RELOC_PPC64_GOT16_DS:
case BFD_RELOC_16_GOTOFF: r = R_PPC_GOT16; break;
+ case BFD_RELOC_PPC64_GOT16_LO_DS:
case BFD_RELOC_LO16_GOTOFF: r = R_PPC_GOT16_LO; break;
case BFD_RELOC_HI16_GOTOFF: r = R_PPC_GOT16_HI; break;
case BFD_RELOC_HI16_S_GOTOFF: r = R_PPC_GOT16_HA; break;
case BFD_RELOC_32_PCREL: r = R_PPC_REL32; break;
case BFD_RELOC_32_PLTOFF: r = R_PPC_PLT32; break;
case BFD_RELOC_32_PLT_PCREL: r = R_PPC_PLTREL32; break;
+ case BFD_RELOC_PPC64_PLT16_LO_DS:
case BFD_RELOC_LO16_PLTOFF: r = R_PPC_PLT16_LO; break;
case BFD_RELOC_HI16_PLTOFF: r = R_PPC_PLT16_HI; break;
case BFD_RELOC_HI16_S_PLTOFF: r = R_PPC_PLT16_HA; break;
case BFD_RELOC_GPREL16: r = R_PPC_SDAREL16; break;
+ case BFD_RELOC_PPC64_SECTOFF_DS:
case BFD_RELOC_16_BASEREL: r = R_PPC_SECTOFF; break;
+ case BFD_RELOC_PPC64_SECTOFF_LO_DS:
case BFD_RELOC_LO16_BASEREL: r = R_PPC_SECTOFF_LO; break;
case BFD_RELOC_HI16_BASEREL: r = R_PPC_SECTOFF_HI; break;
case BFD_RELOC_HI16_S_BASEREL: r = R_PPC_SECTOFF_HA; break;
case BFD_RELOC_CTOR: r = R_PPC_ADDR32; break;
+ case BFD_RELOC_PPC64_TOC16_DS:
case BFD_RELOC_PPC_TOC16: r = R_PPC_TOC16; break;
case BFD_RELOC_PPC_TLS: r = R_PPC_TLS; break;
case BFD_RELOC_PPC_TLSGD: r = R_PPC_TLSGD; break;
case BFD_RELOC_PPC_TLSLD: r = R_PPC_TLSLD; break;
case BFD_RELOC_PPC_DTPMOD: r = R_PPC_DTPMOD32; break;
+ case BFD_RELOC_PPC64_TPREL16_DS:
case BFD_RELOC_PPC_TPREL16: r = R_PPC_TPREL16; break;
+ case BFD_RELOC_PPC64_TPREL16_LO_DS:
case BFD_RELOC_PPC_TPREL16_LO: r = R_PPC_TPREL16_LO; break;
case BFD_RELOC_PPC_TPREL16_HI: r = R_PPC_TPREL16_HI; break;
case BFD_RELOC_PPC_TPREL16_HA: r = R_PPC_TPREL16_HA; break;
case BFD_RELOC_PPC_TPREL: r = R_PPC_TPREL32; break;
+ case BFD_RELOC_PPC64_DTPREL16_DS:
case BFD_RELOC_PPC_DTPREL16: r = R_PPC_DTPREL16; break;
+ case BFD_RELOC_PPC64_DTPREL16_LO_DS:
case BFD_RELOC_PPC_DTPREL16_LO: r = R_PPC_DTPREL16_LO; break;
case BFD_RELOC_PPC_DTPREL16_HI: r = R_PPC_DTPREL16_HI; break;
case BFD_RELOC_PPC_DTPREL16_HA: r = R_PPC_DTPREL16_HA; break;
return insn;
}
+static bfd_boolean
+is_insn_ds_form (unsigned int insn)
+{
+ return ((insn & (0x3f << 26)) == 58u << 26 /* ld,ldu,lwa */
+ || (insn & (0x3f << 26)) == 62u << 26 /* std,stdu,stq */
+ || (insn & (0x3f << 26)) == 57u << 26 /* lfdp */
+ || (insn & (0x3f << 26)) == 61u << 26 /* stfdp */);
+}
+
+static bfd_boolean
+is_insn_dq_form (unsigned int insn)
+{
+ return (insn & (0x3f << 26)) == 56u << 26; /* lq */
+}
+
/* The RELOCATE_SECTION function is called by the ELF backend linker
to handle the relocations for a section.
Bits 0:15 are not used. */
addend += 0x8000;
break;
+
+ case R_PPC_ADDR16:
+ case R_PPC_ADDR16_LO:
+ case R_PPC_GOT16:
+ case R_PPC_GOT16_LO:
+ case R_PPC_SDAREL16:
+ case R_PPC_SECTOFF:
+ case R_PPC_SECTOFF_LO:
+ case R_PPC_DTPREL16:
+ case R_PPC_DTPREL16_LO:
+ case R_PPC_TPREL16:
+ case R_PPC_TPREL16_LO:
+ case R_PPC_GOT_TLSGD16:
+ case R_PPC_GOT_TLSGD16_LO:
+ case R_PPC_GOT_TLSLD16:
+ case R_PPC_GOT_TLSLD16_LO:
+ case R_PPC_GOT_DTPREL16:
+ case R_PPC_GOT_DTPREL16_LO:
+ case R_PPC_GOT_TPREL16:
+ case R_PPC_GOT_TPREL16_LO:
+ {
+ /* The 32-bit ABI lacks proper relocations to deal with
+ certain 64-bit instructions. Prevent damage to bits
+ that make up part of the insn opcode. */
+ unsigned int insn, mask, lobit;
+
+ insn = bfd_get_32 (output_bfd, contents + rel->r_offset - d_offset);
+ mask = 0;
+ if (is_insn_ds_form (insn))
+ mask = 3;
+ else if (is_insn_dq_form (insn))
+ mask = 15;
+ else
+ break;
+ lobit = mask & (relocation + addend);
+ if (lobit != 0)
+ {
+ addend -= lobit;
+ info->callbacks->einfo
+ (_("%P: %H: error: %s against `%s' not a multiple of %u\n"),
+ input_bfd, input_section, rel->r_offset,
+ howto->name, sym_name, mask + 1);
+ bfd_set_error (bfd_error_bad_value);
+ ret = FALSE;
+ }
+ addend += insn & mask;
+ }
+ break;
}
#ifdef DEBUG
goto error_ret;
/* Mark toc entries referenced as used. */
- repeat = 0;
do
- for (rel = relstart; rel < relstart + sec->reloc_count; ++rel)
- {
- enum elf_ppc64_reloc_type r_type;
- unsigned long r_symndx;
- asection *sym_sec;
- struct elf_link_hash_entry *h;
- Elf_Internal_Sym *sym;
- bfd_vma val;
- enum {no_check, check_lo, check_ha} insn_check;
-
- r_type = ELF64_R_TYPE (rel->r_info);
- switch (r_type)
- {
- default:
- insn_check = no_check;
- break;
+ {
+ repeat = 0;
+ for (rel = relstart; rel < relstart + sec->reloc_count; ++rel)
+ {
+ enum elf_ppc64_reloc_type r_type;
+ unsigned long r_symndx;
+ asection *sym_sec;
+ struct elf_link_hash_entry *h;
+ Elf_Internal_Sym *sym;
+ bfd_vma val;
+ enum {no_check, check_lo, check_ha} insn_check;
- case R_PPC64_GOT_TLSLD16_HA:
- case R_PPC64_GOT_TLSGD16_HA:
- case R_PPC64_GOT_TPREL16_HA:
- case R_PPC64_GOT_DTPREL16_HA:
- case R_PPC64_GOT16_HA:
- case R_PPC64_TOC16_HA:
- insn_check = check_ha;
- break;
+ r_type = ELF64_R_TYPE (rel->r_info);
+ switch (r_type)
+ {
+ default:
+ insn_check = no_check;
+ break;
- case R_PPC64_GOT_TLSLD16_LO:
- case R_PPC64_GOT_TLSGD16_LO:
- case R_PPC64_GOT_TPREL16_LO_DS:
- case R_PPC64_GOT_DTPREL16_LO_DS:
- case R_PPC64_GOT16_LO:
- case R_PPC64_GOT16_LO_DS:
- case R_PPC64_TOC16_LO:
- case R_PPC64_TOC16_LO_DS:
- insn_check = check_lo;
- break;
- }
+ case R_PPC64_GOT_TLSLD16_HA:
+ case R_PPC64_GOT_TLSGD16_HA:
+ case R_PPC64_GOT_TPREL16_HA:
+ case R_PPC64_GOT_DTPREL16_HA:
+ case R_PPC64_GOT16_HA:
+ case R_PPC64_TOC16_HA:
+ insn_check = check_ha;
+ break;
- if (insn_check != no_check)
- {
- bfd_vma off = rel->r_offset & ~3;
- unsigned char buf[4];
- unsigned int insn;
+ case R_PPC64_GOT_TLSLD16_LO:
+ case R_PPC64_GOT_TLSGD16_LO:
+ case R_PPC64_GOT_TPREL16_LO_DS:
+ case R_PPC64_GOT_DTPREL16_LO_DS:
+ case R_PPC64_GOT16_LO:
+ case R_PPC64_GOT16_LO_DS:
+ case R_PPC64_TOC16_LO:
+ case R_PPC64_TOC16_LO_DS:
+ insn_check = check_lo;
+ break;
+ }
- if (!bfd_get_section_contents (ibfd, sec, buf, off, 4))
- {
- free (used);
- goto error_ret;
- }
- insn = bfd_get_32 (ibfd, buf);
- if (insn_check == check_lo
- ? !ok_lo_toc_insn (insn)
- : ((insn & ((0x3f << 26) | 0x1f << 16))
- != ((15u << 26) | (2 << 16)) /* addis rt,2,imm */))
- {
- char str[12];
+ if (insn_check != no_check)
+ {
+ bfd_vma off = rel->r_offset & ~3;
+ unsigned char buf[4];
+ unsigned int insn;
- ppc64_elf_tdata (ibfd)->unexpected_toc_insn = 1;
- sprintf (str, "%#08x", insn);
- info->callbacks->einfo
- (_("%P: %H: toc optimization is not supported for"
- " %s instruction.\n"),
- ibfd, sec, rel->r_offset & ~3, str);
- }
- }
+ if (!bfd_get_section_contents (ibfd, sec, buf, off, 4))
+ {
+ free (used);
+ goto error_ret;
+ }
+ insn = bfd_get_32 (ibfd, buf);
+ if (insn_check == check_lo
+ ? !ok_lo_toc_insn (insn)
+ : ((insn & ((0x3f << 26) | 0x1f << 16))
+ != ((15u << 26) | (2 << 16)) /* addis rt,2,imm */))
+ {
+ char str[12];
- switch (r_type)
- {
- case R_PPC64_TOC16:
- case R_PPC64_TOC16_LO:
- case R_PPC64_TOC16_HI:
- case R_PPC64_TOC16_HA:
- case R_PPC64_TOC16_DS:
- case R_PPC64_TOC16_LO_DS:
- /* In case we're taking addresses of toc entries. */
- case R_PPC64_ADDR64:
- break;
+ ppc64_elf_tdata (ibfd)->unexpected_toc_insn = 1;
+ sprintf (str, "%#08x", insn);
+ info->callbacks->einfo
+ (_("%P: %H: toc optimization is not supported for"
+ " %s instruction.\n"),
+ ibfd, sec, rel->r_offset & ~3, str);
+ }
+ }
- default:
- continue;
- }
+ switch (r_type)
+ {
+ case R_PPC64_TOC16:
+ case R_PPC64_TOC16_LO:
+ case R_PPC64_TOC16_HI:
+ case R_PPC64_TOC16_HA:
+ case R_PPC64_TOC16_DS:
+ case R_PPC64_TOC16_LO_DS:
+ /* In case we're taking addresses of toc entries. */
+ case R_PPC64_ADDR64:
+ break;
- r_symndx = ELF64_R_SYM (rel->r_info);
- if (!get_sym_h (&h, &sym, &sym_sec, NULL, &local_syms,
- r_symndx, ibfd))
- {
- free (used);
- goto error_ret;
- }
+ default:
+ continue;
+ }
- if (sym_sec != toc)
- continue;
+ r_symndx = ELF64_R_SYM (rel->r_info);
+ if (!get_sym_h (&h, &sym, &sym_sec, NULL, &local_syms,
+ r_symndx, ibfd))
+ {
+ free (used);
+ goto error_ret;
+ }
- if (h != NULL)
- val = h->root.u.def.value;
- else
- val = sym->st_value;
- val += rel->r_addend;
+ if (sym_sec != toc)
+ continue;
- if (val >= toc->size)
- continue;
+ if (h != NULL)
+ val = h->root.u.def.value;
+ else
+ val = sym->st_value;
+ val += rel->r_addend;
- if ((skip[val >> 3] & can_optimize) != 0)
- {
- bfd_vma off;
- unsigned char opc;
+ if (val >= toc->size)
+ continue;
- switch (r_type)
- {
- case R_PPC64_TOC16_HA:
- break;
+ if ((skip[val >> 3] & can_optimize) != 0)
+ {
+ bfd_vma off;
+ unsigned char opc;
- case R_PPC64_TOC16_LO_DS:
- off = rel->r_offset + (bfd_big_endian (ibfd) ? -2 : 3);
- if (!bfd_get_section_contents (ibfd, sec, &opc, off, 1))
- {
- free (used);
- goto error_ret;
- }
- if ((opc & (0x3f << 2)) == (58u << 2))
+ switch (r_type)
+ {
+ case R_PPC64_TOC16_HA:
break;
- /* Fall thru */
- default:
- /* Wrong sort of reloc, or not a ld. We may
- as well clear ref_from_discarded too. */
- skip[val >> 3] = 0;
- }
- }
+ case R_PPC64_TOC16_LO_DS:
+ off = rel->r_offset;
+ off += (bfd_big_endian (ibfd) ? -2 : 3);
+ if (!bfd_get_section_contents (ibfd, sec, &opc,
+ off, 1))
+ {
+ free (used);
+ goto error_ret;
+ }
+ if ((opc & (0x3f << 2)) == (58u << 2))
+ break;
+ /* Fall thru */
- /* For the toc section, we only mark as used if
- this entry itself isn't unused. */
- if (sec == toc
- && !used[val >> 3]
- && (used[rel->r_offset >> 3]
- || !(skip[rel->r_offset >> 3] & ref_from_discarded)))
- /* Do all the relocs again, to catch reference
- chains. */
- repeat = 1;
-
- used[val >> 3] = 1;
- }
+ default:
+ /* Wrong sort of reloc, or not a ld. We may
+ as well clear ref_from_discarded too. */
+ skip[val >> 3] = 0;
+ }
+ }
+
+ if (sec != toc)
+ used[val >> 3] = 1;
+ /* For the toc section, we only mark as used if this
+ entry itself isn't unused. */
+ else if ((used[rel->r_offset >> 3]
+ || !(skip[rel->r_offset >> 3] & ref_from_discarded))
+ && !used[val >> 3])
+ {
+ /* Do all the relocs again, to catch reference
+ chains. */
+ repeat = 1;
+ used[val >> 3] = 1;
+ }
+ }
+ }
while (repeat);
if (elf_section_data (sec)->relocs != relstart)
bfd_vma glinkoff = GLINK_CALL_STUB_SIZE + pltindex * 8;
bfd_vma to, from;
- if (pltindex > 32767)
- glinkoff += (pltindex - 32767) * 4;
+ if (pltindex > 32768)
+ glinkoff += (pltindex - 32768) * 4;
to = (glinkoff
+ htab->glink->output_offset
+ htab->glink->output_section->vma);
{
if (isec->size == 0
&& isec->output_section->size == 0
+ && !(isec->output_section->flags & SEC_KEEP)
&& !bfd_section_removed_from_list (info->output_bfd,
isec->output_section)
&& elf_section_data (isec->output_section)->dynindx == 0)
htab->plt_static_chain = plt_static_chain;
htab->plt_stub_align = plt_stub_align;
+ if (plt_thread_safe == -1 && !info->executable)
+ plt_thread_safe = 1;
if (plt_thread_safe == -1)
{
- const char *const thread_starter[] =
+ static const char *const thread_starter[] =
{
"pthread_create",
/* libstdc++ */
}
}
-/* Mark if a symbol has a definition in a dynamic object or is
- weak in all dynamic objects. */
-
-static void
-_bfd_elf_mark_dynamic_def_weak (struct elf_link_hash_entry *h,
- asection *sec, int bind)
-{
- if (!h->dynamic_def)
- {
- if (!bfd_is_und_section (sec))
- h->dynamic_def = 1;
- else
- {
- /* Check if this symbol is weak in all dynamic objects. If it
- is the first time we see it in a dynamic object, we mark
- if it is weak. Otherwise, we clear it. */
- if (!h->ref_dynamic)
- {
- if (bind == STB_WEAK)
- h->dynamic_weak = 1;
- }
- else if (bind != STB_WEAK)
- h->dynamic_weak = 0;
- }
- }
-}
-
/* This function is called when we want to define a new symbol. It
handles the various cases which arise when we find a definition in
a dynamic object, or when there is already a definition in a
h = (struct elf_link_hash_entry *) h->root.u.i.link;
/* We have to check it for every instance since the first few may be
- refereences and not all compilers emit symbol type for undefined
+ references and not all compilers emit symbol type for undefined
symbols. */
bfd_elf_link_mark_dynamic_symbol (info, h, sym);
+ /* NEWDYN and OLDDYN indicate whether the new or old symbol,
+ respectively, is from a dynamic object. */
+
+ newdyn = (abfd->flags & DYNAMIC) != 0;
+
+ /* ref_dynamic_nonweak and dynamic_def flags track actual undefined
+ syms and defined syms in dynamic libraries respectively.
+ ref_dynamic on the other hand can be set for a symbol defined in
+ a dynamic library, and def_dynamic may not be set; When the
+ definition in a dynamic lib is overridden by a definition in the
+ executable use of the symbol in the dynamic lib becomes a
+ reference to the executable symbol. */
+ if (newdyn)
+ {
+ if (bfd_is_und_section (sec))
+ {
+ if (bind != STB_WEAK)
+ {
+ h->ref_dynamic_nonweak = 1;
+ hi->ref_dynamic_nonweak = 1;
+ }
+ }
+ else
+ {
+ h->dynamic_def = 1;
+ hi->dynamic_def = 1;
+ }
+ }
+
/* If we just created the symbol, mark it as being an ELF symbol.
Other than that, there is nothing to do--there is no merge issue
with a newly defined symbol--so we just return. */
|| !h->def_regular))
return TRUE;
- /* NEWDYN and OLDDYN indicate whether the new or old symbol,
- respectively, is from a dynamic object. */
-
- newdyn = (abfd->flags & DYNAMIC) != 0;
-
olddyn = FALSE;
if (oldbfd != NULL)
olddyn = (oldbfd->flags & DYNAMIC) != 0;
return FALSE;
}
- /* We need to remember if a symbol has a definition in a dynamic
- object or is weak in all dynamic objects. Internal and hidden
- visibility will make it unavailable to dynamic objects. */
- if (newdyn)
- {
- _bfd_elf_mark_dynamic_def_weak (h, sec, bind);
- if (h != hi)
- _bfd_elf_mark_dynamic_def_weak (hi, sec, bind);
- }
-
/* If the old symbol has non-default visibility, we ignore the new
definition from a dynamic object. */
if (newdyn
h->ref_dynamic = 1;
h->def_dynamic = 0;
- h->dynamic_def = 0;
/* FIXME: Should we check type and size for protected symbol? */
h->size = 0;
h->type = 0;
else
h->ref_dynamic = 1;
h->def_dynamic = 0;
- h->dynamic_def = 0;
/* FIXME: Should we check type and size for protected symbol? */
h->size = 0;
h->type = 0;
bfd_boolean do_it)
{
struct elf_link_hash_table *hash_table;
- bfd_size_type oldsize;
bfd_size_type strindex;
if (!_bfd_elf_link_create_dynstrtab (abfd, info))
return -1;
hash_table = elf_hash_table (info);
- oldsize = _bfd_elf_strtab_size (hash_table->dynstr);
strindex = _bfd_elf_strtab_add (hash_table->dynstr, soname, FALSE);
if (strindex == (bfd_size_type) -1)
return -1;
- if (oldsize == _bfd_elf_strtab_size (hash_table->dynstr))
+ if (_bfd_elf_strtab_refcount (hash_table->dynstr, strindex) != 1)
{
asection *sdyn;
const struct elf_backend_data *bed;
struct bfd_link_hash_entry *old_undefs = NULL;
struct bfd_link_hash_entry *old_undefs_tail = NULL;
long old_dynsymcount = 0;
+ bfd_size_type old_dynstr_size = 0;
size_t tabsize = 0;
size_t hashsize = 0;
old_size = htab->root.table.size;
old_count = htab->root.table.count;
old_dynsymcount = htab->dynsymcount;
+ old_dynstr_size = _bfd_elf_strtab_size (htab->dynstr);
for (i = 0; i < htab->root.table.size; i++)
{
}
if (elf_tdata (abfd)->verdef != NULL
- && ! override
&& vernum > 1
&& definition)
h->verinfo.verdef = &elf_tdata (abfd)->verdef[vernum - 1];
else
{
h->def_dynamic = 1;
- h->dynamic_def = 1;
hi->def_dynamic = 1;
- hi->dynamic_def = 1;
}
/* If the indirect symbol has been forced local, don't
memcpy (sym_hash, old_hash, hashsize);
htab->root.undefs = old_undefs;
htab->root.undefs_tail = old_undefs_tail;
+ _bfd_elf_strtab_clear_refs (htab->dynstr, old_dynstr_size);
for (i = 0; i < htab->root.table.size; i++)
{
struct bfd_hash_entry *p;
h = (struct elf_link_hash_entry *) p;
if (h->root.type == bfd_link_hash_warning)
h = (struct elf_link_hash_entry *) h->root.u.i.link;
- if (h->dynindx >= old_dynsymcount)
+ if (h->dynindx >= old_dynsymcount
+ && h->dynstr_index < old_dynstr_size)
_bfd_elf_strtab_delref (htab->dynstr, h->dynstr_index);
/* Preserve the maximum alignment and size for common
symbols even if this dynamic lib isn't on DT_NEEDED
- since it can still be loaded at the run-time by another
+ since it can still be loaded at run time by another
dynamic lib. */
if (h->root.type == bfd_link_hash_common)
{
{
memcpy (h->root.u.i.link, old_ent, htab->root.table.entsize);
old_ent = (char *) old_ent + htab->root.table.entsize;
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
}
- else if (h->root.type == bfd_link_hash_common)
+ if (h->root.type == bfd_link_hash_common)
{
if (size > h->root.u.c.size)
h->root.u.c.size = size;
&& h->ref_dynamic
&& h->def_regular
&& !h->dynamic_def
- && !h->dynamic_weak
+ && h->ref_dynamic_nonweak
&& !elf_link_check_versioned_symbol (flinfo->info, bed, h))
{
bfd *def_bfd;
const struct elf_backend_data *bed = get_elf_backend_data (abfd);
bfd_byte *loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rel);
BFD_ASSERT (loc + bed->s->sizeof_rel <= s->contents + s->size);
- bed->s->swap_reloca_out (abfd, rel, loc);
+ bed->s->swap_reloc_out (abfd, rel, loc);
}
else
output = FALSE;
}
+ else if (sym->flags == 0
+ && (sym->section->owner->flags & BFD_PLUGIN) != 0)
+ /* LTO doesn't set symbol information. We get here with the
+ generic linker for a symbol that was "common" but no longer
+ needs to be global. */
+ output = FALSE;
else
abort ();
return nbfd;
}
+static const struct bfd_iovec opncls_iovec;
+
/* Allocate a new BFD as a member of archive OBFD. */
bfd *
return NULL;
nbfd->xvec = obfd->xvec;
nbfd->iovec = obfd->iovec;
+ if (obfd->iovec == &opncls_iovec)
+ nbfd->iostream = obfd->iostream;
nbfd->my_archive = obfd;
nbfd->direction = read_direction;
nbfd->target_defaulted = obfd->target_defaulted;
if (! BFD_SEND (abfd, _close_and_cleanup, (abfd)))
return FALSE;
- ret = abfd->iovec->bclose (abfd);
+ ret = abfd->iovec->bclose (abfd) == 0;
if (ret)
_maybe_make_executable (abfd);
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2012-09-04 H.J. Lu <hongjiu.lu@intel.com>
+ PR binutils/14493
+ * readelf.c (get_symbol_index_type): Check bad section index.
+
2013-01-07 Roland McGrath <mcgrathr@google.com>
* objcopy.c (deterministic): Make int rather than bfd_boolean,
sprintf (buff, "OS [0x%04x]", type & 0xffff);
else if (type >= SHN_LORESERVE)
sprintf (buff, "RSV[0x%04x]", type & 0xffff);
+ else if (type >= elf_header.e_shnum)
+ sprintf (buff, "bad section index[%3d]", type);
else
sprintf (buff, "%3d", type);
break;
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2012-11-23 Alan Modra <amodra@gmail.com>
+ * config/tc-ppc.c (sticky): New var.
+ (md_parse_option, ppc_machine): Update ppc_parse_cpu calls.
+
+ 2012-11-14 Ulrich Weigand <uweigand@de.ibm.com>
+ * config/tc-ppc.c (md_apply_fix): Leave field zero when emitting
+ an ELF reloc on data as well.
+
+ 2012-11-06 Alan Modra <amodra@gmail.com>
+ * config/tc-ppc.c (md_apply_fix): Fix xcoff build breakage.
+
+ 2012-11-05 Alan Modra <amodra@gmail.com>
+ * config/tc-ppc.c (md_chars_to_number): Delete.
+ (ppc_setup_opcodes): Assert num_powerpc_operands fit.
+ (ppc_is_toc_sym): Move earlier in file.
+ (md_assemble): Move code setting reloc from md_apply_fix. Combine
+ non-ELF code setting fixup with ELF code. Stash opindex in
+ fx_pcrel_adjust. Adjust fixup offset for VLE. Don't set
+ fx_no_overflow here.
+ (md_apply_fix): Rewrite to use ppc_insert_operand for all
+ resolved instruction fields. Leave insn field zero when
+ emitting an ELF reloc in most cases.
+
+ 2012-10-29 Alan Modra <amodra@gmail.com>
+ * sb.c (sb_check): Use __builtin_clzll when size_t is not the
+ same size as long.
+
+ 2012-10-26 Alan Modra <amodra@gmail.com>
+ PR gas/14758
+ * config/tc-ppc.c (ppc_setup_opcodes): Fix comment.
+ (md_assemble): Translate to _DS relocs for ppc32 as well as ppc64.
+ (tc_gen_reloc): Handle _DS relocs in ppc32 mode.
+
+ 2012-10-01 Alan Modra <amodra@gmail.com>
+ * write.c (chain_frchains_together_1): Reorder assertion to avoid
+ uninit warning.
+
+ 2012-08-01 James Lemke <jwlemke@codesourcery.com>
+ * dwarf2dbg.c (out_set_addr): Allow for non-constant value of
+ DWARF2_LINE_MIN_INSN_LENGTH
+ * config/tc-ppc.c (ppc_dwarf2_line_min_insn_length): Declare
+ and initialize.
+ (md_apply_fix): Branch addr can be a multiple of 2 or 4.
+ * config/tc-ppc.h (DWARF2_LINE_MIN_INSN_LENGTH): Now a
+ variable reference.
+
2013-01-10 Roland McGrath <mcgrathr@google.com>
* hash.c (hash_new_sized): Make it global.
/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
int ppc_cie_data_alignment;
+/* The dwarf2 minimum instruction length. */
+int ppc_dwarf2_line_min_insn_length;
+
/* More than this number of nops in an alignment op gets a branch
instead. */
unsigned long nop_limit = 4;
/* The type of processor we are assembling for. This is one or more
of the PPC_OPCODE flags defined in opcode/ppc.h. */
ppc_cpu_t ppc_cpu = 0;
+ppc_cpu_t sticky = 0;
/* Flags set on encountering toc relocs. */
enum {
};
const size_t md_longopts_size = sizeof (md_longopts);
-/* Convert the target integer stored in N bytes in BUF to a host
- integer, returning that value. */
-
-static valueT
-md_chars_to_number (char *buf, int n)
-{
- valueT result = 0;
- unsigned char *p = (unsigned char *) buf;
-
- if (target_big_endian)
- {
- while (n--)
- {
- result <<= 8;
- result |= (*p++ & 0xff);
- }
- }
- else
- {
- while (n--)
- {
- result <<= 8;
- result |= (p[n] & 0xff);
- }
- }
-
- return result;
-}
-
int
md_parse_option (int c, char *arg)
{
break;
case 'm':
- new_cpu = ppc_parse_cpu (ppc_cpu, arg);
+ new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg);
if (new_cpu != 0)
{
ppc_cpu = new_cpu;
}
/* Insert opcodes and macros into hash tables. Called at startup and
- for .cpu pseudo. */
+ for .machine pseudo. */
static void
ppc_setup_opcodes (void)
{
unsigned int i;
+ /* An index into powerpc_operands is stored in struct fix
+ fx_pcrel_adjust which is 8 bits wide. */
+ gas_assert (num_powerpc_operands < 256);
+
/* Check operand masks. Code here and in the disassembler assumes
all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i)
ppc_set_cpu ();
ppc_cie_data_alignment = ppc_obj64 ? -8 : -4;
+ ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4;
#ifdef OBJ_ELF
/* Set the ELF flags if desired. */
return 1;
}
#endif
+
+#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
+/* See whether a symbol is in the TOC section. */
+
+static int
+ppc_is_toc_sym (symbolS *sym)
+{
+#ifdef OBJ_XCOFF
+ return symbol_get_tc (sym)->symbol_class == XMC_TC;
+#endif
+#ifdef OBJ_ELF
+ const char *sname = segment_name (S_GET_SEGMENT (sym));
+ if (ppc_obj64)
+ return strcmp (sname, ".toc") == 0;
+ else
+ return strcmp (sname, ".got") == 0;
+#endif
+}
+#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
\f
#ifdef OBJ_ELF
int addr_mod;
int i;
unsigned int insn_length;
-#ifdef OBJ_ELF
- bfd_reloc_code_real_type reloc;
-#endif
/* Get the opcode. */
for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
{
#ifdef OBJ_ELF
/* Allow @HA, @L, @H on constants. */
+ bfd_reloc_code_real_type reloc;
char *orig_str = str;
if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED)
insn = ppc_insert_operand (insn, operand, ex.X_add_number,
ppc_cpu, (char *) NULL, 0);
}
-#ifdef OBJ_ELF
else
{
+ bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
+#ifdef OBJ_ELF
if (ex.X_op == O_symbol && str[0] == '(')
{
const char *sym_name = S_GET_NAME (ex.X_add_symbol);
break;
}
- if (ppc_obj64
- && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
+ if ((operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
{
switch (reloc)
{
}
}
}
+#endif /* OBJ_ELF */
+
+ if (reloc != BFD_RELOC_UNUSED)
+ ;
+ /* Determine a BFD reloc value based on the operand information.
+ We are only prepared to turn a few of the operands into
+ relocs. */
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0x3fffffc
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_B26;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0xfffc
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_B16;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0x1fe
+ && operand->shift == -1)
+ reloc = BFD_RELOC_PPC_VLE_REL8;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0xfffe
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_VLE_REL15;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0x1fffffe
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_VLE_REL24;
+ else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
+ && operand->bitm == 0x3fffffc
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_BA26;
+ else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
+ && operand->bitm == 0xfffc
+ && operand->shift == 0)
+ reloc = BFD_RELOC_PPC_BA16;
+#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
+ else if ((operand->flags & PPC_OPERAND_PARENS) != 0
+ && (operand->bitm & 0xfff0) == 0xfff0
+ && operand->shift == 0)
+ {
+ if (ppc_is_toc_sym (ex.X_add_symbol))
+ {
+ reloc = BFD_RELOC_PPC_TOC16;
+#ifdef OBJ_ELF
+ if (ppc_obj64
+ && (operand->flags & PPC_OPERAND_DS) != 0)
+ reloc = BFD_RELOC_PPC64_TOC16_DS;
+#endif
+ }
+ else
+ {
+ reloc = BFD_RELOC_16;
+#ifdef OBJ_ELF
+ if (ppc_obj64
+ && (operand->flags & PPC_OPERAND_DS) != 0)
+ reloc = BFD_RELOC_PPC64_ADDR16_DS;
+#endif
+ }
+ }
+#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
/* We need to generate a fixup for this expression. */
if (fc >= MAX_INSN_FIXUPS)
fixups[fc].reloc = reloc;
++fc;
}
-#else /* OBJ_ELF */
- else
- {
- /* We need to generate a fixup for this expression. */
- if (fc >= MAX_INSN_FIXUPS)
- as_fatal (_("too many fixups"));
- fixups[fc].exp = ex;
- fixups[fc].opindex = *opindex_ptr;
- fixups[fc].reloc = BFD_RELOC_UNUSED;
- ++fc;
- }
-#endif /* OBJ_ELF */
if (need_paren)
{
dwarf2_emit_insn (insn_length);
#endif
- /* Create any fixups. At this point we do not use a
- bfd_reloc_code_real_type, but instead just use the
- BFD_RELOC_UNUSED plus the operand index. This lets us easily
- handle fixups for any operand type, although that is admittedly
- not a very exciting feature. We pick a BFD reloc type in
- md_apply_fix. */
+ /* Create any fixups. */
for (i = 0; i < fc; i++)
{
+ fixS *fixP;
if (fixups[i].reloc != BFD_RELOC_UNUSED)
{
reloc_howto_type *reloc_howto;
int size;
int offset;
- fixS *fixP;
reloc_howto = bfd_reloc_type_lookup (stdoutput, fixups[i].reloc);
if (!reloc_howto)
abort ();
size = bfd_get_reloc_size (reloc_howto);
- offset = target_big_endian ? (4 - size) : 0;
+ offset = target_big_endian ? (insn_length - size) : 0;
if (size < 1 || size > 4)
abort ();
&fixups[i].exp,
reloc_howto->pc_relative,
fixups[i].reloc);
-
- /* Turn off complaints that the addend is too large for things like
- foo+100000@ha. */
- switch (fixups[i].reloc)
- {
- case BFD_RELOC_16_GOTOFF:
- case BFD_RELOC_PPC_TOC16:
- case BFD_RELOC_LO16:
- case BFD_RELOC_HI16:
- case BFD_RELOC_HI16_S:
- case BFD_RELOC_PPC_VLE_LO16A:
- case BFD_RELOC_PPC_VLE_LO16D:
- case BFD_RELOC_PPC_VLE_HI16A:
- case BFD_RELOC_PPC_VLE_HI16D:
- case BFD_RELOC_PPC_VLE_HA16A:
- case BFD_RELOC_PPC_VLE_HA16D:
-#ifdef OBJ_ELF
- case BFD_RELOC_PPC64_HIGHER:
- case BFD_RELOC_PPC64_HIGHER_S:
- case BFD_RELOC_PPC64_HIGHEST:
- case BFD_RELOC_PPC64_HIGHEST_S:
-#endif
- fixP->fx_no_overflow = 1;
- break;
- default:
- break;
- }
}
else
{
const struct powerpc_operand *operand;
operand = &powerpc_operands[fixups[i].opindex];
- fix_new_exp (frag_now,
- f - frag_now->fr_literal,
- insn_length,
- &fixups[i].exp,
- (operand->flags & PPC_OPERAND_RELATIVE) != 0,
- ((bfd_reloc_code_real_type)
- (fixups[i].opindex + (int) BFD_RELOC_UNUSED)));
+ fixP = fix_new_exp (frag_now,
+ f - frag_now->fr_literal,
+ insn_length,
+ &fixups[i].exp,
+ (operand->flags & PPC_OPERAND_RELATIVE) != 0,
+ BFD_RELOC_UNUSED);
}
+ fixP->fx_pcrel_adjust = fixups[i].opindex;
}
}
else
ppc_cpu = cpu_history[--curr_hist];
}
- else if ((new_cpu = ppc_parse_cpu (ppc_cpu, cpu_string)) != 0)
+ else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0)
ppc_cpu = new_cpu;
else
as_bad (_("invalid machine `%s'"), cpu_string);
demand_empty_rest_of_line ();
}
-
-/* See whether a symbol is in the TOC section. */
-
-static int
-ppc_is_toc_sym (symbolS *sym)
-{
-#ifdef OBJ_XCOFF
- return symbol_get_tc (sym)->symbol_class == XMC_TC;
-#endif
-#ifdef OBJ_ELF
- const char *sname = segment_name (S_GET_SEGMENT (sym));
- if (ppc_obj64)
- return strcmp (sname, ".toc") == 0;
- else
- return strcmp (sname, ".got") == 0;
-#endif
-}
#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
\f
#ifdef TE_PE
}
/* Apply a fixup to the object code. This is called for all the
- fixups we generated by the call to fix_new_exp, above. In the call
- above we used a reloc code which was the largest legal reloc code
- plus the operand index. Here we undo that to recover the operand
- index. At this point all symbol values should be fully resolved,
- and we attempt to completely resolve the reloc. If we can not do
- that, we determine the correct reloc code and put it back in the
- fixup. */
+ fixups we generated by the calls to fix_new_exp, above. */
void
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
}
- if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ if (fixP->fx_pcrel_adjust != 0)
{
- int opindex;
- const struct powerpc_operand *operand;
+ /* Handle relocs in an insn. */
+
+ int opindex = fixP->fx_pcrel_adjust & 0xff;
+ const struct powerpc_operand *operand = &powerpc_operands[opindex];
char *where;
unsigned long insn;
-
- opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
-
- operand = &powerpc_operands[opindex];
+ offsetT fieldval;
#ifdef OBJ_XCOFF
/* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
fixP->fx_done = 1;
}
#endif
-
- /* Fetch the instruction, insert the fully resolved operand
- value, and stuff the instruction back again. */
- where = fixP->fx_frag->fr_literal + fixP->fx_where;
- if (target_big_endian)
- {
- if (fixP->fx_size == 4)
- insn = bfd_getb32 ((unsigned char *) where);
- else
- insn = bfd_getb16 ((unsigned char *) where);
- }
- else
- {
- if (fixP->fx_size == 4)
- insn = bfd_getl32 ((unsigned char *) where);
- else
- insn = bfd_getl16 ((unsigned char *) where);
- }
- insn = ppc_insert_operand (insn, operand, (offsetT) value,
- fixP->tc_fix_data.ppc_cpu,
- fixP->fx_file, fixP->fx_line);
- if (target_big_endian)
- {
- if (fixP->fx_size == 4)
- bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
- else
- bfd_putb16 ((bfd_vma) insn, (unsigned char *) where);
- }
- else
- {
- if (fixP->fx_size == 4)
- bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
- else
- bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
- }
-
- if (fixP->fx_done)
- /* Nothing else to do here. */
- return;
-
- gas_assert (fixP->fx_addsy != NULL);
-
- /* Determine a BFD reloc value based on the operand information.
- We are only prepared to turn a few of the operands into
- relocs. */
- if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
- && operand->bitm == 0x3fffffc
- && operand->shift == 0)
- fixP->fx_r_type = BFD_RELOC_PPC_B26;
- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
- && operand->bitm == 0xfffc
- && operand->shift == 0)
- {
- fixP->fx_r_type = BFD_RELOC_PPC_B16;
-#ifdef OBJ_XCOFF
- fixP->fx_size = 2;
- if (target_big_endian)
- fixP->fx_where += 2;
-#endif
- }
- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
- && operand->bitm == 0x1fe
- && operand->shift == -1)
- fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL8;
- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
- && operand->bitm == 0xfffe
- && operand->shift == 0)
- fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL15;
- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
- && operand->bitm == 0x1fffffe
- && operand->shift == 0)
- fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL24;
- else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
- && operand->bitm == 0x3fffffc
- && operand->shift == 0)
- fixP->fx_r_type = BFD_RELOC_PPC_BA26;
- else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
- && operand->bitm == 0xfffc
- && operand->shift == 0)
- {
- fixP->fx_r_type = BFD_RELOC_PPC_BA16;
-#ifdef OBJ_XCOFF
- fixP->fx_size = 2;
- if (target_big_endian)
- fixP->fx_where += 2;
-#endif
- }
-#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
- else if ((operand->flags & PPC_OPERAND_PARENS) != 0
- && (operand->bitm & 0xfff0) == 0xfff0
- && operand->shift == 0)
- {
- if (ppc_is_toc_sym (fixP->fx_addsy))
- {
- fixP->fx_r_type = BFD_RELOC_PPC_TOC16;
-#ifdef OBJ_ELF
- if (ppc_obj64
- && (operand->flags & PPC_OPERAND_DS) != 0)
- fixP->fx_r_type = BFD_RELOC_PPC64_TOC16_DS;
-#endif
- }
- else
- {
- fixP->fx_r_type = BFD_RELOC_16;
-#ifdef OBJ_ELF
- if (ppc_obj64
- && (operand->flags & PPC_OPERAND_DS) != 0)
- fixP->fx_r_type = BFD_RELOC_PPC64_ADDR16_DS;
-#endif
- }
- fixP->fx_size = 2;
- if (target_big_endian)
- fixP->fx_where += 2;
- }
-#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
- else
- {
- char *sfile;
- unsigned int sline;
-
- /* Use expr_symbol_where to see if this is an expression
- symbol. */
- if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("unresolved expression that must be resolved"));
- else
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("unsupported relocation against %s"),
- S_GET_NAME (fixP->fx_addsy));
- fixP->fx_done = 1;
- return;
- }
- }
- else
- {
-#ifdef OBJ_ELF
- ppc_elf_validate_fix (fixP, seg);
-#endif
+ fieldval = value;
switch (fixP->fx_r_type)
{
- case BFD_RELOC_CTOR:
- if (ppc_obj64)
- goto ctor64;
- /* fall through */
-
- case BFD_RELOC_32:
- if (fixP->fx_pcrel)
- fixP->fx_r_type = BFD_RELOC_32_PCREL;
- /* fall through */
-
- case BFD_RELOC_RVA:
- case BFD_RELOC_32_PCREL:
- case BFD_RELOC_PPC_EMB_NADDR32:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 4);
- break;
-
- case BFD_RELOC_64:
- ctor64:
- if (fixP->fx_pcrel)
- fixP->fx_r_type = BFD_RELOC_64_PCREL;
- /* fall through */
-
- case BFD_RELOC_64_PCREL:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 8);
- break;
-
- case BFD_RELOC_GPREL16:
- case BFD_RELOC_16_GOT_PCREL:
- case BFD_RELOC_16_GOTOFF:
- case BFD_RELOC_LO16_GOTOFF:
- case BFD_RELOC_HI16_GOTOFF:
- case BFD_RELOC_HI16_S_GOTOFF:
- case BFD_RELOC_16_BASEREL:
- case BFD_RELOC_LO16_BASEREL:
- case BFD_RELOC_HI16_BASEREL:
- case BFD_RELOC_HI16_S_BASEREL:
- case BFD_RELOC_PPC_EMB_NADDR16:
- case BFD_RELOC_PPC_EMB_NADDR16_LO:
- case BFD_RELOC_PPC_EMB_NADDR16_HI:
- case BFD_RELOC_PPC_EMB_NADDR16_HA:
- case BFD_RELOC_PPC_EMB_SDAI16:
- case BFD_RELOC_PPC_EMB_SDA2REL:
- case BFD_RELOC_PPC_EMB_SDA2I16:
- case BFD_RELOC_PPC_EMB_RELSEC16:
- case BFD_RELOC_PPC_EMB_RELST_LO:
- case BFD_RELOC_PPC_EMB_RELST_HI:
- case BFD_RELOC_PPC_EMB_RELST_HA:
- case BFD_RELOC_PPC_EMB_RELSDA:
- case BFD_RELOC_PPC_TOC16:
#ifdef OBJ_ELF
- case BFD_RELOC_PPC64_TOC16_LO:
- case BFD_RELOC_PPC64_TOC16_HI:
- case BFD_RELOC_PPC64_TOC16_HA:
-#endif
- if (fixP->fx_pcrel)
- {
- if (fixP->fx_addsy != NULL)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("cannot emit PC relative %s relocation against %s"),
- bfd_get_reloc_code_name (fixP->fx_r_type),
- S_GET_NAME (fixP->fx_addsy));
- else
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("cannot emit PC relative %s relocation"),
- bfd_get_reloc_code_name (fixP->fx_r_type));
- }
-
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 2);
- break;
-
- case BFD_RELOC_16:
+ case BFD_RELOC_PPC64_ADDR16_LO_DS:
if (fixP->fx_pcrel)
- fixP->fx_r_type = BFD_RELOC_16_PCREL;
+ goto bad_pcrel;
/* fall through */
-
- case BFD_RELOC_16_PCREL:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 2);
- break;
-
+#endif
case BFD_RELOC_LO16:
if (fixP->fx_pcrel)
fixP->fx_r_type = BFD_RELOC_LO16_PCREL;
/* fall through */
-
case BFD_RELOC_LO16_PCREL:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 2);
+ fieldval = SEX16 (value);
break;
- /* This case happens when you write, for example,
- lis %r3,(L1-L2)@ha
- where L1 and L2 are defined later. */
case BFD_RELOC_HI16:
if (fixP->fx_pcrel)
fixP->fx_r_type = BFD_RELOC_HI16_PCREL;
/* fall through */
-
case BFD_RELOC_HI16_PCREL:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HI (value), 2);
+ fieldval = SEX16 (PPC_HI (value));
break;
case BFD_RELOC_HI16_S:
if (fixP->fx_pcrel)
fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL;
/* fall through */
-
case BFD_RELOC_HI16_S_PCREL:
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HA (value), 2);
+ fieldval = SEX16 (PPC_HA (value));
break;
- case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
- case BFD_RELOC_PPC_VLE_LO16A:
- {
- int tval = PPC_VLE_LO16A (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
+#ifdef OBJ_ELF
+ case BFD_RELOC_PPC64_HIGHER:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ fieldval = SEX16 (PPC_HIGHER (value));
break;
- case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
- case BFD_RELOC_PPC_VLE_LO16D:
- {
- int tval = PPC_VLE_LO16D (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
+ case BFD_RELOC_PPC64_HIGHER_S:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ fieldval = SEX16 (PPC_HIGHERA (value));
break;
- case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
- case BFD_RELOC_PPC_VLE_HI16A:
- {
- int tval = PPC_VLE_HI16A (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
- break;
-
- case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
- case BFD_RELOC_PPC_VLE_HI16D:
- {
- int tval = PPC_VLE_HI16D (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
- break;
-
- case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
- case BFD_RELOC_PPC_VLE_HA16A:
- {
- int tval = PPC_VLE_HA16A (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
- break;
-
- case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
- case BFD_RELOC_PPC_VLE_HA16D:
- {
- int tval = PPC_VLE_HA16D (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
- break;
-
- case BFD_RELOC_PPC_VLE_SDA21_LO:
- {
- int tval = PPC_LO (value);
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | tval), 4);
- }
- break;
-
- case BFD_RELOC_PPC_VLE_SDA21:
- {
- valueT oldval = md_chars_to_number (
- fixP->fx_frag->fr_literal + fixP->fx_where, 4);
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- (oldval | value), 4);
- }
- break;
-
-#ifdef OBJ_XCOFF
- case BFD_RELOC_NONE:
- break;
-#endif
-
-#ifdef OBJ_ELF
- case BFD_RELOC_PPC64_HIGHER:
- if (fixP->fx_pcrel)
- abort ();
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HIGHER (value), 2);
- break;
-
- case BFD_RELOC_PPC64_HIGHER_S:
- if (fixP->fx_pcrel)
- abort ();
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HIGHERA (value), 2);
- break;
-
- case BFD_RELOC_PPC64_HIGHEST:
- if (fixP->fx_pcrel)
- abort ();
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HIGHEST (value), 2);
+ case BFD_RELOC_PPC64_HIGHEST:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ fieldval = SEX16 (PPC_HIGHEST (value));
break;
case BFD_RELOC_PPC64_HIGHEST_S:
if (fixP->fx_pcrel)
- abort ();
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- PPC_HIGHESTA (value), 2);
- break;
-
- case BFD_RELOC_PPC64_ADDR16_DS:
- case BFD_RELOC_PPC64_ADDR16_LO_DS:
- case BFD_RELOC_PPC64_GOT16_DS:
- case BFD_RELOC_PPC64_GOT16_LO_DS:
- case BFD_RELOC_PPC64_PLT16_LO_DS:
- case BFD_RELOC_PPC64_SECTOFF_DS:
- case BFD_RELOC_PPC64_SECTOFF_LO_DS:
- case BFD_RELOC_PPC64_TOC16_DS:
- case BFD_RELOC_PPC64_TOC16_LO_DS:
- case BFD_RELOC_PPC64_PLTGOT16_DS:
- case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
- if (fixP->fx_pcrel)
- abort ();
- {
- char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
- unsigned long val, mask;
-
- if (target_big_endian)
- val = bfd_getb32 (where - 2);
- else
- val = bfd_getl32 (where);
- mask = 0xfffc;
- /* lq insns reserve the four lsbs. */
- if ((ppc_cpu & PPC_OPCODE_POWER4) != 0
- && (val & (0x3f << 26)) == (56u << 26))
- mask = 0xfff0;
- val |= value & mask;
- if (target_big_endian)
- bfd_putb16 ((bfd_vma) val, where);
- else
- bfd_putl16 ((bfd_vma) val, where);
- }
+ goto bad_pcrel;
+ fieldval = SEX16 (PPC_HIGHESTA (value));
break;
- case BFD_RELOC_PPC_B16_BRTAKEN:
- case BFD_RELOC_PPC_B16_BRNTAKEN:
- case BFD_RELOC_PPC_BA16_BRTAKEN:
- case BFD_RELOC_PPC_BA16_BRNTAKEN:
- break;
-
- case BFD_RELOC_PPC_TLS:
- case BFD_RELOC_PPC_TLSGD:
- case BFD_RELOC_PPC_TLSLD:
- break;
-
- case BFD_RELOC_PPC_DTPMOD:
+ /* The following relocs can't be calculated by the assembler.
+ Leave the field zero. */
case BFD_RELOC_PPC_TPREL16:
case BFD_RELOC_PPC_TPREL16_LO:
case BFD_RELOC_PPC_TPREL16_HI:
case BFD_RELOC_PPC_TPREL16_HA:
- case BFD_RELOC_PPC_TPREL:
case BFD_RELOC_PPC_DTPREL16:
case BFD_RELOC_PPC_DTPREL16_LO:
case BFD_RELOC_PPC_DTPREL16_HI:
case BFD_RELOC_PPC_DTPREL16_HA:
- case BFD_RELOC_PPC_DTPREL:
case BFD_RELOC_PPC_GOT_TLSGD16:
case BFD_RELOC_PPC_GOT_TLSGD16_LO:
case BFD_RELOC_PPC_GOT_TLSGD16_HI:
case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
+ gas_assert (fixP->fx_addsy != NULL);
S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ fieldval = 0;
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
break;
-#endif
- /* Because SDA21 modifies the register field, the size is set to 4
- bytes, rather than 2, so offset it here appropriately. */
+
+ /* These also should leave the field zero for the same
+ reason. Note that older versions of gas wrote values
+ here. If we want to go back to the old behaviour, then
+ all _LO and _LO_DS cases will need to be treated like
+ BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
+ case BFD_RELOC_16_GOTOFF:
+ case BFD_RELOC_LO16_GOTOFF:
+ case BFD_RELOC_HI16_GOTOFF:
+ case BFD_RELOC_HI16_S_GOTOFF:
+ case BFD_RELOC_LO16_PLTOFF:
+ case BFD_RELOC_HI16_PLTOFF:
+ case BFD_RELOC_HI16_S_PLTOFF:
+ case BFD_RELOC_GPREL16:
+ case BFD_RELOC_16_BASEREL:
+ case BFD_RELOC_LO16_BASEREL:
+ case BFD_RELOC_HI16_BASEREL:
+ case BFD_RELOC_HI16_S_BASEREL:
+ case BFD_RELOC_PPC_TOC16:
+ case BFD_RELOC_PPC64_TOC16_LO:
+ case BFD_RELOC_PPC64_TOC16_HI:
+ case BFD_RELOC_PPC64_TOC16_HA:
+ case BFD_RELOC_PPC64_PLTGOT16:
+ case BFD_RELOC_PPC64_PLTGOT16_LO:
+ case BFD_RELOC_PPC64_PLTGOT16_HI:
+ case BFD_RELOC_PPC64_PLTGOT16_HA:
+ case BFD_RELOC_PPC64_GOT16_DS:
+ case BFD_RELOC_PPC64_GOT16_LO_DS:
+ case BFD_RELOC_PPC64_PLT16_LO_DS:
+ case BFD_RELOC_PPC64_SECTOFF_DS:
+ case BFD_RELOC_PPC64_SECTOFF_LO_DS:
+ case BFD_RELOC_PPC64_TOC16_DS:
+ case BFD_RELOC_PPC64_TOC16_LO_DS:
+ case BFD_RELOC_PPC64_PLTGOT16_DS:
+ case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
+ case BFD_RELOC_PPC_EMB_NADDR16:
+ case BFD_RELOC_PPC_EMB_NADDR16_LO:
+ case BFD_RELOC_PPC_EMB_NADDR16_HI:
+ case BFD_RELOC_PPC_EMB_NADDR16_HA:
+ case BFD_RELOC_PPC_EMB_SDAI16:
+ case BFD_RELOC_PPC_EMB_SDA2I16:
+ case BFD_RELOC_PPC_EMB_SDA2REL:
case BFD_RELOC_PPC_EMB_SDA21:
+ case BFD_RELOC_PPC_EMB_MRKREF:
+ case BFD_RELOC_PPC_EMB_RELSEC16:
+ case BFD_RELOC_PPC_EMB_RELST_LO:
+ case BFD_RELOC_PPC_EMB_RELST_HI:
+ case BFD_RELOC_PPC_EMB_RELST_HA:
+ case BFD_RELOC_PPC_EMB_BIT_FLD:
+ case BFD_RELOC_PPC_EMB_RELSDA:
+ case BFD_RELOC_PPC_VLE_SDA21:
+ case BFD_RELOC_PPC_VLE_SDA21_LO:
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
+ gas_assert (fixP->fx_addsy != NULL);
+ /* Fall thru */
+
+ case BFD_RELOC_PPC_TLS:
+ case BFD_RELOC_PPC_TLSGD:
+ case BFD_RELOC_PPC_TLSLD:
+ fieldval = 0;
if (fixP->fx_pcrel)
- abort ();
+ goto bad_pcrel;
+ break;
+#endif
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where
- + ((target_big_endian) ? 2 : 0),
- value, 2);
+ default:
break;
+ }
- case BFD_RELOC_8:
- if (fixP->fx_pcrel)
+#ifdef OBJ_ELF
+/* powerpc uses RELA style relocs, so if emitting a reloc the field
+ contents can stay at zero. */
+#define APPLY_RELOC fixP->fx_done
+#else
+#define APPLY_RELOC 1
+#endif
+ if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL)
+ {
+ /* Fetch the instruction, insert the fully resolved operand
+ value, and stuff the instruction back again. */
+ where = fixP->fx_frag->fr_literal + fixP->fx_where;
+ if (target_big_endian)
{
- /* This can occur if there is a bug in the input assembler, eg:
- ".byte <undefined_symbol> - ." */
- if (fixP->fx_addsy)
- as_bad (_("unable to handle reference to symbol %s"),
- S_GET_NAME (fixP->fx_addsy));
+ if (fixP->fx_size == 4)
+ insn = bfd_getb32 ((unsigned char *) where);
else
- as_bad (_("unable to resolve expression"));
- fixP->fx_done = 1;
+ insn = bfd_getb16 ((unsigned char *) where);
+ }
+ else
+ {
+ if (fixP->fx_size == 4)
+ insn = bfd_getl32 ((unsigned char *) where);
+ else
+ insn = bfd_getl16 ((unsigned char *) where);
+ }
+ insn = ppc_insert_operand (insn, operand, fieldval,
+ fixP->tc_fix_data.ppc_cpu,
+ fixP->fx_file, fixP->fx_line);
+ if (target_big_endian)
+ {
+ if (fixP->fx_size == 4)
+ bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
+ else
+ bfd_putb16 ((bfd_vma) insn, (unsigned char *) where);
}
else
- md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
- value, 1);
+ {
+ if (fixP->fx_size == 4)
+ bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
+ else
+ bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
+ }
+ }
+
+ if (fixP->fx_done)
+ /* Nothing else to do here. */
+ return;
+
+ gas_assert (fixP->fx_addsy != NULL);
+ if (fixP->fx_r_type == BFD_RELOC_UNUSED)
+ {
+ char *sfile;
+ unsigned int sline;
+
+ /* Use expr_symbol_where to see if this is an expression
+ symbol. */
+ if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unresolved expression that must be resolved"));
+ else
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unsupported relocation against %s"),
+ S_GET_NAME (fixP->fx_addsy));
+ fixP->fx_done = 1;
+ return;
+ }
+ }
+ else
+ {
+ int size = 0;
+ offsetT fieldval = value;
+
+ /* Handle relocs in data. */
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_CTOR:
+ if (ppc_obj64)
+ goto ctor64;
+ /* fall through */
+
+ case BFD_RELOC_32:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_32_PCREL;
+ /* fall through */
+
+ case BFD_RELOC_32_PCREL:
+ case BFD_RELOC_RVA:
+ size = 4;
break;
- case BFD_RELOC_24_PLT_PCREL:
- case BFD_RELOC_PPC_LOCAL24PC:
- if (!fixP->fx_pcrel && !fixP->fx_done)
- abort ();
+ case BFD_RELOC_64:
+ ctor64:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_64_PCREL;
+ /* fall through */
- if (fixP->fx_done)
- {
- char *where;
- unsigned long insn;
+ case BFD_RELOC_64_PCREL:
+ size = 8;
+ break;
- /* Fetch the instruction, insert the fully resolved operand
- value, and stuff the instruction back again. */
- where = fixP->fx_frag->fr_literal + fixP->fx_where;
- if (target_big_endian)
- insn = bfd_getb32 ((unsigned char *) where);
+ case BFD_RELOC_16:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_16_PCREL;
+ /* fall through */
+
+ case BFD_RELOC_16_PCREL:
+ size = 2;
+ break;
+
+ case BFD_RELOC_8:
+ if (fixP->fx_pcrel)
+ {
+#ifdef OBJ_ELF
+ bad_pcrel:
+#endif
+ if (fixP->fx_addsy)
+ {
+ char *sfile;
+ unsigned int sline;
+
+ /* Use expr_symbol_where to see if this is an
+ expression symbol. */
+ if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unresolved expression that must"
+ " be resolved"));
+ else
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("cannot emit PC relative %s relocation"
+ " against %s"),
+ bfd_get_reloc_code_name (fixP->fx_r_type),
+ S_GET_NAME (fixP->fx_addsy));
+ }
else
- insn = bfd_getl32 ((unsigned char *) where);
- if ((value & 3) != 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("must branch to an address a multiple of 4"));
- if ((offsetT) value < -0x40000000
- || (offsetT) value >= 0x40000000)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("@local or @plt branch destination is too far away, %ld bytes"),
- (long) value);
- insn = insn | (value & 0x03fffffc);
- if (target_big_endian)
- bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
- else
- bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
+ _("unable to resolve expression"));
+ fixP->fx_done = 1;
}
+ else
+ size = 1;
break;
case BFD_RELOC_VTABLE_INHERIT:
- fixP->fx_done = 0;
if (fixP->fx_addsy
&& !S_IS_DEFINED (fixP->fx_addsy)
&& !S_IS_WEAK (fixP->fx_addsy))
S_SET_WEAK (fixP->fx_addsy);
- break;
+ /* Fall thru */
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = 0;
break;
#ifdef OBJ_ELF
- /* Generated by reference to `sym@tocbase'. The sym is
- ignored by the linker. */
+ /* These can appear with @l etc. in data. */
+ case BFD_RELOC_LO16:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_LO16_PCREL;
+ case BFD_RELOC_LO16_PCREL:
+ size = 2;
+ break;
+
+ case BFD_RELOC_HI16:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_HI16_PCREL;
+ case BFD_RELOC_HI16_PCREL:
+ size = 2;
+ fieldval = PPC_HI (value);
+ break;
+
+ case BFD_RELOC_HI16_S:
+ if (fixP->fx_pcrel)
+ fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL;
+ case BFD_RELOC_HI16_S_PCREL:
+ size = 2;
+ fieldval = PPC_HA (value);
+ break;
+
+ case BFD_RELOC_PPC64_HIGHER:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ size = 2;
+ fieldval = PPC_HIGHER (value);
+ break;
+
+ case BFD_RELOC_PPC64_HIGHER_S:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ size = 2;
+ fieldval = PPC_HIGHERA (value);
+ break;
+
+ case BFD_RELOC_PPC64_HIGHEST:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ size = 2;
+ fieldval = PPC_HIGHEST (value);
+ break;
+
+ case BFD_RELOC_PPC64_HIGHEST_S:
+ if (fixP->fx_pcrel)
+ goto bad_pcrel;
+ size = 2;
+ fieldval = PPC_HIGHESTA (value);
+ break;
+
+ case BFD_RELOC_PPC_DTPMOD:
+ case BFD_RELOC_PPC_TPREL:
+ case BFD_RELOC_PPC_DTPREL:
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ break;
+
+ /* Just punt all of these to the linker. */
+ case BFD_RELOC_PPC_B16_BRTAKEN:
+ case BFD_RELOC_PPC_B16_BRNTAKEN:
+ case BFD_RELOC_16_GOTOFF:
+ case BFD_RELOC_LO16_GOTOFF:
+ case BFD_RELOC_HI16_GOTOFF:
+ case BFD_RELOC_HI16_S_GOTOFF:
+ case BFD_RELOC_LO16_PLTOFF:
+ case BFD_RELOC_HI16_PLTOFF:
+ case BFD_RELOC_HI16_S_PLTOFF:
+ case BFD_RELOC_PPC_COPY:
+ case BFD_RELOC_PPC_GLOB_DAT:
+ case BFD_RELOC_16_BASEREL:
+ case BFD_RELOC_LO16_BASEREL:
+ case BFD_RELOC_HI16_BASEREL:
+ case BFD_RELOC_HI16_S_BASEREL:
+ case BFD_RELOC_PPC_TLS:
+ case BFD_RELOC_PPC_DTPREL16_LO:
+ case BFD_RELOC_PPC_DTPREL16_HI:
+ case BFD_RELOC_PPC_DTPREL16_HA:
+ case BFD_RELOC_PPC_TPREL16_LO:
+ case BFD_RELOC_PPC_TPREL16_HI:
+ case BFD_RELOC_PPC_TPREL16_HA:
+ case BFD_RELOC_PPC_GOT_TLSGD16:
+ case BFD_RELOC_PPC_GOT_TLSGD16_LO:
+ case BFD_RELOC_PPC_GOT_TLSGD16_HI:
+ case BFD_RELOC_PPC_GOT_TLSGD16_HA:
+ case BFD_RELOC_PPC_GOT_TLSLD16:
+ case BFD_RELOC_PPC_GOT_TLSLD16_LO:
+ case BFD_RELOC_PPC_GOT_TLSLD16_HI:
+ case BFD_RELOC_PPC_GOT_TLSLD16_HA:
+ case BFD_RELOC_PPC_GOT_DTPREL16:
+ case BFD_RELOC_PPC_GOT_DTPREL16_LO:
+ case BFD_RELOC_PPC_GOT_DTPREL16_HI:
+ case BFD_RELOC_PPC_GOT_DTPREL16_HA:
+ case BFD_RELOC_PPC_GOT_TPREL16:
+ case BFD_RELOC_PPC_GOT_TPREL16_LO:
+ case BFD_RELOC_PPC_GOT_TPREL16_HI:
+ case BFD_RELOC_PPC_GOT_TPREL16_HA:
+ case BFD_RELOC_24_PLT_PCREL:
+ case BFD_RELOC_PPC_LOCAL24PC:
+ case BFD_RELOC_32_PLT_PCREL:
+ case BFD_RELOC_GPREL16:
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ case BFD_RELOC_PPC_EMB_NADDR32:
+ case BFD_RELOC_PPC_EMB_NADDR16:
+ case BFD_RELOC_PPC_EMB_NADDR16_LO:
+ case BFD_RELOC_PPC_EMB_NADDR16_HI:
+ case BFD_RELOC_PPC_EMB_NADDR16_HA:
+ case BFD_RELOC_PPC_EMB_SDAI16:
+ case BFD_RELOC_PPC_EMB_SDA2REL:
+ case BFD_RELOC_PPC_EMB_SDA2I16:
+ case BFD_RELOC_PPC_EMB_SDA21:
+ case BFD_RELOC_PPC_VLE_SDA21_LO:
+ case BFD_RELOC_PPC_EMB_MRKREF:
+ case BFD_RELOC_PPC_EMB_RELSEC16:
+ case BFD_RELOC_PPC_EMB_RELST_LO:
+ case BFD_RELOC_PPC_EMB_RELST_HI:
+ case BFD_RELOC_PPC_EMB_RELST_HA:
+ case BFD_RELOC_PPC_EMB_BIT_FLD:
+ case BFD_RELOC_PPC_EMB_RELSDA:
case BFD_RELOC_PPC64_TOC:
+ case BFD_RELOC_PPC_TOC16:
+ case BFD_RELOC_PPC64_TOC16_LO:
+ case BFD_RELOC_PPC64_TOC16_HI:
+ case BFD_RELOC_PPC64_TOC16_HA:
+ case BFD_RELOC_PPC64_DTPREL16_HIGHER:
+ case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
+ case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
+ case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
+ case BFD_RELOC_PPC64_TPREL16_HIGHER:
+ case BFD_RELOC_PPC64_TPREL16_HIGHERA:
+ case BFD_RELOC_PPC64_TPREL16_HIGHEST:
+ case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
fixP->fx_done = 0;
break;
#endif
+
+#ifdef OBJ_XCOFF
+ case BFD_RELOC_NONE:
+ break;
+#endif
+
default:
fprintf (stderr,
_("Gas failure, reloc value %d\n"), fixP->fx_r_type);
fflush (stderr);
abort ();
}
+
+ if (size && APPLY_RELOC)
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ fieldval, size);
}
#ifdef OBJ_ELF
+ ppc_elf_validate_fix (fixP, seg);
fixP->fx_addnumber = value;
/* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
extern int ppc_cie_data_alignment;
-#define DWARF2_LINE_MIN_INSN_LENGTH 4
+extern int ppc_dwarf2_line_min_insn_length;
+
+#define DWARF2_LINE_MIN_INSN_LENGTH ppc_dwarf2_line_min_insn_length
#define DWARF2_DEFAULT_RETURN_COLUMN 0x41
#define DWARF2_CIE_DATA_ALIGNMENT ppc_cie_data_alignment
emit_expr (&exp, sizeof_address);
}
-#if DWARF2_LINE_MIN_INSN_LENGTH > 1
static void scale_addr_delta (addressT *);
static void
scale_addr_delta (addressT *addr_delta)
{
static int printed_this = 0;
- if (*addr_delta % DWARF2_LINE_MIN_INSN_LENGTH != 0)
+ if (DWARF2_LINE_MIN_INSN_LENGTH > 1)
{
- if (!printed_this)
- as_bad("unaligned opcodes detected in executable segment");
- printed_this = 1;
+ if (*addr_delta % DWARF2_LINE_MIN_INSN_LENGTH != 0 && !printed_this)
+ {
+ as_bad("unaligned opcodes detected in executable segment");
+ printed_this = 1;
+ }
+ *addr_delta /= DWARF2_LINE_MIN_INSN_LENGTH;
}
- *addr_delta /= DWARF2_LINE_MIN_INSN_LENGTH;
}
-#else
-#define scale_addr_delta(A)
-#endif
/* Encode a pair of line and address skips as efficiently as possible.
Note that the line skip is signed, whereas the address skip is unsigned.
if ((ssize_t) want < 0)
as_fatal ("string buffer overflow");
#if GCC_VERSION >= 3004
- max = (size_t) 1 << (CHAR_BIT * sizeof (want) - __builtin_clzl (want));
+ max = (size_t) 1 << (CHAR_BIT * sizeof (want)
+ - (sizeof (want) <= sizeof (long)
+ ? __builtin_clzl ((long) want)
+ : __builtin_clzll ((long long) want)));
#else
max = 128;
while (want > max)
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2012-11-23 Alan Modra <amodra@gmail.com>
+ * gas/ppc/astest2.d: Pass -Mppc to objdump.
+
+ 2012-11-14 Ulrich Weigand <uweigand@de.ibm.com>
+ * gas/ppc/astest.d: Update for fixup changes.
+ * gas/ppc/astest64.d: Likewise.
+ * gas/ppc/astest2.d: Likewise.
+ * gas/ppc/astest2_64.d: Likewise.
+ * gas/ppc/test1elf32.d: Likewise.
+ * gas/ppc/test1elf64.d: Likewise.
+
+ 2012-10-29 Alan Modra <amodra@gmail.com>
+ * gas/cfi/cfi.exp: Remove redundant ppc test. Exclude
+ powerpc-pe targets from cfi-common-6 test.
+ * gas/cfi/cfi-ppc-1.d: Use objdump to handle pe.
+ * gas/cfi/cfi-ppc-1.s: Don't use .type and .size.
+ * gas/ppc/ppc.exp: Exclude various tests for powerpc-pe. Exclude
+ vle tests for le targets.
+ * gas/ppc/476.d, * gas/ppc/476.s: Update for le output. Use .text
+ rather than section directive with quotes.
+ * gas/ppc/a2.d, * gas/ppc/a2.s: Likewise.
+ * gas/ppc/altivec.d, * gas/ppc/altivec.s: Likewise.
+ * gas/ppc/altivec2.d: Likewise.
+ * gas/ppc/altivec_and_spe.d: Likewise.
+ * gas/ppc/astest.d: Likewise.
+ * gas/ppc/astest2.d: Likewise.
+ * gas/ppc/astest2_64.d: Likewise.
+ * gas/ppc/astest64.d: Likewise.
+ * gas/ppc/booke.d, * gas/ppc/booke.s: Likewise.
+ * gas/ppc/cell.d, * gas/ppc/cell.s: Likewise.
+ * gas/ppc/common.d, * gas/ppc/common.s: Likewise.
+ * gas/ppc/e500.d, * gas/ppc/e500.s: Likewise.
+ * gas/ppc/e500mc.d, * gas/ppc/e500mc.s: Likewise.
+ * gas/ppc/e500mc64_nop.d, * gas/ppc/e500mc64_nop.s: Likewise.
+ * gas/ppc/e5500_nop.d, * gas/ppc/e5500_nop.s: Likewise.
+ * gas/ppc/e6500.d, * gas/ppc/e6500.s: Likewise.
+ * gas/ppc/e6500_nop.d, * gas/ppc/e6500_nop.s: Likewise.
+ * gas/ppc/machine.d: Likewise.
+ * gas/ppc/power4.d, * gas/ppc/power4.s: Likewise.
+ * gas/ppc/power4_32.d, * gas/ppc/power4_32.s: Likewise.
+ * gas/ppc/power6.d, * gas/ppc/power6.s: Likewise.
+ * gas/ppc/power7.d, * gas/ppc/power7.s: Likewise.
+ * gas/ppc/ppc750ps.d, * gas/ppc/ppc750ps.s: Likewise.
+ * gas/ppc/regnames.d: Likewise.
+ * gas/ppc/simpshft.d: Likewise.
+ * gas/ppc/test1elf32.d: Likewise.
+ * gas/ppc/test1elf64.d: Likewise.
+ * gas/ppc/titan.d, * gas/ppc/titan.s: Likewise.
+ * gas/ppc/vle-reloc.s: Likewise.
+ * gas/ppc/vle-simple-1.s: Likewise.
+ * gas/ppc/vle-simple-2.s: Likewise.
+ * gas/ppc/vle-simple-3.s: Likewise.
+ * gas/ppc/vle-simple-4.s: Likewise.
+ * gas/ppc/vle-simple-5.s: Likewise.
+ * gas/ppc/vle-simple-6.s: Likewise.
+ * gas/ppc/vle.s: Likewise.
+ * gas/ppc/vsx.d, * gas/ppc/vsx.s: Likewise.
+
+ 2012-10-26 Alan Modra <amodra@gmail.com>
+ * gas/ppc/power4.s: Fix invalid lq offsets.
+ * gas/ppc/power4.d: Update.
+
+ 2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
+ * gas/ppc/altivec.s <vcfpsxws>: Fix opcode spelling.
+
+ 2012-10-05 Peter Bergner <bergner@vnet.ibm.com>
+ * gas/ppc/power7.d: Add tests for mfppr, mfppr32, mtppr and mtppr32.
+ * gas/ppc/power7.s: Likewise.
+ * gas/ppc/altivec.d: Add tests for all legacy Altivec instructions.
+ * gas/ppc/altivec.s: Likewise.
+ * gas/ppc/altivec2.d: New test file.
+ * gas/ppc/altivec2.s: Likewise.
+ * gas/ppc/ppc.exp: Run it.
+
+ 2012-08-01 James Lemke <jwlemke@codesourcery.com>
+ * gas/cfi/cfi-ppc-1.d: Allow for code alignment of 2 or 4.
+
2012-12-20 Greta Yorsh <Greta.Yorsh@arm.com>
* gas/arm/srs-t2.s: Add tests for missing srs modes.
-#readelf: -wf
+#objdump: -Wf
#name: CFI on ppc
#as: -a32
+.*
+
Contents of the .eh_frame section:
00000000 00000010 00000000 CIE
Version: 1
Augmentation: "zR"
- Code alignment factor: 4
+ Code alignment factor: [24]
Data alignment factor: -4
Return address column: 65
- Augmentation data: 1b
+ Augmentation data: [01]b
DW_CFA_def_cfa: r1 ofs 0
.text
.align 2
.globl foo
- .type foo, @function
foo:
.cfi_startproc
stwu 1,-48(1)
addi 1,1,48
blr
.cfi_endproc
- .size foo, .-foo
run_dump_test "cfi-alpha-2"
run_dump_test "cfi-alpha-3"
-} elseif { [istarget ppc*-*-*] || [istarget powerpc*-*-*] } then {
+} elseif { [istarget powerpc*-*-*] } then {
run_dump_test "cfi-ppc-1"
} elseif { [istarget s390*-*-*] } then {
# This test uses .subsection/.previous which are elf-specific.
run_dump_test "cfi-common-5"
}
- # MIPS doesn't support PC relative cfi directives.
- if { ![istarget "mips*-*"] } then {
+ # Some targets don't support PC relative cfi directives
+ if { ![istarget "mips*-*"] &&
+ !([istarget powerpc*-*-*] && [is_pecoff_format]) } then {
run_dump_test "cfi-common-6"
}
run_dump_test "cfi-common-7"
#as: -a32 -m476
#name: PowerPC 476 instructions
-.*: +file format elf32-powerpc.*
+.*
Disassembly of section \.text:
0+00 <ppc476>:
- 0: 7c 64 2a 14 add r3,r4,r5
- 4: 7c 64 2a 15 add\. r3,r4,r5
- 8: 7c 64 28 14 addc r3,r4,r5
- c: 7c 64 28 15 addc\. r3,r4,r5
- 10: 7c 64 2c 14 addco r3,r4,r5
- 14: 7c 64 2c 15 addco\. r3,r4,r5
- 18: 7c 64 29 14 adde r3,r4,r5
- 1c: 7c 64 29 15 adde\. r3,r4,r5
- 20: 7c 64 2d 14 addeo r3,r4,r5
- 24: 7c 64 2d 15 addeo\. r3,r4,r5
- 28: 38 64 ff 80 addi r3,r4,-128
- 2c: 30 64 ff 80 addic r3,r4,-128
- 30: 34 64 ff 80 addic\. r3,r4,-128
- 34: 3c 64 ff 80 addis r3,r4,-128
- 38: 7c 64 01 d4 addme r3,r4
- 3c: 7c 64 01 d5 addme\. r3,r4
- 40: 7c 64 05 d4 addmeo r3,r4
- 44: 7c 64 05 d5 addmeo\. r3,r4
- 48: 7c 64 2e 14 addo r3,r4,r5
- 4c: 7c 64 2e 15 addo\. r3,r4,r5
- 50: 7c 64 01 94 addze r3,r4
- 54: 7c 64 01 95 addze\. r3,r4
- 58: 7c 64 05 94 addzeo r3,r4
- 5c: 7c 64 05 95 addzeo\. r3,r4
- 60: 7c 83 28 38 and r3,r4,r5
- 64: 7c 83 28 39 and\. r3,r4,r5
- 68: 7d cd 78 78 andc r13,r14,r15
- 6c: 7e 30 90 79 andc\. r16,r17,r18
- 70: 70 83 de ad andi\. r3,r4,57005
- 74: 74 83 de ad andis\. r3,r4,57005
- 78:
48 00 00 02 ba 0 <ppc476>
- 7c:
40 01 00 00 bdnzf gt,7c <ppc476\+0x7c>
- 80:
40 85 00 02 blea cr1,0 <ppc476>
- 84: 4d 80 04 20 bltctr
- 88: 4c 8a 04 20 bnectr cr2
- 8c: 4c 86 04 20 bnectr cr1
- 90: 4c 86 04 20 bnectr cr1
- 94: 4d 80 04 21 bltctrl
- 98: 4c 8a 04 21 bnectrl cr2
- 9c: 4c 86 04 21 bnectrl cr1
- a0: 4c 86 04 21 bnectrl cr1
- a4:
40 43 00 01 bdzfl so,a4 <ppc476\+0xa4>
- a8: 4d 80 00 20 bltlr
- ac: 4c 8a 00 20 bnelr cr2
- b0: 4c 86 00 20 bnelr cr1
- b4: 4c 86 00 20 bnelr cr1
- b8: 4d 80 00 21 bltlrl
- bc: 4c 8a 00 21 bnelrl cr2
- c0: 4c 86 00 21 bnelrl cr1
- c4: 4c 86 00 21 bnelrl cr1
- c8:
48 00 00 00 b c8 <ppc476\+0xc8>
- cc:
48 00 00 01 bl cc <ppc476\+0xcc>
- d0: 54 83 00 36 rlwinm r3,r4,0,0,27
- d4: 7c 03 20 00 cmpw r3,r4
- d8: 7f 83 20 00 cmpw cr7,r3,r4
- dc: 7c 83 2b f8 cmpb r3,r4,r5
- e0: 7c 83 2b f8 cmpb r3,r4,r5
- e4: 2c 03 ff 59 cmpwi r3,-167
- e8: 2f 83 ff 59 cmpwi cr7,r3,-167
- ec: 7c 03 20 40 cmplw r3,r4
- f0: 7f 83 20 40 cmplw cr7,r3,r4
- f4: 28 03 00 a7 cmplwi r3,167
- f8: 2b 83 00 a7 cmplwi cr7,r3,167
- fc: 7c 03 20 40 cmplw r3,r4
- 100: 28 03 00 a7 cmplwi r3,167
- 104: 7c 03 20 00 cmpw r3,r4
- 108: 2c 03 ff 59 cmpwi r3,-167
- 10c: 7d 6a 00 34 cntlzw r10,r11
- 110: 7d 6a 00 35 cntlzw\. r10,r11
- 114: 4c 85 32 02 crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq
- 118: 4c 64 29 02 crandc so,4\*cr1\+lt,4\*cr1\+gt
- 11c: 4c e0 0a 42 creqv 4\*cr1\+so,lt,gt
- 120: 4c 22 19 c2 crnand gt,eq,so
- 124: 4c 01 10 42 crnor lt,gt,eq
- 128: 4c a6 3b 82 cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so
- 12c: 4c 43 23 42 crorc eq,so,4\*cr1\+lt
- 130: 4c c7 01 82 crxor 4\*cr1\+eq,4\*cr1\+so,lt
- 134: 7c 09 55 ec dcba r9,r10
- 138: 7c 06 38 ac dcbf r6,r7
- 13c: 7c 06 38 ac dcbf r6,r7
- 140: 7c 06 3b ac dcbi r6,r7
- 144: 7c 85 33 0c dcblc 4,r5,r6
- 148: 7c 06 38 6c dcbst r6,r7
- 14c: 7c c0 2a 2c dcbt 0,r5,6
- 150: 7c 05 32 2c dcbt r5,r6
- 154: 7c c8 2a 2c dcbt r8,r5,6
- 158: 7c e8 49 4c dcbtls 7,r8,r9
- 15c: 7c e0 31 ec dcbtst 0,r6,7
- 160: 7c 06 39 ec dcbtst r6,r7
- 164: 7c e9 31 ec dcbtst r9,r6,7
- 168: 7d 4b 61 0c dcbtstls 10,r11,r12
- 16c: 7c 01 17 ec dcbz r1,r2
- 170: 7c 05 37 ec dcbz r5,r6
- 174: 7c 00 03 8c dccci
- 178: 7c 00 03 8c dccci
- 17c: 7c 00 03 8c dccci
- 180: 7c 20 03 8c dci 1
- 184: 7d 4b 63 d6 divw r10,r11,r12
- 188: 7d 6c 6b d7 divw\. r11,r12,r13
- 18c: 7d 4b 67 d6 divwo r10,r11,r12
- 190: 7d 6c 6f d7 divwo\. r11,r12,r13
- 194: 7d 4b 63 96 divwu r10,r11,r12
- 198: 7d 6c 6b 97 divwu\. r11,r12,r13
- 19c: 7d 4b 67 96 divwuo r10,r11,r12
- 1a0: 7d 6c 6f 97 divwuo\. r11,r12,r13
- 1a4: 7c 83 28 9c dlmzb r3,r4,r5
- 1a8: 7c 83 28 9d dlmzb\. r3,r4,r5
- 1ac: 7d 6a 62 38 eqv r10,r11,r12
- 1b0: 7d 6a 62 39 eqv\. r10,r11,r12
- 1b4: 54 83 20 26 rlwinm r3,r4,4,0,19
- 1b8: 7c 83 07 74 extsb r3,r4
- 1bc: 7c 83 07 75 extsb\. r3,r4
- 1c0: 7c 83 07 34 extsh r3,r4
- 1c4: 7c 83 07 35 extsh\. r3,r4
- 1c8: fe a0 fa 10 fabs f21,f31
- 1cc: fe a0 fa 11 fabs\. f21,f31
- 1d0: fd 4b 60 2a fadd f10,f11,f12
- 1d4: fd 4b 60 2b fadd\. f10,f11,f12
- 1d8: ed 4b 60 2a fadds f10,f11,f12
- 1dc: ed 4b 60 2b fadds\. f10,f11,f12
- 1e0: fd 40 5e 9c fcfid f10,f11
- 1e4: fd 40 5e 9d fcfid\. f10,f11
- 1e8: fd 8a 58 40 fcmpo cr3,f10,f11
- 1ec: fd 84 28 00 fcmpu cr3,f4,f5
- 1f0: fd 4b 60 10 fcpsgn f10,f11,f12
- 1f4: fd 4b 60 11 fcpsgn\. f10,f11,f12
- 1f8: fd 40 5e 5c fctid f10,f11
- 1fc: fd 40 5e 5d fctid\. f10,f11
- 200: fd 40 5e 5e fctidz f10,f11
- 204: fd 40 5e 5f fctidz\. f10,f11
- 208: fd 40 58 1c fctiw f10,f11
- 20c: fd 40 58 1d fctiw\. f10,f11
- 210: fd 40 58 1e fctiwz f10,f11
- 214: fd 40 58 1f fctiwz\. f10,f11
- 218: fd 4b 60 24 fdiv f10,f11,f12
- 21c: fd 4b 60 25 fdiv\. f10,f11,f12
- 220: ed 4b 60 24 fdivs f10,f11,f12
- 224: ed 4b 60 25 fdivs\. f10,f11,f12
- 228: fd 4b 6b 3a fmadd f10,f11,f12,f13
- 22c: fd 4b 6b 3b fmadd\. f10,f11,f12,f13
- 230: ed 4b 6b 3a fmadds f10,f11,f12,f13
- 234: ed 4b 6b 3b fmadds\. f10,f11,f12,f13
- 238: fc 60 20 90 fmr f3,f4
- 23c: fc 60 20 91 fmr\. f3,f4
- 240: fd 4b 6b 38 fmsub f10,f11,f12,f13
- 244: fd 4b 6b 39 fmsub\. f10,f11,f12,f13
- 248: ed 4b 6b 38 fmsubs f10,f11,f12,f13
- 24c: ed 4b 6b 39 fmsubs\. f10,f11,f12,f13
- 250: fd 4b 03 32 fmul f10,f11,f12
- 254: fd 4b 03 33 fmul\. f10,f11,f12
- 258: ed 4b 03 32 fmuls f10,f11,f12
- 25c: ed 4b 03 33 fmuls\. f10,f11,f12
- 260: fe 80 f1 10 fnabs f20,f30
- 264: fe 80 f1 11 fnabs\. f20,f30
- 268: fc 60 20 50 fneg f3,f4
- 26c: fc 60 20 51 fneg\. f3,f4
- 270: fd 4b 6b 3e fnmadd f10,f11,f12,f13
- 274: fd 4b 6b 3f fnmadd\. f10,f11,f12,f13
- 278: ed 4b 6b 3e fnmadds f10,f11,f12,f13
- 27c: ed 4b 6b 3f fnmadds\. f10,f11,f12,f13
- 280: fd 4b 6b 3c fnmsub f10,f11,f12,f13
- 284: fd 4b 6b 3d fnmsub\. f10,f11,f12,f13
- 288: ed 4b 6b 3c fnmsubs f10,f11,f12,f13
- 28c: ed 4b 6b 3d fnmsubs\. f10,f11,f12,f13
- 290: fd c0 78 30 fre f14,f15
- 294: fd c0 78 31 fre\. f14,f15
- 298: ed c0 78 30 fres f14,f15
- 29c: ed c0 78 31 fres\. f14,f15
- 2a0: fd 40 5b d0 frim f10,f11
- 2a4: fd 40 5b d1 frim\. f10,f11
- 2a8: fd 40 5b 10 frin f10,f11
- 2ac: fd 40 5b 11 frin\. f10,f11
- 2b0: fd 40 5b 90 frip f10,f11
- 2b4: fd 40 5b 91 frip\. f10,f11
- 2b8: fd 40 5b 50 friz f10,f11
- 2bc: fd 40 5b 51 friz\. f10,f11
- 2c0: fc c0 38 18 frsp f6,f7
- 2c4: fd 00 48 19 frsp\. f8,f9
- 2c8: fd c0 78 34 frsqrte f14,f15
- 2cc: fd c0 78 35 frsqrte\. f14,f15
- 2d0: ed c0 78 34 frsqrtes f14,f15
- 2d4: ed c0 78 35 frsqrtes\. f14,f15
- 2d8: fd 4b 6b 2e fsel f10,f11,f12,f13
- 2dc: fd 4b 6b 2f fsel\. f10,f11,f12,f13
- 2e0: fd 40 58 2c fsqrt f10,f11
- 2e4: fd 40 58 2d fsqrt\. f10,f11
- 2e8: ed 40 58 2c fsqrts f10,f11
- 2ec: ed 40 58 2d fsqrts\. f10,f11
- 2f0: fd 4b 60 28 fsub f10,f11,f12
- 2f4: fd 4b 60 29 fsub\. f10,f11,f12
- 2f8: ed 4b 60 28 fsubs f10,f11,f12
- 2fc: ed 4b 60 29 fsubs\. f10,f11,f12
- 300: 7c 03 27 ac icbi r3,r4
- 304: 7e 11 91 cc icblc 16,r17,r18
- 308: 7c a8 48 2c icbt 5,r8,r9
- 30c: 7d ae 7b cc icbtls 13,r14,r15
- 310: 7c 00 07 8c iccci
- 314: 7c 00 07 8c iccci
- 318: 7c 00 07 8c iccci
- 31c: 7c 20 07 8c ici 1
- 320: 7c 03 27 cc icread r3,r4
- 324: 50 83 65 36 rlwimi r3,r4,12,20,27
- 328: 7c 43 27 1e isel r2,r3,r4,28
- 32c: 4c 00 01 2c isync
- 330: 89 21 00 00 lbz r9,0\(r1\)
- 334: 8d 41 00 01 lbzu r10,1\(r1\)
- 338: 7e 95 b0 ee lbzux r20,r21,r22
- 33c: 7c 64 28 ae lbzx r3,r4,r5
- 340: ca a1 00 08 lfd f21,8\(r1\)
- 344: ce c1 00 10 lfdu f22,16\(r1\)
- 348: 7e 95 b4 ee lfdux f20,r21,r22
- 34c: 7d ae 7c ae lfdx f13,r14,r15
- 350: 7d 43 26 ae lfiwax f10,r3,r4
- 354: c2 61 00 00 lfs f19,0\(r1\)
- 358: c6 81 00 04 lfsu f20,4\(r1\)
- 35c: 7d 4b 64 6e lfsux f10,r11,r12
- 360: 7d 4b 64 2e lfsx f10,r11,r12
- 364: a9 e1 00 06 lha r15,6\(r1\)
- 368: ae 01 00 08 lhau r16,8\(r1\)
- 36c: 7d 2a 5a ee lhaux r9,r10,r11
- 370: 7d 2a 5a ae lhax r9,r10,r11
- 374: 7c 64 2e 2c lhbrx r3,r4,r5
- 378: a1 a1 00 00 lhz r13,0\(r1\)
- 37c: a5 c1 00 02 lhzu r14,2\(r1\)
- 380: 7e 96 c2 6e lhzux r20,r22,r24
- 384: 7e f8 ca 2e lhzx r23,r24,r25
- 388: b8 61 ff f0 lmw r3,-16\(r1\)
- 38c: 7c a4 84 aa lswi r5,r4,16
- 390: 7c 64 2c 2a lswx r3,r4,r5
- 394: 7c 64 28 28 lwarx r3,r4,r5
- 398: 7c 64 28 28 lwarx r3,r4,r5
- 39c: 7c 64 28 29 lwarx r3,r4,r5,1
- 3a0: 7c 64 2c 2c lwbrx r3,r4,r5
- 3a4: 80 c7 00 00 lwz r6,0\(r7\)
- 3a8: 84 61 00 10 lwzu r3,16\(r1\)
- 3ac: 7c 64 28 6e lwzux r3,r4,r5
- 3b0: 7c 64 28 2e lwzx r3,r4,r5
- 3b4: 10 64 29 58 macchw r3,r4,r5
- 3b8: 10 64 29 59 macchw\. r3,r4,r5
- 3bc: 10 64 2d 58 macchwo r3,r4,r5
- 3c0: 10 64 2d 59 macchwo\. r3,r4,r5
- 3c4: 10 64 29 d8 macchws r3,r4,r5
- 3c8: 10 64 29 d9 macchws\. r3,r4,r5
- 3cc: 10 64 2d d8 macchwso r3,r4,r5
- 3d0: 10 64 2d d9 macchwso\. r3,r4,r5
- 3d4: 10 64 29 98 macchwsu r3,r4,r5
- 3d8: 10 64 29 99 macchwsu\. r3,r4,r5
- 3dc: 10 64 2d 98 macchwsuo r3,r4,r5
- 3e0: 10 64 2d 99 macchwsuo\. r3,r4,r5
- 3e4: 10 64 29 18 macchwu r3,r4,r5
- 3e8: 10 64 29 19 macchwu\. r3,r4,r5
- 3ec: 10 64 2d 18 macchwuo r3,r4,r5
- 3f0: 10 64 2d 19 macchwuo\. r3,r4,r5
- 3f4: 10 64 28 58 machhw r3,r4,r5
- 3f8: 10 64 28 59 machhw\. r3,r4,r5
- 3fc: 10 64 2c 58 machhwo r3,r4,r5
- 400: 10 64 2c 59 machhwo\. r3,r4,r5
- 404: 10 64 28 d8 machhws r3,r4,r5
- 408: 10 64 28 d9 machhws\. r3,r4,r5
- 40c: 10 64 2c d8 machhwso r3,r4,r5
- 410: 10 64 2c d9 machhwso\. r3,r4,r5
- 414: 10 64 28 98 machhwsu r3,r4,r5
- 418: 10 64 28 99 machhwsu\. r3,r4,r5
- 41c: 10 64 2c 98 machhwsuo r3,r4,r5
- 420: 10 64 2c 99 machhwsuo\. r3,r4,r5
- 424: 10 64 28 18 machhwu r3,r4,r5
- 428: 10 64 28 19 machhwu\. r3,r4,r5
- 42c: 10 64 2c 18 machhwuo r3,r4,r5
- 430: 10 64 2c 19 machhwuo\. r3,r4,r5
- 434: 10 64 2b 58 maclhw r3,r4,r5
- 438: 10 64 2b 59 maclhw\. r3,r4,r5
- 43c: 10 64 2f 58 maclhwo r3,r4,r5
- 440: 10 64 2f 59 maclhwo\. r3,r4,r5
- 444: 10 64 2b d8 maclhws r3,r4,r5
- 448: 10 64 2b d9 maclhws\. r3,r4,r5
- 44c: 10 64 2f d8 maclhwso r3,r4,r5
- 450: 10 64 2f d9 maclhwso\. r3,r4,r5
- 454: 10 64 2b 98 maclhwsu r3,r4,r5
- 458: 10 64 2b 99 maclhwsu\. r3,r4,r5
- 45c: 10 64 2f 98 maclhwsuo r3,r4,r5
- 460: 10 64 2f 99 maclhwsuo\. r3,r4,r5
- 464: 10 64 2b 18 maclhwu r3,r4,r5
- 468: 10 64 2b 19 maclhwu\. r3,r4,r5
- 46c: 10 64 2f 18 maclhwuo r3,r4,r5
- 470: 10 64 2f 19 maclhwuo\. r3,r4,r5
- 474: 7c 00 06 ac mbar
- 478: 7c 00 06 ac mbar
- 47c: 7c 20 06 ac mbar 1
- 480: 4c 04 00 00 mcrf cr0,cr1
- 484: fd 90 00 80 mcrfs cr3,cr4
- 488: 7d 80 04 00 mcrxr cr3
- 48c: 7c 60 00 26 mfcr r3
- 490: 7c 60 00 26 mfcr r3
- 494: 7c aa 3a 86 mfdcr r5,234
- 498: 7c 64 02 46 mfdcrux r3,r4
- 49c: 7c 85 02 06 mfdcrx r4,r5
- 4a0: ff c0 04 8e mffs f30
- 4a4: ff e0 04 8f mffs\. f31
- 4a8: 7e 60 00 a6 mfmsr r19
- 4ac: 7c 78 00 26 mfocrf r3,128
- 4b0: 7c 60 22 a6 mfspr r3,128
- 4b4: 7c 6c 42 e6 mftbl r3
- 4b8: 7c 00 04 ac msync
- 4bc: 7c 78 01 20 mtocrf 128,r3
- 4c0: 7c 6f f1 20 mtcr r3
- 4c4: 7d 10 6b 86 mtdcr 432,r8
- 4c8: 7c 83 03 46 mtdcrux r3,r4
- 4cc: 7c e6 03 06 mtdcrx r6,r7
- 4d0: fc 60 00 8c mtfsb0 so
- 4d4: fc 60 00 8d mtfsb0\. so
- 4d8: fc 60 00 4c mtfsb1 so
- 4dc: fc 60 00 4d mtfsb1\. so
- 4e0: fc 0c 55 8e mtfsf 6,f10
- 4e4: fc 0c 55 8e mtfsf 6,f10
- 4e8: fc 0d 55 8e mtfsf 6,f10,0,1
- 4ec: fe 0c 55 8e mtfsf 6,f10,1,0
- 4f0: fc 0c 5d 8f mtfsf\. 6,f11
- 4f4: fc 0c 5d 8f mtfsf\. 6,f11
- 4f8: fc 0d 5d 8f mtfsf\. 6,f11,0,1
- 4fc: fe 0c 5d 8f mtfsf\. 6,f11,1,0
- 500: ff 00 01 0c mtfsfi 6,0
- 504: ff 00 01 0c mtfsfi 6,0
- 508: ff 00 01 0c mtfsfi 6,0
- 50c: ff 01 01 0c mtfsfi 6,0,1
- 510: ff 00 f1 0d mtfsfi\. 6,15
- 514: ff 00 f1 0d mtfsfi\. 6,15
- 518: ff 00 f1 0d mtfsfi\. 6,15
- 51c: ff 01 f1 0d mtfsfi\. 6,15,1
- 520: 7d 40 01 24 mtmsr r10
- 524: 7c 78 01 20 mtocrf 128,r3
- 528: 7c 60 23 a6 mtspr 128,r3
- 52c: 10 64 29 50 mulchw r3,r4,r5
- 530: 10 64 29 51 mulchw\. r3,r4,r5
- 534: 10 64 29 10 mulchwu r3,r4,r5
- 538: 10 64 29 11 mulchwu\. r3,r4,r5
- 53c: 10 64 28 50 mulhhw r3,r4,r5
- 540: 10 64 28 51 mulhhw\. r3,r4,r5
- 544: 10 64 28 10 mulhhwu r3,r4,r5
- 548: 10 64 28 11 mulhhwu\. r3,r4,r5
- 54c: 7c 64 28 96 mulhw r3,r4,r5
- 550: 7c 64 28 97 mulhw\. r3,r4,r5
- 554: 7c 64 28 16 mulhwu r3,r4,r5
- 558: 7c 64 28 17 mulhwu\. r3,r4,r5
- 55c: 10 64 2b 50 mullhw r3,r4,r5
- 560: 10 64 2b 51 mullhw\. r3,r4,r5
- 564: 10 64 2b 10 mullhwu r3,r4,r5
- 568: 10 64 2b 11 mullhwu\. r3,r4,r5
- 56c: 1c 64 00 05 mulli r3,r4,5
- 570: 7c 64 29 d6 mullw r3,r4,r5
- 574: 7c 64 29 d7 mullw\. r3,r4,r5
- 578: 7c 64 2d d6 mullwo r3,r4,r5
- 57c: 7c 64 2d d7 mullwo\. r3,r4,r5
- 580: 7f bc f3 b8 nand r28,r29,r30
- 584: 7f bc f3 b9 nand\. r28,r29,r30
- 588: 7c 64 00 d0 neg r3,r4
- 58c: 7c 64 00 d1 neg\. r3,r4
- 590: 7e 11 04 d0 nego r16,r17
- 594: 7e 53 04 d1 nego\. r18,r19
- 598: 10 64 29 5c nmacchw r3,r4,r5
- 59c: 10 64 29 5d nmacchw\. r3,r4,r5
- 5a0: 10 64 2d 5c nmacchwo r3,r4,r5
- 5a4: 10 64 2d 5d nmacchwo\. r3,r4,r5
- 5a8: 10 64 29 dc nmacchws r3,r4,r5
- 5ac: 10 64 29 dd nmacchws\. r3,r4,r5
- 5b0: 10 64 2d dc nmacchwso r3,r4,r5
- 5b4: 10 64 2d dd nmacchwso\. r3,r4,r5
- 5b8: 10 64 28 5c nmachhw r3,r4,r5
- 5bc: 10 64 28 5d nmachhw\. r3,r4,r5
- 5c0: 10 64 2c 5c nmachhwo r3,r4,r5
- 5c4: 10 64 2c 5d nmachhwo\. r3,r4,r5
- 5c8: 10 64 28 dc nmachhws r3,r4,r5
- 5cc: 10 64 28 dd nmachhws\. r3,r4,r5
- 5d0: 10 64 2c dc nmachhwso r3,r4,r5
- 5d4: 10 64 2c dd nmachhwso\. r3,r4,r5
- 5d8: 10 64 2b 5c nmaclhw r3,r4,r5
- 5dc: 10 64 2b 5d nmaclhw\. r3,r4,r5
- 5e0: 10 64 2f 5c nmaclhwo r3,r4,r5
- 5e4: 10 64 2f 5d nmaclhwo\. r3,r4,r5
- 5e8: 10 64 2b dc nmaclhws r3,r4,r5
- 5ec: 10 64 2b dd nmaclhws\. r3,r4,r5
- 5f0: 10 64 2f dc nmaclhwso r3,r4,r5
- 5f4: 10 64 2f dd nmaclhwso\. r3,r4,r5
- 5f8: 7e b4 b0 f8 nor r20,r21,r22
- 5fc: 7e b4 b0 f9 nor\. r20,r21,r22
- 600: 7c 40 23 78 or r0,r2,r4
- 604: 7d cc 83 79 or\. r12,r14,r16
- 608: 7e 0f 8b 38 orc r15,r16,r17
- 60c: 7e 72 a3 39 orc\. r18,r19,r20
- 610: 60 21 00 00 ori r1,r1,0
- 614: 64 83 de ad oris r3,r4,57005
- 618: 7c 83 00 f4 popcntb r3,r4
- 61c: 7c 83 01 34 prtyw r3,r4
- 620: 4c 00 00 66 rfci
- 624: 4c 00 00 64 rfi
- 628: 4c 00 00 4c rfmci
- 62c: 50 83 65 36 rlwimi r3,r4,12,20,27
- 630: 50 83 65 37 rlwimi\. r3,r4,12,20,27
- 634: 54 83 00 36 rlwinm r3,r4,0,0,27
- 638: 54 83 d1 be rlwinm r3,r4,26,6,31
- 63c: 54 83 20 26 rlwinm r3,r4,4,0,19
- 640: 54 83 00 37 rlwinm\. r3,r4,0,0,27
- 644: 5c 83 28 3e rotlw r3,r4,r5
- 648: 5c 83 28 3f rotlw\. r3,r4,r5
- 64c: 5c 83 28 3e rotlw r3,r4,r5
- 650: 5c 83 28 3f rotlw\. r3,r4,r5
- 654: 44 00 00 02 sc
- 658: 7c 83 28 30 slw r3,r4,r5
- 65c: 7c 83 28 31 slw\. r3,r4,r5
- 660: 7c 83 2e 30 sraw r3,r4,r5
- 664: 7c 83 2e 31 sraw\. r3,r4,r5
- 668: 7c 83 86 70 srawi r3,r4,16
- 66c: 7c 83 86 71 srawi\. r3,r4,16
- 670: 7c 83 2c 30 srw r3,r4,r5
- 674: 7c 83 2c 31 srw\. r3,r4,r5
- 678: 54 83 d1 be rlwinm r3,r4,26,6,31
- 67c: 99 61 00 02 stb r11,2\(r1\)
- 680: 9d 81 00 03 stbu r12,3\(r1\)
- 684: 7d ae 79 ee stbux r13,r14,r15
- 688: 7c 64 29 ae stbx r3,r4,r5
- 68c: db 21 00 20 stfd f25,32\(r1\)
- 690: df 41 00 28 stfdu f26,40\(r1\)
- 694: 7c 01 15 ee stfdux f0,r1,r2
- 698: 7f be fd ae stfdx f29,r30,r31
- 69c: 7d 43 27 ae stfiwx f10,r3,r4
- 6a0: d2 e1 00 14 stfs f23,20\(r1\)
- 6a4: d7 01 00 18 stfsu f24,24\(r1\)
- 6a8: 7f 5b e5 6e stfsux f26,r27,r28
- 6ac: 7e f8 cd 2e stfsx f23,r24,r25
- 6b0: b2 21 00 0a sth r17,10\(r1\)
- 6b4: 7c c7 47 2c sthbrx r6,r7,r8
- 6b8: b6 41 00 0c sthu r18,12\(r1\)
- 6bc: 7e b6 bb 6e sthux r21,r22,r23
- 6c0: 7d 8d 73 2e sthx r12,r13,r14
- 6c4: bc c1 ff f0 stmw r6,-16\(r1\)
- 6c8: 7c 64 85 aa stswi r3,r4,16
- 6cc: 7c 64 2d 2a stswx r3,r4,r5
- 6d0: 90 c7 ff f0 stw r6,-16\(r7\)
- 6d4: 7c 64 2d 2c stwbrx r3,r4,r5
- 6d8: 7c 64 29 2d stwcx\. r3,r4,r5
- 6dc: 94 61 00 10 stwu r3,16\(r1\)
- 6e0: 7c 64 29 6e stwux r3,r4,r5
- 6e4: 7c 64 29 2e stwx r3,r4,r5
- 6e8: 7c 64 28 50 subf r3,r4,r5
- 6ec: 7c 64 28 51 subf\. r3,r4,r5
- 6f0: 7c 64 28 10 subfc r3,r4,r5
- 6f4: 7c 64 28 11 subfc\. r3,r4,r5
- 6f8: 7c 64 2c 10 subfco r3,r4,r5
- 6fc: 7c 64 2c 11 subfco\. r3,r4,r5
- 700: 7c 64 29 10 subfe r3,r4,r5
- 704: 7c 64 29 11 subfe\. r3,r4,r5
- 708: 7c 64 2d 10 subfeo r3,r4,r5
- 70c: 7c 64 2d 11 subfeo\. r3,r4,r5
- 710: 20 64 00 05 subfic r3,r4,5
- 714: 7c 64 01 d0 subfme r3,r4
- 718: 7c 64 01 d1 subfme\. r3,r4
- 71c: 7c 64 05 d0 subfmeo r3,r4
- 720: 7c 64 05 d1 subfmeo\. r3,r4
- 724: 7c 64 2c 50 subfo r3,r4,r5
- 728: 7c 64 2c 51 subfo\. r3,r4,r5
- 72c: 7c 64 01 90 subfze r3,r4
- 730: 7c 64 01 91 subfze\. r3,r4
- 734: 7c 64 05 90 subfzeo r3,r4
- 738: 7c 64 05 91 subfzeo\. r3,r4
- 73c: 7c 07 46 24 tlbivax r7,r8
- 740: 7c 22 3f 64 tlbre r1,r2,7
- 744: 7c 0b 67 24 tlbsx r11,r12
- 748: 7d 8d 77 24 tlbsx r12,r13,r14
- 74c: 7d 8d 77 25 tlbsx\. r12,r13,r14
- 750: 7c 00 04 6c tlbsync
- 754: 7c 00 07 a4 tlbwe
- 758: 7c 00 07 a4 tlbwe
- 75c: 7c 21 0f a4 tlbwe r1,r1,1
- 760: 7f e0 00 08 trap
- 764: 7f e0 00 08 trap
- 768: 7c 83 20 08 tweq r3,r4
- 76c: 7c a3 20 08 twlge r3,r4
- 770: 7c 83 20 08 tweq r3,r4
- 774: 0d 03 00 0f twgti r3,15
- 778: 0c c3 00 0f twllei r3,15
- 77c: 0d 03 00 0f twgti r3,15
- 780: 7c a3 20 08 twlge r3,r4
- 784: 0c c3 00 0f twllei r3,15
- 788: 7c 60 01 06 wrtee r3
- 78c: 7c 00 81 46 wrteei 1
- 790: 7f dd fa 78 xor r29,r30,r31
- 794: 7f dd fa 79 xor\. r29,r30,r31
- 798: 68 83 de ad xori r3,r4,57005
- 79c: 6c 83 de ad xoris r3,r4,57005
+ 0: (7c 64 2a 14|14 2a 64 7c) add r3,r4,r5
+ 4: (7c 64 2a 15|15 2a 64 7c) add\. r3,r4,r5
+ 8: (7c 64 28 14|14 28 64 7c) addc r3,r4,r5
+ c: (7c 64 28 15|15 28 64 7c) addc\. r3,r4,r5
+ 10: (7c 64 2c 14|14 2c 64 7c) addco r3,r4,r5
+ 14: (7c 64 2c 15|15 2c 64 7c) addco\. r3,r4,r5
+ 18: (7c 64 29 14|14 29 64 7c) adde r3,r4,r5
+ 1c: (7c 64 29 15|15 29 64 7c) adde\. r3,r4,r5
+ 20: (7c 64 2d 14|14 2d 64 7c) addeo r3,r4,r5
+ 24: (7c 64 2d 15|15 2d 64 7c) addeo\. r3,r4,r5
+ 28: (38 64 ff 80|80 ff 64 38) addi r3,r4,-128
+ 2c: (30 64 ff 80|80 ff 64 30) addic r3,r4,-128
+ 30: (34 64 ff 80|80 ff 64 34) addic\. r3,r4,-128
+ 34: (3c 64 ff 80|80 ff 64 3c) addis r3,r4,-128
+ 38: (7c 64 01 d4|d4 01 64 7c) addme r3,r4
+ 3c: (7c 64 01 d5|d5 01 64 7c) addme\. r3,r4
+ 40: (7c 64 05 d4|d4 05 64 7c) addmeo r3,r4
+ 44: (7c 64 05 d5|d5 05 64 7c) addmeo\. r3,r4
+ 48: (7c 64 2e 14|14 2e 64 7c) addo r3,r4,r5
+ 4c: (7c 64 2e 15|15 2e 64 7c) addo\. r3,r4,r5
+ 50: (7c 64 01 94|94 01 64 7c) addze r3,r4
+ 54: (7c 64 01 95|95 01 64 7c) addze\. r3,r4
+ 58: (7c 64 05 94|94 05 64 7c) addzeo r3,r4
+ 5c: (7c 64 05 95|95 05 64 7c) addzeo\. r3,r4
+ 60: (7c 83 28 38|38 28 83 7c) and r3,r4,r5
+ 64: (7c 83 28 39|39 28 83 7c) and\. r3,r4,r5
+ 68: (7d cd 78 78|78 78 cd 7d) andc r13,r14,r15
+ 6c: (7e 30 90 79|79 90 30 7e) andc\. r16,r17,r18
+ 70: (70 83 de ad|ad de 83 70) andi\. r3,r4,57005
+ 74: (74 83 de ad|ad de 83 74) andis\. r3,r4,57005
+ 78:
(48 00 00 02|02 00 00 48) ba 0 <ppc476>
+ 7c:
(40 01 00 00|00 00 01 40) bdnzf gt,7c <ppc476\+0x7c>
+ 80:
(40 85 00 02|02 00 85 40) blea cr1,0 <ppc476>
+ 84: (4d 80 04 20|20 04 80 4d) bltctr
+ 88: (4c 8a 04 20|20 04 8a 4c) bnectr cr2
+ 8c: (4c 86 04 20|20 04 86 4c) bnectr cr1
+ 90: (4c 86 04 20|20 04 86 4c) bnectr cr1
+ 94: (4d 80 04 21|21 04 80 4d) bltctrl
+ 98: (4c 8a 04 21|21 04 8a 4c) bnectrl cr2
+ 9c: (4c 86 04 21|21 04 86 4c) bnectrl cr1
+ a0: (4c 86 04 21|21 04 86 4c) bnectrl cr1
+ a4:
(40 43 00 01|01 00 43 40) bdzfl so,a4 <ppc476\+0xa4>
+ a8: (4d 80 00 20|20 00 80 4d) bltlr
+ ac: (4c 8a 00 20|20 00 8a 4c) bnelr cr2
+ b0: (4c 86 00 20|20 00 86 4c) bnelr cr1
+ b4: (4c 86 00 20|20 00 86 4c) bnelr cr1
+ b8: (4d 80 00 21|21 00 80 4d) bltlrl
+ bc: (4c 8a 00 21|21 00 8a 4c) bnelrl cr2
+ c0: (4c 86 00 21|21 00 86 4c) bnelrl cr1
+ c4: (4c 86 00 21|21 00 86 4c) bnelrl cr1
+ c8:
(48 00 00 00|00 00 00 48) b c8 <ppc476\+0xc8>
+ cc:
(48 00 00 01|01 00 00 48) bl cc <ppc476\+0xcc>
+ d0: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+ d4: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
+ d8: (7f 83 20 00|00 20 83 7f) cmpw cr7,r3,r4
+ dc: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+ e0: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+ e4: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
+ e8: (2f 83 ff 59|59 ff 83 2f) cmpwi cr7,r3,-167
+ ec: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
+ f0: (7f 83 20 40|40 20 83 7f) cmplw cr7,r3,r4
+ f4: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
+ f8: (2b 83 00 a7|a7 00 83 2b) cmplwi cr7,r3,167
+ fc: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
+ 100: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
+ 104: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
+ 108: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
+ 10c: (7d 6a 00 34|34 00 6a 7d) cntlzw r10,r11
+ 110: (7d 6a 00 35|35 00 6a 7d) cntlzw\. r10,r11
+ 114: (4c 85 32 02|02 32 85 4c) crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq
+ 118: (4c 64 29 02|02 29 64 4c) crandc so,4\*cr1\+lt,4\*cr1\+gt
+ 11c: (4c e0 0a 42|42 0a e0 4c) creqv 4\*cr1\+so,lt,gt
+ 120: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
+ 124: (4c 01 10 42|42 10 01 4c) crnor lt,gt,eq
+ 128: (4c a6 3b 82|82 3b a6 4c) cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so
+ 12c: (4c 43 23 42|42 23 43 4c) crorc eq,so,4\*cr1\+lt
+ 130: (4c c7 01 82|82 01 c7 4c) crxor 4\*cr1\+eq,4\*cr1\+so,lt
+ 134: (7c 09 55 ec|ec 55 09 7c) dcba r9,r10
+ 138: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
+ 13c: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
+ 140: (7c 06 3b ac|ac 3b 06 7c) dcbi r6,r7
+ 144: (7c 85 33 0c|0c 33 85 7c) dcblc 4,r5,r6
+ 148: (7c 06 38 6c|6c 38 06 7c) dcbst r6,r7
+ 14c: (7c c0 2a 2c|2c 2a c0 7c) dcbt 0,r5,6
+ 150: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+ 154: (7c c8 2a 2c|2c 2a c8 7c) dcbt r8,r5,6
+ 158: (7c e8 49 4c|4c 49 e8 7c) dcbtls 7,r8,r9
+ 15c: (7c e0 31 ec|ec 31 e0 7c) dcbtst 0,r6,7
+ 160: (7c 06 39 ec|ec 39 06 7c) dcbtst r6,r7
+ 164: (7c e9 31 ec|ec 31 e9 7c) dcbtst r9,r6,7
+ 168: (7d 4b 61 0c|0c 61 4b 7d) dcbtstls 10,r11,r12
+ 16c: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
+ 170: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
+ 174: (7c 00 03 8c|8c 03 00 7c) dccci
+ 178: (7c 00 03 8c|8c 03 00 7c) dccci
+ 17c: (7c 00 03 8c|8c 03 00 7c) dccci
+ 180: (7c 20 03 8c|8c 03 20 7c) dci 1
+ 184: (7d 4b 63 d6|d6 63 4b 7d) divw r10,r11,r12
+ 188: (7d 6c 6b d7|d7 6b 6c 7d) divw\. r11,r12,r13
+ 18c: (7d 4b 67 d6|d6 67 4b 7d) divwo r10,r11,r12
+ 190: (7d 6c 6f d7|d7 6f 6c 7d) divwo\. r11,r12,r13
+ 194: (7d 4b 63 96|96 63 4b 7d) divwu r10,r11,r12
+ 198: (7d 6c 6b 97|97 6b 6c 7d) divwu\. r11,r12,r13
+ 19c: (7d 4b 67 96|96 67 4b 7d) divwuo r10,r11,r12
+ 1a0: (7d 6c 6f 97|97 6f 6c 7d) divwuo\. r11,r12,r13
+ 1a4: (7c 83 28 9c|9c 28 83 7c) dlmzb r3,r4,r5
+ 1a8: (7c 83 28 9d|9d 28 83 7c) dlmzb\. r3,r4,r5
+ 1ac: (7d 6a 62 38|38 62 6a 7d) eqv r10,r11,r12
+ 1b0: (7d 6a 62 39|39 62 6a 7d) eqv\. r10,r11,r12
+ 1b4: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
+ 1b8: (7c 83 07 74|74 07 83 7c) extsb r3,r4
+ 1bc: (7c 83 07 75|75 07 83 7c) extsb\. r3,r4
+ 1c0: (7c 83 07 34|34 07 83 7c) extsh r3,r4
+ 1c4: (7c 83 07 35|35 07 83 7c) extsh\. r3,r4
+ 1c8: (fe a0 fa 10|10 fa a0 fe) fabs f21,f31
+ 1cc: (fe a0 fa 11|11 fa a0 fe) fabs\. f21,f31
+ 1d0: (fd 4b 60 2a|2a 60 4b fd) fadd f10,f11,f12
+ 1d4: (fd 4b 60 2b|2b 60 4b fd) fadd\. f10,f11,f12
+ 1d8: (ed 4b 60 2a|2a 60 4b ed) fadds f10,f11,f12
+ 1dc: (ed 4b 60 2b|2b 60 4b ed) fadds\. f10,f11,f12
+ 1e0: (fd 40 5e 9c|9c 5e 40 fd) fcfid f10,f11
+ 1e4: (fd 40 5e 9d|9d 5e 40 fd) fcfid\. f10,f11
+ 1e8: (fd 8a 58 40|40 58 8a fd) fcmpo cr3,f10,f11
+ 1ec: (fd 84 28 00|00 28 84 fd) fcmpu cr3,f4,f5
+ 1f0: (fd 4b 60 10|10 60 4b fd) fcpsgn f10,f11,f12
+ 1f4: (fd 4b 60 11|11 60 4b fd) fcpsgn\. f10,f11,f12
+ 1f8: (fd 40 5e 5c|5c 5e 40 fd) fctid f10,f11
+ 1fc: (fd 40 5e 5d|5d 5e 40 fd) fctid\. f10,f11
+ 200: (fd 40 5e 5e|5e 5e 40 fd) fctidz f10,f11
+ 204: (fd 40 5e 5f|5f 5e 40 fd) fctidz\. f10,f11
+ 208: (fd 40 58 1c|1c 58 40 fd) fctiw f10,f11
+ 20c: (fd 40 58 1d|1d 58 40 fd) fctiw\. f10,f11
+ 210: (fd 40 58 1e|1e 58 40 fd) fctiwz f10,f11
+ 214: (fd 40 58 1f|1f 58 40 fd) fctiwz\. f10,f11
+ 218: (fd 4b 60 24|24 60 4b fd) fdiv f10,f11,f12
+ 21c: (fd 4b 60 25|25 60 4b fd) fdiv\. f10,f11,f12
+ 220: (ed 4b 60 24|24 60 4b ed) fdivs f10,f11,f12
+ 224: (ed 4b 60 25|25 60 4b ed) fdivs\. f10,f11,f12
+ 228: (fd 4b 6b 3a|3a 6b 4b fd) fmadd f10,f11,f12,f13
+ 22c: (fd 4b 6b 3b|3b 6b 4b fd) fmadd\. f10,f11,f12,f13
+ 230: (ed 4b 6b 3a|3a 6b 4b ed) fmadds f10,f11,f12,f13
+ 234: (ed 4b 6b 3b|3b 6b 4b ed) fmadds\. f10,f11,f12,f13
+ 238: (fc 60 20 90|90 20 60 fc) fmr f3,f4
+ 23c: (fc 60 20 91|91 20 60 fc) fmr\. f3,f4
+ 240: (fd 4b 6b 38|38 6b 4b fd) fmsub f10,f11,f12,f13
+ 244: (fd 4b 6b 39|39 6b 4b fd) fmsub\. f10,f11,f12,f13
+ 248: (ed 4b 6b 38|38 6b 4b ed) fmsubs f10,f11,f12,f13
+ 24c: (ed 4b 6b 39|39 6b 4b ed) fmsubs\. f10,f11,f12,f13
+ 250: (fd 4b 03 32|32 03 4b fd) fmul f10,f11,f12
+ 254: (fd 4b 03 33|33 03 4b fd) fmul\. f10,f11,f12
+ 258: (ed 4b 03 32|32 03 4b ed) fmuls f10,f11,f12
+ 25c: (ed 4b 03 33|33 03 4b ed) fmuls\. f10,f11,f12
+ 260: (fe 80 f1 10|10 f1 80 fe) fnabs f20,f30
+ 264: (fe 80 f1 11|11 f1 80 fe) fnabs\. f20,f30
+ 268: (fc 60 20 50|50 20 60 fc) fneg f3,f4
+ 26c: (fc 60 20 51|51 20 60 fc) fneg\. f3,f4
+ 270: (fd 4b 6b 3e|3e 6b 4b fd) fnmadd f10,f11,f12,f13
+ 274: (fd 4b 6b 3f|3f 6b 4b fd) fnmadd\. f10,f11,f12,f13
+ 278: (ed 4b 6b 3e|3e 6b 4b ed) fnmadds f10,f11,f12,f13
+ 27c: (ed 4b 6b 3f|3f 6b 4b ed) fnmadds\. f10,f11,f12,f13
+ 280: (fd 4b 6b 3c|3c 6b 4b fd) fnmsub f10,f11,f12,f13
+ 284: (fd 4b 6b 3d|3d 6b 4b fd) fnmsub\. f10,f11,f12,f13
+ 288: (ed 4b 6b 3c|3c 6b 4b ed) fnmsubs f10,f11,f12,f13
+ 28c: (ed 4b 6b 3d|3d 6b 4b ed) fnmsubs\. f10,f11,f12,f13
+ 290: (fd c0 78 30|30 78 c0 fd) fre f14,f15
+ 294: (fd c0 78 31|31 78 c0 fd) fre\. f14,f15
+ 298: (ed c0 78 30|30 78 c0 ed) fres f14,f15
+ 29c: (ed c0 78 31|31 78 c0 ed) fres\. f14,f15
+ 2a0: (fd 40 5b d0|d0 5b 40 fd) frim f10,f11
+ 2a4: (fd 40 5b d1|d1 5b 40 fd) frim\. f10,f11
+ 2a8: (fd 40 5b 10|10 5b 40 fd) frin f10,f11
+ 2ac: (fd 40 5b 11|11 5b 40 fd) frin\. f10,f11
+ 2b0: (fd 40 5b 90|90 5b 40 fd) frip f10,f11
+ 2b4: (fd 40 5b 91|91 5b 40 fd) frip\. f10,f11
+ 2b8: (fd 40 5b 50|50 5b 40 fd) friz f10,f11
+ 2bc: (fd 40 5b 51|51 5b 40 fd) friz\. f10,f11
+ 2c0: (fc c0 38 18|18 38 c0 fc) frsp f6,f7
+ 2c4: (fd 00 48 19|19 48 00 fd) frsp\. f8,f9
+ 2c8: (fd c0 78 34|34 78 c0 fd) frsqrte f14,f15
+ 2cc: (fd c0 78 35|35 78 c0 fd) frsqrte\. f14,f15
+ 2d0: (ed c0 78 34|34 78 c0 ed) frsqrtes f14,f15
+ 2d4: (ed c0 78 35|35 78 c0 ed) frsqrtes\. f14,f15
+ 2d8: (fd 4b 6b 2e|2e 6b 4b fd) fsel f10,f11,f12,f13
+ 2dc: (fd 4b 6b 2f|2f 6b 4b fd) fsel\. f10,f11,f12,f13
+ 2e0: (fd 40 58 2c|2c 58 40 fd) fsqrt f10,f11
+ 2e4: (fd 40 58 2d|2d 58 40 fd) fsqrt\. f10,f11
+ 2e8: (ed 40 58 2c|2c 58 40 ed) fsqrts f10,f11
+ 2ec: (ed 40 58 2d|2d 58 40 ed) fsqrts\. f10,f11
+ 2f0: (fd 4b 60 28|28 60 4b fd) fsub f10,f11,f12
+ 2f4: (fd 4b 60 29|29 60 4b fd) fsub\. f10,f11,f12
+ 2f8: (ed 4b 60 28|28 60 4b ed) fsubs f10,f11,f12
+ 2fc: (ed 4b 60 29|29 60 4b ed) fsubs\. f10,f11,f12
+ 300: (7c 03 27 ac|ac 27 03 7c) icbi r3,r4
+ 304: (7e 11 91 cc|cc 91 11 7e) icblc 16,r17,r18
+ 308: (7c a8 48 2c|2c 48 a8 7c) icbt 5,r8,r9
+ 30c: (7d ae 7b cc|cc 7b ae 7d) icbtls 13,r14,r15
+ 310: (7c 00 07 8c|8c 07 00 7c) iccci
+ 314: (7c 00 07 8c|8c 07 00 7c) iccci
+ 318: (7c 00 07 8c|8c 07 00 7c) iccci
+ 31c: (7c 20 07 8c|8c 07 20 7c) ici 1
+ 320: (7c 03 27 cc|cc 27 03 7c) icread r3,r4
+ 324: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
+ 328: (7c 43 27 1e|1e 27 43 7c) isel r2,r3,r4,28
+ 32c: (4c 00 01 2c|2c 01 00 4c) isync
+ 330: (89 21 00 00|00 00 21 89) lbz r9,0\(r1\)
+ 334: (8d 41 00 01|01 00 41 8d) lbzu r10,1\(r1\)
+ 338: (7e 95 b0 ee|ee b0 95 7e) lbzux r20,r21,r22
+ 33c: (7c 64 28 ae|ae 28 64 7c) lbzx r3,r4,r5
+ 340: (ca a1 00 08|08 00 a1 ca) lfd f21,8\(r1\)
+ 344: (ce c1 00 10|10 00 c1 ce) lfdu f22,16\(r1\)
+ 348: (7e 95 b4 ee|ee b4 95 7e) lfdux f20,r21,r22
+ 34c: (7d ae 7c ae|ae 7c ae 7d) lfdx f13,r14,r15
+ 350: (7d 43 26 ae|ae 26 43 7d) lfiwax f10,r3,r4
+ 354: (c2 61 00 00|00 00 61 c2) lfs f19,0\(r1\)
+ 358: (c6 81 00 04|04 00 81 c6) lfsu f20,4\(r1\)
+ 35c: (7d 4b 64 6e|6e 64 4b 7d) lfsux f10,r11,r12
+ 360: (7d 4b 64 2e|2e 64 4b 7d) lfsx f10,r11,r12
+ 364: (a9 e1 00 06|06 00 e1 a9) lha r15,6\(r1\)
+ 368: (ae 01 00 08|08 00 01 ae) lhau r16,8\(r1\)
+ 36c: (7d 2a 5a ee|ee 5a 2a 7d) lhaux r9,r10,r11
+ 370: (7d 2a 5a ae|ae 5a 2a 7d) lhax r9,r10,r11
+ 374: (7c 64 2e 2c|2c 2e 64 7c) lhbrx r3,r4,r5
+ 378: (a1 a1 00 00|00 00 a1 a1) lhz r13,0\(r1\)
+ 37c: (a5 c1 00 02|02 00 c1 a5) lhzu r14,2\(r1\)
+ 380: (7e 96 c2 6e|6e c2 96 7e) lhzux r20,r22,r24
+ 384: (7e f8 ca 2e|2e ca f8 7e) lhzx r23,r24,r25
+ 388: (b8 61 ff f0|f0 ff 61 b8) lmw r3,-16\(r1\)
+ 38c: (7c a4 84 aa|aa 84 a4 7c) lswi r5,r4,16
+ 390: (7c 64 2c 2a|2a 2c 64 7c) lswx r3,r4,r5
+ 394: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
+ 398: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
+ 39c: (7c 64 28 29|29 28 64 7c) lwarx r3,r4,r5,1
+ 3a0: (7c 64 2c 2c|2c 2c 64 7c) lwbrx r3,r4,r5
+ 3a4: (80 c7 00 00|00 00 c7 80) lwz r6,0\(r7\)
+ 3a8: (84 61 00 10|10 00 61 84) lwzu r3,16\(r1\)
+ 3ac: (7c 64 28 6e|6e 28 64 7c) lwzux r3,r4,r5
+ 3b0: (7c 64 28 2e|2e 28 64 7c) lwzx r3,r4,r5
+ 3b4: (10 64 29 58|58 29 64 10) macchw r3,r4,r5
+ 3b8: (10 64 29 59|59 29 64 10) macchw\. r3,r4,r5
+ 3bc: (10 64 2d 58|58 2d 64 10) macchwo r3,r4,r5
+ 3c0: (10 64 2d 59|59 2d 64 10) macchwo\. r3,r4,r5
+ 3c4: (10 64 29 d8|d8 29 64 10) macchws r3,r4,r5
+ 3c8: (10 64 29 d9|d9 29 64 10) macchws\. r3,r4,r5
+ 3cc: (10 64 2d d8|d8 2d 64 10) macchwso r3,r4,r5
+ 3d0: (10 64 2d d9|d9 2d 64 10) macchwso\. r3,r4,r5
+ 3d4: (10 64 29 98|98 29 64 10) macchwsu r3,r4,r5
+ 3d8: (10 64 29 99|99 29 64 10) macchwsu\. r3,r4,r5
+ 3dc: (10 64 2d 98|98 2d 64 10) macchwsuo r3,r4,r5
+ 3e0: (10 64 2d 99|99 2d 64 10) macchwsuo\. r3,r4,r5
+ 3e4: (10 64 29 18|18 29 64 10) macchwu r3,r4,r5
+ 3e8: (10 64 29 19|19 29 64 10) macchwu\. r3,r4,r5
+ 3ec: (10 64 2d 18|18 2d 64 10) macchwuo r3,r4,r5
+ 3f0: (10 64 2d 19|19 2d 64 10) macchwuo\. r3,r4,r5
+ 3f4: (10 64 28 58|58 28 64 10) machhw r3,r4,r5
+ 3f8: (10 64 28 59|59 28 64 10) machhw\. r3,r4,r5
+ 3fc: (10 64 2c 58|58 2c 64 10) machhwo r3,r4,r5
+ 400: (10 64 2c 59|59 2c 64 10) machhwo\. r3,r4,r5
+ 404: (10 64 28 d8|d8 28 64 10) machhws r3,r4,r5
+ 408: (10 64 28 d9|d9 28 64 10) machhws\. r3,r4,r5
+ 40c: (10 64 2c d8|d8 2c 64 10) machhwso r3,r4,r5
+ 410: (10 64 2c d9|d9 2c 64 10) machhwso\. r3,r4,r5
+ 414: (10 64 28 98|98 28 64 10) machhwsu r3,r4,r5
+ 418: (10 64 28 99|99 28 64 10) machhwsu\. r3,r4,r5
+ 41c: (10 64 2c 98|98 2c 64 10) machhwsuo r3,r4,r5
+ 420: (10 64 2c 99|99 2c 64 10) machhwsuo\. r3,r4,r5
+ 424: (10 64 28 18|18 28 64 10) machhwu r3,r4,r5
+ 428: (10 64 28 19|19 28 64 10) machhwu\. r3,r4,r5
+ 42c: (10 64 2c 18|18 2c 64 10) machhwuo r3,r4,r5
+ 430: (10 64 2c 19|19 2c 64 10) machhwuo\. r3,r4,r5
+ 434: (10 64 2b 58|58 2b 64 10) maclhw r3,r4,r5
+ 438: (10 64 2b 59|59 2b 64 10) maclhw\. r3,r4,r5
+ 43c: (10 64 2f 58|58 2f 64 10) maclhwo r3,r4,r5
+ 440: (10 64 2f 59|59 2f 64 10) maclhwo\. r3,r4,r5
+ 444: (10 64 2b d8|d8 2b 64 10) maclhws r3,r4,r5
+ 448: (10 64 2b d9|d9 2b 64 10) maclhws\. r3,r4,r5
+ 44c: (10 64 2f d8|d8 2f 64 10) maclhwso r3,r4,r5
+ 450: (10 64 2f d9|d9 2f 64 10) maclhwso\. r3,r4,r5
+ 454: (10 64 2b 98|98 2b 64 10) maclhwsu r3,r4,r5
+ 458: (10 64 2b 99|99 2b 64 10) maclhwsu\. r3,r4,r5
+ 45c: (10 64 2f 98|98 2f 64 10) maclhwsuo r3,r4,r5
+ 460: (10 64 2f 99|99 2f 64 10) maclhwsuo\. r3,r4,r5
+ 464: (10 64 2b 18|18 2b 64 10) maclhwu r3,r4,r5
+ 468: (10 64 2b 19|19 2b 64 10) maclhwu\. r3,r4,r5
+ 46c: (10 64 2f 18|18 2f 64 10) maclhwuo r3,r4,r5
+ 470: (10 64 2f 19|19 2f 64 10) maclhwuo\. r3,r4,r5
+ 474: (7c 00 06 ac|ac 06 00 7c) mbar
+ 478: (7c 00 06 ac|ac 06 00 7c) mbar
+ 47c: (7c 20 06 ac|ac 06 20 7c) mbar 1
+ 480: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
+ 484: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
+ 488: (7d 80 04 00|00 04 80 7d) mcrxr cr3
+ 48c: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 490: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 494: (7c aa 3a 86|86 3a aa 7c) mfdcr r5,234
+ 498: (7c 64 02 46|46 02 64 7c) mfdcrux r3,r4
+ 49c: (7c 85 02 06|06 02 85 7c) mfdcrx r4,r5
+ 4a0: (ff c0 04 8e|8e 04 c0 ff) mffs f30
+ 4a4: (ff e0 04 8f|8f 04 e0 ff) mffs\. f31
+ 4a8: (7e 60 00 a6|a6 00 60 7e) mfmsr r19
+ 4ac: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ 4b0: (7c 60 22 a6|a6 22 60 7c) mfspr r3,128
+ 4b4: (7c 6c 42 e6|e6 42 6c 7c) mftbl r3
+ 4b8: (7c 00 04 ac|ac 04 00 7c) msync
+ 4bc: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 4c0: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 4c4: (7d 10 6b 86|86 6b 10 7d) mtdcr 432,r8
+ 4c8: (7c 83 03 46|46 03 83 7c) mtdcrux r3,r4
+ 4cc: (7c e6 03 06|06 03 e6 7c) mtdcrx r6,r7
+ 4d0: (fc 60 00 8c|8c 00 60 fc) mtfsb0 so
+ 4d4: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. so
+ 4d8: (fc 60 00 4c|4c 00 60 fc) mtfsb1 so
+ 4dc: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. so
+ 4e0: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+ 4e4: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+ 4e8: (fc 0d 55 8e|8e 55 0d fc) mtfsf 6,f10,0,1
+ 4ec: (fe 0c 55 8e|8e 55 0c fe) mtfsf 6,f10,1,0
+ 4f0: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
+ 4f4: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
+ 4f8: (fc 0d 5d 8f|8f 5d 0d fc) mtfsf\. 6,f11,0,1
+ 4fc: (fe 0c 5d 8f|8f 5d 0c fe) mtfsf\. 6,f11,1,0
+ 500: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ 504: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ 508: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ 50c: (ff 01 01 0c|0c 01 01 ff) mtfsfi 6,0,1
+ 510: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+ 514: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+ 518: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+ 51c: (ff 01 f1 0d|0d f1 01 ff) mtfsfi\. 6,15,1
+ 520: (7d 40 01 24|24 01 40 7d) mtmsr r10
+ 524: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 528: (7c 60 23 a6|a6 23 60 7c) mtspr 128,r3
+ 52c: (10 64 29 50|50 29 64 10) mulchw r3,r4,r5
+ 530: (10 64 29 51|51 29 64 10) mulchw\. r3,r4,r5
+ 534: (10 64 29 10|10 29 64 10) mulchwu r3,r4,r5
+ 538: (10 64 29 11|11 29 64 10) mulchwu\. r3,r4,r5
+ 53c: (10 64 28 50|50 28 64 10) mulhhw r3,r4,r5
+ 540: (10 64 28 51|51 28 64 10) mulhhw\. r3,r4,r5
+ 544: (10 64 28 10|10 28 64 10) mulhhwu r3,r4,r5
+ 548: (10 64 28 11|11 28 64 10) mulhhwu\. r3,r4,r5
+ 54c: (7c 64 28 96|96 28 64 7c) mulhw r3,r4,r5
+ 550: (7c 64 28 97|97 28 64 7c) mulhw\. r3,r4,r5
+ 554: (7c 64 28 16|16 28 64 7c) mulhwu r3,r4,r5
+ 558: (7c 64 28 17|17 28 64 7c) mulhwu\. r3,r4,r5
+ 55c: (10 64 2b 50|50 2b 64 10) mullhw r3,r4,r5
+ 560: (10 64 2b 51|51 2b 64 10) mullhw\. r3,r4,r5
+ 564: (10 64 2b 10|10 2b 64 10) mullhwu r3,r4,r5
+ 568: (10 64 2b 11|11 2b 64 10) mullhwu\. r3,r4,r5
+ 56c: (1c 64 00 05|05 00 64 1c) mulli r3,r4,5
+ 570: (7c 64 29 d6|d6 29 64 7c) mullw r3,r4,r5
+ 574: (7c 64 29 d7|d7 29 64 7c) mullw\. r3,r4,r5
+ 578: (7c 64 2d d6|d6 2d 64 7c) mullwo r3,r4,r5
+ 57c: (7c 64 2d d7|d7 2d 64 7c) mullwo\. r3,r4,r5
+ 580: (7f bc f3 b8|b8 f3 bc 7f) nand r28,r29,r30
+ 584: (7f bc f3 b9|b9 f3 bc 7f) nand\. r28,r29,r30
+ 588: (7c 64 00 d0|d0 00 64 7c) neg r3,r4
+ 58c: (7c 64 00 d1|d1 00 64 7c) neg\. r3,r4
+ 590: (7e 11 04 d0|d0 04 11 7e) nego r16,r17
+ 594: (7e 53 04 d1|d1 04 53 7e) nego\. r18,r19
+ 598: (10 64 29 5c|5c 29 64 10) nmacchw r3,r4,r5
+ 59c: (10 64 29 5d|5d 29 64 10) nmacchw\. r3,r4,r5
+ 5a0: (10 64 2d 5c|5c 2d 64 10) nmacchwo r3,r4,r5
+ 5a4: (10 64 2d 5d|5d 2d 64 10) nmacchwo\. r3,r4,r5
+ 5a8: (10 64 29 dc|dc 29 64 10) nmacchws r3,r4,r5
+ 5ac: (10 64 29 dd|dd 29 64 10) nmacchws\. r3,r4,r5
+ 5b0: (10 64 2d dc|dc 2d 64 10) nmacchwso r3,r4,r5
+ 5b4: (10 64 2d dd|dd 2d 64 10) nmacchwso\. r3,r4,r5
+ 5b8: (10 64 28 5c|5c 28 64 10) nmachhw r3,r4,r5
+ 5bc: (10 64 28 5d|5d 28 64 10) nmachhw\. r3,r4,r5
+ 5c0: (10 64 2c 5c|5c 2c 64 10) nmachhwo r3,r4,r5
+ 5c4: (10 64 2c 5d|5d 2c 64 10) nmachhwo\. r3,r4,r5
+ 5c8: (10 64 28 dc|dc 28 64 10) nmachhws r3,r4,r5
+ 5cc: (10 64 28 dd|dd 28 64 10) nmachhws\. r3,r4,r5
+ 5d0: (10 64 2c dc|dc 2c 64 10) nmachhwso r3,r4,r5
+ 5d4: (10 64 2c dd|dd 2c 64 10) nmachhwso\. r3,r4,r5
+ 5d8: (10 64 2b 5c|5c 2b 64 10) nmaclhw r3,r4,r5
+ 5dc: (10 64 2b 5d|5d 2b 64 10) nmaclhw\. r3,r4,r5
+ 5e0: (10 64 2f 5c|5c 2f 64 10) nmaclhwo r3,r4,r5
+ 5e4: (10 64 2f 5d|5d 2f 64 10) nmaclhwo\. r3,r4,r5
+ 5e8: (10 64 2b dc|dc 2b 64 10) nmaclhws r3,r4,r5
+ 5ec: (10 64 2b dd|dd 2b 64 10) nmaclhws\. r3,r4,r5
+ 5f0: (10 64 2f dc|dc 2f 64 10) nmaclhwso r3,r4,r5
+ 5f4: (10 64 2f dd|dd 2f 64 10) nmaclhwso\. r3,r4,r5
+ 5f8: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
+ 5fc: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
+ 600: (7c 40 23 78|78 23 40 7c) or r0,r2,r4
+ 604: (7d cc 83 79|79 83 cc 7d) or\. r12,r14,r16
+ 608: (7e 0f 8b 38|38 8b 0f 7e) orc r15,r16,r17
+ 60c: (7e 72 a3 39|39 a3 72 7e) orc\. r18,r19,r20
+ 610: (60 21 00 00|00 00 21 60) ori r1,r1,0
+ 614: (64 83 de ad|ad de 83 64) oris r3,r4,57005
+ 618: (7c 83 00 f4|f4 00 83 7c) popcntb r3,r4
+ 61c: (7c 83 01 34|34 01 83 7c) prtyw r3,r4
+ 620: (4c 00 00 66|66 00 00 4c) rfci
+ 624: (4c 00 00 64|64 00 00 4c) rfi
+ 628: (4c 00 00 4c|4c 00 00 4c) rfmci
+ 62c: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
+ 630: (50 83 65 37|37 65 83 50) rlwimi\. r3,r4,12,20,27
+ 634: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+ 638: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+ 63c: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
+ 640: (54 83 00 37|37 00 83 54) rlwinm\. r3,r4,0,0,27
+ 644: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
+ 648: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
+ 64c: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
+ 650: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
+ 654: (44 00 00 02|02 00 00 44) sc
+ 658: (7c 83 28 30|30 28 83 7c) slw r3,r4,r5
+ 65c: (7c 83 28 31|31 28 83 7c) slw\. r3,r4,r5
+ 660: (7c 83 2e 30|30 2e 83 7c) sraw r3,r4,r5
+ 664: (7c 83 2e 31|31 2e 83 7c) sraw\. r3,r4,r5
+ 668: (7c 83 86 70|70 86 83 7c) srawi r3,r4,16
+ 66c: (7c 83 86 71|71 86 83 7c) srawi\. r3,r4,16
+ 670: (7c 83 2c 30|30 2c 83 7c) srw r3,r4,r5
+ 674: (7c 83 2c 31|31 2c 83 7c) srw\. r3,r4,r5
+ 678: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+ 67c: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
+ 680: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
+ 684: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
+ 688: (7c 64 29 ae|ae 29 64 7c) stbx r3,r4,r5
+ 68c: (db 21 00 20|20 00 21 db) stfd f25,32\(r1\)
+ 690: (df 41 00 28|28 00 41 df) stfdu f26,40\(r1\)
+ 694: (7c 01 15 ee|ee 15 01 7c) stfdux f0,r1,r2
+ 698: (7f be fd ae|ae fd be 7f) stfdx f29,r30,r31
+ 69c: (7d 43 27 ae|ae 27 43 7d) stfiwx f10,r3,r4
+ 6a0: (d2 e1 00 14|14 00 e1 d2) stfs f23,20\(r1\)
+ 6a4: (d7 01 00 18|18 00 01 d7) stfsu f24,24\(r1\)
+ 6a8: (7f 5b e5 6e|6e e5 5b 7f) stfsux f26,r27,r28
+ 6ac: (7e f8 cd 2e|2e cd f8 7e) stfsx f23,r24,r25
+ 6b0: (b2 21 00 0a|0a 00 21 b2) sth r17,10\(r1\)
+ 6b4: (7c c7 47 2c|2c 47 c7 7c) sthbrx r6,r7,r8
+ 6b8: (b6 41 00 0c|0c 00 41 b6) sthu r18,12\(r1\)
+ 6bc: (7e b6 bb 6e|6e bb b6 7e) sthux r21,r22,r23
+ 6c0: (7d 8d 73 2e|2e 73 8d 7d) sthx r12,r13,r14
+ 6c4: (bc c1 ff f0|f0 ff c1 bc) stmw r6,-16\(r1\)
+ 6c8: (7c 64 85 aa|aa 85 64 7c) stswi r3,r4,16
+ 6cc: (7c 64 2d 2a|2a 2d 64 7c) stswx r3,r4,r5
+ 6d0: (90 c7 ff f0|f0 ff c7 90) stw r6,-16\(r7\)
+ 6d4: (7c 64 2d 2c|2c 2d 64 7c) stwbrx r3,r4,r5
+ 6d8: (7c 64 29 2d|2d 29 64 7c) stwcx\. r3,r4,r5
+ 6dc: (94 61 00 10|10 00 61 94) stwu r3,16\(r1\)
+ 6e0: (7c 64 29 6e|6e 29 64 7c) stwux r3,r4,r5
+ 6e4: (7c 64 29 2e|2e 29 64 7c) stwx r3,r4,r5
+ 6e8: (7c 64 28 50|50 28 64 7c) subf r3,r4,r5
+ 6ec: (7c 64 28 51|51 28 64 7c) subf\. r3,r4,r5
+ 6f0: (7c 64 28 10|10 28 64 7c) subfc r3,r4,r5
+ 6f4: (7c 64 28 11|11 28 64 7c) subfc\. r3,r4,r5
+ 6f8: (7c 64 2c 10|10 2c 64 7c) subfco r3,r4,r5
+ 6fc: (7c 64 2c 11|11 2c 64 7c) subfco\. r3,r4,r5
+ 700: (7c 64 29 10|10 29 64 7c) subfe r3,r4,r5
+ 704: (7c 64 29 11|11 29 64 7c) subfe\. r3,r4,r5
+ 708: (7c 64 2d 10|10 2d 64 7c) subfeo r3,r4,r5
+ 70c: (7c 64 2d 11|11 2d 64 7c) subfeo\. r3,r4,r5
+ 710: (20 64 00 05|05 00 64 20) subfic r3,r4,5
+ 714: (7c 64 01 d0|d0 01 64 7c) subfme r3,r4
+ 718: (7c 64 01 d1|d1 01 64 7c) subfme\. r3,r4
+ 71c: (7c 64 05 d0|d0 05 64 7c) subfmeo r3,r4
+ 720: (7c 64 05 d1|d1 05 64 7c) subfmeo\. r3,r4
+ 724: (7c 64 2c 50|50 2c 64 7c) subfo r3,r4,r5
+ 728: (7c 64 2c 51|51 2c 64 7c) subfo\. r3,r4,r5
+ 72c: (7c 64 01 90|90 01 64 7c) subfze r3,r4
+ 730: (7c 64 01 91|91 01 64 7c) subfze\. r3,r4
+ 734: (7c 64 05 90|90 05 64 7c) subfzeo r3,r4
+ 738: (7c 64 05 91|91 05 64 7c) subfzeo\. r3,r4
+ 73c: (7c 07 46 24|24 46 07 7c) tlbivax r7,r8
+ 740: (7c 22 3f 64|64 3f 22 7c) tlbre r1,r2,7
+ 744: (7c 0b 67 24|24 67 0b 7c) tlbsx r11,r12
+ 748: (7d 8d 77 24|24 77 8d 7d) tlbsx r12,r13,r14
+ 74c: (7d 8d 77 25|25 77 8d 7d) tlbsx\. r12,r13,r14
+ 750: (7c 00 04 6c|6c 04 00 7c) tlbsync
+ 754: (7c 00 07 a4|a4 07 00 7c) tlbwe
+ 758: (7c 00 07 a4|a4 07 00 7c) tlbwe
+ 75c: (7c 21 0f a4|a4 0f 21 7c) tlbwe r1,r1,1
+ 760: (7f e0 00 08|08 00 e0 7f) trap
+ 764: (7f e0 00 08|08 00 e0 7f) trap
+ 768: (7c 83 20 08|08 20 83 7c) tweq r3,r4
+ 76c: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
+ 770: (7c 83 20 08|08 20 83 7c) tweq r3,r4
+ 774: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
+ 778: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
+ 77c: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
+ 780: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
+ 784: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
+ 788: (7c 60 01 06|06 01 60 7c) wrtee r3
+ 78c: (7c 00 81 46|46 81 00 7c) wrteei 1
+ 790: (7f dd fa 78|78 fa dd 7f) xor r29,r30,r31
+ 794: (7f dd fa 79|79 fa dd 7f) xor\. r29,r30,r31
+ 798: (68 83 de ad|ad de 83 68) xori r3,r4,57005
+ 79c: (6c 83 de ad|ad de 83 6c) xoris r3,r4,57005
- .section ".text"
+ .text
ppc476:
add 3,4,5
add. 3,4,5
#name: A2 tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 7c 85 32 15 add\. r4,r5,r6
- 4: 7c 85 32 14 add r4,r5,r6
- 8: 7c 85 30 15 addc\. r4,r5,r6
- c: 7c 85 30 14 addc r4,r5,r6
- 10: 7c 85 34 15 addco\. r4,r5,r6
- 14: 7c 85 34 14 addco r4,r5,r6
- 18: 7c 85 31 15 adde\. r4,r5,r6
- 1c: 7c 85 31 14 adde r4,r5,r6
- 20: 7c 85 35 15 addeo\. r4,r5,r6
- 24: 7c 85 35 14 addeo r4,r5,r6
- 28: 38 85 00 0d addi r4,r5,13
- 2c: 38 85 ff f3 addi r4,r5,-13
- 30: 34 85 00 0d addic\. r4,r5,13
- 34: 34 85 ff f3 addic\. r4,r5,-13
- 38: 30 85 00 0d addic r4,r5,13
- 3c: 30 85 ff f3 addic r4,r5,-13
- 40: 3c 85 00 17 addis r4,r5,23
- 44: 3c 85 ff e9 addis r4,r5,-23
- 48: 7c 85 01 d5 addme\. r4,r5
- 4c: 7c 85 01 d4 addme r4,r5
- 50: 7c 85 05 d5 addmeo\. r4,r5
- 54: 7c 85 05 d4 addmeo r4,r5
- 58: 7c 85 36 15 addo\. r4,r5,r6
- 5c: 7c 85 36 14 addo r4,r5,r6
- 60: 7c 85 01 95 addze\. r4,r5
- 64: 7c 85 01 94 addze r4,r5
- 68: 7c 85 05 95 addzeo\. r4,r5
- 6c: 7c 85 05 94 addzeo r4,r5
- 70: 7c a4 30 39 and\. r4,r5,r6
- 74: 7c a4 30 38 and r4,r5,r6
- 78: 7c a4 30 79 andc\. r4,r5,r6
- 7c: 7c a4 30 78 andc r4,r5,r6
- 80: 70 a4 00 06 andi\. r4,r5,6
- 84: 74 a4 00 06 andis\. r4,r5,6
- 88: 00 00 02 00 attn
- 8c: 48 00 00 02 ba 0 <start>
+ 0: (7c 85 32 15|15 32 85 7c) add\. r4,r5,r6
+ 4: (7c 85 32 14|14 32 85 7c) add r4,r5,r6
+ 8: (7c 85 30 15|15 30 85 7c) addc\. r4,r5,r6
+ c: (7c 85 30 14|14 30 85 7c) addc r4,r5,r6
+ 10: (7c 85 34 15|15 34 85 7c) addco\. r4,r5,r6
+ 14: (7c 85 34 14|14 34 85 7c) addco r4,r5,r6
+ 18: (7c 85 31 15|15 31 85 7c) adde\. r4,r5,r6
+ 1c: (7c 85 31 14|14 31 85 7c) adde r4,r5,r6
+ 20: (7c 85 35 15|15 35 85 7c) addeo\. r4,r5,r6
+ 24: (7c 85 35 14|14 35 85 7c) addeo r4,r5,r6
+ 28: (38 85 00 0d|0d 00 85 38) addi r4,r5,13
+ 2c: (38 85 ff f3|f3 ff 85 38) addi r4,r5,-13
+ 30: (34 85 00 0d|0d 00 85 34) addic\. r4,r5,13
+ 34: (34 85 ff f3|f3 ff 85 34) addic\. r4,r5,-13
+ 38: (30 85 00 0d|0d 00 85 30) addic r4,r5,13
+ 3c: (30 85 ff f3|f3 ff 85 30) addic r4,r5,-13
+ 40: (3c 85 00 17|17 00 85 3c) addis r4,r5,23
+ 44: (3c 85 ff e9|e9 ff 85 3c) addis r4,r5,-23
+ 48: (7c 85 01 d5|d5 01 85 7c) addme\. r4,r5
+ 4c: (7c 85 01 d4|d4 01 85 7c) addme r4,r5
+ 50: (7c 85 05 d5|d5 05 85 7c) addmeo\. r4,r5
+ 54: (7c 85 05 d4|d4 05 85 7c) addmeo r4,r5
+ 58: (7c 85 36 15|15 36 85 7c) addo\. r4,r5,r6
+ 5c: (7c 85 36 14|14 36 85 7c) addo r4,r5,r6
+ 60: (7c 85 01 95|95 01 85 7c) addze\. r4,r5
+ 64: (7c 85 01 94|94 01 85 7c) addze r4,r5
+ 68: (7c 85 05 95|95 05 85 7c) addzeo\. r4,r5
+ 6c: (7c 85 05 94|94 05 85 7c) addzeo r4,r5
+ 70: (7c a4 30 39|39 30 a4 7c) and\. r4,r5,r6
+ 74: (7c a4 30 38|38 30 a4 7c) and r4,r5,r6
+ 78: (7c a4 30 79|79 30 a4 7c) andc\. r4,r5,r6
+ 7c: (7c a4 30 78|78 30 a4 7c) andc r4,r5,r6
+ 80: (70 a4 00 06|06 00 a4 70) andi\. r4,r5,6
+ 84: (74 a4 00 06|06 00 a4 74) andis\. r4,r5,6
+ 88: (00 00 02 00|00 02 00 00) attn
+ 8c: (48 00 00 02|02 00 00 48) ba 0 <start>
8c: R_PPC(|64)_ADDR24 label_abs
- 90: 40 01 00 00 bdnzf gt,90 <start\+0x90>
+ 90: (40 01 00 00|00 00 01 40) bdnzf gt,90 <start\+0x90>
90: R_PPC(|64)_REL14 foo
- 94: 40 01 00 00 bdnzf gt,94 <start\+0x94>
+ 94: (40 01 00 00|00 00 01 40) bdnzf gt,94 <start\+0x94>
94: R_PPC(|64)_REL14 foo
- 98: 40 01 00 00 bdnzf gt,98 <start\+0x98>
+ 98: (40 01 00 00|00 00 01 40) bdnzf gt,98 <start\+0x98>
98: R_PPC(|64)_REL14 foo
- 9c: 40 85 00 02 blea cr1,0 <start>
+ 9c: (40 85 00 02|02 00 85 40) blea cr1,0 <start>
9c: R_PPC(|64)_ADDR14 foo_abs
- a0: 40 c5 00 02 blea- cr1,0 <start>
+ a0: (40 c5 00 02|02 00 c5 40) blea- cr1,0 <start>
a0: R_PPC(|64)_ADDR14 foo_abs
- a4: 40 e5 00 02 blea\+ cr1,0 <start>
+ a4: (40 e5 00 02|02 00 e5 40) blea\+ cr1,0 <start>
a4: R_PPC(|64)_ADDR14 foo_abs
- a8: 4c 86 0c 20 bcctr 4,4\*cr1\+eq,1
- ac: 4c 86 04 20 bnectr cr1
- b0: 4c a6 04 20 bcctr\+ 4,4\*cr1\+eq
- b4: 4c 86 0c 21 bcctrl 4,4\*cr1\+eq,1
- b8: 4c 86 04 21 bnectrl cr1
- bc: 4c a6 04 21 bcctrl\+ 4,4\*cr1\+eq
- c0: 40 01 00 01 bdnzfl gt,c0 <start\+0xc0>
+ a8: (4c 86 0c 20|20 0c 86 4c) bcctr 4,4\*cr1\+eq,1
+ ac: (4c 86 04 20|20 04 86 4c) bnectr cr1
+ b0: (4c a6 04 20|20 04 a6 4c) bcctr\+ 4,4\*cr1\+eq
+ b4: (4c 86 0c 21|21 0c 86 4c) bcctrl 4,4\*cr1\+eq,1
+ b8: (4c 86 04 21|21 04 86 4c) bnectrl cr1
+ bc: (4c a6 04 21|21 04 a6 4c) bcctrl\+ 4,4\*cr1\+eq
+ c0: (40 01 00 01|01 00 01 40) bdnzfl gt,c0 <start\+0xc0>
c0: R_PPC(|64)_REL14 foo
- c4: 40 01 00 01 bdnzfl gt,c4 <start\+0xc4>
+ c4: (40 01 00 01|01 00 01 40) bdnzfl gt,c4 <start\+0xc4>
c4: R_PPC(|64)_REL14 foo
- c8: 40 01 00 01 bdnzfl gt,c8 <start\+0xc8>
+ c8: (40 01 00 01|01 00 01 40) bdnzfl gt,c8 <start\+0xc8>
c8: R_PPC(|64)_REL14 foo
- cc: 40 85 00 03 blela cr1,0 <start>
+ cc: (40 85 00 03|03 00 85 40) blela cr1,0 <start>
cc: R_PPC(|64)_ADDR14 foo_abs
- d0: 40 c5 00 03 blela- cr1,0 <start>
+ d0: (40 c5 00 03|03 00 c5 40) blela- cr1,0 <start>
d0: R_PPC(|64)_ADDR14 foo_abs
- d4: 40 e5 00 03 blela\+ cr1,0 <start>
+ d4: (40 e5 00 03|03 00 e5 40) blela\+ cr1,0 <start>
d4: R_PPC(|64)_ADDR14 foo_abs
- d8: 4c 86 08 20 bclr 4,4\*cr1\+eq,1
- dc: 4c 86 00 20 bnelr cr1
- e0: 4c a6 00 20 bclr\+ 4,4\*cr1\+eq
- e4: 4c 86 08 21 bclrl 4,4\*cr1\+eq,1
- e8: 4c 86 00 21 bnelrl cr1
- ec: 4c a6 00 21 bclrl\+ 4,4\*cr1\+eq
- f0: 48 00 00 00 b f0 <start\+0xf0>
+ d8: (4c 86 08 20|20 08 86 4c) bclr 4,4\*cr1\+eq,1
+ dc: (4c 86 00 20|20 00 86 4c) bnelr cr1
+ e0: (4c a6 00 20|20 00 a6 4c) bclr\+ 4,4\*cr1\+eq
+ e4: (4c 86 08 21|21 08 86 4c) bclrl 4,4\*cr1\+eq,1
+ e8: (4c 86 00 21|21 00 86 4c) bnelrl cr1
+ ec: (4c a6 00 21|21 00 a6 4c) bclrl\+ 4,4\*cr1\+eq
+ f0: (48 00 00 00|00 00 00 48) b f0 <start\+0xf0>
f0: R_PPC(|64)_REL24 label
- f4: 48 00 00 03 bla 0 <start>
+ f4: (48 00 00 03|03 00 00 48) bla 0 <start>
f4: R_PPC(|64)_ADDR24 label_abs
- f8: 48 00 00 01 bl f8 <start\+0xf8>
+ f8: (48 00 00 01|01 00 00 48) bl f8 <start\+0xf8>
f8: R_PPC(|64)_REL24 label
- fc: 7d 6a 61 f8 bpermd r10,r11,r12
- 100: 7c a7 40 00 cmpd cr1,r7,r8
- 104: 7d 6a 63 f8 cmpb r10,r11,r12
- 108: 2c aa 00 0d cmpdi cr1,r10,13
- 10c: 2c aa ff f3 cmpdi cr1,r10,-13
- 110: 7c a7 40 40 cmpld cr1,r7,r8
- 114: 28 aa 00 64 cmpldi cr1,r10,100
- 118: 7e b4 00 75 cntlzd\. r20,r21
- 11c: 7e b4 00 74 cntlzd r20,r21
- 120: 7e b4 00 35 cntlzw\. r20,r21
- 124: 7e b4 00 34 cntlzw r20,r21
- 128: 4c 22 1a 02 crand gt,eq,so
- 12c: 4c 22 19 02 crandc gt,eq,so
- 130: 4c 22 1a 42 creqv gt,eq,so
- 134: 4c 22 19 c2 crnand gt,eq,so
- 138: 4c 22 18 42 crnor gt,eq,so
- 13c: 4c 22 1b 82 cror gt,eq,so
- 140: 4c 22 1b 42 crorc gt,eq,so
- 144: 4c 22 19 82 crxor gt,eq,so
- 148: 7c 0a 5d ec dcba r10,r11
- 14c: 7c 0a 58 ac dcbf r10,r11
- 150: 7c 2a 58 ac dcbfl r10,r11
- 154: 7c 0a 58 fe dcbfep r10,r11
- 158: 7c 0a 5b ac dcbi r10,r11
- 15c: 7c 0a 5b 0c dcblc r10,r11
- 160: 7c 2a 5b 0c dcblc 1,r10,r11
- 164: 7c 0a 58 6c dcbst r10,r11
- 168: 7c 0a 58 7e dcbstep r10,r11
- 16c: 7c 0a 5a 2c dcbt r10,r11
- 170: 7c 2a 5a 2c dcbt r10,r11,1
- 174: 7d 4b 62 7e dcbtep r10,r11,r12
- 178: 7c 0a 59 4c dcbtls r10,r11
- 17c: 7c 2a 59 4c dcbtls 1,r10,r11
- 180: 7c 0a 59 ec dcbtst r10,r11
- 184: 7c 2a 59 ec dcbtst r10,r11,1
- 188: 7d 4b 61 fe dcbtstep r10,r11,r12
- 18c: 7c 0a 59 0c dcbtstls r10,r11
- 190: 7c 2a 59 0c dcbtstls 1,r10,r11
- 194: 7c 0a 5f ec dcbz r10,r11
- 198: 7c 0a 5f fe dcbzep r10,r11
- 19c: 7c 00 03 8c dccci
- 1a0: 7c 00 03 8c dccci
- 1a4: 7c 00 03 8c dccci
- 1a8: 7d 40 03 8c dci 10
- 1ac: 7e 95 b3 d3 divd\. r20,r21,r22
- 1b0: 7e 95 b3 d2 divd r20,r21,r22
- 1b4: 7e 95 b7 d3 divdo\. r20,r21,r22
- 1b8: 7e 95 b7 d2 divdo r20,r21,r22
- 1bc: 7e 95 b3 93 divdu\. r20,r21,r22
- 1c0: 7e 95 b3 92 divdu r20,r21,r22
- 1c4: 7e 95 b7 93 divduo\. r20,r21,r22
- 1c8: 7e 95 b7 92 divduo r20,r21,r22
- 1cc: 7e 95 b3 d7 divw\. r20,r21,r22
- 1d0: 7e 95 b3 d6 divw r20,r21,r22
- 1d4: 7e 95 b7 d7 divwo\. r20,r21,r22
- 1d8: 7e 95 b7 d6 divwo r20,r21,r22
- 1dc: 7e 95 b3 97 divwu\. r20,r21,r22
- 1e0: 7e 95 b3 96 divwu r20,r21,r22
- 1e4: 7e 95 b7 97 divwuo\. r20,r21,r22
- 1e8: 7e 95 b7 96 divwuo r20,r21,r22
- 1ec: 7e b4 b2 39 eqv\. r20,r21,r22
- 1f0: 7e b4 b2 38 eqv r20,r21,r22
- 1f4: 7c 0a 58 66 eratilx 0,r10,r11
- 1f8: 7c 2a 58 66 eratilx 1,r10,r11
- 1fc: 7c ea 58 66 eratilx 7,r10,r11
- 200: 7d 4b 66 66 erativax r10,r11,r12
- 204: 7d 4b 01 66 eratre r10,r11,0
- 208: 7d 4b 19 66 eratre r10,r11,3
- 20c: 7d 4b 61 27 eratsx\. r10,r11,r12
- 210: 7d 4b 61 26 eratsx r10,r11,r12
- 214: 7d 4b 01 a6 eratwe r10,r11,0
- 218: 7d 4b 19 a6 eratwe r10,r11,3
- 21c: 7d 6a 07 75 extsb\. r10,r11
- 220: 7d 6a 07 74 extsb r10,r11
- 224: 7d 6a 07 35 extsh\. r10,r11
- 228: 7d 6a 07 34 extsh r10,r11
- 22c: 7d 6a 07 b5 extsw\. r10,r11
- 230: 7d 6a 07 b4 extsw r10,r11
- 234: fe 80 aa 11 fabs\. f20,f21
- 238: fe 80 aa 10 fabs f20,f21
- 23c: fe 95 b0 2b fadd\. f20,f21,f22
- 240: fe 95 b0 2a fadd f20,f21,f22
- 244: ee 95 b0 2b fadds\. f20,f21,f22
- 248: ee 95 b0 2a fadds f20,f21,f22
- 24c: fe 80 ae 9d fcfid\. f20,f21
- 250: fe 80 ae 9c fcfid f20,f21
- 254: fc 14 a8 40 fcmpo cr0,f20,f21
- 258: fc 94 a8 40 fcmpo cr1,f20,f21
- 25c: fc 14 a8 00 fcmpu cr0,f20,f21
- 260: fc 94 a8 00 fcmpu cr1,f20,f21
- 264: fe 95 b0 11 fcpsgn\. f20,f21,f22
- 268: fe 95 b0 10 fcpsgn f20,f21,f22
- 26c: fe 80 ae 5d fctid\. f20,f21
- 270: fe 80 ae 5c fctid f20,f21
- 274: fe 80 ae 5f fctidz\. f20,f21
- 278: fe 80 ae 5e fctidz f20,f21
- 27c: fe 80 a8 1d fctiw\. f20,f21
- 280: fe 80 a8 1c fctiw f20,f21
- 284: fe 80 a8 1f fctiwz\. f20,f21
- 288: fe 80 a8 1e fctiwz f20,f21
- 28c: fe 95 b0 25 fdiv\. f20,f21,f22
- 290: fe 95 b0 24 fdiv f20,f21,f22
- 294: ee 95 b0 25 fdivs\. f20,f21,f22
- 298: ee 95 b0 24 fdivs f20,f21,f22
- 29c: fe 95 bd bb fmadd\. f20,f21,f22,f23
- 2a0: fe 95 bd ba fmadd f20,f21,f22,f23
- 2a4: ee 95 bd bb fmadds\. f20,f21,f22,f23
- 2a8: ee 95 bd ba fmadds f20,f21,f22,f23
- 2ac: fe 80 a8 91 fmr\. f20,f21
- 2b0: fe 80 a8 90 fmr f20,f21
- 2b4: fe 95 bd b9 fmsub\. f20,f21,f22,f23
- 2b8: fe 95 bd b8 fmsub f20,f21,f22,f23
- 2bc: ee 95 bd b9 fmsubs\. f20,f21,f22,f23
- 2c0: ee 95 bd b8 fmsubs f20,f21,f22,f23
- 2c4: fe 95 05 b3 fmul\. f20,f21,f22
- 2c8: fe 95 05 b2 fmul f20,f21,f22
- 2cc: ee 95 05 b3 fmuls\. f20,f21,f22
- 2d0: ee 95 05 b2 fmuls f20,f21,f22
- 2d4: fe 80 a9 11 fnabs\. f20,f21
- 2d8: fe 80 a9 10 fnabs f20,f21
- 2dc: fe 80 a8 51 fneg\. f20,f21
- 2e0: fe 80 a8 50 fneg f20,f21
- 2e4: fe 95 bd bf fnmadd\. f20,f21,f22,f23
- 2e8: fe 95 bd be fnmadd f20,f21,f22,f23
- 2ec: ee 95 bd bf fnmadds\. f20,f21,f22,f23
- 2f0: ee 95 bd be fnmadds f20,f21,f22,f23
- 2f4: fe 95 bd bd fnmsub\. f20,f21,f22,f23
- 2f8: fe 95 bd bc fnmsub f20,f21,f22,f23
- 2fc: ee 95 bd bd fnmsubs\. f20,f21,f22,f23
- 300: ee 95 bd bc fnmsubs f20,f21,f22,f23
- 304: fe 80 a8 31 fre\. f20,f21
- 308: fe 80 a8 30 fre f20,f21
- 30c: fe 80 a8 31 fre\. f20,f21
- 310: fe 80 a8 30 fre f20,f21
- 314: fe 81 a8 31 fre\. f20,f21,1
- 318: fe 81 a8 30 fre f20,f21,1
- 31c: ee 80 a8 31 fres\. f20,f21
- 320: ee 80 a8 30 fres f20,f21
- 324: ee 80 a8 31 fres\. f20,f21
- 328: ee 80 a8 30 fres f20,f21
- 32c: ee 81 a8 31 fres\. f20,f21,1
- 330: ee 81 a8 30 fres f20,f21,1
- 334: fe 80 ab d1 frim\. f20,f21
- 338: fe 80 ab d0 frim f20,f21
- 33c: fe 80 ab 11 frin\. f20,f21
- 340: fe 80 ab 10 frin f20,f21
- 344: fe 80 ab 91 frip\. f20,f21
- 348: fe 80 ab 90 frip f20,f21
- 34c: fe 80 ab 51 friz\. f20,f21
- 350: fe 80 ab 50 friz f20,f21
- 354: fe 80 a8 19 frsp\. f20,f21
- 358: fe 80 a8 18 frsp f20,f21
- 35c: fe 80 a8 35 frsqrte\. f20,f21
- 360: fe 80 a8 34 frsqrte f20,f21
- 364: fe 80 a8 35 frsqrte\. f20,f21
- 368: fe 80 a8 34 frsqrte f20,f21
- 36c: fe 81 a8 35 frsqrte\. f20,f21,1
- 370: fe 81 a8 34 frsqrte f20,f21,1
- 374: ee 80 a8 34 frsqrtes f20,f21
- 378: ee 80 a8 35 frsqrtes\. f20,f21
- 37c: ee 80 a8 34 frsqrtes f20,f21
- 380: ee 80 a8 35 frsqrtes\. f20,f21
- 384: ee 81 a8 34 frsqrtes f20,f21,1
- 388: ee 81 a8 35 frsqrtes\. f20,f21,1
- 38c: fe 95 bd af fsel\. f20,f21,f22,f23
- 390: fe 95 bd ae fsel f20,f21,f22,f23
- 394: fe 80 a8 2d fsqrt\. f20,f21
- 398: fe 80 a8 2c fsqrt f20,f21
- 39c: ee 80 a8 2d fsqrts\. f20,f21
- 3a0: ee 80 a8 2c fsqrts f20,f21
- 3a4: fe 95 b0 29 fsub\. f20,f21,f22
- 3a8: fe 95 b0 28 fsub f20,f21,f22
- 3ac: ee 95 b0 29 fsubs\. f20,f21,f22
- 3b0: ee 95 b0 28 fsubs f20,f21,f22
- 3b4: 7c 0a 5f ac icbi r10,r11
- 3b8: 7c 0a 5f be icbiep r10,r11
- 3bc: 7c 0a 58 2c icbt r10,r11
- 3c0: 7c ea 58 2c icbt 7,r10,r11
- 3c4: 7c 0a 5b cc icbtls r10,r11
- 3c8: 7c ea 5b cc icbtls 7,r10,r11
- 3cc: 7c 00 07 8c iccci
- 3d0: 7c 00 07 8c iccci
- 3d4: 7c 00 07 8c iccci
- 3d8: 7d 40 07 8c ici 10
- 3dc: 7d 4b 63 2d icswx\. r10,r11,r12
- 3e0: 7d 4b 63 2c icswx r10,r11,r12
- 3e4: 7d 4b 65 de isel r10,r11,r12,23
- 3e8: 4c 00 01 2c isync
- 3ec: 7d 4b 60 be lbepx r10,r11,r12
- 3f0: 89 4b ff ef lbz r10,-17\(r11\)
- 3f4: 89 4b 00 11 lbz r10,17\(r11\)
- 3f8: 8d 4b ff ff lbzu r10,-1\(r11\)
- 3fc: 8d 4b 00 01 lbzu r10,1\(r11\)
- 400: 7d 4b 68 ee lbzux r10,r11,r13
- 404: 7d 4b 68 ae lbzx r10,r11,r13
- 408: e9 4b ff f8 ld r10,-8\(r11\)
- 40c: e9 4b 00 08 ld r10,8\(r11\)
- 410: 7d 4b 60 a8 ldarx r10,r11,r12
- 414: 7d 4b 60 a9 ldarx r10,r11,r12,1
- 418: 7d 4b 64 28 ldbrx r10,r11,r12
- 41c: 7d 4b 60 3a ldepx r10,r11,r12
- 420: e9 4b ff f9 ldu r10,-8\(r11\)
- 424: e9 4b 00 09 ldu r10,8\(r11\)
- 428: 7d 4b 60 6a ldux r10,r11,r12
- 42c: 7d 4b 60 2a ldx r10,r11,r12
- 430: ca 8a ff f8 lfd f20,-8\(r10\)
- 434: ca 8a 00 08 lfd f20,8\(r10\)
- 438: 7e 8a 5c be lfdepx f20,r10,r11
- 43c: ce 8a ff f8 lfdu f20,-8\(r10\)
- 440: ce 8a 00 08 lfdu f20,8\(r10\)
- 444: 7e 8a 5c ee lfdux f20,r10,r11
- 448: 7e 8a 5c ae lfdx f20,r10,r11
- 44c: 7e 8a 5e ae lfiwax f20,r10,r11
- 450: 7e 8a 5e ee lfiwzx f20,r10,r11
- 454: c2 8a ff fc lfs f20,-4\(r10\)
- 458: c2 8a 00 04 lfs f20,4\(r10\)
- 45c: c6 8a ff fc lfsu f20,-4\(r10\)
- 460: c6 8a 00 04 lfsu f20,4\(r10\)
- 464: 7e 8a 5c 6e lfsux f20,r10,r11
- 468: 7e 8a 5c 2e lfsx f20,r10,r11
- 46c: a9 4b 00 02 lha r10,2\(r11\)
- 470: ad 4b ff fe lhau r10,-2\(r11\)
- 474: 7d 4b 62 ee lhaux r10,r11,r12
- 478: 7d 4b 62 ae lhax r10,r11,r12
- 47c: 7d 4b 66 2c lhbrx r10,r11,r12
- 480: 7d 4b 62 3e lhepx r10,r11,r12
- 484: a1 4b ff fe lhz r10,-2\(r11\)
- 488: a1 4b 00 02 lhz r10,2\(r11\)
- 48c: a5 4b ff fe lhzu r10,-2\(r11\)
- 490: a5 4b 00 02 lhzu r10,2\(r11\)
- 494: 7d 4b 62 6e lhzux r10,r11,r12
- 498: 7d 4b 62 2e lhzx r10,r11,r12
- 49c: ba 8a 00 10 lmw r20,16\(r10\)
- 4a0: 7d 4b 0c aa lswi r10,r11,1
- 4a4: 7d 8b 04 aa lswi r12,r11,32
- 4a8: 7d 4b 64 2a lswx r10,r11,r12
- 4ac: e9 4b ff fe lwa r10,-4\(r11\)
- 4b0: e9 4b 00 06 lwa r10,4\(r11\)
- 4b4: 7d 4b 60 28 lwarx r10,r11,r12
- 4b8: 7d 4b 60 29 lwarx r10,r11,r12,1
- 4bc: 7d 4b 62 ea lwaux r10,r11,r12
- 4c0: 7d 4b 62 aa lwax r10,r11,r12
- 4c4: 7d 4b 64 2c lwbrx r10,r11,r12
- 4c8: 7d 4b 60 3e lwepx r10,r11,r12
- 4cc: 81 4b ff fc lwz r10,-4\(r11\)
- 4d0: 81 4b 00 04 lwz r10,4\(r11\)
- 4d4: 85 4b ff fc lwzu r10,-4\(r11\)
- 4d8: 85 4b 00 04 lwzu r10,4\(r11\)
- 4dc: 7d 4b 60 6e lwzux r10,r11,r12
- 4e0: 7d 4b 60 2e lwzx r10,r11,r12
- 4e4: 7c 00 06 ac mbar
- 4e8: 7c 00 06 ac mbar
- 4ec: 7c 00 06 ac mbar
- 4f0: 7c 20 06 ac mbar 1
- 4f4: 4c 04 00 00 mcrf cr0,cr1
- 4f8: fd 90 00 80 mcrfs cr3,cr4
- 4fc: 7c 00 04 00 mcrxr cr0
- 500: 7d 80 04 00 mcrxr cr3
- 504: 7c 60 00 26 mfcr r3
- 508: 7c 60 00 26 mfcr r3
- 50c: 7c 70 10 26 mfocrf r3,1
- 510: 7c 78 00 26 mfocrf r3,128
- 514: 7d 4a 3a 87 mfdcr\. r10,234
- 518: 7d 4a 3a 86 mfdcr r10,234
- 51c: 7d 4b 02 07 mfdcrx\. r10,r11
- 520: 7d 4b 02 06 mfdcrx r10,r11
- 524: fe 80 04 8f mffs\. f20
- 528: fe 80 04 8e mffs f20
- 52c: 7d 40 00 a6 mfmsr r10
- 530: 7c 70 10 26 mfocrf r3,1
- 534: 7c 78 00 26 mfocrf r3,128
- 538: 7d 4a 3a a6 mfspr r10,234
- 53c: 7d 4c 42 e6 mftbl r10
- 540: 7d 4d 42 e6 mftbu r10
- 544: 7c 00 51 dc msgclr r10
- 548: 7c 00 51 9c msgsnd r10
- 54c: 7c 60 01 20 mtcrf 0,r3
- 550: 7c 70 11 20 mtocrf 1,r3
- 554: 7c 78 01 20 mtocrf 128,r3
- 558: 7c 6f f1 20 mtcr r3
- 55c: 7d 4a 3b 87 mtdcr\. 234,r10
- 560: 7d 4a 3b 86 mtdcr 234,r10
- 564: 7d 6a 03 07 mtdcrx\. r10,r11
- 568: 7d 6a 03 06 mtdcrx r10,r11
- 56c: fc 60 00 8d mtfsb0\. so
- 570: fc 60 00 8c mtfsb0 so
- 574: fc 60 00 4d mtfsb1\. so
- 578: fc 60 00 4c mtfsb1 so
- 57c: fc 0c a5 8f mtfsf\. 6,f20
- 580: fc 0c a5 8e mtfsf 6,f20
- 584: fc 0c a5 8f mtfsf\. 6,f20
- 588: fc 0c a5 8e mtfsf 6,f20
- 58c: fe 0d a5 8f mtfsf\. 6,f20,1,1
- 590: fe 0d a5 8e mtfsf 6,f20,1,1
- 594: ff 00 01 0d mtfsfi\. 6,0
- 598: ff 00 01 0c mtfsfi 6,0
- 59c: ff 00 d1 0d mtfsfi\. 6,13
- 5a0: ff 00 d1 0c mtfsfi 6,13
- 5a4: ff 01 d1 0d mtfsfi\. 6,13,1
- 5a8: ff 01 d1 0c mtfsfi 6,13,1
- 5ac: 7d 40 01 24 mtmsr r10
- 5b0: 7d 40 01 24 mtmsr r10
- 5b4: 7d 41 01 24 mtmsr r10,1
- 5b8: 7c 70 11 20 mtocrf 1,r3
- 5bc: 7c 78 01 20 mtocrf 128,r3
- 5c0: 7d 4a 3b a6 mtspr 234,r10
- 5c4: 7e 95 b0 93 mulhd\. r20,r21,r22
- 5c8: 7e 95 b0 92 mulhd r20,r21,r22
- 5cc: 7e 95 b0 13 mulhdu\. r20,r21,r22
- 5d0: 7e 95 b0 12 mulhdu r20,r21,r22
- 5d4: 7e 95 b0 97 mulhw\. r20,r21,r22
- 5d8: 7e 95 b0 96 mulhw r20,r21,r22
- 5dc: 7e 95 b0 17 mulhwu\. r20,r21,r22
- 5e0: 7e 95 b0 16 mulhwu r20,r21,r22
- 5e4: 7e 95 b1 d3 mulld\. r20,r21,r22
- 5e8: 7e 95 b1 d2 mulld r20,r21,r22
- 5ec: 7e 95 b5 d3 mulldo\. r20,r21,r22
- 5f0: 7e 95 b5 d2 mulldo r20,r21,r22
- 5f4: 1e 95 00 64 mulli r20,r21,100
- 5f8: 1e 95 ff 9c mulli r20,r21,-100
- 5fc: 7e 95 b1 d7 mullw\. r20,r21,r22
- 600: 7e 95 b1 d6 mullw r20,r21,r22
- 604: 7e 95 b5 d7 mullwo\. r20,r21,r22
- 608: 7e 95 b5 d6 mullwo r20,r21,r22
- 60c: 7e b4 b3 b9 nand\. r20,r21,r22
- 610: 7e b4 b3 b8 nand r20,r21,r22
- 614: 7e 95 00 d1 neg\. r20,r21
- 618: 7e 95 00 d0 neg r20,r21
- 61c: 7e 95 04 d1 nego\. r20,r21
- 620: 7e 95 04 d0 nego r20,r21
- 624: 7e b4 b0 f9 nor\. r20,r21,r22
- 628: 7e b4 b0 f8 nor r20,r21,r22
- 62c: 7e b4 b3 79 or\. r20,r21,r22
- 630: 7e b4 b3 78 or r20,r21,r22
- 634: 7e b4 b3 39 orc\. r20,r21,r22
- 638: 7e b4 b3 38 orc r20,r21,r22
- 63c: 62 b4 10 00 ori r20,r21,4096
- 640: 66 b4 10 00 oris r20,r21,4096
- 644: 7d 6a 00 f4 popcntb r10,r11
- 648: 7d 6a 03 f4 popcntd r10,r11
- 64c: 7d 6a 02 f4 popcntw r10,r11
- 650: 7d 6a 01 74 prtyd r10,r11
- 654: 7d 6a 01 34 prtyw r10,r11
- 658: 4c 00 00 66 rfci
- 65c: 4c 00 00 cc rfgi
- 660: 4c 00 00 64 rfi
- 664: 4c 00 00 4c rfmci
- 668: 79 6a 67 f1 rldcl\. r10,r11,r12,63
- 66c: 79 6a 67 f0 rldcl r10,r11,r12,63
- 670: 79 6a 67 f3 rldcr\. r10,r11,r12,63
- 674: 79 6a 67 f2 rldcr r10,r11,r12,63
- 678: 79 6a bf e9 rldic\. r10,r11,23,63
- 67c: 79 6a bf e8 rldic r10,r11,23,63
- 680: 79 6a bf e1 rldicl\. r10,r11,23,63
- 684: 79 6a bf e0 rldicl r10,r11,23,63
- 688: 79 6a bf e5 rldicr\. r10,r11,23,63
- 68c: 79 6a bf e4 rldicr r10,r11,23,63
- 690: 79 6a bf ed rldimi\. r10,r11,23,63
- 694: 79 6a bf ec rldimi r10,r11,23,63
- 698: 51 6a b8 3f rlwimi\. r10,r11,23,0,31
- 69c: 51 6a b8 3e rlwimi r10,r11,23,0,31
- 6a0: 55 6a b8 3f rotlwi\. r10,r11,23
- 6a4: 55 6a b8 3e rotlwi r10,r11,23
- 6a8: 5d 6a b8 3f rotlw\. r10,r11,r23
- 6ac: 5d 6a b8 3e rotlw r10,r11,r23
- 6b0: 44 00 00 02 sc
- 6b4: 44 00 0c 82 sc 100
- 6b8: 7d 6a 60 37 sld\. r10,r11,r12
- 6bc: 7d 6a 60 36 sld r10,r11,r12
- 6c0: 7d 6a 60 31 slw\. r10,r11,r12
- 6c4: 7d 6a 60 30 slw r10,r11,r12
- 6c8: 7d 6a 66 35 srad\. r10,r11,r12
- 6cc: 7d 6a 66 34 srad r10,r11,r12
- 6d0: 7d 6a fe 77 sradi\. r10,r11,63
- 6d4: 7d 6a fe 76 sradi r10,r11,63
- 6d8: 7d 6a 66 31 sraw\. r10,r11,r12
- 6dc: 7d 6a 66 30 sraw r10,r11,r12
- 6e0: 7d 6a fe 71 srawi\. r10,r11,31
- 6e4: 7d 6a fe 70 srawi r10,r11,31
- 6e8: 7d 6a 64 37 srd\. r10,r11,r12
- 6ec: 7d 6a 64 36 srd r10,r11,r12
- 6f0: 7d 6a 64 31 srw\. r10,r11,r12
- 6f4: 7d 6a 64 30 srw r10,r11,r12
- 6f8: 99 4b ff ff stb r10,-1\(r11\)
- 6fc: 99 4b 00 01 stb r10,1\(r11\)
- 700: 7d 4b 61 be stbepx r10,r11,r12
- 704: 9d 4b ff ff stbu r10,-1\(r11\)
- 708: 9d 4b 00 01 stbu r10,1\(r11\)
- 70c: 7d 4b 61 ee stbux r10,r11,r12
- 710: 7d 4b 61 ae stbx r10,r11,r12
- 714: f9 4b ff f8 std r10,-8\(r11\)
- 718: f9 4b 00 08 std r10,8\(r11\)
- 71c: 7d 4b 65 28 stdbrx r10,r11,r12
- 720: 7d 4b 61 ad stdcx\. r10,r11,r12
- 724: 7d 4b 61 3a stdepx r10,r11,r12
- 728: f9 4b ff f9 stdu r10,-8\(r11\)
- 72c: f9 4b 00 09 stdu r10,8\(r11\)
- 730: 7d 4b 61 6a stdux r10,r11,r12
- 734: 7d 4b 61 2a stdx r10,r11,r12
- 738: da 8a ff f8 stfd f20,-8\(r10\)
- 73c: da 8a 00 08 stfd f20,8\(r10\)
- 740: 7e 8a 5d be stfdepx f20,r10,r11
- 744: de 8a ff f8 stfdu f20,-8\(r10\)
- 748: de 8a 00 08 stfdu f20,8\(r10\)
- 74c: 7e 8a 5d ee stfdux f20,r10,r11
- 750: 7e 8a 5d ae stfdx f20,r10,r11
- 754: 7e 8a 5f ae stfiwx f20,r10,r11
- 758: d2 8a ff fc stfs f20,-4\(r10\)
- 75c: d2 8a 00 04 stfs f20,4\(r10\)
- 760: d6 8a ff fc stfsu f20,-4\(r10\)
- 764: d6 8a 00 04 stfsu f20,4\(r10\)
- 768: 7e 8a 5d 6e stfsux f20,r10,r11
- 76c: 7e 8a 5d 2e stfsx f20,r10,r11
- 770: b1 4b ff fe sth r10,-2\(r11\)
- 774: b1 4b 00 02 sth r10,2\(r11\)
- 778: b1 4b ff fc sth r10,-4\(r11\)
- 77c: b1 4b 00 04 sth r10,4\(r11\)
- 780: 7d 4b 67 2c sthbrx r10,r11,r12
- 784: 7d 4b 63 3e sthepx r10,r11,r12
- 788: b5 4b ff fe sthu r10,-2\(r11\)
- 78c: b5 4b 00 02 sthu r10,2\(r11\)
- 790: 7d 4b 63 6e sthux r10,r11,r12
- 794: 7d 4b 63 2e sthx r10,r11,r12
- 798: be 8a 00 10 stmw r20,16\(r10\)
- 79c: 7d 4b 0d aa stswi r10,r11,1
- 7a0: 7d 4b 05 aa stswi r10,r11,32
- 7a4: 7d 4b 65 2a stswx r10,r11,r12
- 7a8: 7d 4b 65 2c stwbrx r10,r11,r12
- 7ac: 7d 4b 61 2d stwcx\. r10,r11,r12
- 7b0: 7d 4b 61 3e stwepx r10,r11,r12
- 7b4: 95 4b ff fc stwu r10,-4\(r11\)
- 7b8: 95 4b 00 04 stwu r10,4\(r11\)
- 7bc: 7d 4b 61 6e stwux r10,r11,r12
- 7c0: 7d 4b 61 2e stwx r10,r11,r12
- 7c4: 7e 95 b0 51 subf\. r20,r21,r22
- 7c8: 7e 95 b0 50 subf r20,r21,r22
- 7cc: 7e 95 b0 11 subfc\. r20,r21,r22
- 7d0: 7e 95 b0 10 subfc r20,r21,r22
- 7d4: 7e 95 b4 11 subfco\. r20,r21,r22
- 7d8: 7e 95 b4 10 subfco r20,r21,r22
- 7dc: 7e 95 b1 11 subfe\. r20,r21,r22
- 7e0: 7e 95 b1 10 subfe r20,r21,r22
- 7e4: 7e 95 b5 11 subfeo\. r20,r21,r22
- 7e8: 7e 95 b5 10 subfeo r20,r21,r22
- 7ec: 22 95 00 64 subfic r20,r21,100
- 7f0: 22 95 ff 9c subfic r20,r21,-100
- 7f4: 7e 95 01 d1 subfme\. r20,r21
- 7f8: 7e 95 01 d0 subfme r20,r21
- 7fc: 7e 95 05 d1 subfmeo\. r20,r21
- 800: 7e 95 05 d0 subfmeo r20,r21
- 804: 7e 95 b4 51 subfo\. r20,r21,r22
- 808: 7e 95 b4 50 subfo r20,r21,r22
- 80c: 7e 95 01 91 subfze\. r20,r21
- 810: 7e 95 01 90 subfze r20,r21
- 814: 7e 95 05 91 subfzeo\. r20,r21
- 818: 7e 95 05 90 subfzeo r20,r21
- 81c: 7c 00 04 ac sync
- 820: 7c 00 04 ac sync
- 824: 7c 00 04 ac sync
- 828: 7c 20 04 ac lwsync
- 82c: 7c aa 58 88 tdlge r10,r11
- 830: 08 aa 00 64 tdlgei r10,100
- 834: 08 aa ff 9c tdlgei r10,-100
- 838: 7c 6a 58 24 tlbilxva r10,r11
- 83c: 7c 0a 5e 24 tlbivax r10,r11
- 840: 7c 00 07 64 tlbre
- 844: 7d 4b 3f 64 tlbre r10,r11,7
- 848: 7c 0a 5e a5 tlbsrx\. r10,r11
- 84c: 7d 4b 67 25 tlbsx\. r10,r11,r12
- 850: 7d 4b 67 24 tlbsx r10,r11,r12
- 854: 7c 00 04 6c tlbsync
- 858: 7c 00 07 a4 tlbwe
- 85c: 7d 4b 3f a4 tlbwe r10,r11,7
- 860: 7c aa 58 08 twlge r10,r11
- 864: 0c aa 00 64 twlgei r10,100
- 868: 0c aa ff 9c twlgei r10,-100
- 86c: 7c 00 00 7c wait
- 870: 7c 00 00 7c wait
- 874: 7c 20 00 7c waitrsv
- 878: 7c 40 00 7c waitimpl
- 87c: 7c 40 00 7c waitimpl
- 880: 7c 20 00 7c waitrsv
- 884: 7c 00 01 6c wchkall
- 888: 7c 00 01 6c wchkall
- 88c: 7d 80 01 6c wchkall cr3
- 890: 7c 2a 5f 4c wclr 1,r10,r11
- 894: 7c 20 07 4c wclrall 1
- 898: 7c 4a 5f 4c wclrone r10,r11
- 89c: 7d 40 01 06 wrtee r10
- 8a0: 7c 00 81 46 wrteei 1
- 8a4: 7d 6a 62 79 xor\. r10,r11,r12
- 8a8: 7d 6a 62 78 xor r10,r11,r12
- 8ac: 69 6a 10 00 xori r10,r11,4096
- 8b0: 6d 6a 10 00 xoris r10,r11,4096
+ fc: (7d 6a 61 f8|f8 61 6a 7d) bpermd r10,r11,r12
+ 100: (7c a7 40 00|00 40 a7 7c) cmpd cr1,r7,r8
+ 104: (7d 6a 63 f8|f8 63 6a 7d) cmpb r10,r11,r12
+ 108: (2c aa 00 0d|0d 00 aa 2c) cmpdi cr1,r10,13
+ 10c: (2c aa ff f3|f3 ff aa 2c) cmpdi cr1,r10,-13
+ 110: (7c a7 40 40|40 40 a7 7c) cmpld cr1,r7,r8
+ 114: (28 aa 00 64|64 00 aa 28) cmpldi cr1,r10,100
+ 118: (7e b4 00 75|75 00 b4 7e) cntlzd\. r20,r21
+ 11c: (7e b4 00 74|74 00 b4 7e) cntlzd r20,r21
+ 120: (7e b4 00 35|35 00 b4 7e) cntlzw\. r20,r21
+ 124: (7e b4 00 34|34 00 b4 7e) cntlzw r20,r21
+ 128: (4c 22 1a 02|02 1a 22 4c) crand gt,eq,so
+ 12c: (4c 22 19 02|02 19 22 4c) crandc gt,eq,so
+ 130: (4c 22 1a 42|42 1a 22 4c) creqv gt,eq,so
+ 134: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
+ 138: (4c 22 18 42|42 18 22 4c) crnor gt,eq,so
+ 13c: (4c 22 1b 82|82 1b 22 4c) cror gt,eq,so
+ 140: (4c 22 1b 42|42 1b 22 4c) crorc gt,eq,so
+ 144: (4c 22 19 82|82 19 22 4c) crxor gt,eq,so
+ 148: (7c 0a 5d ec|ec 5d 0a 7c) dcba r10,r11
+ 14c: (7c 0a 58 ac|ac 58 0a 7c) dcbf r10,r11
+ 150: (7c 2a 58 ac|ac 58 2a 7c) dcbfl r10,r11
+ 154: (7c 0a 58 fe|fe 58 0a 7c) dcbfep r10,r11
+ 158: (7c 0a 5b ac|ac 5b 0a 7c) dcbi r10,r11
+ 15c: (7c 0a 5b 0c|0c 5b 0a 7c) dcblc r10,r11
+ 160: (7c 2a 5b 0c|0c 5b 2a 7c) dcblc 1,r10,r11
+ 164: (7c 0a 58 6c|6c 58 0a 7c) dcbst r10,r11
+ 168: (7c 0a 58 7e|7e 58 0a 7c) dcbstep r10,r11
+ 16c: (7c 0a 5a 2c|2c 5a 0a 7c) dcbt r10,r11
+ 170: (7c 2a 5a 2c|2c 5a 2a 7c) dcbt r10,r11,1
+ 174: (7d 4b 62 7e|7e 62 4b 7d) dcbtep r10,r11,r12
+ 178: (7c 0a 59 4c|4c 59 0a 7c) dcbtls r10,r11
+ 17c: (7c 2a 59 4c|4c 59 2a 7c) dcbtls 1,r10,r11
+ 180: (7c 0a 59 ec|ec 59 0a 7c) dcbtst r10,r11
+ 184: (7c 2a 59 ec|ec 59 2a 7c) dcbtst r10,r11,1
+ 188: (7d 4b 61 fe|fe 61 4b 7d) dcbtstep r10,r11,r12
+ 18c: (7c 0a 59 0c|0c 59 0a 7c) dcbtstls r10,r11
+ 190: (7c 2a 59 0c|0c 59 2a 7c) dcbtstls 1,r10,r11
+ 194: (7c 0a 5f ec|ec 5f 0a 7c) dcbz r10,r11
+ 198: (7c 0a 5f fe|fe 5f 0a 7c) dcbzep r10,r11
+ 19c: (7c 00 03 8c|8c 03 00 7c) dccci
+ 1a0: (7c 00 03 8c|8c 03 00 7c) dccci
+ 1a4: (7c 00 03 8c|8c 03 00 7c) dccci
+ 1a8: (7d 40 03 8c|8c 03 40 7d) dci 10
+ 1ac: (7e 95 b3 d3|d3 b3 95 7e) divd\. r20,r21,r22
+ 1b0: (7e 95 b3 d2|d2 b3 95 7e) divd r20,r21,r22
+ 1b4: (7e 95 b7 d3|d3 b7 95 7e) divdo\. r20,r21,r22
+ 1b8: (7e 95 b7 d2|d2 b7 95 7e) divdo r20,r21,r22
+ 1bc: (7e 95 b3 93|93 b3 95 7e) divdu\. r20,r21,r22
+ 1c0: (7e 95 b3 92|92 b3 95 7e) divdu r20,r21,r22
+ 1c4: (7e 95 b7 93|93 b7 95 7e) divduo\. r20,r21,r22
+ 1c8: (7e 95 b7 92|92 b7 95 7e) divduo r20,r21,r22
+ 1cc: (7e 95 b3 d7|d7 b3 95 7e) divw\. r20,r21,r22
+ 1d0: (7e 95 b3 d6|d6 b3 95 7e) divw r20,r21,r22
+ 1d4: (7e 95 b7 d7|d7 b7 95 7e) divwo\. r20,r21,r22
+ 1d8: (7e 95 b7 d6|d6 b7 95 7e) divwo r20,r21,r22
+ 1dc: (7e 95 b3 97|97 b3 95 7e) divwu\. r20,r21,r22
+ 1e0: (7e 95 b3 96|96 b3 95 7e) divwu r20,r21,r22
+ 1e4: (7e 95 b7 97|97 b7 95 7e) divwuo\. r20,r21,r22
+ 1e8: (7e 95 b7 96|96 b7 95 7e) divwuo r20,r21,r22
+ 1ec: (7e b4 b2 39|39 b2 b4 7e) eqv\. r20,r21,r22
+ 1f0: (7e b4 b2 38|38 b2 b4 7e) eqv r20,r21,r22
+ 1f4: (7c 0a 58 66|66 58 0a 7c) eratilx 0,r10,r11
+ 1f8: (7c 2a 58 66|66 58 2a 7c) eratilx 1,r10,r11
+ 1fc: (7c ea 58 66|66 58 ea 7c) eratilx 7,r10,r11
+ 200: (7d 4b 66 66|66 66 4b 7d) erativax r10,r11,r12
+ 204: (7d 4b 01 66|66 01 4b 7d) eratre r10,r11,0
+ 208: (7d 4b 19 66|66 19 4b 7d) eratre r10,r11,3
+ 20c: (7d 4b 61 27|27 61 4b 7d) eratsx\. r10,r11,r12
+ 210: (7d 4b 61 26|26 61 4b 7d) eratsx r10,r11,r12
+ 214: (7d 4b 01 a6|a6 01 4b 7d) eratwe r10,r11,0
+ 218: (7d 4b 19 a6|a6 19 4b 7d) eratwe r10,r11,3
+ 21c: (7d 6a 07 75|75 07 6a 7d) extsb\. r10,r11
+ 220: (7d 6a 07 74|74 07 6a 7d) extsb r10,r11
+ 224: (7d 6a 07 35|35 07 6a 7d) extsh\. r10,r11
+ 228: (7d 6a 07 34|34 07 6a 7d) extsh r10,r11
+ 22c: (7d 6a 07 b5|b5 07 6a 7d) extsw\. r10,r11
+ 230: (7d 6a 07 b4|b4 07 6a 7d) extsw r10,r11
+ 234: (fe 80 aa 11|11 aa 80 fe) fabs\. f20,f21
+ 238: (fe 80 aa 10|10 aa 80 fe) fabs f20,f21
+ 23c: (fe 95 b0 2b|2b b0 95 fe) fadd\. f20,f21,f22
+ 240: (fe 95 b0 2a|2a b0 95 fe) fadd f20,f21,f22
+ 244: (ee 95 b0 2b|2b b0 95 ee) fadds\. f20,f21,f22
+ 248: (ee 95 b0 2a|2a b0 95 ee) fadds f20,f21,f22
+ 24c: (fe 80 ae 9d|9d ae 80 fe) fcfid\. f20,f21
+ 250: (fe 80 ae 9c|9c ae 80 fe) fcfid f20,f21
+ 254: (fc 14 a8 40|40 a8 14 fc) fcmpo cr0,f20,f21
+ 258: (fc 94 a8 40|40 a8 94 fc) fcmpo cr1,f20,f21
+ 25c: (fc 14 a8 00|00 a8 14 fc) fcmpu cr0,f20,f21
+ 260: (fc 94 a8 00|00 a8 94 fc) fcmpu cr1,f20,f21
+ 264: (fe 95 b0 11|11 b0 95 fe) fcpsgn\. f20,f21,f22
+ 268: (fe 95 b0 10|10 b0 95 fe) fcpsgn f20,f21,f22
+ 26c: (fe 80 ae 5d|5d ae 80 fe) fctid\. f20,f21
+ 270: (fe 80 ae 5c|5c ae 80 fe) fctid f20,f21
+ 274: (fe 80 ae 5f|5f ae 80 fe) fctidz\. f20,f21
+ 278: (fe 80 ae 5e|5e ae 80 fe) fctidz f20,f21
+ 27c: (fe 80 a8 1d|1d a8 80 fe) fctiw\. f20,f21
+ 280: (fe 80 a8 1c|1c a8 80 fe) fctiw f20,f21
+ 284: (fe 80 a8 1f|1f a8 80 fe) fctiwz\. f20,f21
+ 288: (fe 80 a8 1e|1e a8 80 fe) fctiwz f20,f21
+ 28c: (fe 95 b0 25|25 b0 95 fe) fdiv\. f20,f21,f22
+ 290: (fe 95 b0 24|24 b0 95 fe) fdiv f20,f21,f22
+ 294: (ee 95 b0 25|25 b0 95 ee) fdivs\. f20,f21,f22
+ 298: (ee 95 b0 24|24 b0 95 ee) fdivs f20,f21,f22
+ 29c: (fe 95 bd bb|bb bd 95 fe) fmadd\. f20,f21,f22,f23
+ 2a0: (fe 95 bd ba|ba bd 95 fe) fmadd f20,f21,f22,f23
+ 2a4: (ee 95 bd bb|bb bd 95 ee) fmadds\. f20,f21,f22,f23
+ 2a8: (ee 95 bd ba|ba bd 95 ee) fmadds f20,f21,f22,f23
+ 2ac: (fe 80 a8 91|91 a8 80 fe) fmr\. f20,f21
+ 2b0: (fe 80 a8 90|90 a8 80 fe) fmr f20,f21
+ 2b4: (fe 95 bd b9|b9 bd 95 fe) fmsub\. f20,f21,f22,f23
+ 2b8: (fe 95 bd b8|b8 bd 95 fe) fmsub f20,f21,f22,f23
+ 2bc: (ee 95 bd b9|b9 bd 95 ee) fmsubs\. f20,f21,f22,f23
+ 2c0: (ee 95 bd b8|b8 bd 95 ee) fmsubs f20,f21,f22,f23
+ 2c4: (fe 95 05 b3|b3 05 95 fe) fmul\. f20,f21,f22
+ 2c8: (fe 95 05 b2|b2 05 95 fe) fmul f20,f21,f22
+ 2cc: (ee 95 05 b3|b3 05 95 ee) fmuls\. f20,f21,f22
+ 2d0: (ee 95 05 b2|b2 05 95 ee) fmuls f20,f21,f22
+ 2d4: (fe 80 a9 11|11 a9 80 fe) fnabs\. f20,f21
+ 2d8: (fe 80 a9 10|10 a9 80 fe) fnabs f20,f21
+ 2dc: (fe 80 a8 51|51 a8 80 fe) fneg\. f20,f21
+ 2e0: (fe 80 a8 50|50 a8 80 fe) fneg f20,f21
+ 2e4: (fe 95 bd bf|bf bd 95 fe) fnmadd\. f20,f21,f22,f23
+ 2e8: (fe 95 bd be|be bd 95 fe) fnmadd f20,f21,f22,f23
+ 2ec: (ee 95 bd bf|bf bd 95 ee) fnmadds\. f20,f21,f22,f23
+ 2f0: (ee 95 bd be|be bd 95 ee) fnmadds f20,f21,f22,f23
+ 2f4: (fe 95 bd bd|bd bd 95 fe) fnmsub\. f20,f21,f22,f23
+ 2f8: (fe 95 bd bc|bc bd 95 fe) fnmsub f20,f21,f22,f23
+ 2fc: (ee 95 bd bd|bd bd 95 ee) fnmsubs\. f20,f21,f22,f23
+ 300: (ee 95 bd bc|bc bd 95 ee) fnmsubs f20,f21,f22,f23
+ 304: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
+ 308: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
+ 30c: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
+ 310: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
+ 314: (fe 81 a8 31|31 a8 81 fe) fre\. f20,f21,1
+ 318: (fe 81 a8 30|30 a8 81 fe) fre f20,f21,1
+ 31c: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
+ 320: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
+ 324: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
+ 328: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
+ 32c: (ee 81 a8 31|31 a8 81 ee) fres\. f20,f21,1
+ 330: (ee 81 a8 30|30 a8 81 ee) fres f20,f21,1
+ 334: (fe 80 ab d1|d1 ab 80 fe) frim\. f20,f21
+ 338: (fe 80 ab d0|d0 ab 80 fe) frim f20,f21
+ 33c: (fe 80 ab 11|11 ab 80 fe) frin\. f20,f21
+ 340: (fe 80 ab 10|10 ab 80 fe) frin f20,f21
+ 344: (fe 80 ab 91|91 ab 80 fe) frip\. f20,f21
+ 348: (fe 80 ab 90|90 ab 80 fe) frip f20,f21
+ 34c: (fe 80 ab 51|51 ab 80 fe) friz\. f20,f21
+ 350: (fe 80 ab 50|50 ab 80 fe) friz f20,f21
+ 354: (fe 80 a8 19|19 a8 80 fe) frsp\. f20,f21
+ 358: (fe 80 a8 18|18 a8 80 fe) frsp f20,f21
+ 35c: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
+ 360: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
+ 364: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
+ 368: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
+ 36c: (fe 81 a8 35|35 a8 81 fe) frsqrte\. f20,f21,1
+ 370: (fe 81 a8 34|34 a8 81 fe) frsqrte f20,f21,1
+ 374: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
+ 378: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
+ 37c: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
+ 380: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
+ 384: (ee 81 a8 34|34 a8 81 ee) frsqrtes f20,f21,1
+ 388: (ee 81 a8 35|35 a8 81 ee) frsqrtes\. f20,f21,1
+ 38c: (fe 95 bd af|af bd 95 fe) fsel\. f20,f21,f22,f23
+ 390: (fe 95 bd ae|ae bd 95 fe) fsel f20,f21,f22,f23
+ 394: (fe 80 a8 2d|2d a8 80 fe) fsqrt\. f20,f21
+ 398: (fe 80 a8 2c|2c a8 80 fe) fsqrt f20,f21
+ 39c: (ee 80 a8 2d|2d a8 80 ee) fsqrts\. f20,f21
+ 3a0: (ee 80 a8 2c|2c a8 80 ee) fsqrts f20,f21
+ 3a4: (fe 95 b0 29|29 b0 95 fe) fsub\. f20,f21,f22
+ 3a8: (fe 95 b0 28|28 b0 95 fe) fsub f20,f21,f22
+ 3ac: (ee 95 b0 29|29 b0 95 ee) fsubs\. f20,f21,f22
+ 3b0: (ee 95 b0 28|28 b0 95 ee) fsubs f20,f21,f22
+ 3b4: (7c 0a 5f ac|ac 5f 0a 7c) icbi r10,r11
+ 3b8: (7c 0a 5f be|be 5f 0a 7c) icbiep r10,r11
+ 3bc: (7c 0a 58 2c|2c 58 0a 7c) icbt r10,r11
+ 3c0: (7c ea 58 2c|2c 58 ea 7c) icbt 7,r10,r11
+ 3c4: (7c 0a 5b cc|cc 5b 0a 7c) icbtls r10,r11
+ 3c8: (7c ea 5b cc|cc 5b ea 7c) icbtls 7,r10,r11
+ 3cc: (7c 00 07 8c|8c 07 00 7c) iccci
+ 3d0: (7c 00 07 8c|8c 07 00 7c) iccci
+ 3d4: (7c 00 07 8c|8c 07 00 7c) iccci
+ 3d8: (7d 40 07 8c|8c 07 40 7d) ici 10
+ 3dc: (7d 4b 63 2d|2d 63 4b 7d) icswx\. r10,r11,r12
+ 3e0: (7d 4b 63 2c|2c 63 4b 7d) icswx r10,r11,r12
+ 3e4: (7d 4b 65 de|de 65 4b 7d) isel r10,r11,r12,23
+ 3e8: (4c 00 01 2c|2c 01 00 4c) isync
+ 3ec: (7d 4b 60 be|be 60 4b 7d) lbepx r10,r11,r12
+ 3f0: (89 4b ff ef|ef ff 4b 89) lbz r10,-17\(r11\)
+ 3f4: (89 4b 00 11|11 00 4b 89) lbz r10,17\(r11\)
+ 3f8: (8d 4b ff ff|ff ff 4b 8d) lbzu r10,-1\(r11\)
+ 3fc: (8d 4b 00 01|01 00 4b 8d) lbzu r10,1\(r11\)
+ 400: (7d 4b 68 ee|ee 68 4b 7d) lbzux r10,r11,r13
+ 404: (7d 4b 68 ae|ae 68 4b 7d) lbzx r10,r11,r13
+ 408: (e9 4b ff f8|f8 ff 4b e9) ld r10,-8\(r11\)
+ 40c: (e9 4b 00 08|08 00 4b e9) ld r10,8\(r11\)
+ 410: (7d 4b 60 a8|a8 60 4b 7d) ldarx r10,r11,r12
+ 414: (7d 4b 60 a9|a9 60 4b 7d) ldarx r10,r11,r12,1
+ 418: (7d 4b 64 28|28 64 4b 7d) ldbrx r10,r11,r12
+ 41c: (7d 4b 60 3a|3a 60 4b 7d) ldepx r10,r11,r12
+ 420: (e9 4b ff f9|f9 ff 4b e9) ldu r10,-8\(r11\)
+ 424: (e9 4b 00 09|09 00 4b e9) ldu r10,8\(r11\)
+ 428: (7d 4b 60 6a|6a 60 4b 7d) ldux r10,r11,r12
+ 42c: (7d 4b 60 2a|2a 60 4b 7d) ldx r10,r11,r12
+ 430: (ca 8a ff f8|f8 ff 8a ca) lfd f20,-8\(r10\)
+ 434: (ca 8a 00 08|08 00 8a ca) lfd f20,8\(r10\)
+ 438: (7e 8a 5c be|be 5c 8a 7e) lfdepx f20,r10,r11
+ 43c: (ce 8a ff f8|f8 ff 8a ce) lfdu f20,-8\(r10\)
+ 440: (ce 8a 00 08|08 00 8a ce) lfdu f20,8\(r10\)
+ 444: (7e 8a 5c ee|ee 5c 8a 7e) lfdux f20,r10,r11
+ 448: (7e 8a 5c ae|ae 5c 8a 7e) lfdx f20,r10,r11
+ 44c: (7e 8a 5e ae|ae 5e 8a 7e) lfiwax f20,r10,r11
+ 450: (7e 8a 5e ee|ee 5e 8a 7e) lfiwzx f20,r10,r11
+ 454: (c2 8a ff fc|fc ff 8a c2) lfs f20,-4\(r10\)
+ 458: (c2 8a 00 04|04 00 8a c2) lfs f20,4\(r10\)
+ 45c: (c6 8a ff fc|fc ff 8a c6) lfsu f20,-4\(r10\)
+ 460: (c6 8a 00 04|04 00 8a c6) lfsu f20,4\(r10\)
+ 464: (7e 8a 5c 6e|6e 5c 8a 7e) lfsux f20,r10,r11
+ 468: (7e 8a 5c 2e|2e 5c 8a 7e) lfsx f20,r10,r11
+ 46c: (a9 4b 00 02|02 00 4b a9) lha r10,2\(r11\)
+ 470: (ad 4b ff fe|fe ff 4b ad) lhau r10,-2\(r11\)
+ 474: (7d 4b 62 ee|ee 62 4b 7d) lhaux r10,r11,r12
+ 478: (7d 4b 62 ae|ae 62 4b 7d) lhax r10,r11,r12
+ 47c: (7d 4b 66 2c|2c 66 4b 7d) lhbrx r10,r11,r12
+ 480: (7d 4b 62 3e|3e 62 4b 7d) lhepx r10,r11,r12
+ 484: (a1 4b ff fe|fe ff 4b a1) lhz r10,-2\(r11\)
+ 488: (a1 4b 00 02|02 00 4b a1) lhz r10,2\(r11\)
+ 48c: (a5 4b ff fe|fe ff 4b a5) lhzu r10,-2\(r11\)
+ 490: (a5 4b 00 02|02 00 4b a5) lhzu r10,2\(r11\)
+ 494: (7d 4b 62 6e|6e 62 4b 7d) lhzux r10,r11,r12
+ 498: (7d 4b 62 2e|2e 62 4b 7d) lhzx r10,r11,r12
+ 49c: (ba 8a 00 10|10 00 8a ba) lmw r20,16\(r10\)
+ 4a0: (7d 4b 0c aa|aa 0c 4b 7d) lswi r10,r11,1
+ 4a4: (7d 8b 04 aa|aa 04 8b 7d) lswi r12,r11,32
+ 4a8: (7d 4b 64 2a|2a 64 4b 7d) lswx r10,r11,r12
+ 4ac: (e9 4b ff fe|fe ff 4b e9) lwa r10,-4\(r11\)
+ 4b0: (e9 4b 00 06|06 00 4b e9) lwa r10,4\(r11\)
+ 4b4: (7d 4b 60 28|28 60 4b 7d) lwarx r10,r11,r12
+ 4b8: (7d 4b 60 29|29 60 4b 7d) lwarx r10,r11,r12,1
+ 4bc: (7d 4b 62 ea|ea 62 4b 7d) lwaux r10,r11,r12
+ 4c0: (7d 4b 62 aa|aa 62 4b 7d) lwax r10,r11,r12
+ 4c4: (7d 4b 64 2c|2c 64 4b 7d) lwbrx r10,r11,r12
+ 4c8: (7d 4b 60 3e|3e 60 4b 7d) lwepx r10,r11,r12
+ 4cc: (81 4b ff fc|fc ff 4b 81) lwz r10,-4\(r11\)
+ 4d0: (81 4b 00 04|04 00 4b 81) lwz r10,4\(r11\)
+ 4d4: (85 4b ff fc|fc ff 4b 85) lwzu r10,-4\(r11\)
+ 4d8: (85 4b 00 04|04 00 4b 85) lwzu r10,4\(r11\)
+ 4dc: (7d 4b 60 6e|6e 60 4b 7d) lwzux r10,r11,r12
+ 4e0: (7d 4b 60 2e|2e 60 4b 7d) lwzx r10,r11,r12
+ 4e4: (7c 00 06 ac|ac 06 00 7c) mbar
+ 4e8: (7c 00 06 ac|ac 06 00 7c) mbar
+ 4ec: (7c 00 06 ac|ac 06 00 7c) mbar
+ 4f0: (7c 20 06 ac|ac 06 20 7c) mbar 1
+ 4f4: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
+ 4f8: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
+ 4fc: (7c 00 04 00|00 04 00 7c) mcrxr cr0
+ 500: (7d 80 04 00|00 04 80 7d) mcrxr cr3
+ 504: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 508: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 50c: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+ 510: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ 514: (7d 4a 3a 87|87 3a 4a 7d) mfdcr\. r10,234
+ 518: (7d 4a 3a 86|86 3a 4a 7d) mfdcr r10,234
+ 51c: (7d 4b 02 07|07 02 4b 7d) mfdcrx\. r10,r11
+ 520: (7d 4b 02 06|06 02 4b 7d) mfdcrx r10,r11
+ 524: (fe 80 04 8f|8f 04 80 fe) mffs\. f20
+ 528: (fe 80 04 8e|8e 04 80 fe) mffs f20
+ 52c: (7d 40 00 a6|a6 00 40 7d) mfmsr r10
+ 530: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+ 534: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ 538: (7d 4a 3a a6|a6 3a 4a 7d) mfspr r10,234
+ 53c: (7d 4c 42 e6|e6 42 4c 7d) mftbl r10
+ 540: (7d 4d 42 e6|e6 42 4d 7d) mftbu r10
+ 544: (7c 00 51 dc|dc 51 00 7c) msgclr r10
+ 548: (7c 00 51 9c|9c 51 00 7c) msgsnd r10
+ 54c: (7c 60 01 20|20 01 60 7c) mtcrf 0,r3
+ 550: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+ 554: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 558: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 55c: (7d 4a 3b 87|87 3b 4a 7d) mtdcr\. 234,r10
+ 560: (7d 4a 3b 86|86 3b 4a 7d) mtdcr 234,r10
+ 564: (7d 6a 03 07|07 03 6a 7d) mtdcrx\. r10,r11
+ 568: (7d 6a 03 06|06 03 6a 7d) mtdcrx r10,r11
+ 56c: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. so
+ 570: (fc 60 00 8c|8c 00 60 fc) mtfsb0 so
+ 574: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. so
+ 578: (fc 60 00 4c|4c 00 60 fc) mtfsb1 so
+ 57c: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
+ 580: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
+ 584: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
+ 588: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
+ 58c: (fe 0d a5 8f|8f a5 0d fe) mtfsf\. 6,f20,1,1
+ 590: (fe 0d a5 8e|8e a5 0d fe) mtfsf 6,f20,1,1
+ 594: (ff 00 01 0d|0d 01 00 ff) mtfsfi\. 6,0
+ 598: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ 59c: (ff 00 d1 0d|0d d1 00 ff) mtfsfi\. 6,13
+ 5a0: (ff 00 d1 0c|0c d1 00 ff) mtfsfi 6,13
+ 5a4: (ff 01 d1 0d|0d d1 01 ff) mtfsfi\. 6,13,1
+ 5a8: (ff 01 d1 0c|0c d1 01 ff) mtfsfi 6,13,1
+ 5ac: (7d 40 01 24|24 01 40 7d) mtmsr r10
+ 5b0: (7d 40 01 24|24 01 40 7d) mtmsr r10
+ 5b4: (7d 41 01 24|24 01 41 7d) mtmsr r10,1
+ 5b8: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+ 5bc: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 5c0: (7d 4a 3b a6|a6 3b 4a 7d) mtspr 234,r10
+ 5c4: (7e 95 b0 93|93 b0 95 7e) mulhd\. r20,r21,r22
+ 5c8: (7e 95 b0 92|92 b0 95 7e) mulhd r20,r21,r22
+ 5cc: (7e 95 b0 13|13 b0 95 7e) mulhdu\. r20,r21,r22
+ 5d0: (7e 95 b0 12|12 b0 95 7e) mulhdu r20,r21,r22
+ 5d4: (7e 95 b0 97|97 b0 95 7e) mulhw\. r20,r21,r22
+ 5d8: (7e 95 b0 96|96 b0 95 7e) mulhw r20,r21,r22
+ 5dc: (7e 95 b0 17|17 b0 95 7e) mulhwu\. r20,r21,r22
+ 5e0: (7e 95 b0 16|16 b0 95 7e) mulhwu r20,r21,r22
+ 5e4: (7e 95 b1 d3|d3 b1 95 7e) mulld\. r20,r21,r22
+ 5e8: (7e 95 b1 d2|d2 b1 95 7e) mulld r20,r21,r22
+ 5ec: (7e 95 b5 d3|d3 b5 95 7e) mulldo\. r20,r21,r22
+ 5f0: (7e 95 b5 d2|d2 b5 95 7e) mulldo r20,r21,r22
+ 5f4: (1e 95 00 64|64 00 95 1e) mulli r20,r21,100
+ 5f8: (1e 95 ff 9c|9c ff 95 1e) mulli r20,r21,-100
+ 5fc: (7e 95 b1 d7|d7 b1 95 7e) mullw\. r20,r21,r22
+ 600: (7e 95 b1 d6|d6 b1 95 7e) mullw r20,r21,r22
+ 604: (7e 95 b5 d7|d7 b5 95 7e) mullwo\. r20,r21,r22
+ 608: (7e 95 b5 d6|d6 b5 95 7e) mullwo r20,r21,r22
+ 60c: (7e b4 b3 b9|b9 b3 b4 7e) nand\. r20,r21,r22
+ 610: (7e b4 b3 b8|b8 b3 b4 7e) nand r20,r21,r22
+ 614: (7e 95 00 d1|d1 00 95 7e) neg\. r20,r21
+ 618: (7e 95 00 d0|d0 00 95 7e) neg r20,r21
+ 61c: (7e 95 04 d1|d1 04 95 7e) nego\. r20,r21
+ 620: (7e 95 04 d0|d0 04 95 7e) nego r20,r21
+ 624: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
+ 628: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
+ 62c: (7e b4 b3 79|79 b3 b4 7e) or\. r20,r21,r22
+ 630: (7e b4 b3 78|78 b3 b4 7e) or r20,r21,r22
+ 634: (7e b4 b3 39|39 b3 b4 7e) orc\. r20,r21,r22
+ 638: (7e b4 b3 38|38 b3 b4 7e) orc r20,r21,r22
+ 63c: (62 b4 10 00|00 10 b4 62) ori r20,r21,4096
+ 640: (66 b4 10 00|00 10 b4 66) oris r20,r21,4096
+ 644: (7d 6a 00 f4|f4 00 6a 7d) popcntb r10,r11
+ 648: (7d 6a 03 f4|f4 03 6a 7d) popcntd r10,r11
+ 64c: (7d 6a 02 f4|f4 02 6a 7d) popcntw r10,r11
+ 650: (7d 6a 01 74|74 01 6a 7d) prtyd r10,r11
+ 654: (7d 6a 01 34|34 01 6a 7d) prtyw r10,r11
+ 658: (4c 00 00 66|66 00 00 4c) rfci
+ 65c: (4c 00 00 cc|cc 00 00 4c) rfgi
+ 660: (4c 00 00 64|64 00 00 4c) rfi
+ 664: (4c 00 00 4c|4c 00 00 4c) rfmci
+ 668: (79 6a 67 f1|f1 67 6a 79) rldcl\. r10,r11,r12,63
+ 66c: (79 6a 67 f0|f0 67 6a 79) rldcl r10,r11,r12,63
+ 670: (79 6a 67 f3|f3 67 6a 79) rldcr\. r10,r11,r12,63
+ 674: (79 6a 67 f2|f2 67 6a 79) rldcr r10,r11,r12,63
+ 678: (79 6a bf e9|e9 bf 6a 79) rldic\. r10,r11,23,63
+ 67c: (79 6a bf e8|e8 bf 6a 79) rldic r10,r11,23,63
+ 680: (79 6a bf e1|e1 bf 6a 79) rldicl\. r10,r11,23,63
+ 684: (79 6a bf e0|e0 bf 6a 79) rldicl r10,r11,23,63
+ 688: (79 6a bf e5|e5 bf 6a 79) rldicr\. r10,r11,23,63
+ 68c: (79 6a bf e4|e4 bf 6a 79) rldicr r10,r11,23,63
+ 690: (79 6a bf ed|ed bf 6a 79) rldimi\. r10,r11,23,63
+ 694: (79 6a bf ec|ec bf 6a 79) rldimi r10,r11,23,63
+ 698: (51 6a b8 3f|3f b8 6a 51) rlwimi\. r10,r11,23,0,31
+ 69c: (51 6a b8 3e|3e b8 6a 51) rlwimi r10,r11,23,0,31
+ 6a0: (55 6a b8 3f|3f b8 6a 55) rotlwi\. r10,r11,23
+ 6a4: (55 6a b8 3e|3e b8 6a 55) rotlwi r10,r11,23
+ 6a8: (5d 6a b8 3f|3f b8 6a 5d) rotlw\. r10,r11,r23
+ 6ac: (5d 6a b8 3e|3e b8 6a 5d) rotlw r10,r11,r23
+ 6b0: (44 00 00 02|02 00 00 44) sc
+ 6b4: (44 00 0c 82|82 0c 00 44) sc 100
+ 6b8: (7d 6a 60 37|37 60 6a 7d) sld\. r10,r11,r12
+ 6bc: (7d 6a 60 36|36 60 6a 7d) sld r10,r11,r12
+ 6c0: (7d 6a 60 31|31 60 6a 7d) slw\. r10,r11,r12
+ 6c4: (7d 6a 60 30|30 60 6a 7d) slw r10,r11,r12
+ 6c8: (7d 6a 66 35|35 66 6a 7d) srad\. r10,r11,r12
+ 6cc: (7d 6a 66 34|34 66 6a 7d) srad r10,r11,r12
+ 6d0: (7d 6a fe 77|77 fe 6a 7d) sradi\. r10,r11,63
+ 6d4: (7d 6a fe 76|76 fe 6a 7d) sradi r10,r11,63
+ 6d8: (7d 6a 66 31|31 66 6a 7d) sraw\. r10,r11,r12
+ 6dc: (7d 6a 66 30|30 66 6a 7d) sraw r10,r11,r12
+ 6e0: (7d 6a fe 71|71 fe 6a 7d) srawi\. r10,r11,31
+ 6e4: (7d 6a fe 70|70 fe 6a 7d) srawi r10,r11,31
+ 6e8: (7d 6a 64 37|37 64 6a 7d) srd\. r10,r11,r12
+ 6ec: (7d 6a 64 36|36 64 6a 7d) srd r10,r11,r12
+ 6f0: (7d 6a 64 31|31 64 6a 7d) srw\. r10,r11,r12
+ 6f4: (7d 6a 64 30|30 64 6a 7d) srw r10,r11,r12
+ 6f8: (99 4b ff ff|ff ff 4b 99) stb r10,-1\(r11\)
+ 6fc: (99 4b 00 01|01 00 4b 99) stb r10,1\(r11\)
+ 700: (7d 4b 61 be|be 61 4b 7d) stbepx r10,r11,r12
+ 704: (9d 4b ff ff|ff ff 4b 9d) stbu r10,-1\(r11\)
+ 708: (9d 4b 00 01|01 00 4b 9d) stbu r10,1\(r11\)
+ 70c: (7d 4b 61 ee|ee 61 4b 7d) stbux r10,r11,r12
+ 710: (7d 4b 61 ae|ae 61 4b 7d) stbx r10,r11,r12
+ 714: (f9 4b ff f8|f8 ff 4b f9) std r10,-8\(r11\)
+ 718: (f9 4b 00 08|08 00 4b f9) std r10,8\(r11\)
+ 71c: (7d 4b 65 28|28 65 4b 7d) stdbrx r10,r11,r12
+ 720: (7d 4b 61 ad|ad 61 4b 7d) stdcx\. r10,r11,r12
+ 724: (7d 4b 61 3a|3a 61 4b 7d) stdepx r10,r11,r12
+ 728: (f9 4b ff f9|f9 ff 4b f9) stdu r10,-8\(r11\)
+ 72c: (f9 4b 00 09|09 00 4b f9) stdu r10,8\(r11\)
+ 730: (7d 4b 61 6a|6a 61 4b 7d) stdux r10,r11,r12
+ 734: (7d 4b 61 2a|2a 61 4b 7d) stdx r10,r11,r12
+ 738: (da 8a ff f8|f8 ff 8a da) stfd f20,-8\(r10\)
+ 73c: (da 8a 00 08|08 00 8a da) stfd f20,8\(r10\)
+ 740: (7e 8a 5d be|be 5d 8a 7e) stfdepx f20,r10,r11
+ 744: (de 8a ff f8|f8 ff 8a de) stfdu f20,-8\(r10\)
+ 748: (de 8a 00 08|08 00 8a de) stfdu f20,8\(r10\)
+ 74c: (7e 8a 5d ee|ee 5d 8a 7e) stfdux f20,r10,r11
+ 750: (7e 8a 5d ae|ae 5d 8a 7e) stfdx f20,r10,r11
+ 754: (7e 8a 5f ae|ae 5f 8a 7e) stfiwx f20,r10,r11
+ 758: (d2 8a ff fc|fc ff 8a d2) stfs f20,-4\(r10\)
+ 75c: (d2 8a 00 04|04 00 8a d2) stfs f20,4\(r10\)
+ 760: (d6 8a ff fc|fc ff 8a d6) stfsu f20,-4\(r10\)
+ 764: (d6 8a 00 04|04 00 8a d6) stfsu f20,4\(r10\)
+ 768: (7e 8a 5d 6e|6e 5d 8a 7e) stfsux f20,r10,r11
+ 76c: (7e 8a 5d 2e|2e 5d 8a 7e) stfsx f20,r10,r11
+ 770: (b1 4b ff fe|fe ff 4b b1) sth r10,-2\(r11\)
+ 774: (b1 4b 00 02|02 00 4b b1) sth r10,2\(r11\)
+ 778: (b1 4b ff fc|fc ff 4b b1) sth r10,-4\(r11\)
+ 77c: (b1 4b 00 04|04 00 4b b1) sth r10,4\(r11\)
+ 780: (7d 4b 67 2c|2c 67 4b 7d) sthbrx r10,r11,r12
+ 784: (7d 4b 63 3e|3e 63 4b 7d) sthepx r10,r11,r12
+ 788: (b5 4b ff fe|fe ff 4b b5) sthu r10,-2\(r11\)
+ 78c: (b5 4b 00 02|02 00 4b b5) sthu r10,2\(r11\)
+ 790: (7d 4b 63 6e|6e 63 4b 7d) sthux r10,r11,r12
+ 794: (7d 4b 63 2e|2e 63 4b 7d) sthx r10,r11,r12
+ 798: (be 8a 00 10|10 00 8a be) stmw r20,16\(r10\)
+ 79c: (7d 4b 0d aa|aa 0d 4b 7d) stswi r10,r11,1
+ 7a0: (7d 4b 05 aa|aa 05 4b 7d) stswi r10,r11,32
+ 7a4: (7d 4b 65 2a|2a 65 4b 7d) stswx r10,r11,r12
+ 7a8: (7d 4b 65 2c|2c 65 4b 7d) stwbrx r10,r11,r12
+ 7ac: (7d 4b 61 2d|2d 61 4b 7d) stwcx\. r10,r11,r12
+ 7b0: (7d 4b 61 3e|3e 61 4b 7d) stwepx r10,r11,r12
+ 7b4: (95 4b ff fc|fc ff 4b 95) stwu r10,-4\(r11\)
+ 7b8: (95 4b 00 04|04 00 4b 95) stwu r10,4\(r11\)
+ 7bc: (7d 4b 61 6e|6e 61 4b 7d) stwux r10,r11,r12
+ 7c0: (7d 4b 61 2e|2e 61 4b 7d) stwx r10,r11,r12
+ 7c4: (7e 95 b0 51|51 b0 95 7e) subf\. r20,r21,r22
+ 7c8: (7e 95 b0 50|50 b0 95 7e) subf r20,r21,r22
+ 7cc: (7e 95 b0 11|11 b0 95 7e) subfc\. r20,r21,r22
+ 7d0: (7e 95 b0 10|10 b0 95 7e) subfc r20,r21,r22
+ 7d4: (7e 95 b4 11|11 b4 95 7e) subfco\. r20,r21,r22
+ 7d8: (7e 95 b4 10|10 b4 95 7e) subfco r20,r21,r22
+ 7dc: (7e 95 b1 11|11 b1 95 7e) subfe\. r20,r21,r22
+ 7e0: (7e 95 b1 10|10 b1 95 7e) subfe r20,r21,r22
+ 7e4: (7e 95 b5 11|11 b5 95 7e) subfeo\. r20,r21,r22
+ 7e8: (7e 95 b5 10|10 b5 95 7e) subfeo r20,r21,r22
+ 7ec: (22 95 00 64|64 00 95 22) subfic r20,r21,100
+ 7f0: (22 95 ff 9c|9c ff 95 22) subfic r20,r21,-100
+ 7f4: (7e 95 01 d1|d1 01 95 7e) subfme\. r20,r21
+ 7f8: (7e 95 01 d0|d0 01 95 7e) subfme r20,r21
+ 7fc: (7e 95 05 d1|d1 05 95 7e) subfmeo\. r20,r21
+ 800: (7e 95 05 d0|d0 05 95 7e) subfmeo r20,r21
+ 804: (7e 95 b4 51|51 b4 95 7e) subfo\. r20,r21,r22
+ 808: (7e 95 b4 50|50 b4 95 7e) subfo r20,r21,r22
+ 80c: (7e 95 01 91|91 01 95 7e) subfze\. r20,r21
+ 810: (7e 95 01 90|90 01 95 7e) subfze r20,r21
+ 814: (7e 95 05 91|91 05 95 7e) subfzeo\. r20,r21
+ 818: (7e 95 05 90|90 05 95 7e) subfzeo r20,r21
+ 81c: (7c 00 04 ac|ac 04 00 7c) sync
+ 820: (7c 00 04 ac|ac 04 00 7c) sync
+ 824: (7c 00 04 ac|ac 04 00 7c) sync
+ 828: (7c 20 04 ac|ac 04 20 7c) lwsync
+ 82c: (7c aa 58 88|88 58 aa 7c) tdlge r10,r11
+ 830: (08 aa 00 64|64 00 aa 08) tdlgei r10,100
+ 834: (08 aa ff 9c|9c ff aa 08) tdlgei r10,-100
+ 838: (7c 6a 58 24|24 58 6a 7c) tlbilxva r10,r11
+ 83c: (7c 0a 5e 24|24 5e 0a 7c) tlbivax r10,r11
+ 840: (7c 00 07 64|64 07 00 7c) tlbre
+ 844: (7d 4b 3f 64|64 3f 4b 7d) tlbre r10,r11,7
+ 848: (7c 0a 5e a5|a5 5e 0a 7c) tlbsrx\. r10,r11
+ 84c: (7d 4b 67 25|25 67 4b 7d) tlbsx\. r10,r11,r12
+ 850: (7d 4b 67 24|24 67 4b 7d) tlbsx r10,r11,r12
+ 854: (7c 00 04 6c|6c 04 00 7c) tlbsync
+ 858: (7c 00 07 a4|a4 07 00 7c) tlbwe
+ 85c: (7d 4b 3f a4|a4 3f 4b 7d) tlbwe r10,r11,7
+ 860: (7c aa 58 08|08 58 aa 7c) twlge r10,r11
+ 864: (0c aa 00 64|64 00 aa 0c) twlgei r10,100
+ 868: (0c aa ff 9c|9c ff aa 0c) twlgei r10,-100
+ 86c: (7c 00 00 7c|7c 00 00 7c) wait
+ 870: (7c 00 00 7c|7c 00 00 7c) wait
+ 874: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 878: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 87c: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 880: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 884: (7c 00 01 6c|6c 01 00 7c) wchkall
+ 888: (7c 00 01 6c|6c 01 00 7c) wchkall
+ 88c: (7d 80 01 6c|6c 01 80 7d) wchkall cr3
+ 890: (7c 2a 5f 4c|4c 5f 2a 7c) wclr 1,r10,r11
+ 894: (7c 20 07 4c|4c 07 20 7c) wclrall 1
+ 898: (7c 4a 5f 4c|4c 5f 4a 7c) wclrone r10,r11
+ 89c: (7d 40 01 06|06 01 40 7d) wrtee r10
+ 8a0: (7c 00 81 46|46 81 00 7c) wrteei 1
+ 8a4: (7d 6a 62 79|79 62 6a 7d) xor\. r10,r11,r12
+ 8a8: (7d 6a 62 78|78 62 6a 7d) xor r10,r11,r12
+ 8ac: (69 6a 10 00|00 10 6a 69) xori r10,r11,4096
+ 8b0: (6d 6a 10 00|00 10 6a 6d) xoris r10,r11,4096
- .section ".text"
+ .text
start:
add. 4,5,6
add 4,5,6
#objdump: -dr
#name: AltiVec tests
-.*: +file format elf32-powerpc.*
+.*
Disassembly of section \.text:
00000000 <start>:
- 0: 7c 60 06 6c dss 3
- 4: 7e 00 06 6c dssall
- 8: 7c 25 22 ac dst r5,r4,1
- c: 7e 08 3a ac dstt r8,r7,0
- 10: 7c 65 32 ec dstst r5,r6,3
- 14: 7e 44 2a ec dststt r4,r5,2
+ 0: (7c 60 06 6c|6c 06 60 7c) dss 3
+ 4: (7e 00 06 6c|6c 06 00 7e) dssall
+ 8: (7c 25 22 ac|ac 22 25 7c) dst r5,r4,1
+ c: (7e 08 3a ac|ac 3a 08 7e) dstt r8,r7,0
+ 10: (7c 65 32 ec|ec 32 65 7c) dstst r5,r6,3
+ 14: (7e 44 2a ec|ec 2a 44 7e) dststt r4,r5,2
+ 18: (7f d6 c0 0e|0e c0 d6 7f) lvebx v30,r22,r24
+ 1c: (7e a0 c0 0e|0e c0 a0 7e) lvebx v21,0,r24
+ 20: (7d 50 10 4e|4e 10 50 7d) lvehx v10,r16,r2
+ 24: (7e 80 b8 4e|4e b8 80 7e) lvehx v20,0,r23
+ 28: (7e 24 90 8e|8e 90 24 7e) lvewx v17,r4,r18
+ 2c: (7e e0 40 8e|8e 40 e0 7e) lvewx v23,0,r8
+ 30: (7c c0 c8 0c|0c c8 c0 7c) lvsl v6,0,r25
+ 34: (7c 40 30 0c|0c 30 40 7c) lvsl v2,0,r6
+ 38: (7e d0 60 4c|4c 60 d0 7e) lvsr v22,r16,r12
+ 3c: (7c 00 e8 4c|4c e8 00 7c) lvsr v0,0,r29
+ 40: (7d e5 6a ce|ce 6a e5 7d) lvxl v15,r5,r13
+ 44: (7e 60 ba ce|ce ba 60 7e) lvxl v19,0,r23
+ 48: (7e c1 10 ce|ce 10 c1 7e) lvx v22,r1,r2
+ 4c: (7e 40 88 ce|ce 88 40 7e) lvx v18,0,r17
+ 50: (7f e0 42 a6|a6 42 e0 7f) mfvrsave r31
+ 54: (13 00 06 04|04 06 00 13) mfvscr v24
+ 58: (7d 40 43 a6|a6 43 40 7d) mtvrsave r10
+ 5c: (10 00 ce 44|44 ce 00 10) mtvscr v25
+ 60: (7e 5b 51 0e|0e 51 5b 7e) stvebx v18,r27,r10
+ 64: (7e 00 31 0e|0e 31 00 7e) stvebx v16,0,r6
+ 68: (7e 2d 81 4e|4e 81 2d 7e) stvehx v17,r13,r16
+ 6c: (7e e0 a1 4e|4e a1 e0 7e) stvehx v23,0,r20
+ 70: (7d 73 f9 8e|8e f9 73 7d) stvewx v11,r19,r31
+ 74: (7f e0 09 8e|8e 09 e0 7f) stvewx v31,0,r1
+ 78: (7f 55 8b ce|ce 8b 55 7f) stvxl v26,r21,r17
+ 7c: (7d a0 b3 ce|ce b3 a0 7d) stvxl v13,0,r22
+ 80: (7d 7f f9 ce|ce f9 7f 7d) stvx v11,r31,r31
+ 84: (7f c0 81 ce|ce 81 c0 7f) stvx v30,0,r16
+ 88: (13 07 e1 80|80 e1 07 13) vaddcuw v24,v7,v28
+ 8c: (10 7e 58 0a|0a 58 7e 10) vaddfp v3,v30,v11
+ 90: (11 1c 4b 00|00 4b 1c 11) vaddsbs v8,v28,v9
+ 94: (10 e5 23 40|40 23 e5 10) vaddshs v7,v5,v4
+ 98: (12 da db 80|80 db da 12) vaddsws v22,v26,v27
+ 9c: (12 0e e0 00|00 e0 0e 12) vaddubm v16,v14,v28
+ a0: (10 c1 ca 00|00 ca c1 10) vaddubs v6,v1,v25
+ a4: (10 44 30 40|40 30 44 10) vadduhm v2,v4,v6
+ a8: (13 55 42 40|40 42 55 13) vadduhs v26,v21,v8
+ ac: (13 bf 08 80|80 08 bf 13) vadduwm v29,v31,v1
+ b0: (12 ed 22 80|80 22 ed 12) vadduws v23,v13,v4
+ b4: (13 d0 4c 44|44 4c d0 13) vandc v30,v16,v9
+ b8: (10 6d dc 04|04 dc 6d 10) vand v3,v13,v27
+ bc: (10 86 8d 02|02 8d 86 10) vavgsb v4,v6,v17
+ c0: (12 fc 9d 42|42 9d fc 12) vavgsh v23,v28,v19
+ c4: (11 0f fd 82|82 fd 0f 11) vavgsw v8,v15,v31
+ c8: (10 c7 cc 02|02 cc c7 10) vavgub v6,v7,v25
+ cc: (13 36 54 42|42 54 36 13) vavguh v25,v22,v10
+ d0: (10 77 ec 82|82 ec 77 10) vavguw v3,v23,v29
+ d4: (11 c6 13 ca|ca 13 c6 11) vctsxs v14,v2,6
+ d8: (11 34 fb 8a|8a fb 34 11) vctuxs v9,v31,20
+ dc: (13 03 f3 4a|4a f3 03 13) vcfsx v24,v30,3
+ e0: (12 3d ab 0a|0a ab 3d 12) vcfux v17,v21,29
+ e4: (12 5c 03 c6|c6 03 5c 12) vcmpbfp v18,v28,v0
+ e8: (12 7a 1f c6|c6 1f 7a 12) vcmpbfp\. v19,v26,v3
+ ec: (12 02 58 c6|c6 58 02 12) vcmpeqfp v16,v2,v11
+ f0: (12 ed 6c c6|c6 6c ed 12) vcmpeqfp\. v23,v13,v13
+ f4: (13 33 50 06|06 50 33 13) vcmpequb v25,v19,v10
+ f8: (12 4b 14 06|06 14 4b 12) vcmpequb\. v18,v11,v2
+ fc: (11 39 38 46|46 38 39 11) vcmpequh v9,v25,v7
+ 100: (11 d8 ac 46|46 ac d8 11) vcmpequh\. v14,v24,v21
+ 104: (13 0c 28 86|86 28 0c 13) vcmpequw v24,v12,v5
+ 108: (12 70 0c 86|86 0c 70 12) vcmpequw\. v19,v16,v1
+ 10c: (12 f1 81 c6|c6 81 f1 12) vcmpgefp v23,v17,v16
+ 110: (12 7d 8d c6|c6 8d 7d 12) vcmpgefp\. v19,v29,v17
+ 114: (12 1c 6a c6|c6 6a 1c 12) vcmpgtfp v16,v28,v13
+ 118: (11 d8 3e c6|c6 3e d8 11) vcmpgtfp\. v14,v24,v7
+ 11c: (12 16 33 06|06 33 16 12) vcmpgtsb v16,v22,v6
+ 120: (10 4c 77 06|06 77 4c 10) vcmpgtsb\. v2,v12,v14
+ 124: (13 83 eb 46|46 eb 83 13) vcmpgtsh v28,v3,v29
+ 128: (12 13 6f 46|46 6f 13 12) vcmpgtsh\. v16,v19,v13
+ 12c: (11 e0 2b 86|86 2b e0 11) vcmpgtsw v15,v0,v5
+ 130: (12 ad 07 86|86 07 ad 12) vcmpgtsw\. v21,v13,v0
+ 134: (10 aa f2 06|06 f2 aa 10) vcmpgtub v5,v10,v30
+ 138: (10 ed 56 06|06 56 ed 10) vcmpgtub\. v7,v13,v10
+ 13c: (13 0f 82 46|46 82 0f 13) vcmpgtuh v24,v15,v16
+ 140: (13 35 de 46|46 de 35 13) vcmpgtuh\. v25,v21,v27
+ 144: (12 3b 32 86|86 32 3b 12) vcmpgtuw v17,v27,v6
+ 148: (11 15 de 86|86 de 15 11) vcmpgtuw\. v8,v21,v27
+ 14c: (10 2e 0b 4a|4a 0b 2e 10) vcfsx v1,v1,14
+ 150: (10 99 7b ca|ca 7b 99 10) vctsxs v4,v15,25
+ 154: (13 8e bb 8a|8a bb 8e 13) vctuxs v28,v23,14
+ 158: (10 c0 33 0a|0a 33 c0 10) vcfux v6,v6,0
+ 15c: (10 00 41 8a|8a 41 00 10) vexptefp v0,v8
+ 160: (12 c0 d9 ca|ca d9 c0 12) vlogefp v22,v27
+ 164: (12 f2 91 6e|6e 91 f2 12) vmaddfp v23,v18,v5,v18
+ 168: (11 ad dc 0a|0a dc ad 11) vmaxfp v13,v13,v27
+ 16c: (11 17 71 02|02 71 17 11) vmaxsb v8,v23,v14
+ 170: (12 71 01 42|42 01 71 12) vmaxsh v19,v17,v0
+ 174: (12 63 b1 82|82 b1 63 12) vmaxsw v19,v3,v22
+ 178: (12 fe e0 02|02 e0 fe 12) vmaxub v23,v30,v28
+ 17c: (11 34 b8 42|42 b8 34 11) vmaxuh v9,v20,v23
+ 180: (12 b3 08 82|82 08 b3 12) vmaxuw v21,v19,v1
+ 184: (12 cd 2d a0|a0 2d cd 12) vmhaddshs v22,v13,v5,v22
+ 188: (13 e0 1c a1|a1 1c e0 13) vmhraddshs v31,v0,v3,v18
+ 18c: (10 55 c4 4a|4a c4 55 10) vminfp v2,v21,v24
+ 190: (12 86 53 02|02 53 86 12) vminsb v20,v6,v10
+ 194: (12 5b d3 42|42 d3 5b 12) vminsh v18,v27,v26
+ 198: (10 64 0b 82|82 0b 64 10) vminsw v3,v4,v1
+ 19c: (10 e0 6a 02|02 6a e0 10) vminub v7,v0,v13
+ 1a0: (10 0c 32 42|42 32 0c 10) vminuh v0,v12,v6
+ 1a4: (10 c3 0a 82|82 0a c3 10) vminuw v6,v3,v1
+ 1a8: (10 7d 1e a2|a2 1e 7d 10) vmladduhm v3,v29,v3,v26
+ 1ac: (12 a5 f8 0c|0c f8 a5 12) vmrghb v21,v5,v31
+ 1b0: (12 b8 00 4c|4c 00 b8 12) vmrghh v21,v24,v0
+ 1b4: (12 00 b0 8c|8c b0 00 12) vmrghw v16,v0,v22
+ 1b8: (10 31 81 0c|0c 81 31 10) vmrglb v1,v17,v16
+ 1bc: (11 c8 79 4c|4c 79 c8 11) vmrglh v14,v8,v15
+ 1c0: (13 f5 29 8c|8c 29 f5 13) vmrglw v31,v21,v5
+ 1c4: (13 09 4c 84|84 4c 09 13) vmr v24,v9
+ 1c8: (13 09 4c 84|84 4c 09 13) vmr v24,v9
+ 1cc: (10 18 7d e5|e5 7d 18 10) vmsummbm v0,v24,v15,v23
+ 1d0: (10 24 3e 68|68 3e 24 10) vmsumshm v1,v4,v7,v25
+ 1d4: (11 28 6f e9|e9 6f 28 11) vmsumshs v9,v8,v13,v31
+ 1d8: (12 ff 67 a4|a4 67 ff 12) vmsumubm v23,v31,v12,v30
+ 1dc: (13 a0 d5 66|66 d5 a0 13) vmsumuhm v29,v0,v26,v21
+ 1e0: (13 6e c9 67|67 c9 6e 13) vmsumuhs v27,v14,v25,v5
+ 1e4: (11 59 73 08|08 73 59 11) vmulesb v10,v25,v14
+ 1e8: (10 32 43 48|48 43 32 10) vmulesh v1,v18,v8
+ 1ec: (12 2e 4a 08|08 4a 2e 12) vmuleub v17,v14,v9
+ 1f0: (10 ba 4a 48|48 4a ba 10) vmuleuh v5,v26,v9
+ 1f4: (12 b2 31 08|08 31 b2 12) vmulosb v21,v18,v6
+ 1f8: (10 85 41 48|48 41 85 10) vmulosh v4,v5,v8
+ 1fc: (10 49 98 08|08 98 49 10) vmuloub v2,v9,v19
+ 200: (13 a5 20 48|48 20 a5 13) vmulouh v29,v5,v4
+ 204: (11 02 29 af|af 29 02 11) vnmsubfp v8,v2,v6,v5
+ 208: (13 e9 55 04|04 55 e9 13) vnor v31,v9,v10
+ 20c: (13 3f fd 04|04 fd 3f 13) vnot v25,v31
+ 210: (13 3f fd 04|04 fd 3f 13) vnot v25,v31
+ 214: (12 e7 14 84|84 14 e7 12) vor v23,v7,v2
+ 218: (10 1c b6 6b|6b b6 1c 10) vperm v0,v28,v22,v25
+ 21c: (12 19 8b 0e|0e 8b 19 12) vpkpx v16,v25,v17
+ 220: (11 90 89 8e|8e 89 90 11) vpkshss v12,v16,v17
+ 224: (10 33 b9 0e|0e b9 33 10) vpkshus v1,v19,v23
+ 228: (13 27 69 ce|ce 69 27 13) vpkswss v25,v7,v13
+ 22c: (10 98 51 4e|4e 51 98 10) vpkswus v4,v24,v10
+ 230: (11 3b 60 0e|0e 60 3b 11) vpkuhum v9,v27,v12
+ 234: (12 ca c8 8e|8e c8 ca 12) vpkuhus v22,v10,v25
+ 238: (13 d2 00 4e|4e 00 d2 13) vpkuwum v30,v18,v0
+ 23c: (10 e3 b0 ce|ce b0 e3 10) vpkuwus v7,v3,v22
+ 240: (13 00 e1 0a|0a e1 00 13) vrefp v24,v28
+ 244: (12 20 9a ca|ca 9a 20 12) vrfim v17,v19
+ 248: (13 00 ca 0a|0a ca 00 13) vrfin v24,v25
+ 24c: (10 60 2a 8a|8a 2a 60 10) vrfip v3,v5
+ 250: (11 00 52 4a|4a 52 00 11) vrfiz v8,v10
+ 254: (13 52 f0 04|04 f0 52 13) vrlb v26,v18,v30
+ 258: (12 11 c8 44|44 c8 11 12) vrlh v16,v17,v25
+ 25c: (12 fe 48 84|84 48 fe 12) vrlw v23,v30,v9
+ 260: (10 40 91 4a|4a 91 40 10) vrsqrtefp v2,v18
+ 264: (12 8e 92 aa|aa 92 8e 12) vsel v20,v14,v18,v10
+ 268: (13 39 61 04|04 61 39 13) vslb v25,v25,v12
+ 26c: (11 29 61 ec|ec 61 29 11) vsldoi v9,v9,v12,7
+ 270: (11 c2 59 44|44 59 c2 11) vslh v14,v2,v11
+ 274: (13 c5 34 0c|0c 34 c5 13) vslo v30,v5,v6
+ 278: (12 de 49 c4|c4 49 de 12) vsl v22,v30,v9
+ 27c: (13 5a 19 84|84 19 5a 13) vslw v26,v26,v3
+ 280: (10 26 a2 0c|0c a2 26 10) vspltb v1,v20,6
+ 284: (12 03 92 4c|4c 92 03 12) vsplth v16,v18,3
+ 288: (13 33 03 0c|0c 03 33 13) vspltisb v25,-13
+ 28c: (12 ca 03 4c|4c 03 ca 12) vspltish v22,10
+ 290: (11 ad 03 8c|8c 03 ad 11) vspltisw v13,13
+ 294: (11 22 92 8c|8c 92 22 11) vspltw v9,v18,2
+ 298: (11 d6 03 04|04 03 d6 11) vsrab v14,v22,v0
+ 29c: (11 8c 93 44|44 93 8c 11) vsrah v12,v12,v18
+ 2a0: (10 42 6b 84|84 6b 42 10) vsraw v2,v2,v13
+ 2a4: (10 fb 2a 04|04 2a fb 10) vsrb v7,v27,v5
+ 2a8: (10 eb ea 44|44 ea eb 10) vsrh v7,v11,v29
+ 2ac: (12 5e fc 4c|4c fc 5e 12) vsro v18,v30,v31
+ 2b0: (10 49 e2 c4|c4 e2 49 10) vsr v2,v9,v28
+ 2b4: (10 19 02 84|84 02 19 10) vsrw v0,v25,v0
+ 2b8: (13 02 55 80|80 55 02 13) vsubcuw v24,v2,v10
+ 2bc: (12 d8 a0 4a|4a a0 d8 12) vsubfp v22,v24,v20
+ 2c0: (11 56 6f 00|00 6f 56 11) vsubsbs v10,v22,v13
+ 2c4: (13 11 e7 40|40 e7 11 13) vsubshs v24,v17,v28
+ 2c8: (11 5a 07 80|80 07 5a 11) vsubsws v10,v26,v0
+ 2cc: (12 0b c4 00|00 c4 0b 12) vsububm v16,v11,v24
+ 2d0: (11 75 0e 00|00 0e 75 11) vsububs v11,v21,v1
+ 2d4: (10 cc c4 40|40 c4 cc 10) vsubuhm v6,v12,v24
+ 2d8: (13 cb 4e 40|40 4e cb 13) vsubuhs v30,v11,v9
+ 2dc: (12 74 6c 80|80 6c 74 12) vsubuwm v19,v20,v13
+ 2e0: (12 59 36 80|80 36 59 12) vsubuws v18,v25,v6
+ 2e4: (13 2a 96 88|88 96 2a 13) vsum2sws v25,v10,v18
+ 2e8: (11 b0 af 08|08 af b0 11) vsum4sbs v13,v16,v21
+ 2ec: (12 e8 26 48|48 26 e8 12) vsum4shs v23,v8,v4
+ 2f0: (13 8d f6 08|08 f6 8d 13) vsum4ubs v28,v13,v30
+ 2f4: (12 ca 47 88|88 47 ca 12) vsumsws v22,v10,v8
+ 2f8: (13 00 73 4e|4e 73 00 13) vupkhpx v24,v14
+ 2fc: (10 40 b2 0e|0e b2 40 10) vupkhsb v2,v22
+ 300: (12 00 12 4e|4e 12 00 12) vupkhsh v16,v2
+ 304: (11 40 d3 ce|ce d3 40 11) vupklpx v10,v26
+ 308: (11 e0 e2 8e|8e e2 e0 11) vupklsb v15,v28
+ 30c: (11 00 42 ce|ce 42 00 11) vupklsh v8,v8
+ 310: (13 20 1c c4|c4 1c 20 13) vxor v25,v0,v3
+#pass
# PowerPC AltiVec tests
#as: -m601 -maltivec
- .section ".text"
+ .text
start:
dss 3
dssall
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2
+ lvebx 30,22,24
+ lvebx 21,0,24
+ lvehx 10,16,2
+ lvehx 20,0,23
+ lvewx 17,4,18
+ lvewx 23,0,8
+ lvsl 6,0,25
+ lvsl 2,0,6
+ lvsr 22,16,12
+ lvsr 0,0,29
+ lvxl 15,5,13
+ lvxl 19,0,23
+ lvx 22,1,2
+ lvx 18,0,17
+ mfvrsave 31
+ mfvscr 24
+ mtvrsave 10
+ mtvscr 25
+ stvebx 18,27,10
+ stvebx 16,0,6
+ stvehx 17,13,16
+ stvehx 23,0,20
+ stvewx 11,19,31
+ stvewx 31,0,1
+ stvxl 26,21,17
+ stvxl 13,0,22
+ stvx 11,31,31
+ stvx 30,0,16
+ vaddcuw 24,7,28
+ vaddfp 3,30,11
+ vaddsbs 8,28,9
+ vaddshs 7,5,4
+ vaddsws 22,26,27
+ vaddubm 16,14,28
+ vaddubs 6,1,25
+ vadduhm 2,4,6
+ vadduhs 26,21,8
+ vadduwm 29,31,1
+ vadduws 23,13,4
+ vandc 30,16,9
+ vand 3,13,27
+ vavgsb 4,6,17
+ vavgsh 23,28,19
+ vavgsw 8,15,31
+ vavgub 6,7,25
+ vavguh 25,22,10
+ vavguw 3,23,29
+ vcfpsxws 14,2,6
+ vcfpuxws 9,31,20
+ vcfsx 24,30,3
+ vcfux 17,21,29
+ vcmpbfp 18,28,0
+ vcmpbfp. 19,26,3
+ vcmpeqfp 16,2,11
+ vcmpeqfp. 23,13,13
+ vcmpequb 25,19,10
+ vcmpequb. 18,11,2
+ vcmpequh 9,25,7
+ vcmpequh. 14,24,21
+ vcmpequw 24,12,5
+ vcmpequw. 19,16,1
+ vcmpgefp 23,17,16
+ vcmpgefp. 19,29,17
+ vcmpgtfp 16,28,13
+ vcmpgtfp. 14,24,7
+ vcmpgtsb 16,22,6
+ vcmpgtsb. 2,12,14
+ vcmpgtsh 28,3,29
+ vcmpgtsh. 16,19,13
+ vcmpgtsw 15,0,5
+ vcmpgtsw. 21,13,0
+ vcmpgtub 5,10,30
+ vcmpgtub. 7,13,10
+ vcmpgtuh 24,15,16
+ vcmpgtuh. 25,21,27
+ vcmpgtuw 17,27,6
+ vcmpgtuw. 8,21,27
+ vcsxwfp 1,1,14
+ vctsxs 4,15,25
+ vctuxs 28,23,14
+ vcuxwfp 6,6,0
+ vexptefp 0,8
+ vlogefp 22,27
+ vmaddfp 23,18,5,18
+ vmaxfp 13,13,27
+ vmaxsb 8,23,14
+ vmaxsh 19,17,0
+ vmaxsw 19,3,22
+ vmaxub 23,30,28
+ vmaxuh 9,20,23
+ vmaxuw 21,19,1
+ vmhaddshs 22,13,5,22
+ vmhraddshs 31,0,3,18
+ vminfp 2,21,24
+ vminsb 20,6,10
+ vminsh 18,27,26
+ vminsw 3,4,1
+ vminub 7,0,13
+ vminuh 0,12,6
+ vminuw 6,3,1
+ vmladduhm 3,29,3,26
+ vmrghb 21,5,31
+ vmrghh 21,24,0
+ vmrghw 16,0,22
+ vmrglb 1,17,16
+ vmrglh 14,8,15
+ vmrglw 31,21,5
+ vmr 24,9,
+ vor 24,9,9
+ vmsummbm 0,24,15,23
+ vmsumshm 1,4,7,25
+ vmsumshs 9,8,13,31
+ vmsumubm 23,31,12,30
+ vmsumuhm 29,0,26,21
+ vmsumuhs 27,14,25,5
+ vmulesb 10,25,14
+ vmulesh 1,18,8
+ vmuleub 17,14,9
+ vmuleuh 5,26,9
+ vmulosb 21,18,6
+ vmulosh 4,5,8
+ vmuloub 2,9,19
+ vmulouh 29,5,4
+ vnmsubfp 8,2,6,5
+ vnor 31,9,10
+ vnor 25,31,31
+ vnot 25,31,
+ vor 23,7,2
+ vperm 0,28,22,25
+ vpkpx 16,25,17
+ vpkshss 12,16,17
+ vpkshus 1,19,23
+ vpkswss 25,7,13
+ vpkswus 4,24,10
+ vpkuhum 9,27,12
+ vpkuhus 22,10,25
+ vpkuwum 30,18,0
+ vpkuwus 7,3,22
+ vrefp 24,28
+ vrfim 17,19
+ vrfin 24,25
+ vrfip 3,5
+ vrfiz 8,10
+ vrlb 26,18,30
+ vrlh 16,17,25
+ vrlw 23,30,9
+ vrsqrtefp 2,18
+ vsel 20,14,18,10
+ vslb 25,25,12
+ vsldoi 9,9,12,7
+ vslh 14,2,11
+ vslo 30,5,6
+ vsl 22,30,9
+ vslw 26,26,3
+ vspltb 1,20,6
+ vsplth 16,18,3
+ vspltisb 25,-13
+ vspltish 22,10
+ vspltisw 13,13
+ vspltw 9,18,2
+ vsrab 14,22,0
+ vsrah 12,12,18
+ vsraw 2,2,13
+ vsrb 7,27,5
+ vsrh 7,11,29
+ vsro 18,30,31
+ vsr 2,9,28
+ vsrw 0,25,0
+ vsubcuw 24,2,10
+ vsubfp 22,24,20
+ vsubsbs 10,22,13
+ vsubshs 24,17,28
+ vsubsws 10,26,0
+ vsububm 16,11,24
+ vsububs 11,21,1
+ vsubuhm 6,12,24
+ vsubuhs 30,11,9
+ vsubuwm 19,20,13
+ vsubuws 18,25,6
+ vsum2sws 25,10,18
+ vsum4sbs 13,16,21
+ vsum4shs 23,8,4
+ vsum4ubs 28,13,30
+ vsumsws 22,10,8
+ vupkhpx 24,14
+ vupkhsb 2,22
+ vupkhsh 16,2
+ vupklpx 10,26
+ vupklsb 15,28
+ vupklsh 8,8
+ vxor 25,0,3
#objdump: -d -Maltivec -Mppc64
#name: Check that ISA extensions can be specified before CPU selection
-.*: +file format elf.*-powerpc.*
+.*
Disassembly of section \.text:
0+00 <.*>:
- 0: 7e 00 06 6c dssall
- 4: 7d 00 83 a6 mtspr 512,r8
- 8: 4c 00 00 24 rfid
+ 0: (7e 00 06 6c|6c 06 00 7e) dssall
+ 4: (7d 00 83 a6|a6 83 00 7d) mtspr 512,r8
+ 8: (4c 00 00 24|24 00 00 4c) rfid
+#pass
#objdump: -Dr
#name: PowerPC test 1
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+0000000 <foo>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
0+000000c <a>:
- c:
48 00 00 04 b 10 <apfour>
+ c:
(48 00 00 04|04 00 00 48) b 10 <apfour>
0+0000010 <apfour>:
- 10:
48 00 00 08 b 18 <apfour\+0x8>
- 14: 48 00 00 00 b 14 <apfour\+0x4>
+ 10:
(48 00 00 08|08 00 00 48) b 18 <apfour\+0x8>
+ 14: (48 00 00 00|00 00 00 48) b .*
14: R_PPC_REL24 x
- 18: 48 00 00 04 b 1c <apfour\+0xc>
+ 18: (48 00 00 0.|0. 00 00 48) b .*
18: R_PPC_REL24 \.data\+0x4
- 1c: 48 00 00 00 b 1c <apfour\+0xc>
+ 1c: (48 00 00 00|00 00 00 48) b .*
1c: R_PPC_REL24 z
- 20: 48 00 00 14 b 34 <apfour\+0x24>
+ 20: (48 00 00 ..|.. 00 00 48) b .*
20: R_PPC_REL24 z\+0x14
- 24:
48 00 00 04 b 28 <apfour\+0x18>
- 28: 48 00 00 00 b 28 <apfour\+0x18>
+ 24:
(48 00 00 04|04 00 00 48) b 28 <apfour\+0x18>
+ 28: (48 00 00 00|00 00 00 48) b .*
28: R_PPC_REL24 a
- 2c:
4b ff ff e4 b 10 <apfour>
- 30: 48 00 00 04 b 34 <apfour\+0x24>
+ 2c:
(4b ff ff e4|e4 ff ff 4b) b 10 <apfour>
+ 30: (48 00 00 0.|0. 00 00 48) b .*
30: R_PPC_REL24 a\+0x4
- 34:
4b ff ff e0 b 14 <apfour\+0x4>
- 38: 48 00 00 00 b 38 <apfour\+0x28>
+ 34:
(4b ff ff e0|e0 ff ff 4b) b 14 <apfour\+0x4>
+ 38: (48 00 00 00|00 00 00 48) b .*
38: R_PPC_LOCAL24PC a
- 3c:
4b ff ff d4 b 10 <apfour>
- 40: 00 00 00 40 \.long 0x40
+ 3c:
(4b ff ff d4|d4 ff ff 4b) b 10 <apfour>
+ \.\.\.
40: R_PPC_ADDR32 \.text\+0x40
- 44: 00 00 00 4c \.long 0x4c
44: R_PPC_ADDR32 \.text\+0x4c
- 48: 00 00 00 00 \.long 0x0
48: R_PPC_REL32 x
- 4c: 00 00 00 04 \.long 0x4
4c: R_PPC_REL32 x\+0x4
- 50: 00 00 00 00 \.long 0x0
50: R_PPC_REL32 z
- 54: 00 00 00 04 \.long 0x4
54: R_PPC_REL32 \.data\+0x4
- 58: 00 00 00 00 \.long 0x0
58: R_PPC_ADDR32 x
- 5c: 00 00 00 04 \.long 0x4
5c: R_PPC_ADDR32 \.data\+0x4
- 60: 00 00 00 00 \.long 0x0
60: R_PPC_ADDR32 z
- 64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC_ADDR32 x-0x4
- 68: 00 00 00 00 \.long 0x0
68: R_PPC_ADDR32 \.data
- 6c: ff ff ff fc fnmsub f31,f31,f31,f31
6c: R_PPC_ADDR32 z-0x4
- 70: ff ff ff 9c \.long 0xffffff9c
- 74: ff ff ff 9c \.long 0xffffff9c
- 78: 00 00 00 00 \.long 0x0
+ 70: (ff ff ff 9c|9c ff ff ff) \.long 0xffffff9c
+ 74: (ff ff ff 9c|9c ff ff ff) \.long 0xffffff9c
+ \.\.\.
78: R_PPC_ADDR32 a
- 7c: 00 00 00 10 \.long 0x10
7c: R_PPC_ADDR32 \.text\+0x10
- 80: 00 00 00 10 \.long 0x10
80: R_PPC_ADDR32 \.text\+0x10
- 84: ff ff ff fc fnmsub f31,f31,f31,f31
- 88: 00 00 00 12 \.long 0x12
+ 84: (ff ff ff fc|fc ff ff ff) fnmsub f31,f31,f31,f31
+ \.\.\.
88: R_PPC_ADDR32 \.text\+0x12
- 8c: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
0+0000000 <x>:
-#objdump: -Dr
+#objdump: -Dr -Mppc
#name: PowerPC test 2
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+0000000 <foo>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
- c: 48 00 00 04 b 10 <foo\+0x10>
- 10: 48 00 00 08 b 18 <foo\+0x18>
- 14: 48 00 00 00 b 14 <foo\+0x14>
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
+ c: (48 00 00 04|04 00 00 48) b 10 <foo\+0x10>
+ 10: (48 00 00 08|08 00 00 48) b 18 <foo\+0x18>
+ 14: (48 00 00 00|00 00 00 48) b .*
14: R_PPC_REL24 x
- 18: 48 00 00 04 b 1c <foo\+0x1c>
+ 18: (48 00 00 0.|0. 00 00 48) b .*
18: R_PPC_REL24 \.data\+0x4
- 1c: 48 00 00 00 b 1c <foo\+0x1c>
+ 1c: (48 00 00 00|00 00 00 48) b .*
1c: R_PPC_REL24 z
- 20: 48 00 00 14 b 34 <foo\+0x34>
+ 20: (48 00 00 ..|.. 00 00 48) b .*
20: R_PPC_REL24 z\+0x14
- 24: 48 00 00 04 b 28 <foo\+0x28>
- 28: 48 00 00 00 b 28 <foo\+0x28>
+ 24: (48 00 00 04|04 00 00 48) b 28 <foo\+0x28>
+ 28: (48 00 00 00|00 00 00 48) b .*
28: R_PPC_REL24 a
- 2c:
48 00 00 50 b 7c <apfour>
- 30: 48 00 00 04 b 34 <foo\+0x34>
+ 2c:
(48 00 00 50|50 00 00 48) b 7c <apfour>
+ 30: (48 00 00 0.|0. 00 00 48) b .*
30: R_PPC_REL24 a\+0x4
- 34:
48 00 00 4c b 80 <apfour\+0x4>
- 38: 48 00 00 00 b 38 <foo\+0x38>
+ 34:
(48 00 00 4c|4c 00 00 48) b 80 <apfour\+0x4>
+ 38: (48 00 00 00|00 00 00 48) b .*
38: R_PPC_LOCAL24PC a
- 3c:
48 00 00 40 b 7c <apfour>
- 40: 00 00 00 40 \.long 0x40
+ 3c:
(48 00 00 40|40 00 00 48) b 7c <apfour>
+ \.\.\.
40: R_PPC_ADDR32 \.text\+0x40
- 44: 00 00 00 4c \.long 0x4c
44: R_PPC_ADDR32 \.text\+0x4c
- 48: 00 00 00 00 \.long 0x0
48: R_PPC_REL32 x
- 4c: 00 00 00 04 \.long 0x4
4c: R_PPC_REL32 x\+0x4
- 50: 00 00 00 00 \.long 0x0
50: R_PPC_REL32 z
- 54: 00 00 00 04 \.long 0x4
54: R_PPC_REL32 \.data\+0x4
- 58: 00 00 00 00 \.long 0x0
58: R_PPC_ADDR32 x
- 5c: 00 00 00 04 \.long 0x4
5c: R_PPC_ADDR32 \.data\+0x4
- 60: 00 00 00 00 \.long 0x0
60: R_PPC_ADDR32 z
- 64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC_ADDR32 x-0x4
- 68: 00 00 00 00 \.long 0x0
68: R_PPC_ADDR32 \.data
- 6c: ff ff ff fc fnmsub f31,f31,f31,f31
6c: R_PPC_ADDR32 z-0x4
- 70: 00 00 00 08 \.long 0x8
- 74: 00 00 00 08 \.long 0x8
+ 70: (00 00 00 08|08 00 00 00) \.long 0x8
+ 74: (00 00 00 08|08 00 00 00) \.long 0x8
0+0000078 <a>:
- 78: 00 00 00 00 \.long 0x0
+ 78: (00 00 00 00|00 00 00 00) \.long 0x0
78: R_PPC_ADDR32 a
0+000007c <apfour>:
- 7c: 00 00 00 7c \.long 0x7c
+ \.\.\.
7c: R_PPC_ADDR32 \.text\+0x7c
- 80: 00 00 00 7c \.long 0x7c
80: R_PPC_ADDR32 \.text\+0x7c
- 84: ff ff ff fc fnmsub f31,f31,f31,f31
- 88: 00 00 00 7e \.long 0x7e
+ 84: (ff ff ff fc|fc ff ff ff) fnmsub f31,f31,f31,f31
+ \.\.\.
88: R_PPC_ADDR32 \.text\+0x7e
- 8c: 00 00 00 00 \.long 0x0
- 90: 60 00 00 00 nop
- 94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
- 98: 41 a9 ff f8 bgt- cr2,90 <apfour\+0x14>
- 9c: 40 8d ff f4 ble\+ cr3,90 <apfour\+0x14>
- a0: 41 91 ff f0 bgt\+ cr4,90 <apfour\+0x14>
- a4: 40 95 00 10 ble- cr5,b4 <nop>
- a8: 41 99 00 0c bgt- cr6,b4 <nop>
- ac: 40 bd 00 08 ble\+ cr7,b4 <nop>
- b0: 41 a1 00 04 bgt\+ b4 <nop>
+ 90: (60 00 00 00|00 00 00 60) nop
+ 94: (40 a5 ff fc|fc ff a5 40) ble- cr1,90 <apfour\+0x14>
+ 98: (41 a9 ff f8|f8 ff a9 41) bgt- cr2,90 <apfour\+0x14>
+ 9c: (40 8d ff f4|f4 ff 8d 40) ble\+ cr3,90 <apfour\+0x14>
+ a0: (41 91 ff f0|f0 ff 91 41) bgt\+ cr4,90 <apfour\+0x14>
+ a4: (40 95 00 10|10 00 95 40) ble- cr5,b4 <nop>
+ a8: (41 99 00 0c|0c 00 99 41) bgt- cr6,b4 <nop>
+ ac: (40 bd 00 08|08 00 bd 40) ble\+ cr7,b4 <nop>
+ b0: (41 a1 00 04|04 00 a1 41) bgt\+ b4 <nop>
Disassembly of section \.data:
0+0000000 <x>:
#objdump: -Dr
#name: PowerPC 64-bit test 2
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0000000000000000 <foo>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
- c: 48 00 00 04 b 10 <foo\+0x10>
- 10: 48 00 00 08 b 18 <foo\+0x18>
- 14: 48 00 00 00 b 14 <foo\+0x14>
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
+ c: (48 00 00 04|04 00 00 48) b 10 <foo\+0x10>
+ 10: (48 00 00 08|08 00 00 48) b 18 <foo\+0x18>
+ 14: (48 00 00 00|00 00 00 48) b .*
14: R_PPC64_REL24 x
- 18: 48 00 00 04 b 1c <foo\+0x1c>
+ 18: (48 00 00 0.|0. 00 00 48) b .*
18: R_PPC64_REL24 \.data\+0x4
- 1c: 48 00 00 00 b 1c <foo\+0x1c>
+ 1c: (48 00 00 00|00 00 00 48) b .*
1c: R_PPC64_REL24 z
- 20: 48 00 00 14 b 34 <foo\+0x34>
+ 20: (48 00 00 ..|.. 00 00 48) b .*
20: R_PPC64_REL24 z\+0x14
- 24: 48 00 00 04 b 28 <foo\+0x28>
- 28: 48 00 00 00 b 28 <foo\+0x28>
+ 24: (48 00 00 04|04 00 00 48) b 28 <foo\+0x28>
+ 28: (48 00 00 00|00 00 00 48) b .*
28: R_PPC64_REL24 a
- 2c:
48 00 00 48 b 74 <apfour>
- 30: 48 00 00 04 b 34 <foo\+0x34>
+ 2c:
(48 00 00 48|48 00 00 48) b 74 <apfour>
+ 30: (48 00 00 0.|0. 00 00 48) b .*
30: R_PPC64_REL24 a\+0x4
- 34:
48 00 00 44 b 78 <apfour\+0x4>
- 38: 00 00 00 38 \.long 0x38
+ 34:
(48 00 00 44|44 00 00 48) b 78 <apfour\+0x4>
+ \.\.\.
38: R_PPC64_ADDR32 \.text\+0x38
- 3c: 00 00 00 44 \.long 0x44
3c: R_PPC64_ADDR32 \.text\+0x44
- 40: 00 00 00 00 \.long 0x0
40: R_PPC64_REL32 x
- 44: 00 00 00 04 \.long 0x4
44: R_PPC64_REL32 x\+0x4
- 48: 00 00 00 00 \.long 0x0
48: R_PPC64_REL32 z
- 4c: 00 00 00 04 \.long 0x4
4c: R_PPC64_REL32 \.data\+0x4
- 50: 00 00 00 00 \.long 0x0
50: R_PPC64_ADDR32 x
- 54: 00 00 00 04 \.long 0x4
54: R_PPC64_ADDR32 \.data\+0x4
- 58: 00 00 00 00 \.long 0x0
58: R_PPC64_ADDR32 z
- 5c: ff ff ff fc fnmsub f31,f31,f31,f31
5c: R_PPC64_ADDR32 x-0x4
- 60: 00 00 00 00 \.long 0x0
60: R_PPC64_ADDR32 \.data
- 64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC64_ADDR32 z-0x4
- 68: 00 00 00 08 \.long 0x8
- 6c: 00 00 00 08 \.long 0x8
+ 68: (00 00 00 08|08 00 00 00) \.long 0x8
+ 6c: (00 00 00 08|08 00 00 00) \.long 0x8
0000000000000070 <a>:
- 70: 00 00 00 00 \.long 0x0
+ 70: (00 00 00 00|00 00 00 00) \.long 0x0
70: R_PPC64_ADDR32 a
0000000000000074 <apfour>:
- 74: 00 00 00 74 \.long 0x74
+ \.\.\.
74: R_PPC64_ADDR32 \.text\+0x74
- 78: 00 00 00 74 \.long 0x74
78: R_PPC64_ADDR32 \.text\+0x74
- 7c: ff ff ff fc fnmsub f31,f31,f31,f31
- 80: 00 00 00 76 \.long 0x76
+ 7c: (ff ff ff fc|fc ff ff ff) fnmsub f31,f31,f31,f31
+ \.\.\.
80: R_PPC64_ADDR32 \.text\+0x76
- 84: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
0000000000000000 <x>:
#objdump: -Dr
#name: PowerPC 64-bit test 1
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0000000000000000 <foo>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
000000000000000c <a>:
- c:
48 00 00 04 b 10 <apfour>
+ c:
(48 00 00 04|04 00 00 48) b 10 <apfour>
0000000000000010 <apfour>:
- 10:
48 00 00 08 b 18 <apfour\+0x8>
- 14: 48 00 00 00 b 14 <apfour\+0x4>
+ 10:
(48 00 00 08|08 00 00 48) b 18 <apfour\+0x8>
+ 14: (48 00 00 00|00 00 00 48) b .*
14: R_PPC64_REL24 x
- 18: 48 00 00 04 b 1c <apfour\+0xc>
+ 18: (48 00 00 0.|0. 00 00 48) b .*
18: R_PPC64_REL24 \.data\+0x4
- 1c: 48 00 00 00 b 1c <apfour\+0xc>
+ 1c: (48 00 00 00|00 00 00 48) b .*
1c: R_PPC64_REL24 z
- 20: 48 00 00 14 b 34 <apfour\+0x24>
+ 20: (48 00 00 ..|.. 00 00 48) b .*
20: R_PPC64_REL24 z\+0x14
- 24:
48 00 00 04 b 28 <apfour\+0x18>
- 28: 48 00 00 00 b 28 <apfour\+0x18>
+ 24:
(48 00 00 04|04 00 00 48) b 28 <apfour\+0x18>
+ 28: (48 00 00 00|00 00 00 48) b .*
28: R_PPC64_REL24 a
- 2c:
4b ff ff e4 b 10 <apfour>
- 30: 48 00 00 04 b 34 <apfour\+0x24>
+ 2c:
(4b ff ff e4|e4 ff ff 4b) b 10 <apfour>
+ 30: (48 00 00 0.|0. 00 00 48) b .*
30: R_PPC64_REL24 a\+0x4
- 34:
4b ff ff e0 b 14 <apfour\+0x4>
- 38: 00 00 00 38 \.long 0x38
+ 34:
(4b ff ff e0|e0 ff ff 4b) b 14 <apfour\+0x4>
+ \.\.\.
38: R_PPC64_ADDR32 \.text\+0x38
- 3c: 00 00 00 44 \.long 0x44
3c: R_PPC64_ADDR32 \.text\+0x44
- 40: 00 00 00 00 \.long 0x0
40: R_PPC64_REL32 x
- 44: 00 00 00 04 \.long 0x4
44: R_PPC64_REL32 x\+0x4
- 48: 00 00 00 00 \.long 0x0
48: R_PPC64_REL32 z
- 4c: 00 00 00 04 \.long 0x4
4c: R_PPC64_REL32 \.data\+0x4
- 50: 00 00 00 00 \.long 0x0
50: R_PPC64_ADDR32 x
- 54: 00 00 00 04 \.long 0x4
54: R_PPC64_ADDR32 \.data\+0x4
- 58: 00 00 00 00 \.long 0x0
58: R_PPC64_ADDR32 z
- 5c: ff ff ff fc fnmsub f31,f31,f31,f31
5c: R_PPC64_ADDR32 x-0x4
- 60: 00 00 00 00 \.long 0x0
60: R_PPC64_ADDR32 \.data
- 64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC64_ADDR32 z-0x4
- 68: ff ff ff a4 \.long 0xffffffa4
- 6c: ff ff ff a4 \.long 0xffffffa4
- 70: 00 00 00 00 \.long 0x0
+ 68: (ff ff ff a4|a4 ff ff ff) \.long 0xffffffa4
+ 6c: (ff ff ff a4|a4 ff ff ff) \.long 0xffffffa4
+ \.\.\.
70: R_PPC64_ADDR32 a
- 74: 00 00 00 10 \.long 0x10
74: R_PPC64_ADDR32 \.text\+0x10
- 78: 00 00 00 10 \.long 0x10
78: R_PPC64_ADDR32 \.text\+0x10
- 7c: ff ff ff fc fnmsub f31,f31,f31,f31
- 80: 00 00 00 12 \.long 0x12
+ 7c: (ff ff ff fc|fc ff ff ff) fnmsub f31,f31,f31,f31
+ \.\.\.
80: R_PPC64_ADDR32 \.text\+0x12
- 84: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
0000000000000000 <x>:
#objdump: -dr -Mbooke
#name: BookE tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+0000000 <branch_target_1>:
- 0: 7c a8 48 2c icbt 5,r8,r9
- 4: 7c a6 02 26 mfapidi r5,r6
- 8: 7c 07 46 24 tlbivax r7,r8
- c: 7c 0b 67 24 tlbsx r11,r12
- 10: 7c 00 07 a4 tlbwe
- 14: 7c 00 07 a4 tlbwe
- 18: 7c 21 0f a4 tlbwe r1,r1,1
+ 0: (7c a8 48 2c|2c 48 a8 7c) icbt 5,r8,r9
+ 4: (7c a6 02 26|26 02 a6 7c) mfapidi r5,r6
+ 8: (7c 07 46 24|24 46 07 7c) tlbivax r7,r8
+ c: (7c 0b 67 24|24 67 0b 7c) tlbsx r11,r12
+ 10: (7c 00 07 a4|a4 07 00 7c) tlbwe
+ 14: (7c 00 07 a4|a4 07 00 7c) tlbwe
+ 18: (7c 21 0f a4|a4 0f 21 7c) tlbwe r1,r1,1
0+000001c <branch_target_2>:
- 1c: 4c 00 00 66 rfci
- 20: 7c 60 01 06 wrtee r3
- 24: 7c 00 81 46 wrteei 1
- 28: 7c 85 02 06 mfdcrx r4,r5
- 2c: 7c aa 3a 86 mfdcr r5,234
- 30: 7c e6 03 06 mtdcrx r6,r7
- 34: 7d 10 6b 86 mtdcr 432,r8
- 38: 7c 00 04 ac msync
- 3c: 7c 09 55 ec dcba r9,r10
- 40: 7c 00 06 ac mbar
- 44: 7c 00 06 ac mbar
- 48: 7c 20 06 ac mbar 1
- 4c: 7d 8d 77 24 tlbsx r12,r13,r14
- 50: 7d 8d 77 25 tlbsx\. r12,r13,r14
- 54: 7c 12 42 a6 mfsprg r0,2
- 58: 7c 12 42 a6 mfsprg r0,2
- 5c: 7c 12 43 a6 mtsprg 2,r0
- 60: 7c 12 43 a6 mtsprg 2,r0
- 64: 7c 07 42 a6 mfsprg r0,7
- 68: 7c 07 42 a6 mfsprg r0,7
- 6c: 7c 17 43 a6 mtsprg 7,r0
- 70: 7c 17 43 a6 mtsprg 7,r0
- 74: 7c 05 32 2c dcbt r5,r6
- 78: 7c 05 32 2c dcbt r5,r6
- 7c: 7d 05 32 2c dcbt 8,r5,r6
+ 1c: (4c 00 00 66|66 00 00 4c) rfci
+ 20: (7c 60 01 06|06 01 60 7c) wrtee r3
+ 24: (7c 00 81 46|46 81 00 7c) wrteei 1
+ 28: (7c 85 02 06|06 02 85 7c) mfdcrx r4,r5
+ 2c: (7c aa 3a 86|86 3a aa 7c) mfdcr r5,234
+ 30: (7c e6 03 06|06 03 e6 7c) mtdcrx r6,r7
+ 34: (7d 10 6b 86|86 6b 10 7d) mtdcr 432,r8
+ 38: (7c 00 04 ac|ac 04 00 7c) msync
+ 3c: (7c 09 55 ec|ec 55 09 7c) dcba r9,r10
+ 40: (7c 00 06 ac|ac 06 00 7c) mbar
+ 44: (7c 00 06 ac|ac 06 00 7c) mbar
+ 48: (7c 20 06 ac|ac 06 20 7c) mbar 1
+ 4c: (7d 8d 77 24|24 77 8d 7d) tlbsx r12,r13,r14
+ 50: (7d 8d 77 25|25 77 8d 7d) tlbsx\. r12,r13,r14
+ 54: (7c 12 42 a6|a6 42 12 7c) mfsprg r0,2
+ 58: (7c 12 42 a6|a6 42 12 7c) mfsprg r0,2
+ 5c: (7c 12 43 a6|a6 43 12 7c) mtsprg 2,r0
+ 60: (7c 12 43 a6|a6 43 12 7c) mtsprg 2,r0
+ 64: (7c 07 42 a6|a6 42 07 7c) mfsprg r0,7
+ 68: (7c 07 42 a6|a6 42 07 7c) mfsprg r0,7
+ 6c: (7c 17 43 a6|a6 43 17 7c) mtsprg 7,r0
+ 70: (7c 17 43 a6|a6 43 17 7c) mtsprg 7,r0
+ 74: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+ 78: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+ 7c: (7d 05 32 2c|2c 32 05 7d) dcbt 8,r5,r6
# Motorola PowerPC BookE tests
#as: -mbooke
- .section ".text"
+ .text
branch_target_1:
icbt 5, 8, 9
#name: Cell tests (includes Altivec)
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <.text>:
- 0: 7c 01 14 0e lvlx v0,r1,r2
- 4: 7c 00 14 0e lvlx v0,0,r2
- 8: 7c 01 16 0e lvlxl v0,r1,r2
- c: 7c 00 16 0e lvlxl v0,0,r2
- 10: 7c 01 14 4e lvrx v0,r1,r2
- 14: 7c 00 14 4e lvrx v0,0,r2
- 18: 7c 01 16 4e lvrxl v0,r1,r2
- 1c: 7c 00 16 4e lvrxl v0,0,r2
- 20: 7c 01 15 0e stvlx v0,r1,r2
- 24: 7c 00 15 0e stvlx v0,0,r2
- 28: 7c 01 17 0e stvlxl v0,r1,r2
- 2c: 7c 00 17 0e stvlxl v0,0,r2
- 30: 7c 01 15 4e stvrx v0,r1,r2
- 34: 7c 00 15 4e stvrx v0,0,r2
- 38: 7c 01 17 4e stvrxl v0,r1,r2
- 3c: 7c 00 17 4e stvrxl v0,0,r2
- 40: 7c 00 0c 28 ldbrx r0,0,r1
- 44: 7c 01 14 28 ldbrx r0,r1,r2
- 48: 7c 00 0d 28 stdbrx r0,0,r1
- 4c: 7c 01 15 28 stdbrx r0,r1,r2
- 50: 7c 60 06 6c dss 3
- 54: 7e 00 06 6c dssall
- 58: 7c 25 22 ac dst r5,r4,1
- 5c: 7e 08 3a ac dstt r8,r7,0
- 60: 7c 65 32 ec dstst r5,r6,3
- 64: 7e 44 2a ec dststt r4,r5,2
+ 0: (7c 01 14 0e|0e 14 01 7c) lvlx v0,r1,r2
+ 4: (7c 00 14 0e|0e 14 00 7c) lvlx v0,0,r2
+ 8: (7c 01 16 0e|0e 16 01 7c) lvlxl v0,r1,r2
+ c: (7c 00 16 0e|0e 16 00 7c) lvlxl v0,0,r2
+ 10: (7c 01 14 4e|4e 14 01 7c) lvrx v0,r1,r2
+ 14: (7c 00 14 4e|4e 14 00 7c) lvrx v0,0,r2
+ 18: (7c 01 16 4e|4e 16 01 7c) lvrxl v0,r1,r2
+ 1c: (7c 00 16 4e|4e 16 00 7c) lvrxl v0,0,r2
+ 20: (7c 01 15 0e|0e 15 01 7c) stvlx v0,r1,r2
+ 24: (7c 00 15 0e|0e 15 00 7c) stvlx v0,0,r2
+ 28: (7c 01 17 0e|0e 17 01 7c) stvlxl v0,r1,r2
+ 2c: (7c 00 17 0e|0e 17 00 7c) stvlxl v0,0,r2
+ 30: (7c 01 15 4e|4e 15 01 7c) stvrx v0,r1,r2
+ 34: (7c 00 15 4e|4e 15 00 7c) stvrx v0,0,r2
+ 38: (7c 01 17 4e|4e 17 01 7c) stvrxl v0,r1,r2
+ 3c: (7c 00 17 4e|4e 17 00 7c) stvrxl v0,0,r2
+ 40: (7c 00 0c 28|28 0c 00 7c) ldbrx r0,0,r1
+ 44: (7c 01 14 28|28 14 01 7c) ldbrx r0,r1,r2
+ 48: (7c 00 0d 28|28 0d 00 7c) stdbrx r0,0,r1
+ 4c: (7c 01 15 28|28 15 01 7c) stdbrx r0,r1,r2
+ 50: (7c 60 06 6c|6c 06 60 7c) dss 3
+ 54: (7e 00 06 6c|6c 06 00 7e) dssall
+ 58: (7c 25 22 ac|ac 22 25 7c) dst r5,r4,1
+ 5c: (7e 08 3a ac|ac 3a 08 7e) dstt r8,r7,0
+ 60: (7c 65 32 ec|ec 32 65 7c) dstst r5,r6,3
+ 64: (7e 44 2a ec|ec 2a 44 7e) dststt r4,r5,2
- .section ".text"
+ .text
lvlx %r0, %r1, %r2
lvlx %r0, 0, %r2
lvlxl %r0, %r1, %r2
#as: -a32 -mcom
#name: PowerPC COMMON instructions
-.*: +file format elf32-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 7c 83 28 39 and. r3,r4,r5
- 4: 7c 83 28 38 and r3,r4,r5
- 8: 7d cd 78 78 andc r13,r14,r15
- c: 7e 30 90 79 andc. r16,r17,r18
- 10: 48 00 00 02 ba 0 <start>
- 14: 40 01 00 00 bdnzf- 1,14 <start\+0x14>
- 18: 40 85 00 02 blea- 1,0 <start>
- 1c: 40 43 00 01 bdzfl- 3,1c <start\+0x1c>
- 20: 41 47 00 03 bdztla- 7,0 <start>
- 24: 4e 80 04 20 bctr
- 28: 4e 80 04 21 bctrl
- 2c: 42 40 00 02 bdza- 0 <start>
- 30: 42 40 00 00 bdz- 30 <start\+0x30>
- 34: 42 40 00 03 bdzla- 0 <start>
- 38: 42 40 00 01 bdzl- 38 <start\+0x38>
- 3c: 41 82 00 00 beq- 3c <start\+0x3c>
- 40: 41 8a 00 02 beqa- 2,0 <start>
- 44: 41 86 00 01 beql- 1,44 <start\+0x44>
- 48: 41 8e 00 03 beqla- 3,0 <start>
- 4c: 40 80 00 00 bge- 4c <start\+0x4c>
- 50: 40 90 00 02 bgea- 4,0 <start>
- 54: 40 88 00 01 bgel- 2,54 <start\+0x54>
- 58: 40 98 00 03 bgela- 6,0 <start>
- 5c: 41 91 00 00 bgt- 4,5c <start\+0x5c>
- 60: 41 99 00 02 bgta- 6,0 <start>
- 64: 41 95 00 01 bgtl- 5,64 <start\+0x64>
- 68: 41 9d 00 03 bgtla- 7,0 <start>
- 6c: 48 00 00 00 b 6c <start\+0x6c>
- 70: 48 00 00 03 bla 0 <start>
- 74: 40 81 00 00 ble- 74 <start\+0x74>
- 78: 40 91 00 02 blea- 4,0 <start>
- 7c: 40 89 00 01 blel- 2,7c <start\+0x7c>
- 80: 40 99 00 03 blela- 6,0 <start>
- 84: 48 00 00 01 bl 84 <start\+0x84>
- 88: 41 80 00 00 blt- 88 <start\+0x88>
- 8c: 41 88 00 02 blta- 2,0 <start>
- 90: 41 84 00 01 bltl- 1,90 <start\+0x90>
- 94: 41 8c 00 03 bltla- 3,0 <start>
- 98: 40 82 00 00 bne- 98 <start\+0x98>
- 9c: 40 8a 00 02 bnea- 2,0 <start>
- a0: 40 86 00 01 bnel- 1,a0 <start\+0xa0>
- a4: 40 8e 00 03 bnela- 3,0 <start>
- a8: 40 85 00 00 ble- 1,a8 <start\+0xa8>
- ac: 40 95 00 02 blea- 5,0 <start>
- b0: 40 8d 00 01 blel- 3,b0 <start\+0xb0>
- b4: 40 9d 00 03 blela- 7,0 <start>
- b8: 40 84 00 00 bge- 1,b8 <start\+0xb8>
- bc: 40 94 00 02 bgea- 5,0 <start>
- c0: 40 8c 00 01 bgel- 3,c0 <start\+0xc0>
- c4: 40 9c 00 03 bgela- 7,0 <start>
- c8: 40 93 00 00 bns- 4,c8 <start\+0xc8>
- cc: 40 9b 00 02 bnsa- 6,0 <start>
- d0: 40 97 00 01 bnsl- 5,d0 <start\+0xd0>
- d4: 40 9f 00 03 bnsla- 7,0 <start>
- d8: 41 93 00 00 bso- 4,d8 <start\+0xd8>
- dc: 41 9b 00 02 bsoa- 6,0 <start>
- e0: 41 97 00 01 bsol- 5,e0 <start\+0xe0>
- e4: 41 9f 00 03 bsola- 7,0 <start>
- e8: 4c 85 32 02 crand 4,5,6
- ec: 4c 64 29 02 crandc 3,4,5
- f0: 4c e0 0a 42 creqv 7,0,1
- f4: 4c 22 19 c2 crnand 1,2,3
- f8: 4c 01 10 42 crnor 0,1,2
- fc: 4c a6 3b 82 cror 5,6,7
- 100: 4c 43 23 42 crorc 2,3,4
- 104: 4c c7 01 82 crxor 6,7,0
- 108: 7d 6a 62 39 eqv. r10,r11,r12
- 10c: 7d 6a 62 38 eqv r10,r11,r12
- 110: fe a0 fa 11 fabs. f21,f31
- 114: fe a0 fa 10 fabs f21,f31
- 118: fd 8a 58 40 fcmpo 3,f10,f11
- 11c: fd 84 28 00 fcmpu 3,f4,f5
- 120: fc 60 20 91 fmr. f3,f4
- 124: fc 60 20 90 fmr f3,f4
- 128: fe 80 f1 11 fnabs. f20,f30
- 12c: fe 80 f1 10 fnabs f20,f30
- 130: fc 60 20 51 fneg. f3,f4
- 134: fc 60 20 50 fneg f3,f4
- 138: fc c0 38 18 frsp f6,f7
- 13c: fd 00 48 19 frsp. f8,f9
- 140: 89 21 00 00 lbz r9,0\(r1\)
- 144: 8d 41 00 01 lbzu r10,1\(r1\)
- 148: 7e 95 b0 ee lbzux r20,r21,r22
- 14c: 7c 64 28 ae lbzx r3,r4,r5
- 150: ca a1 00 08 lfd f21,8\(r1\)
- 154: ce c1 00 10 lfdu f22,16\(r1\)
- 158: 7e 95 b4 ee lfdux f20,r21,r22
- 15c: 7d ae 7c ae lfdx f13,r14,r15
- 160: c2 61 00 00 lfs f19,0\(r1\)
- 164: c6 81 00 04 lfsu f20,4\(r1\)
- 168: 7d 4b 64 6e lfsux f10,r11,r12
- 16c: 7d 4b 64 2e lfsx f10,r11,r12
- 170: a9 e1 00 06 lha r15,6\(r1\)
- 174: ae 01 00 08 lhau r16,8\(r1\)
- 178: 7d 2a 5a ee lhaux r9,r10,r11
- 17c: 7d 2a 5a ae lhax r9,r10,r11
- 180: 7c 64 2e 2c lhbrx r3,r4,r5
- 184: a1 a1 00 00 lhz r13,0\(r1\)
- 188: a5 c1 00 02 lhzu r14,2\(r1\)
- 18c: 7e 96 c2 6e lhzux r20,r22,r24
- 190: 7e f8 ca 2e lhzx r23,r24,r25
- 194: 4c 04 00 00 mcrf 0,1
- 198: fd 90 00 80 mcrfs 3,4
- 19c: 7d 80 04 00 mcrxr 3
- 1a0: 7c 60 00 26 mfcr r3
- 1a4: 7c 69 02 a6 mfctr r3
- 1a8: 7c b3 02 a6 mfdar r5
- 1ac: 7c 92 02 a6 mfdsisr r4
- 1b0: ff c0 04 8e mffs f30
- 1b4: ff e0 04 8f mffs. f31
- 1b8: 7c 48 02 a6 mflr r2
- 1bc: 7e 60 00 a6 mfmsr r19
- 1c0: 7c 78 00 26 mfocrf r3,128
- 1c4: 7c 25 02 a6 mfrtcl r1
- 1c8: 7c 04 02 a6 mfrtcu r0
- 1cc: 7c d9 02 a6 mfsdr1 r6
- 1d0: 7c 60 22 a6 mfspr r3,128
- 1d4: 7c fa 02 a6 mfsrr0 r7
- 1d8: 7d 1b 02 a6 mfsrr1 r8
- 1dc: 7f c1 02 a6 mfxer r30
- 1e0: 7f fe fb 79 mr. r30,r31
- 1e4: 7f fe fb 78 mr r30,r31
- 1e8: 7c 6f f1 20 mtcr r3
- 1ec: 7c 68 01 20 mtcrf 128,r3
- 1f0: 7e 69 03 a6 mtctr r19
- 1f4: 7e b3 03 a6 mtdar r21
- 1f8: 7f 16 03 a6 mtdec r24
- 1fc: 7e 92 03 a6 mtdsisr r20
- 200: fc 60 00 8d mtfsb0. 3
- 204: fc 60 00 8c mtfsb0 3
- 208: fc 60 00 4d mtfsb1. 3
- 20c: fc 60 00 4c mtfsb1 3
- 210: fc 0c 55 8e mtfsf 6,f10
- 214: fc 0c 5d 8f mtfsf. 6,f11
- 218: ff 00 01 0c mtfsfi 6,0
- 21c: ff 00 f1 0d mtfsfi. 6,15
- 220: 7e 48 03 a6 mtlr r18
- 224: 7d 40 01 24 mtmsr r10
- 228: 7c 78 01 20 mtocrf 128,r3
- 22c: 7e f5 03 a6 mtrtcl r23
- 230: 7e d4 03 a6 mtrtcu r22
- 234: 7f 39 03 a6 mtsdr1 r25
- 238: 7c 60 23 a6 mtspr 128,r3
- 23c: 7f 5a 03 a6 mtsrr0 r26
- 240: 7f 7b 03 a6 mtsrr1 r27
- 244: 7e 21 03 a6 mtxer r17
- 248: 7f bc f3 b9 nand. r28,r29,r30
- 24c: 7f bc f3 b8 nand r28,r29,r30
- 250: 7c 64 00 d1 neg. r3,r4
- 254: 7c 64 00 d0 neg r3,r4
- 258: 7e 11 04 d0 nego r16,r17
- 25c: 7e 53 04 d1 nego. r18,r19
- 260: 7e b4 b0 f9 nor. r20,r21,r22
- 264: 7e b4 b0 f8 nor r20,r21,r22
- 268: 7e b4 a8 f9 not. r20,r21
- 26c: 7e b4 a8 f8 not r20,r21
- 270: 7c 40 23 78 or r0,r2,r4
- 274: 7d cc 83 79 or. r12,r14,r16
- 278: 7e 0f 8b 38 orc r15,r16,r17
- 27c: 7e 72 a3 39 orc. r18,r19,r20
- 280: 4c 00 00 64 rfi
- 284: 99 61 00 02 stb r11,2\(r1\)
- 288: 9d 81 00 03 stbu r12,3\(r1\)
- 28c: 7d ae 79 ee stbux r13,r14,r15
- 290: 7c 64 29 ae stbx r3,r4,r5
- 294: db 21 00 20 stfd f25,32\(r1\)
- 298: df 41 00 28 stfdu f26,40\(r1\)
- 29c: 7c 01 15 ee stfdux f0,r1,r2
- 2a0: 7f be fd ae stfdx f29,r30,r31
- 2a4: d2 e1 00 14 stfs f23,20\(r1\)
- 2a8: d7 01 00 18 stfsu f24,24\(r1\)
- 2ac: 7f 5b e5 6e stfsux f26,r27,r28
- 2b0: 7e f8 cd 2e stfsx f23,r24,r25
- 2b4: b2 21 00 0a sth r17,10\(r1\)
- 2b8: 7c c7 47 2c sthbrx r6,r7,r8
- 2bc: b6 41 00 0c sthu r18,12\(r1\)
- 2c0: 7e b6 bb 6e sthux r21,r22,r23
- 2c4: 7d 8d 73 2e sthx r12,r13,r14
- 2c8: 7f dd fa 79 xor. r29,r30,r31
- 2cc: 7f dd fa 78 xor r29,r30,r31
- 2d0: 60 00 00 00 nop
- 2d4: 60 00 00 00 nop
- 2d8: 68 00 00 00 xnop
- 2dc: 68 00 00 00 xnop
+ 0: (7c 83 28 39|39 28 83 7c) and. r3,r4,r5
+ 4: (7c 83 28 38|38 28 83 7c) and r3,r4,r5
+ 8: (7d cd 78 78|78 78 cd 7d) andc r13,r14,r15
+ c: (7e 30 90 79|79 90 30 7e) andc. r16,r17,r18
+ 10: (48 00 00 02|02 00 00 48) ba 0 <start>
+ 14: (40 01 00 00|00 00 01 40) bdnzf- 1,14 <start\+0x14>
+ 18: (40 85 00 02|02 00 85 40) blea- 1,0 <start>
+ 1c: (40 43 00 01|01 00 43 40) bdzfl- 3,1c <start\+0x1c>
+ 20: (41 47 00 03|03 00 47 41) bdztla- 7,0 <start>
+ 24: (4e 80 04 20|20 04 80 4e) bctr
+ 28: (4e 80 04 21|21 04 80 4e) bctrl
+ 2c: (42 40 00 02|02 00 40 42) bdza- 0 <start>
+ 30: (42 40 00 00|00 00 40 42) bdz- 30 <start\+0x30>
+ 34: (42 40 00 03|03 00 40 42) bdzla- 0 <start>
+ 38: (42 40 00 01|01 00 40 42) bdzl- 38 <start\+0x38>
+ 3c: (41 82 00 00|00 00 82 41) beq- 3c <start\+0x3c>
+ 40: (41 8a 00 02|02 00 8a 41) beqa- 2,0 <start>
+ 44: (41 86 00 01|01 00 86 41) beql- 1,44 <start\+0x44>
+ 48: (41 8e 00 03|03 00 8e 41) beqla- 3,0 <start>
+ 4c: (40 80 00 00|00 00 80 40) bge- 4c <start\+0x4c>
+ 50: (40 90 00 02|02 00 90 40) bgea- 4,0 <start>
+ 54: (40 88 00 01|01 00 88 40) bgel- 2,54 <start\+0x54>
+ 58: (40 98 00 03|03 00 98 40) bgela- 6,0 <start>
+ 5c: (41 91 00 00|00 00 91 41) bgt- 4,5c <start\+0x5c>
+ 60: (41 99 00 02|02 00 99 41) bgta- 6,0 <start>
+ 64: (41 95 00 01|01 00 95 41) bgtl- 5,64 <start\+0x64>
+ 68: (41 9d 00 03|03 00 9d 41) bgtla- 7,0 <start>
+ 6c: (48 00 00 00|00 00 00 48) b 6c <start\+0x6c>
+ 70: (48 00 00 03|03 00 00 48) bla 0 <start>
+ 74: (40 81 00 00|00 00 81 40) ble- 74 <start\+0x74>
+ 78: (40 91 00 02|02 00 91 40) blea- 4,0 <start>
+ 7c: (40 89 00 01|01 00 89 40) blel- 2,7c <start\+0x7c>
+ 80: (40 99 00 03|03 00 99 40) blela- 6,0 <start>
+ 84: (48 00 00 01|01 00 00 48) bl 84 <start\+0x84>
+ 88: (41 80 00 00|00 00 80 41) blt- 88 <start\+0x88>
+ 8c: (41 88 00 02|02 00 88 41) blta- 2,0 <start>
+ 90: (41 84 00 01|01 00 84 41) bltl- 1,90 <start\+0x90>
+ 94: (41 8c 00 03|03 00 8c 41) bltla- 3,0 <start>
+ 98: (40 82 00 00|00 00 82 40) bne- 98 <start\+0x98>
+ 9c: (40 8a 00 02|02 00 8a 40) bnea- 2,0 <start>
+ a0: (40 86 00 01|01 00 86 40) bnel- 1,a0 <start\+0xa0>
+ a4: (40 8e 00 03|03 00 8e 40) bnela- 3,0 <start>
+ a8: (40 85 00 00|00 00 85 40) ble- 1,a8 <start\+0xa8>
+ ac: (40 95 00 02|02 00 95 40) blea- 5,0 <start>
+ b0: (40 8d 00 01|01 00 8d 40) blel- 3,b0 <start\+0xb0>
+ b4: (40 9d 00 03|03 00 9d 40) blela- 7,0 <start>
+ b8: (40 84 00 00|00 00 84 40) bge- 1,b8 <start\+0xb8>
+ bc: (40 94 00 02|02 00 94 40) bgea- 5,0 <start>
+ c0: (40 8c 00 01|01 00 8c 40) bgel- 3,c0 <start\+0xc0>
+ c4: (40 9c 00 03|03 00 9c 40) bgela- 7,0 <start>
+ c8: (40 93 00 00|00 00 93 40) bns- 4,c8 <start\+0xc8>
+ cc: (40 9b 00 02|02 00 9b 40) bnsa- 6,0 <start>
+ d0: (40 97 00 01|01 00 97 40) bnsl- 5,d0 <start\+0xd0>
+ d4: (40 9f 00 03|03 00 9f 40) bnsla- 7,0 <start>
+ d8: (41 93 00 00|00 00 93 41) bso- 4,d8 <start\+0xd8>
+ dc: (41 9b 00 02|02 00 9b 41) bsoa- 6,0 <start>
+ e0: (41 97 00 01|01 00 97 41) bsol- 5,e0 <start\+0xe0>
+ e4: (41 9f 00 03|03 00 9f 41) bsola- 7,0 <start>
+ e8: (4c 85 32 02|02 32 85 4c) crand 4,5,6
+ ec: (4c 64 29 02|02 29 64 4c) crandc 3,4,5
+ f0: (4c e0 0a 42|42 0a e0 4c) creqv 7,0,1
+ f4: (4c 22 19 c2|c2 19 22 4c) crnand 1,2,3
+ f8: (4c 01 10 42|42 10 01 4c) crnor 0,1,2
+ fc: (4c a6 3b 82|82 3b a6 4c) cror 5,6,7
+ 100: (4c 43 23 42|42 23 43 4c) crorc 2,3,4
+ 104: (4c c7 01 82|82 01 c7 4c) crxor 6,7,0
+ 108: (7d 6a 62 39|39 62 6a 7d) eqv. r10,r11,r12
+ 10c: (7d 6a 62 38|38 62 6a 7d) eqv r10,r11,r12
+ 110: (fe a0 fa 11|11 fa a0 fe) fabs. f21,f31
+ 114: (fe a0 fa 10|10 fa a0 fe) fabs f21,f31
+ 118: (fd 8a 58 40|40 58 8a fd) fcmpo 3,f10,f11
+ 11c: (fd 84 28 00|00 28 84 fd) fcmpu 3,f4,f5
+ 120: (fc 60 20 91|91 20 60 fc) fmr. f3,f4
+ 124: (fc 60 20 90|90 20 60 fc) fmr f3,f4
+ 128: (fe 80 f1 11|11 f1 80 fe) fnabs. f20,f30
+ 12c: (fe 80 f1 10|10 f1 80 fe) fnabs f20,f30
+ 130: (fc 60 20 51|51 20 60 fc) fneg. f3,f4
+ 134: (fc 60 20 50|50 20 60 fc) fneg f3,f4
+ 138: (fc c0 38 18|18 38 c0 fc) frsp f6,f7
+ 13c: (fd 00 48 19|19 48 00 fd) frsp. f8,f9
+ 140: (89 21 00 00|00 00 21 89) lbz r9,0\(r1\)
+ 144: (8d 41 00 01|01 00 41 8d) lbzu r10,1\(r1\)
+ 148: (7e 95 b0 ee|ee b0 95 7e) lbzux r20,r21,r22
+ 14c: (7c 64 28 ae|ae 28 64 7c) lbzx r3,r4,r5
+ 150: (ca a1 00 08|08 00 a1 ca) lfd f21,8\(r1\)
+ 154: (ce c1 00 10|10 00 c1 ce) lfdu f22,16\(r1\)
+ 158: (7e 95 b4 ee|ee b4 95 7e) lfdux f20,r21,r22
+ 15c: (7d ae 7c ae|ae 7c ae 7d) lfdx f13,r14,r15
+ 160: (c2 61 00 00|00 00 61 c2) lfs f19,0\(r1\)
+ 164: (c6 81 00 04|04 00 81 c6) lfsu f20,4\(r1\)
+ 168: (7d 4b 64 6e|6e 64 4b 7d) lfsux f10,r11,r12
+ 16c: (7d 4b 64 2e|2e 64 4b 7d) lfsx f10,r11,r12
+ 170: (a9 e1 00 06|06 00 e1 a9) lha r15,6\(r1\)
+ 174: (ae 01 00 08|08 00 01 ae) lhau r16,8\(r1\)
+ 178: (7d 2a 5a ee|ee 5a 2a 7d) lhaux r9,r10,r11
+ 17c: (7d 2a 5a ae|ae 5a 2a 7d) lhax r9,r10,r11
+ 180: (7c 64 2e 2c|2c 2e 64 7c) lhbrx r3,r4,r5
+ 184: (a1 a1 00 00|00 00 a1 a1) lhz r13,0\(r1\)
+ 188: (a5 c1 00 02|02 00 c1 a5) lhzu r14,2\(r1\)
+ 18c: (7e 96 c2 6e|6e c2 96 7e) lhzux r20,r22,r24
+ 190: (7e f8 ca 2e|2e ca f8 7e) lhzx r23,r24,r25
+ 194: (4c 04 00 00|00 00 04 4c) mcrf 0,1
+ 198: (fd 90 00 80|80 00 90 fd) mcrfs 3,4
+ 19c: (7d 80 04 00|00 04 80 7d) mcrxr 3
+ 1a0: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 1a4: (7c 69 02 a6|a6 02 69 7c) mfctr r3
+ 1a8: (7c b3 02 a6|a6 02 b3 7c) mfdar r5
+ 1ac: (7c 92 02 a6|a6 02 92 7c) mfdsisr r4
+ 1b0: (ff c0 04 8e|8e 04 c0 ff) mffs f30
+ 1b4: (ff e0 04 8f|8f 04 e0 ff) mffs. f31
+ 1b8: (7c 48 02 a6|a6 02 48 7c) mflr r2
+ 1bc: (7e 60 00 a6|a6 00 60 7e) mfmsr r19
+ 1c0: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ 1c4: (7c 25 02 a6|a6 02 25 7c) mfrtcl r1
+ 1c8: (7c 04 02 a6|a6 02 04 7c) mfrtcu r0
+ 1cc: (7c d9 02 a6|a6 02 d9 7c) mfsdr1 r6
+ 1d0: (7c 60 22 a6|a6 22 60 7c) mfspr r3,128
+ 1d4: (7c fa 02 a6|a6 02 fa 7c) mfsrr0 r7
+ 1d8: (7d 1b 02 a6|a6 02 1b 7d) mfsrr1 r8
+ 1dc: (7f c1 02 a6|a6 02 c1 7f) mfxer r30
+ 1e0: (7f fe fb 79|79 fb fe 7f) mr. r30,r31
+ 1e4: (7f fe fb 78|78 fb fe 7f) mr r30,r31
+ 1e8: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 1ec: (7c 68 01 20|20 01 68 7c) mtcrf 128,r3
+ 1f0: (7e 69 03 a6|a6 03 69 7e) mtctr r19
+ 1f4: (7e b3 03 a6|a6 03 b3 7e) mtdar r21
+ 1f8: (7f 16 03 a6|a6 03 16 7f) mtdec r24
+ 1fc: (7e 92 03 a6|a6 03 92 7e) mtdsisr r20
+ 200: (fc 60 00 8d|8d 00 60 fc) mtfsb0. 3
+ 204: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
+ 208: (fc 60 00 4d|4d 00 60 fc) mtfsb1. 3
+ 20c: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
+ 210: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+ 214: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf. 6,f11
+ 218: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ 21c: (ff 00 f1 0d|0d f1 00 ff) mtfsfi. 6,15
+ 220: (7e 48 03 a6|a6 03 48 7e) mtlr r18
+ 224: (7d 40 01 24|24 01 40 7d) mtmsr r10
+ 228: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 22c: (7e f5 03 a6|a6 03 f5 7e) mtrtcl r23
+ 230: (7e d4 03 a6|a6 03 d4 7e) mtrtcu r22
+ 234: (7f 39 03 a6|a6 03 39 7f) mtsdr1 r25
+ 238: (7c 60 23 a6|a6 23 60 7c) mtspr 128,r3
+ 23c: (7f 5a 03 a6|a6 03 5a 7f) mtsrr0 r26
+ 240: (7f 7b 03 a6|a6 03 7b 7f) mtsrr1 r27
+ 244: (7e 21 03 a6|a6 03 21 7e) mtxer r17
+ 248: (7f bc f3 b9|b9 f3 bc 7f) nand. r28,r29,r30
+ 24c: (7f bc f3 b8|b8 f3 bc 7f) nand r28,r29,r30
+ 250: (7c 64 00 d1|d1 00 64 7c) neg. r3,r4
+ 254: (7c 64 00 d0|d0 00 64 7c) neg r3,r4
+ 258: (7e 11 04 d0|d0 04 11 7e) nego r16,r17
+ 25c: (7e 53 04 d1|d1 04 53 7e) nego. r18,r19
+ 260: (7e b4 b0 f9|f9 b0 b4 7e) nor. r20,r21,r22
+ 264: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
+ 268: (7e b4 a8 f9|f9 a8 b4 7e) not. r20,r21
+ 26c: (7e b4 a8 f8|f8 a8 b4 7e) not r20,r21
+ 270: (7c 40 23 78|78 23 40 7c) or r0,r2,r4
+ 274: (7d cc 83 79|79 83 cc 7d) or. r12,r14,r16
+ 278: (7e 0f 8b 38|38 8b 0f 7e) orc r15,r16,r17
+ 27c: (7e 72 a3 39|39 a3 72 7e) orc. r18,r19,r20
+ 280: (4c 00 00 64|64 00 00 4c) rfi
+ 284: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
+ 288: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
+ 28c: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
+ 290: (7c 64 29 ae|ae 29 64 7c) stbx r3,r4,r5
+ 294: (db 21 00 20|20 00 21 db) stfd f25,32\(r1\)
+ 298: (df 41 00 28|28 00 41 df) stfdu f26,40\(r1\)
+ 29c: (7c 01 15 ee|ee 15 01 7c) stfdux f0,r1,r2
+ 2a0: (7f be fd ae|ae fd be 7f) stfdx f29,r30,r31
+ 2a4: (d2 e1 00 14|14 00 e1 d2) stfs f23,20\(r1\)
+ 2a8: (d7 01 00 18|18 00 01 d7) stfsu f24,24\(r1\)
+ 2ac: (7f 5b e5 6e|6e e5 5b 7f) stfsux f26,r27,r28
+ 2b0: (7e f8 cd 2e|2e cd f8 7e) stfsx f23,r24,r25
+ 2b4: (b2 21 00 0a|0a 00 21 b2) sth r17,10\(r1\)
+ 2b8: (7c c7 47 2c|2c 47 c7 7c) sthbrx r6,r7,r8
+ 2bc: (b6 41 00 0c|0c 00 41 b6) sthu r18,12\(r1\)
+ 2c0: (7e b6 bb 6e|6e bb b6 7e) sthux r21,r22,r23
+ 2c4: (7d 8d 73 2e|2e 73 8d 7d) sthx r12,r13,r14
+ 2c8: (7f dd fa 79|79 fa dd 7f) xor. r29,r30,r31
+ 2cc: (7f dd fa 78|78 fa dd 7f) xor r29,r30,r31
+ 2d0: (60 00 00 00|00 00 00 60) nop
+ 2d4: (60 00 00 00|00 00 00 60) nop
+ 2d8: (68 00 00 00|00 00 00 68) xnop
+ 2dc: (68 00 00 00|00 00 00 68) xnop
- .section ".text"
+ .text
start:
and. 3,4,5
and 3,4,5
#objdump: -dr -Me500
#name: e500 tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+0000000 <start>:
- 0: 7c 43 25 de isel r2,r3,r4,23
- 4: 7c 85 33 0c dcblc 4,r5,r6
- 8: 7c e8 49 4c dcbtls 7,r8,r9
- c: 7d 4b 61 0c dcbtstls 10,r11,r12
- 10: 7d ae 7b cc icbtls 13,r14,r15
- 14: 7e 11 91 cc icblc 16,r17,r18
- 18: 7c 89 33 9c mtpmr 201,r4
- 1c: 7c ab 32 9c mfpmr r5,203
- 20: 7c 00 04 0c bblels
- 24: 7c 00 04 4c bbelr
- 28: 7d 00 83 a6 mtspefscr r8
- 2c: 7d 20 82 a6 mfspefscr r9
- 30: 10 a0 22 cf efscfd r5,r4
- 34: 10 a4 02 e4 efdabs r5,r4
- 38: 10 a4 02 e5 efdnabs r5,r4
- 3c: 10 a4 02 e6 efdneg r5,r4
- 40: 10 a4 1a e0 efdadd r5,r4,r3
- 44: 10 a4 1a e1 efdsub r5,r4,r3
- 48: 10 a4 1a e8 efdmul r5,r4,r3
- 4c: 10 a4 1a e9 efddiv r5,r4,r3
- 50: 12 84 1a ec efdcmpgt cr5,r4,r3
- 54: 12 84 1a ed efdcmplt cr5,r4,r3
- 58: 12 84 1a ee efdcmpeq cr5,r4,r3
- 5c: 12 84 1a fc efdtstgt cr5,r4,r3
- 60: 12 84 1a fc efdtstgt cr5,r4,r3
- 64: 12 84 1a fd efdtstlt cr5,r4,r3
- 68: 12 84 1a fe efdtsteq cr5,r4,r3
- 6c: 10 a0 22 f1 efdcfsi r5,r4
- 70: 10 a0 22 e3 efdcfsid r5,r4
- 74: 10 a0 22 f0 efdcfui r5,r4
- 78: 10 a0 22 e2 efdcfuid r5,r4
- 7c: 10 a0 22 f3 efdcfsf r5,r4
- 80: 10 a0 22 f2 efdcfuf r5,r4
- 84: 10 a0 22 f5 efdctsi r5,r4
- 88: 10 a0 22 eb efdctsidz r5,r4
- 8c: 10 a0 22 fa efdctsiz r5,r4
- 90: 10 a0 22 f4 efdctui r5,r4
- 94: 10 a0 22 ea efdctuidz r5,r4
- 98: 10 a0 22 f8 efdctuiz r5,r4
- 9c: 10 a0 22 f7 efdctsf r5,r4
- a0: 10 a0 22 f6 efdctuf r5,r4
- a4: 10 a0 22 ef efdcfs r5,r4
- a8: 7c 20 06 ac mbar 1
- ac: 7c 00 06 ac mbar
- b0: 7c 20 06 ac mbar 1
- b4: 7c 00 04 ac msync
- b8: 7c 00 04 ac msync
+ 0: (7c 43 25 de|de 25 43 7c) isel r2,r3,r4,23
+ 4: (7c 85 33 0c|0c 33 85 7c) dcblc 4,r5,r6
+ 8: (7c e8 49 4c|4c 49 e8 7c) dcbtls 7,r8,r9
+ c: (7d 4b 61 0c|0c 61 4b 7d) dcbtstls 10,r11,r12
+ 10: (7d ae 7b cc|cc 7b ae 7d) icbtls 13,r14,r15
+ 14: (7e 11 91 cc|cc 91 11 7e) icblc 16,r17,r18
+ 18: (7c 89 33 9c|9c 33 89 7c) mtpmr 201,r4
+ 1c: (7c ab 32 9c|9c 32 ab 7c) mfpmr r5,203
+ 20: (7c 00 04 0c|0c 04 00 7c) bblels
+ 24: (7c 00 04 4c|4c 04 00 7c) bbelr
+ 28: (7d 00 83 a6|a6 83 00 7d) mtspefscr r8
+ 2c: (7d 20 82 a6|a6 82 20 7d) mfspefscr r9
+ 30: (10 a0 22 cf|cf 22 a0 10) efscfd r5,r4
+ 34: (10 a4 02 e4|e4 02 a4 10) efdabs r5,r4
+ 38: (10 a4 02 e5|e5 02 a4 10) efdnabs r5,r4
+ 3c: (10 a4 02 e6|e6 02 a4 10) efdneg r5,r4
+ 40: (10 a4 1a e0|e0 1a a4 10) efdadd r5,r4,r3
+ 44: (10 a4 1a e1|e1 1a a4 10) efdsub r5,r4,r3
+ 48: (10 a4 1a e8|e8 1a a4 10) efdmul r5,r4,r3
+ 4c: (10 a4 1a e9|e9 1a a4 10) efddiv r5,r4,r3
+ 50: (12 84 1a ec|ec 1a 84 12) efdcmpgt cr5,r4,r3
+ 54: (12 84 1a ed|ed 1a 84 12) efdcmplt cr5,r4,r3
+ 58: (12 84 1a ee|ee 1a 84 12) efdcmpeq cr5,r4,r3
+ 5c: (12 84 1a fc|fc 1a 84 12) efdtstgt cr5,r4,r3
+ 60: (12 84 1a fc|fc 1a 84 12) efdtstgt cr5,r4,r3
+ 64: (12 84 1a fd|fd 1a 84 12) efdtstlt cr5,r4,r3
+ 68: (12 84 1a fe|fe 1a 84 12) efdtsteq cr5,r4,r3
+ 6c: (10 a0 22 f1|f1 22 a0 10) efdcfsi r5,r4
+ 70: (10 a0 22 e3|e3 22 a0 10) efdcfsid r5,r4
+ 74: (10 a0 22 f0|f0 22 a0 10) efdcfui r5,r4
+ 78: (10 a0 22 e2|e2 22 a0 10) efdcfuid r5,r4
+ 7c: (10 a0 22 f3|f3 22 a0 10) efdcfsf r5,r4
+ 80: (10 a0 22 f2|f2 22 a0 10) efdcfuf r5,r4
+ 84: (10 a0 22 f5|f5 22 a0 10) efdctsi r5,r4
+ 88: (10 a0 22 eb|eb 22 a0 10) efdctsidz r5,r4
+ 8c: (10 a0 22 fa|fa 22 a0 10) efdctsiz r5,r4
+ 90: (10 a0 22 f4|f4 22 a0 10) efdctui r5,r4
+ 94: (10 a0 22 ea|ea 22 a0 10) efdctuidz r5,r4
+ 98: (10 a0 22 f8|f8 22 a0 10) efdctuiz r5,r4
+ 9c: (10 a0 22 f7|f7 22 a0 10) efdctsf r5,r4
+ a0: (10 a0 22 f6|f6 22 a0 10) efdctuf r5,r4
+ a4: (10 a0 22 ef|ef 22 a0 10) efdcfs r5,r4
+ a8: (7c 20 06 ac|ac 06 20 7c) mbar 1
+ ac: (7c 00 06 ac|ac 06 00 7c) mbar
+ b0: (7c 20 06 ac|ac 06 20 7c) mbar 1
+ b4: (7c 00 04 ac|ac 04 00 7c) msync
+ b8: (7c 00 04 ac|ac 04 00 7c) msync
+#pass
# Motorola PowerPC e500 tests
- .section ".text"
+ .text
start:
isel 2, 3, 4, 23
dcblc 4, 5, 6
#objdump: -dr -Me500mc
#name: Power E500MC tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 4c 00 00 4e rfdi
- 4: 4c 00 00 cc rfgi
- 8: 4c 1f f9 8c dnh 0,1023
- c: 4f e0 01 8c dnh 31,0
- 10: 7c 09 57 be icbiep r9,r10
- 14: 7c 00 69 dc msgclr r13
- 18: 7c 00 71 9c msgsnd r14
- 1c: 7c 00 00 7c wait
- 20: 7c 00 00 7c wait
- 24: 7c 20 00 7c waitrsv
- 28: 7c 20 00 7c waitrsv
- 2c: 7c 40 00 7c waitimpl
- 30: 7c 40 00 7c waitimpl
- 34: 7f 9c e3 78 mdors
- 38: 7c 00 02 1c ehpriv
- 3c: 7c 18 cb c6 dsn r24,r25
- 40: 7c 22 18 be lbepx r1,r2,r3
- 44: 7c 85 32 3e lhepx r4,r5,r6
- 48: 7c e8 48 3e lwepx r7,r8,r9
- 4c: 7d 4b 60 3a ldepx r10,r11,r12
- 50: 7d ae 7c be lfdepx f13,r14,r15
- 54: 7e 11 91 be stbepx r16,r17,r18
- 58: 7e 74 ab 3e sthepx r19,r20,r21
- 5c: 7e d7 c1 3e stwepx r22,r23,r24
- 60: 7f 3a d9 3a stdepx r25,r26,r27
- 64: 7f 9d f5 be stfdepx f28,r29,r30
- 68: 7c 01 14 06 lbdx r0,r1,r2
- 6c: 7d 8d 74 46 lhdx r12,r13,r14
- 70: 7c 64 2c 86 lwdx r3,r4,r5
- 74: 7f 5b e6 46 lfddx f26,r27,r28
- 78: 7d f0 8c c6 lddx r15,r16,r17
- 7c: 7c c7 45 06 stbdx r6,r7,r8
- 80: 7e 53 a5 46 sthdx r18,r19,r20
- 84: 7d 2a 5d 86 stwdx r9,r10,r11
- 88: 7f be ff 46 stfddx f29,r30,r31
- 8c: 7e b6 bd c6 stddx r21,r22,r23
- 90: 7c 20 0d ec dcbal 0,r1
- 94: 7c 26 3f ec dcbzl r6,r7
- 98: 7c 1f 00 7e dcbstep r31,r0
- 9c: 7c 01 10 fe dcbfep r1,r2
- a0: 7c 64 29 fe dcbtstep r3,r4,r5
- a4: 7c c7 42 7e dcbtep r6,r7,r8
- a8: 7c 0b 67 fe dcbzep r11,r12
- ac: 7c 00 00 24 tlbilxlpid
- b0: 7c 20 00 24 tlbilxpid
- b4: 7c 62 18 24 tlbilxva r2,r3
- b8: 7c 64 28 24 tlbilxva r4,r5
+ 0: (4c 00 00 4e|4e 00 00 4c) rfdi
+ 4: (4c 00 00 cc|cc 00 00 4c) rfgi
+ 8: (4c 1f f9 8c|8c f9 1f 4c) dnh 0,1023
+ c: (4f e0 01 8c|8c 01 e0 4f) dnh 31,0
+ 10: (7c 09 57 be|be 57 09 7c) icbiep r9,r10
+ 14: (7c 00 69 dc|dc 69 00 7c) msgclr r13
+ 18: (7c 00 71 9c|9c 71 00 7c) msgsnd r14
+ 1c: (7c 00 00 7c|7c 00 00 7c) wait
+ 20: (7c 00 00 7c|7c 00 00 7c) wait
+ 24: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 28: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 2c: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 30: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 34: (7f 9c e3 78|78 e3 9c 7f) mdors
+ 38: (7c 00 02 1c|1c 02 00 7c) ehpriv
+ 3c: (7c 18 cb c6|c6 cb 18 7c) dsn r24,r25
+ 40: (7c 22 18 be|be 18 22 7c) lbepx r1,r2,r3
+ 44: (7c 85 32 3e|3e 32 85 7c) lhepx r4,r5,r6
+ 48: (7c e8 48 3e|3e 48 e8 7c) lwepx r7,r8,r9
+ 4c: (7d 4b 60 3a|3a 60 4b 7d) ldepx r10,r11,r12
+ 50: (7d ae 7c be|be 7c ae 7d) lfdepx f13,r14,r15
+ 54: (7e 11 91 be|be 91 11 7e) stbepx r16,r17,r18
+ 58: (7e 74 ab 3e|3e ab 74 7e) sthepx r19,r20,r21
+ 5c: (7e d7 c1 3e|3e c1 d7 7e) stwepx r22,r23,r24
+ 60: (7f 3a d9 3a|3a d9 3a 7f) stdepx r25,r26,r27
+ 64: (7f 9d f5 be|be f5 9d 7f) stfdepx f28,r29,r30
+ 68: (7c 01 14 06|06 14 01 7c) lbdx r0,r1,r2
+ 6c: (7d 8d 74 46|46 74 8d 7d) lhdx r12,r13,r14
+ 70: (7c 64 2c 86|86 2c 64 7c) lwdx r3,r4,r5
+ 74: (7f 5b e6 46|46 e6 5b 7f) lfddx f26,r27,r28
+ 78: (7d f0 8c c6|c6 8c f0 7d) lddx r15,r16,r17
+ 7c: (7c c7 45 06|06 45 c7 7c) stbdx r6,r7,r8
+ 80: (7e 53 a5 46|46 a5 53 7e) sthdx r18,r19,r20
+ 84: (7d 2a 5d 86|86 5d 2a 7d) stwdx r9,r10,r11
+ 88: (7f be ff 46|46 ff be 7f) stfddx f29,r30,r31
+ 8c: (7e b6 bd c6|c6 bd b6 7e) stddx r21,r22,r23
+ 90: (7c 20 0d ec|ec 0d 20 7c) dcbal 0,r1
+ 94: (7c 26 3f ec|ec 3f 26 7c) dcbzl r6,r7
+ 98: (7c 1f 00 7e|7e 00 1f 7c) dcbstep r31,r0
+ 9c: (7c 01 10 fe|fe 10 01 7c) dcbfep r1,r2
+ a0: (7c 64 29 fe|fe 29 64 7c) dcbtstep r3,r4,r5
+ a4: (7c c7 42 7e|7e 42 c7 7c) dcbtep r6,r7,r8
+ a8: (7c 0b 67 fe|fe 67 0b 7c) dcbzep r11,r12
+ ac: (7c 00 00 24|24 00 00 7c) tlbilxlpid
+ b0: (7c 20 00 24|24 00 20 7c) tlbilxpid
+ b4: (7c 62 18 24|24 18 62 7c) tlbilxva r2,r3
+ b8: (7c 64 28 24|24 28 64 7c) tlbilxva r4,r5
+#pass
# Power E500MC tests
- .section ".text"
+ .text
start:
rfdi
rfgi
#objdump: -dr -Me500mc64
#name: Power E500MC64 nop tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
- c: 60 00 00 00 nop
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
+ c: (60 00 00 00|00 00 00 60) nop
# Power E500MC64 nop tests
- .section ".text"
+ .text
start:
nop
.p2align 4,,15
#objdump: -dr -Me5500
#name: Power E5500 nop tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
- c: 60 00 00 00 nop
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
+ c: (60 00 00 00|00 00 00 60) nop
# Power E5500 nop tests
- .section ".text"
+ .text
start:
nop
.p2align 4,,15
#objdump: -dr -Me6500
#name: Power E6500 tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 10 01 14 03 vabsdub v0,v1,v2
- 4: 10 01 14 43 vabsduh v0,v1,v2
- 8: 10 01 14 83 vabsduw v0,v1,v2
- c: 7c 01 10 dc mvidsplt v0,r1,r2
- 10: 7c 01 10 5c mviwsplt v0,r1,r2
- 14: 7c 00 12 0a lvexbx v0,0,r2
- 18: 7c 01 12 0a lvexbx v0,r1,r2
- 1c: 7c 00 12 4a lvexhx v0,0,r2
- 20: 7c 01 12 4a lvexhx v0,r1,r2
- 24: 7c 00 12 8a lvexwx v0,0,r2
- 28: 7c 01 12 8a lvexwx v0,r1,r2
- 2c: 7c 00 13 0a stvexbx v0,0,r2
- 30: 7c 01 13 0a stvexbx v0,r1,r2
- 34: 7c 00 13 4a stvexhx v0,0,r2
- 38: 7c 01 13 4a stvexhx v0,r1,r2
- 3c: 7c 00 13 8a stvexwx v0,0,r2
- 40: 7c 01 13 8a stvexwx v0,r1,r2
- 44: 7c 00 12 4e lvepx v0,0,r2
- 48: 7c 01 12 4e lvepx v0,r1,r2
- 4c: 7c 00 12 0e lvepxl v0,0,r2
- 50: 7c 01 12 0e lvepxl v0,r1,r2
- 54: 7c 00 16 4e stvepx v0,0,r2
- 58: 7c 01 16 4e stvepx v0,r1,r2
- 5c: 7c 00 16 0e stvepxl v0,0,r2
- 60: 7c 01 16 0e stvepxl v0,r1,r2
- 64: 7c 00 14 8a lvtlx v0,0,r2
- 68: 7c 01 14 8a lvtlx v0,r1,r2
- 6c: 7c 00 16 8a lvtlxl v0,0,r2
- 70: 7c 01 16 8a lvtlxl v0,r1,r2
- 74: 7c 00 14 4a lvtrx v0,0,r2
- 78: 7c 01 14 4a lvtrx v0,r1,r2
- 7c: 7c 00 16 4a lvtrxl v0,0,r2
- 80: 7c 01 16 4a lvtrxl v0,r1,r2
- 84: 7c 00 15 8a stvflx v0,0,r2
- 88: 7c 01 15 8a stvflx v0,r1,r2
- 8c: 7c 00 17 8a stvflxl v0,0,r2
- 90: 7c 01 17 8a stvflxl v0,r1,r2
- 94: 7c 00 15 4a stvfrx v0,0,r2
- 98: 7c 01 15 4a stvfrx v0,r1,r2
- 9c: 7c 00 17 4a stvfrxl v0,0,r2
- a0: 7c 01 17 4a stvfrxl v0,r1,r2
- a4: 7c 00 14 ca lvswx v0,0,r2
- a8: 7c 01 14 ca lvswx v0,r1,r2
- ac: 7c 00 16 ca lvswxl v0,0,r2
- b0: 7c 01 16 ca lvswxl v0,r1,r2
- b4: 7c 00 15 ca stvswx v0,0,r2
- b8: 7c 01 15 ca stvswx v0,r1,r2
- bc: 7c 00 17 ca stvswxl v0,0,r2
- c0: 7c 01 17 ca stvswxl v0,r1,r2
- c4: 7c 00 16 0a lvsm v0,0,r2
- c8: 7c 01 16 0a lvsm v0,r1,r2
- cc: 7f 5a d3 78 miso
- d0: 7c 00 04 ac sync
- d4: 7c 00 04 ac sync
- d8: 7c 20 04 ac lwsync
- dc: 7c 00 04 ac sync
- e0: 7c 07 04 ac sync 0,7
- e4: 7c 28 04 ac sync 1,8
- e8: 7c 00 00 c3 dni 0,0
- ec: 7f ff 00 c3 dni 31,31
- f0: 7c 40 0b 4d dcblq. 2,0,r1
- f4: 7c 43 0b 4d dcblq. 2,r3,r1
- f8: 7c 40 09 8d icblq. 2,0,r1
- fc: 7c 43 09 8d icblq. 2,r3,r1
- 100: 7c 10 02 dc mftmr r0,16
- 104: 7c 10 03 dc mttmr 16,r0
+ 0: (10 01 14 03|03 14 01 10) vabsdub v0,v1,v2
+ 4: (10 01 14 43|43 14 01 10) vabsduh v0,v1,v2
+ 8: (10 01 14 83|83 14 01 10) vabsduw v0,v1,v2
+ c: (7c 01 10 dc|dc 10 01 7c) mvidsplt v0,r1,r2
+ 10: (7c 01 10 5c|5c 10 01 7c) mviwsplt v0,r1,r2
+ 14: (7c 00 12 0a|0a 12 00 7c) lvexbx v0,0,r2
+ 18: (7c 01 12 0a|0a 12 01 7c) lvexbx v0,r1,r2
+ 1c: (7c 00 12 4a|4a 12 00 7c) lvexhx v0,0,r2
+ 20: (7c 01 12 4a|4a 12 01 7c) lvexhx v0,r1,r2
+ 24: (7c 00 12 8a|8a 12 00 7c) lvexwx v0,0,r2
+ 28: (7c 01 12 8a|8a 12 01 7c) lvexwx v0,r1,r2
+ 2c: (7c 00 13 0a|0a 13 00 7c) stvexbx v0,0,r2
+ 30: (7c 01 13 0a|0a 13 01 7c) stvexbx v0,r1,r2
+ 34: (7c 00 13 4a|4a 13 00 7c) stvexhx v0,0,r2
+ 38: (7c 01 13 4a|4a 13 01 7c) stvexhx v0,r1,r2
+ 3c: (7c 00 13 8a|8a 13 00 7c) stvexwx v0,0,r2
+ 40: (7c 01 13 8a|8a 13 01 7c) stvexwx v0,r1,r2
+ 44: (7c 00 12 4e|4e 12 00 7c) lvepx v0,0,r2
+ 48: (7c 01 12 4e|4e 12 01 7c) lvepx v0,r1,r2
+ 4c: (7c 00 12 0e|0e 12 00 7c) lvepxl v0,0,r2
+ 50: (7c 01 12 0e|0e 12 01 7c) lvepxl v0,r1,r2
+ 54: (7c 00 16 4e|4e 16 00 7c) stvepx v0,0,r2
+ 58: (7c 01 16 4e|4e 16 01 7c) stvepx v0,r1,r2
+ 5c: (7c 00 16 0e|0e 16 00 7c) stvepxl v0,0,r2
+ 60: (7c 01 16 0e|0e 16 01 7c) stvepxl v0,r1,r2
+ 64: (7c 00 14 8a|8a 14 00 7c) lvtlx v0,0,r2
+ 68: (7c 01 14 8a|8a 14 01 7c) lvtlx v0,r1,r2
+ 6c: (7c 00 16 8a|8a 16 00 7c) lvtlxl v0,0,r2
+ 70: (7c 01 16 8a|8a 16 01 7c) lvtlxl v0,r1,r2
+ 74: (7c 00 14 4a|4a 14 00 7c) lvtrx v0,0,r2
+ 78: (7c 01 14 4a|4a 14 01 7c) lvtrx v0,r1,r2
+ 7c: (7c 00 16 4a|4a 16 00 7c) lvtrxl v0,0,r2
+ 80: (7c 01 16 4a|4a 16 01 7c) lvtrxl v0,r1,r2
+ 84: (7c 00 15 8a|8a 15 00 7c) stvflx v0,0,r2
+ 88: (7c 01 15 8a|8a 15 01 7c) stvflx v0,r1,r2
+ 8c: (7c 00 17 8a|8a 17 00 7c) stvflxl v0,0,r2
+ 90: (7c 01 17 8a|8a 17 01 7c) stvflxl v0,r1,r2
+ 94: (7c 00 15 4a|4a 15 00 7c) stvfrx v0,0,r2
+ 98: (7c 01 15 4a|4a 15 01 7c) stvfrx v0,r1,r2
+ 9c: (7c 00 17 4a|4a 17 00 7c) stvfrxl v0,0,r2
+ a0: (7c 01 17 4a|4a 17 01 7c) stvfrxl v0,r1,r2
+ a4: (7c 00 14 ca|ca 14 00 7c) lvswx v0,0,r2
+ a8: (7c 01 14 ca|ca 14 01 7c) lvswx v0,r1,r2
+ ac: (7c 00 16 ca|ca 16 00 7c) lvswxl v0,0,r2
+ b0: (7c 01 16 ca|ca 16 01 7c) lvswxl v0,r1,r2
+ b4: (7c 00 15 ca|ca 15 00 7c) stvswx v0,0,r2
+ b8: (7c 01 15 ca|ca 15 01 7c) stvswx v0,r1,r2
+ bc: (7c 00 17 ca|ca 17 00 7c) stvswxl v0,0,r2
+ c0: (7c 01 17 ca|ca 17 01 7c) stvswxl v0,r1,r2
+ c4: (7c 00 16 0a|0a 16 00 7c) lvsm v0,0,r2
+ c8: (7c 01 16 0a|0a 16 01 7c) lvsm v0,r1,r2
+ cc: (7f 5a d3 78|78 d3 5a 7f) miso
+ d0: (7c 00 04 ac|ac 04 00 7c) sync
+ d4: (7c 00 04 ac|ac 04 00 7c) sync
+ d8: (7c 20 04 ac|ac 04 20 7c) lwsync
+ dc: (7c 00 04 ac|ac 04 00 7c) sync
+ e0: (7c 07 04 ac|ac 04 07 7c) sync 0,7
+ e4: (7c 28 04 ac|ac 04 28 7c) sync 1,8
+ e8: (7c 00 00 c3|c3 00 00 7c) dni 0,0
+ ec: (7f ff 00 c3|c3 00 ff 7f) dni 31,31
+ f0: (7c 40 0b 4d|4d 0b 40 7c) dcblq. 2,0,r1
+ f4: (7c 43 0b 4d|4d 0b 43 7c) dcblq. 2,r3,r1
+ f8: (7c 40 09 8d|8d 09 40 7c) icblq. 2,0,r1
+ fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1
+ 100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16
+ 104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0
# Power E6500 tests
- .section ".text"
+ .text
start:
vabsdub 0, 1, 2
vabsduh 0, 1, 2
#objdump: -dr -Me6500
#name: Power E6500 nop tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 60 00 00 00 nop
- 4: 60 00 00 00 nop
- 8: 60 00 00 00 nop
- c: 60 00 00 00 nop
+ 0: (60 00 00 00|00 00 00 60) nop
+ 4: (60 00 00 00|00 00 00 60) nop
+ 8: (60 00 00 00|00 00 00 60) nop
+ c: (60 00 00 00|00 00 00 60) nop
# Power E6500 nop tests
- .section ".text"
+ .text
start:
nop
.p2align 4,,15
.*
Contents of section \.text:
- 0000 7c11eba6 7c100ba6 4c000066 00000200 .*
- 0010 44000002 4c0000a4 7c000224 4e800020 .*
- 0020 7c11eba6 .*
+ 0000 (7c11eba6|a6eb117c) (7c100ba6|a60b107c) (4c000066|6600004c) (00000200|00020000) .*
+ 0010 (44000002|02000044) (4c0000a4|a400004c) (7c000224|2402007c) (4e800020|2000804e) .*
+ 0020 (7c11eba6|a6eb117c) .*
#as: -mpower4
#name: Power4 instructions
-.*: +file format elf64-powerpc
+.*
.*
architecture: powerpc:common64, flags 0x0+11:
HAS_RELOC, HAS_SYMS
Sections:
Idx Name +Size +VMA +LMA +File off +Algn
- +0 \.text +0+dc +0+ +0+ +.*
+ +0 \.text +0+c8 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
- +1 \.data +0+10 +0+ +0+ +.*
+ +1 \.data +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA
+2 \.bss +0+ +0+ +0+ +.*
+ALLOC
- +3 \.toc +0+30 +0+ +0+ +.*
+ +3 \.toc +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, DATA
SYMBOL TABLE:
0+ l +d +\.text 0+ (|\.text)
0+ l +d +\.data 0+ (|\.data)
0+ l +d +\.bss 0+ (|\.bss)
0+ l +\.data 0+ dsym0
-0+8 l +\.data 0+ dsym1
+0+10 l +\.data 0+ dsym1
0+ l +d +\.toc 0+ (|\.toc)
-0+8 l +\.data 0+ usym0
-0+10 l +\.data 0+ usym1
+0+10 l +\.data 0+ usym0
+0+20 l +\.data 0+ usym1
0+ +\*UND\* 0+ esym0
0+ +\*UND\* 0+ esym1
Disassembly of section \.text:
0+ <\.text>:
- +0: e0 83 00 00 lq r4,0\(r3\)
- 2: R_PPC64_ADDR16_LO_DS \.data
- +4: e0 83 00 00 lq r4,0\(r3\)
- 6: R_PPC64_ADDR16_LO_DS \.data\+0x8
- +8: e0 83 00 00 lq r4,0\(r3\)
- a: R_PPC64_ADDR16_LO_DS \.data\+0x8
- +c: e0 83 00 10 lq r4,16\(r3\)
- e: R_PPC64_ADDR16_LO_DS \.data\+0x10
- +10: e0 83 00 00 lq r4,0\(r3\)
- 12: R_PPC64_ADDR16_LO_DS esym0
- +14: e0 83 00 00 lq r4,0\(r3\)
- 16: R_PPC64_ADDR16_LO_DS esym1
- +18: e0 82 00 00 lq r4,0\(r2\)
- 1a: R_PPC64_TOC16_DS \.toc
- +1c: e0 82 00 00 lq r4,0\(r2\)
- 1e: R_PPC64_TOC16_DS \.toc\+0x8
- +20: e0 82 00 10 lq r4,16\(r2\)
- 22: R_PPC64_TOC16_DS \.toc\+0x10
- +24: e0 82 00 10 lq r4,16\(r2\)
- 26: R_PPC64_TOC16_DS \.toc\+0x18
- +28: e0 82 00 20 lq r4,32\(r2\)
- 2a: R_PPC64_TOC16_DS \.toc\+0x20
- +2c: e0 82 00 20 lq r4,32\(r2\)
- 2e: R_PPC64_TOC16_DS \.toc\+0x28
- +30: e0 c2 00 20 lq r6,32\(r2\)
- 32: R_PPC64_TOC16_LO_DS \.toc\+0x28
- +34: e0 80 00 00 lq r4,0\(0\)
- 36: R_PPC64_ADDR16_LO_DS \.text
- +38: e0 c3 00 00 lq r6,0\(r3\)
- 3a: R_PPC64_GOT16_DS dsym0
- +3c: e0 c3 00 00 lq r6,0\(r3\)
- 3e: R_PPC64_GOT16_LO_DS dsym0
- +40: e0 c3 00 00 lq r6,0\(r3\)
- 42: R_PPC64_PLT16_LO_DS \.data
- +44: e0 c3 00 00 lq r6,0\(r3\)
- 46: R_PPC64_SECTOFF_DS \.data\+0x8
- +48: e0 c3 00 00 lq r6,0\(r3\)
- 4a: R_PPC64_SECTOFF_LO_DS \.data\+0x8
- +4c: e0 c4 00 10 lq r6,16\(r4\)
- +50: f8 c7 00 02 stq r6,0\(r7\)
- +54: f8 c7 00 12 stq r6,16\(r7\)
- +58: f8 c7 ff f2 stq r6,-16\(r7\)
- +5c: f8 c7 80 02 stq r6,-32768\(r7\)
- +60: f8 c7 7f f2 stq r6,32752\(r7\)
- +64: 00 00 02 00 attn
- +68: 7c 6f f1 20 mtcr r3
- +6c: 7c 6f f1 20 mtcr r3
- +70: 7c 68 11 20 mtcrf 129,r3
- +74: 7c 70 11 20 mtocrf 1,r3
- +78: 7c 70 21 20 mtocrf 2,r3
- +7c: 7c 70 41 20 mtocrf 4,r3
- +80: 7c 70 81 20 mtocrf 8,r3
- +84: 7c 71 01 20 mtocrf 16,r3
- +88: 7c 72 01 20 mtocrf 32,r3
- +8c: 7c 74 01 20 mtocrf 64,r3
- +90: 7c 78 01 20 mtocrf 128,r3
- +94: 7c 60 00 26 mfcr r3
- +98: 7c 70 10 26 mfocrf r3,1
- +9c: 7c 70 20 26 mfocrf r3,2
- +a0: 7c 70 40 26 mfocrf r3,4
- +a4: 7c 70 80 26 mfocrf r3,8
- +a8: 7c 71 00 26 mfocrf r3,16
- +ac: 7c 72 00 26 mfocrf r3,32
- +b0: 7c 74 00 26 mfocrf r3,64
- +b4: 7c 78 00 26 mfocrf r3,128
- +b8: 7c 01 17 ec dcbz r1,r2
- +bc: 7c 23 27 ec dcbzl r3,r4
- +c0: 7c 05 37 ec dcbz r5,r6
- +c4: e0 40 00 10 lq r2,16\(0\)
- +c8: e0 05 00 10 lq r0,16\(r5\)
- +cc: e0 45 00 10 lq r2,16\(r5\)
- +d0: f8 40 00 12 stq r2,16\(0\)
- +d4: f8 05 00 12 stq r0,16\(r5\)
- +d8: f8 45 00 12 stq r2,16\(r5\)
+.*: (e0 83 00 00|00 00 83 e0) lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data
+.*: (e0 83 00 .0|.0 00 83 e0) lq r4,.*\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x10
+.*: (e0 83 00 .0|.0 00 83 e0) lq r4,.*\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x10
+.*: (e0 83 00 .0|.0 00 83 e0) lq r4,.*\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x20
+.*: (e0 83 00 00|00 00 83 e0) lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS esym0
+.*: (e0 83 00 00|00 00 83 e0) lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS esym1
+.*: (e0 82 00 00|00 00 82 e0) lq r4,0\(r2\)
+.*: R_PPC64_TOC16_DS \.toc
+.*: (e0 82 00 .0|.0 00 82 e0) lq r4,.*\(r2\)
+.*: R_PPC64_TOC16_DS \.toc\+0x10
+.*: (e0 80 00 00|00 00 80 e0) lq r4,0\(0\)
+.*: R_PPC64_ADDR16_LO_DS \.text
+.*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
+.*: R_PPC64_GOT16_DS dsym0
+.*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
+.*: R_PPC64_GOT16_LO_DS dsym0
+.*: (e0 c3 00 00|00 00 c3 e0) lq r6,0\(r3\)
+.*: R_PPC64_PLT16_LO_DS \.data
+.*: (e0 c3 00 .0|.0 00 c3 e0) lq r6,.*\(r3\)
+.*: R_PPC64_SECTOFF_DS \.data\+0x10
+.*: (e0 c3 00 .0|.0 00 c3 e0) lq r6,.*\(r3\)
+.*: R_PPC64_SECTOFF_LO_DS \.data\+0x10
+.*: (e0 c4 00 20|20 00 c4 e0) lq r6,32\(r4\)
+.*: (f8 c7 00 02|02 00 c7 f8) stq r6,0\(r7\)
+.*: (f8 c7 00 12|12 00 c7 f8) stq r6,16\(r7\)
+.*: (f8 c7 ff f2|f2 ff c7 f8) stq r6,-16\(r7\)
+.*: (f8 c7 80 02|02 80 c7 f8) stq r6,-32768\(r7\)
+.*: (f8 c7 7f f2|f2 7f c7 f8) stq r6,32752\(r7\)
+.*: (00 00 02 00|00 02 00 00) attn
+.*: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+.*: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+.*: (7c 68 11 20|20 11 68 7c) mtcrf 129,r3
+.*: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+.*: (7c 70 21 20|20 21 70 7c) mtocrf 2,r3
+.*: (7c 70 41 20|20 41 70 7c) mtocrf 4,r3
+.*: (7c 70 81 20|20 81 70 7c) mtocrf 8,r3
+.*: (7c 71 01 20|20 01 71 7c) mtocrf 16,r3
+.*: (7c 72 01 20|20 01 72 7c) mtocrf 32,r3
+.*: (7c 74 01 20|20 01 74 7c) mtocrf 64,r3
+.*: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+.*: (7c 60 00 26|26 00 60 7c) mfcr r3
+.*: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+.*: (7c 70 20 26|26 20 70 7c) mfocrf r3,2
+.*: (7c 70 40 26|26 40 70 7c) mfocrf r3,4
+.*: (7c 70 80 26|26 80 70 7c) mfocrf r3,8
+.*: (7c 71 00 26|26 00 71 7c) mfocrf r3,16
+.*: (7c 72 00 26|26 00 72 7c) mfocrf r3,32
+.*: (7c 74 00 26|26 00 74 7c) mfocrf r3,64
+.*: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+.*: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
+.*: (7c 23 27 ec|ec 27 23 7c) dcbzl r3,r4
+.*: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
+.*: (e0 40 00 10|10 00 40 e0) lq r2,16\(0\)
+.*: (e0 05 00 10|10 00 05 e0) lq r0,16\(r5\)
+.*: (e0 45 00 10|10 00 45 e0) lq r2,16\(r5\)
+.*: (f8 40 00 12|12 00 40 f8) stq r2,16\(0\)
+.*: (f8 05 00 12|12 00 05 f8) stq r0,16\(r5\)
+.*: (f8 45 00 12|12 00 45 f8) stq r2,16\(r5\)
- .section ".data"
+ .data
+ .p2align 4
dsym0: .llong 0xdeadbeef
+ .llong 0xc0ffee
dsym1:
.section ".toc"
+ .p2align 4
.L_tsym0:
.tc ignored0[TC],dsym0
-.L_tsym1:
.tc ignored1[TC],dsym1
-.L_tsym2:
+.L_tsym1:
.tc ignored2[TC],usym0
-.L_tsym3:
.tc ignored3[TC],usym1
-.L_tsym4:
- .tc ignored4[TC],esym0
-.L_tsym5:
- .tc ignored5[TC],esym1
- .section ".text"
+ .text
+ .p2align 4
lq 4,dsym0@l(3)
lq 4,dsym1@l(3)
lq 4,usym0@l(3)
lq 4,esym1@l(3)
lq 4,.L_tsym0@toc(2)
lq 4,.L_tsym1@toc(2)
- lq 4,.L_tsym2@toc(2)
- lq 4,.L_tsym3@toc(2)
- lq 4,.L_tsym4@toc(2)
- lq 4,.L_tsym5@toc(2)
- lq 6,.L_tsym5@toc@l(2)
lq 4,.text@l(0)
lq 6,dsym0@got(3)
lq 6,dsym0@got@l(3)
.section ".data"
usym0: .llong 0xcafebabe
+ .llong 0xc0ffee
usym1:
#as: -a32 -mpower4
#name: Power4 instructions
-.*: +file format elf32-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 80 c7 00 00 lwz r6,0\(r7\)
- 4: 80 c7 00 10 lwz r6,16\(r7\)
- 8: 80 c7 ff f0 lwz r6,-16\(r7\)
- c: 80 c7 80 00 lwz r6,-32768\(r7\)
- 10: 80 c7 7f f0 lwz r6,32752\(r7\)
- 14: 90 c7 00 00 stw r6,0\(r7\)
- 18: 90 c7 00 10 stw r6,16\(r7\)
- 1c: 90 c7 ff f0 stw r6,-16\(r7\)
- 20: 90 c7 80 00 stw r6,-32768\(r7\)
- 24: 90 c7 7f f0 stw r6,32752\(r7\)
- 28: 00 00 02 00 attn
- 2c: 7c 6f f1 20 mtcr r3
- 30: 7c 6f f1 20 mtcr r3
- 34: 7c 68 11 20 mtcrf 129,r3
- 38: 7c 70 11 20 mtocrf 1,r3
- 3c: 7c 70 21 20 mtocrf 2,r3
- 40: 7c 70 41 20 mtocrf 4,r3
- 44: 7c 70 81 20 mtocrf 8,r3
- 48: 7c 71 01 20 mtocrf 16,r3
- 4c: 7c 72 01 20 mtocrf 32,r3
- 50: 7c 74 01 20 mtocrf 64,r3
- 54: 7c 78 01 20 mtocrf 128,r3
- 58: 7c 60 00 26 mfcr r3
- 5c: 7c 70 10 26 mfocrf r3,1
- 60: 7c 70 20 26 mfocrf r3,2
- 64: 7c 70 40 26 mfocrf r3,4
- 68: 7c 70 80 26 mfocrf r3,8
- 6c: 7c 71 00 26 mfocrf r3,16
- 70: 7c 72 00 26 mfocrf r3,32
- 74: 7c 74 00 26 mfocrf r3,64
- 78: 7c 78 00 26 mfocrf r3,128
- 7c: 7c 01 17 ec dcbz r1,r2
- 80: 7c 23 27 ec dcbzl r3,r4
- 84: 7c 05 37 ec dcbz r5,r6
- 88: 7c 05 32 2c dcbt r5,r6
- 8c: 7c 05 32 2c dcbt r5,r6
- 90: 7d 05 32 2c dcbt r5,r6,8
+ 0: (80 c7 00 00|00 00 c7 80) lwz r6,0\(r7\)
+ 4: (80 c7 00 10|10 00 c7 80) lwz r6,16\(r7\)
+ 8: (80 c7 ff f0|f0 ff c7 80) lwz r6,-16\(r7\)
+ c: (80 c7 80 00|00 80 c7 80) lwz r6,-32768\(r7\)
+ 10: (80 c7 7f f0|f0 7f c7 80) lwz r6,32752\(r7\)
+ 14: (90 c7 00 00|00 00 c7 90) stw r6,0\(r7\)
+ 18: (90 c7 00 10|10 00 c7 90) stw r6,16\(r7\)
+ 1c: (90 c7 ff f0|f0 ff c7 90) stw r6,-16\(r7\)
+ 20: (90 c7 80 00|00 80 c7 90) stw r6,-32768\(r7\)
+ 24: (90 c7 7f f0|f0 7f c7 90) stw r6,32752\(r7\)
+ 28: (00 00 02 00|00 02 00 00) attn
+ 2c: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 30: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 34: (7c 68 11 20|20 11 68 7c) mtcrf 129,r3
+ 38: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+ 3c: (7c 70 21 20|20 21 70 7c) mtocrf 2,r3
+ 40: (7c 70 41 20|20 41 70 7c) mtocrf 4,r3
+ 44: (7c 70 81 20|20 81 70 7c) mtocrf 8,r3
+ 48: (7c 71 01 20|20 01 71 7c) mtocrf 16,r3
+ 4c: (7c 72 01 20|20 01 72 7c) mtocrf 32,r3
+ 50: (7c 74 01 20|20 01 74 7c) mtocrf 64,r3
+ 54: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 58: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 5c: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+ 60: (7c 70 20 26|26 20 70 7c) mfocrf r3,2
+ 64: (7c 70 40 26|26 40 70 7c) mfocrf r3,4
+ 68: (7c 70 80 26|26 80 70 7c) mfocrf r3,8
+ 6c: (7c 71 00 26|26 00 71 7c) mfocrf r3,16
+ 70: (7c 72 00 26|26 00 72 7c) mfocrf r3,32
+ 74: (7c 74 00 26|26 00 74 7c) mfocrf r3,64
+ 78: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ 7c: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
+ 80: (7c 23 27 ec|ec 27 23 7c) dcbzl r3,r4
+ 84: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
+ 88: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+ 8c: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+ 90: (7d 05 32 2c|2c 32 05 7d) dcbt r5,r6,8
+#pass
- .section ".text"
+ .text
start:
lwz 6,0(7)
lwz 6,16(7)
#objdump: -dr -Mpower6
#name: POWER6 tests (includes DFP and Altivec)
-.*: +file format elf32-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 4c 00 03 24 doze
- 4: 4c 00 03 64 nap
- 8: 4c 00 03 a4 sleep
- c: 4c 00 03 e4 rvwinkle
- 10: 7c 83 01 34 prtyw r3,r4
- 14: 7d cd 01 74 prtyd r13,r14
- 18: 7d 5c 02 a6 mfcfar r10
- 1c: 7d 7c 03 a6 mtcfar r11
- 20: 7c 83 2b f8 cmpb r3,r4,r5
- 24: 7c c0 3c be mffgpr f6,r7
- 28: 7d 00 4d be mftgpr r8,f9
- 2c: 7d 4b 66 2a lwzcix r10,r11,r12
- 30: 7d 8e 7e 2e lfdpx f12,r14,r15
- 34: ee 11 90 04 dadd f16,f17,f18
- 38: fe 96 c0 04 daddq f20,f22,f24
- 3c: 7c 60 06 6c dss 3
- 40: 7e 00 06 6c dssall
- 44: 7c 25 22 ac dst r5,r4,1
- 48: 7e 08 3a ac dstt r8,r7,0
- 4c: 7c 65 32 ec dstst r5,r6,3
- 50: 7e 44 2a ec dststt r4,r5,2
- 54: 00 00 02 00 attn
- 58: 7c 6f f1 20 mtcr r3
- 5c: 7c 6f f1 20 mtcr r3
- 60: 7c 68 11 20 mtcrf 129,r3
- 64: 7c 70 11 20 mtocrf 1,r3
- 68: 7c 70 21 20 mtocrf 2,r3
- 6c: 7c 70 41 20 mtocrf 4,r3
- 70: 7c 70 81 20 mtocrf 8,r3
- 74: 7c 71 01 20 mtocrf 16,r3
- 78: 7c 72 01 20 mtocrf 32,r3
- 7c: 7c 74 01 20 mtocrf 64,r3
- 80: 7c 78 01 20 mtocrf 128,r3
- 84: 7c 60 00 26 mfcr r3
- 88: 7c 70 10 26 mfocrf r3,1
- 8c: 7c 70 20 26 mfocrf r3,2
- 90: 7c 70 40 26 mfocrf r3,4
- 94: 7c 70 80 26 mfocrf r3,8
- 98: 7c 71 00 26 mfocrf r3,16
- 9c: 7c 72 00 26 mfocrf r3,32
- a0: 7c 74 00 26 mfocrf r3,64
- a4: 7c 78 00 26 mfocrf r3,128
- a8: 7c 01 17 ec dcbz r1,r2
- ac: 7c 23 27 ec dcbzl r3,r4
- b0: 7c 05 37 ec dcbz r5,r6
- b4: fc 0c 55 8e mtfsf 6,f10
- b8: fc 0c 5d 8f mtfsf. 6,f11
- bc: fc 0c 55 8e mtfsf 6,f10
- c0: fc 0c 5d 8f mtfsf. 6,f11
- c4: fc 0d 55 8e mtfsf 6,f10,0,1
- c8: fc 0d 5d 8f mtfsf. 6,f11,0,1
- cc: fe 0c 55 8e mtfsf 6,f10,1,0
- d0: fe 0c 5d 8f mtfsf. 6,f11,1,0
- d4: ff 00 01 0c mtfsfi 6,0
- d8: ff 00 f1 0d mtfsfi. 6,15
- dc: ff 00 01 0c mtfsfi 6,0
- e0: ff 00 f1 0d mtfsfi. 6,15
- e4: ff 01 01 0c mtfsfi 6,0,1
- e8: ff 01 f1 0d mtfsfi. 6,15,1
- ec: 7d 6a 02 74 cbcdtd r10,r11
- f0: 7d 6a 02 34 cdtbcd r10,r11
- f4: 7d 4b 60 94 addg6s r10,r11,r12
- f8: 60 21 00 00 ori r1,r1,0
- fc: 60 21 00 00 ori r1,r1,0
+ 0: (4c 00 03 24|24 03 00 4c) doze
+ 4: (4c 00 03 64|64 03 00 4c) nap
+ 8: (4c 00 03 a4|a4 03 00 4c) sleep
+ c: (4c 00 03 e4|e4 03 00 4c) rvwinkle
+ 10: (7c 83 01 34|34 01 83 7c) prtyw r3,r4
+ 14: (7d cd 01 74|74 01 cd 7d) prtyd r13,r14
+ 18: (7d 5c 02 a6|a6 02 5c 7d) mfcfar r10
+ 1c: (7d 7c 03 a6|a6 03 7c 7d) mtcfar r11
+ 20: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+ 24: (7c c0 3c be|be 3c c0 7c) mffgpr f6,r7
+ 28: (7d 00 4d be|be 4d 00 7d) mftgpr r8,f9
+ 2c: (7d 4b 66 2a|2a 66 4b 7d) lwzcix r10,r11,r12
+ 30: (7d 8e 7e 2e|2e 7e 8e 7d) lfdpx f12,r14,r15
+ 34: (ee 11 90 04|04 90 11 ee) dadd f16,f17,f18
+ 38: (fe 96 c0 04|04 c0 96 fe) daddq f20,f22,f24
+ 3c: (7c 60 06 6c|6c 06 60 7c) dss 3
+ 40: (7e 00 06 6c|6c 06 00 7e) dssall
+ 44: (7c 25 22 ac|ac 22 25 7c) dst r5,r4,1
+ 48: (7e 08 3a ac|ac 3a 08 7e) dstt r8,r7,0
+ 4c: (7c 65 32 ec|ec 32 65 7c) dstst r5,r6,3
+ 50: (7e 44 2a ec|ec 2a 44 7e) dststt r4,r5,2
+ 54: (00 00 02 00|00 02 00 00) attn
+ 58: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 5c: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+ 60: (7c 68 11 20|20 11 68 7c) mtcrf 129,r3
+ 64: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+ 68: (7c 70 21 20|20 21 70 7c) mtocrf 2,r3
+ 6c: (7c 70 41 20|20 41 70 7c) mtocrf 4,r3
+ 70: (7c 70 81 20|20 81 70 7c) mtocrf 8,r3
+ 74: (7c 71 01 20|20 01 71 7c) mtocrf 16,r3
+ 78: (7c 72 01 20|20 01 72 7c) mtocrf 32,r3
+ 7c: (7c 74 01 20|20 01 74 7c) mtocrf 64,r3
+ 80: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+ 84: (7c 60 00 26|26 00 60 7c) mfcr r3
+ 88: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+ 8c: (7c 70 20 26|26 20 70 7c) mfocrf r3,2
+ 90: (7c 70 40 26|26 40 70 7c) mfocrf r3,4
+ 94: (7c 70 80 26|26 80 70 7c) mfocrf r3,8
+ 98: (7c 71 00 26|26 00 71 7c) mfocrf r3,16
+ 9c: (7c 72 00 26|26 00 72 7c) mfocrf r3,32
+ a0: (7c 74 00 26|26 00 74 7c) mfocrf r3,64
+ a4: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+ a8: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
+ ac: (7c 23 27 ec|ec 27 23 7c) dcbzl r3,r4
+ b0: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
+ b4: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+ b8: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf. 6,f11
+ bc: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+ c0: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf. 6,f11
+ c4: (fc 0d 55 8e|8e 55 0d fc) mtfsf 6,f10,0,1
+ c8: (fc 0d 5d 8f|8f 5d 0d fc) mtfsf. 6,f11,0,1
+ cc: (fe 0c 55 8e|8e 55 0c fe) mtfsf 6,f10,1,0
+ d0: (fe 0c 5d 8f|8f 5d 0c fe) mtfsf. 6,f11,1,0
+ d4: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ d8: (ff 00 f1 0d|0d f1 00 ff) mtfsfi. 6,15
+ dc: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+ e0: (ff 00 f1 0d|0d f1 00 ff) mtfsfi. 6,15
+ e4: (ff 01 01 0c|0c 01 01 ff) mtfsfi 6,0,1
+ e8: (ff 01 f1 0d|0d f1 01 ff) mtfsfi. 6,15,1
+ ec: (7d 6a 02 74|74 02 6a 7d) cbcdtd r10,r11
+ f0: (7d 6a 02 34|34 02 6a 7d) cdtbcd r10,r11
+ f4: (7d 4b 60 94|94 60 4b 7d) addg6s r10,r11,r12
+ f8: (60 21 00 00|00 00 21 60) ori r1,r1,0
+ fc: (60 21 00 00|00 00 21 60) ori r1,r1,0
+#pass
# PowerPC POWER6 AltiVec tests
#as: -mpower6
- .section ".text"
+ .text
start:
doze
nap
#objdump: -dr -Mpower7
#name: POWER7 tests (includes DFP, Altivec and VSX)
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <power7>:
- 0: 7c 64 2e 98 lxvd2x vs3,r4,r5
- 4: 7d 64 2e 99 lxvd2x vs43,r4,r5
- 8: 7c 64 2f 98 stxvd2x vs3,r4,r5
- c: 7d 64 2f 99 stxvd2x vs43,r4,r5
- 10: f0 64 28 50 xxmrghd vs3,vs4,vs5
- 14: f1 6c 68 57 xxmrghd vs43,vs44,vs45
- 18: f0 64 2b 50 xxmrgld vs3,vs4,vs5
- 1c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
- 20: f0 64 28 50 xxmrghd vs3,vs4,vs5
- 24: f1 6c 68 57 xxmrghd vs43,vs44,vs45
- 28: f0 64 2b 50 xxmrgld vs3,vs4,vs5
- 2c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
- 30: f0 64 29 50 xxpermdi vs3,vs4,vs5,1
- 34: f1 6c 69 57 xxpermdi vs43,vs44,vs45,1
- 38: f0 64 2a 50 xxpermdi vs3,vs4,vs5,2
- 3c: f1 6c 6a 57 xxpermdi vs43,vs44,vs45,2
- 40: f0 64 27 80 xvmovdp vs3,vs4
- 44: f1 6c 67 87 xvmovdp vs43,vs44
- 48: f0 64 27 80 xvmovdp vs3,vs4
- 4c: f1 6c 67 87 xvmovdp vs43,vs44
- 50: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5
- 54: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45
- 58: 7c 00 00 7c wait
- 5c: 7c 00 00 7c wait
- 60: 7c 20 00 7c waitrsv
- 64: 7c 20 00 7c waitrsv
- 68: 7c 40 00 7c waitimpl
- 6c: 7c 40 00 7c waitimpl
- 70: 4c 00 03 24 doze
- 74: 4c 00 03 64 nap
- 78: 4c 00 03 a4 sleep
- 7c: 4c 00 03 e4 rvwinkle
- 80: 7c 83 01 34 prtyw r3,r4
- 84: 7d cd 01 74 prtyd r13,r14
- 88: 7d 5c 02 a6 mfcfar r10
- 8c: 7d 7c 03 a6 mtcfar r11
- 90: 7c 83 2b f8 cmpb r3,r4,r5
- 94: 7d 4b 66 2a lwzcix r10,r11,r12
- 98: ee 11 90 04 dadd f16,f17,f18
- 9c: fe 96 c0 04 daddq f20,f22,f24
- a0: 7c 60 06 6c dss 3
- a4: 7e 00 06 6c dssall
- a8: 7c 25 22 ac dst r5,r4,1
- ac: 7e 08 3a ac dstt r8,r7,0
- b0: 7c 65 32 ec dstst r5,r6,3
- b4: 7e 44 2a ec dststt r4,r5,2
- b8: 7d 4b 63 56 divwe r10,r11,r12
- bc: 7d 6c 6b 57 divwe\. r11,r12,r13
- c0: 7d 8d 77 56 divweo r12,r13,r14
- c4: 7d ae 7f 57 divweo\. r13,r14,r15
- c8: 7d 4b 63 16 divweu r10,r11,r12
- cc: 7d 6c 6b 17 divweu\. r11,r12,r13
- d0: 7d 8d 77 16 divweuo r12,r13,r14
- d4: 7d ae 7f 17 divweuo\. r13,r14,r15
- d8: 7e 27 d9 f8 bpermd r7,r17,r27
- dc: 7e 8a 02 f4 popcntw r10,r20
- e0: 7e 8a 03 f4 popcntd r10,r20
- e4: 7e 95 b4 28 ldbrx r20,r21,r22
- e8: 7e 95 b5 28 stdbrx r20,r21,r22
- ec: 7d 40 56 ee lfiwzx f10,0,r10
- f0: 7d 49 56 ee lfiwzx f10,r9,r10
- f4: ec 80 2e 9c fcfids f4,f5
- f8: ec 80 2e 9d fcfids\. f4,f5
- fc: ec 80 2f 9c fcfidus f4,f5
- 100: ec 80 2f 9d fcfidus\. f4,f5
- 104: fc 80 29 1c fctiwu f4,f5
- 108: fc 80 29 1d fctiwu\. f4,f5
- 10c: fc 80 29 1e fctiwuz f4,f5
- 110: fc 80 29 1f fctiwuz\. f4,f5
- 114: fc 80 2f 5c fctidu f4,f5
- 118: fc 80 2f 5d fctidu\. f4,f5
- 11c: fc 80 2f 5e fctiduz f4,f5
- 120: fc 80 2f 5f fctiduz\. f4,f5
- 124: fc 80 2f 9c fcfidu f4,f5
- 128: fc 80 2f 9d fcfidu\. f4,f5
- 12c: fc 0a 59 00 ftdiv cr0,f10,f11
- 130: ff 8a 59 00 ftdiv cr7,f10,f11
- 134: fc 00 51 40 ftsqrt cr0,f10
- 138: ff 80 51 40 ftsqrt cr7,f10
- 13c: 7e 08 4a 2c dcbtt r8,r9
- 140: 7e 08 49 ec dcbtstt r8,r9
- 144: ed 40 66 44 dcffix f10,f12
- 148: ee 80 b6 45 dcffix\. f20,f22
- 14c: 7d 4b 60 68 lbarx r10,r11,r12
- 150: 7d 4b 60 68 lbarx r10,r11,r12
- 154: 7d 4b 60 69 lbarx r10,r11,r12,1
- 158: 7e 95 b0 e8 lharx r20,r21,r22
- 15c: 7e 95 b0 e8 lharx r20,r21,r22
- 160: 7e 95 b0 e9 lharx r20,r21,r22,1
- 164: 7d 4b 65 6d stbcx\. r10,r11,r12
- 168: 7d 4b 65 ad sthcx\. r10,r11,r12
- 16c: fd c0 78 30 fre f14,f15
- 170: fd c0 78 31 fre\. f14,f15
- 174: ed c0 78 30 fres f14,f15
- 178: ed c0 78 31 fres\. f14,f15
- 17c: fd c0 78 34 frsqrte f14,f15
- 180: fd c0 78 35 frsqrte\. f14,f15
- 184: ed c0 78 34 frsqrtes f14,f15
- 188: ed c0 78 35 frsqrtes\. f14,f15
- 18c: 7c 43 27 1e isel r2,r3,r4,28
- 190: 60 42 00 00 ori r2,r2,0
- 194: 60 00 00 00 nop
- 198: 60 00 00 00 nop
- 19c: 60 42 00 00 ori r2,r2,0
- 1a0: 7f 7b db 78 yield
- 1a4: 7f 7b db 78 yield
- 1a8: 7f bd eb 78 mdoio
- 1ac: 7f bd eb 78 mdoio
- 1b0: 7f de f3 78 mdoom
- 1b4: 7f de f3 78 mdoom
+ 0: (7c 64 2e 98|98 2e 64 7c) lxvd2x vs3,r4,r5
+ 4: (7d 64 2e 99|99 2e 64 7d) lxvd2x vs43,r4,r5
+ 8: (7c 64 2f 98|98 2f 64 7c) stxvd2x vs3,r4,r5
+ c: (7d 64 2f 99|99 2f 64 7d) stxvd2x vs43,r4,r5
+ 10: (f0 64 28 50|50 28 64 f0) xxmrghd vs3,vs4,vs5
+ 14: (f1 6c 68 57|57 68 6c f1) xxmrghd vs43,vs44,vs45
+ 18: (f0 64 2b 50|50 2b 64 f0) xxmrgld vs3,vs4,vs5
+ 1c: (f1 6c 6b 57|57 6b 6c f1) xxmrgld vs43,vs44,vs45
+ 20: (f0 64 28 50|50 28 64 f0) xxmrghd vs3,vs4,vs5
+ 24: (f1 6c 68 57|57 68 6c f1) xxmrghd vs43,vs44,vs45
+ 28: (f0 64 2b 50|50 2b 64 f0) xxmrgld vs3,vs4,vs5
+ 2c: (f1 6c 6b 57|57 6b 6c f1) xxmrgld vs43,vs44,vs45
+ 30: (f0 64 29 50|50 29 64 f0) xxpermdi vs3,vs4,vs5,1
+ 34: (f1 6c 69 57|57 69 6c f1) xxpermdi vs43,vs44,vs45,1
+ 38: (f0 64 2a 50|50 2a 64 f0) xxpermdi vs3,vs4,vs5,2
+ 3c: (f1 6c 6a 57|57 6a 6c f1) xxpermdi vs43,vs44,vs45,2
+ 40: (f0 64 27 80|80 27 64 f0) xvmovdp vs3,vs4
+ 44: (f1 6c 67 87|87 67 6c f1) xvmovdp vs43,vs44
+ 48: (f0 64 27 80|80 27 64 f0) xvmovdp vs3,vs4
+ 4c: (f1 6c 67 87|87 67 6c f1) xvmovdp vs43,vs44
+ 50: (f0 64 2f 80|80 2f 64 f0) xvcpsgndp vs3,vs4,vs5
+ 54: (f1 6c 6f 87|87 6f 6c f1) xvcpsgndp vs43,vs44,vs45
+ 58: (7c 00 00 7c|7c 00 00 7c) wait
+ 5c: (7c 00 00 7c|7c 00 00 7c) wait
+ 60: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 64: (7c 20 00 7c|7c 00 20 7c) waitrsv
+ 68: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 6c: (7c 40 00 7c|7c 00 40 7c) waitimpl
+ 70: (4c 00 03 24|24 03 00 4c) doze
+ 74: (4c 00 03 64|64 03 00 4c) nap
+ 78: (4c 00 03 a4|a4 03 00 4c) sleep
+ 7c: (4c 00 03 e4|e4 03 00 4c) rvwinkle
+ 80: (7c 83 01 34|34 01 83 7c) prtyw r3,r4
+ 84: (7d cd 01 74|74 01 cd 7d) prtyd r13,r14
+ 88: (7d 5c 02 a6|a6 02 5c 7d) mfcfar r10
+ 8c: (7d 7c 03 a6|a6 03 7c 7d) mtcfar r11
+ 90: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+ 94: (7d 4b 66 2a|2a 66 4b 7d) lwzcix r10,r11,r12
+ 98: (ee 11 90 04|04 90 11 ee) dadd f16,f17,f18
+ 9c: (fe 96 c0 04|04 c0 96 fe) daddq f20,f22,f24
+ a0: (7c 60 06 6c|6c 06 60 7c) dss 3
+ a4: (7e 00 06 6c|6c 06 00 7e) dssall
+ a8: (7c 25 22 ac|ac 22 25 7c) dst r5,r4,1
+ ac: (7e 08 3a ac|ac 3a 08 7e) dstt r8,r7,0
+ b0: (7c 65 32 ec|ec 32 65 7c) dstst r5,r6,3
+ b4: (7e 44 2a ec|ec 2a 44 7e) dststt r4,r5,2
+ b8: (7d 4b 63 56|56 63 4b 7d) divwe r10,r11,r12
+ bc: (7d 6c 6b 57|57 6b 6c 7d) divwe\. r11,r12,r13
+ c0: (7d 8d 77 56|56 77 8d 7d) divweo r12,r13,r14
+ c4: (7d ae 7f 57|57 7f ae 7d) divweo\. r13,r14,r15
+ c8: (7d 4b 63 16|16 63 4b 7d) divweu r10,r11,r12
+ cc: (7d 6c 6b 17|17 6b 6c 7d) divweu\. r11,r12,r13
+ d0: (7d 8d 77 16|16 77 8d 7d) divweuo r12,r13,r14
+ d4: (7d ae 7f 17|17 7f ae 7d) divweuo\. r13,r14,r15
+ d8: (7e 27 d9 f8|f8 d9 27 7e) bpermd r7,r17,r27
+ dc: (7e 8a 02 f4|f4 02 8a 7e) popcntw r10,r20
+ e0: (7e 8a 03 f4|f4 03 8a 7e) popcntd r10,r20
+ e4: (7e 95 b4 28|28 b4 95 7e) ldbrx r20,r21,r22
+ e8: (7e 95 b5 28|28 b5 95 7e) stdbrx r20,r21,r22
+ ec: (7d 40 56 ee|ee 56 40 7d) lfiwzx f10,0,r10
+ f0: (7d 49 56 ee|ee 56 49 7d) lfiwzx f10,r9,r10
+ f4: (ec 80 2e 9c|9c 2e 80 ec) fcfids f4,f5
+ f8: (ec 80 2e 9d|9d 2e 80 ec) fcfids\. f4,f5
+ fc: (ec 80 2f 9c|9c 2f 80 ec) fcfidus f4,f5
+ 100: (ec 80 2f 9d|9d 2f 80 ec) fcfidus\. f4,f5
+ 104: (fc 80 29 1c|1c 29 80 fc) fctiwu f4,f5
+ 108: (fc 80 29 1d|1d 29 80 fc) fctiwu\. f4,f5
+ 10c: (fc 80 29 1e|1e 29 80 fc) fctiwuz f4,f5
+ 110: (fc 80 29 1f|1f 29 80 fc) fctiwuz\. f4,f5
+ 114: (fc 80 2f 5c|5c 2f 80 fc) fctidu f4,f5
+ 118: (fc 80 2f 5d|5d 2f 80 fc) fctidu\. f4,f5
+ 11c: (fc 80 2f 5e|5e 2f 80 fc) fctiduz f4,f5
+ 120: (fc 80 2f 5f|5f 2f 80 fc) fctiduz\. f4,f5
+ 124: (fc 80 2f 9c|9c 2f 80 fc) fcfidu f4,f5
+ 128: (fc 80 2f 9d|9d 2f 80 fc) fcfidu\. f4,f5
+ 12c: (fc 0a 59 00|00 59 0a fc) ftdiv cr0,f10,f11
+ 130: (ff 8a 59 00|00 59 8a ff) ftdiv cr7,f10,f11
+ 134: (fc 00 51 40|40 51 00 fc) ftsqrt cr0,f10
+ 138: (ff 80 51 40|40 51 80 ff) ftsqrt cr7,f10
+ 13c: (7e 08 4a 2c|2c 4a 08 7e) dcbtt r8,r9
+ 140: (7e 08 49 ec|ec 49 08 7e) dcbtstt r8,r9
+ 144: (ed 40 66 44|44 66 40 ed) dcffix f10,f12
+ 148: (ee 80 b6 45|45 b6 80 ee) dcffix\. f20,f22
+ 14c: (7d 4b 60 68|68 60 4b 7d) lbarx r10,r11,r12
+ 150: (7d 4b 60 68|68 60 4b 7d) lbarx r10,r11,r12
+ 154: (7d 4b 60 69|69 60 4b 7d) lbarx r10,r11,r12,1
+ 158: (7e 95 b0 e8|e8 b0 95 7e) lharx r20,r21,r22
+ 15c: (7e 95 b0 e8|e8 b0 95 7e) lharx r20,r21,r22
+ 160: (7e 95 b0 e9|e9 b0 95 7e) lharx r20,r21,r22,1
+ 164: (7d 4b 65 6d|6d 65 4b 7d) stbcx\. r10,r11,r12
+ 168: (7d 4b 65 ad|ad 65 4b 7d) sthcx\. r10,r11,r12
+ 16c: (fd c0 78 30|30 78 c0 fd) fre f14,f15
+ 170: (fd c0 78 31|31 78 c0 fd) fre\. f14,f15
+ 174: (ed c0 78 30|30 78 c0 ed) fres f14,f15
+ 178: (ed c0 78 31|31 78 c0 ed) fres\. f14,f15
+ 17c: (fd c0 78 34|34 78 c0 fd) frsqrte f14,f15
+ 180: (fd c0 78 35|35 78 c0 fd) frsqrte\. f14,f15
+ 184: (ed c0 78 34|34 78 c0 ed) frsqrtes f14,f15
+ 188: (ed c0 78 35|35 78 c0 ed) frsqrtes\. f14,f15
+ 18c: (7c 43 27 1e|1e 27 43 7c) isel r2,r3,r4,28
+ 190: (60 42 00 00|00 00 42 60) ori r2,r2,0
+ 194: (60 00 00 00|00 00 00 60) nop
+ 198: (60 00 00 00|00 00 00 60) nop
+ 19c: (60 42 00 00|00 00 42 60) ori r2,r2,0
+ 1a0: (7f 7b db 78|78 db 7b 7f) yield
+ 1a4: (7f 7b db 78|78 db 7b 7f) yield
+ 1a8: (7f bd eb 78|78 eb bd 7f) mdoio
+ 1ac: (7f bd eb 78|78 eb bd 7f) mdoio
+ 1b0: (7f de f3 78|78 f3 de 7f) mdoom
+ 1b4: (7f de f3 78|78 f3 de 7f) mdoom
+ 1b8: (7d 40 e2 a6|a6 e2 40 7d) mfppr r10
+ 1bc: (7d 62 e2 a6|a6 e2 62 7d) mfppr32 r11
+ 1c0: (7d 80 e3 a6|a6 e3 80 7d) mtppr r12
+ 1c4: (7d a2 e3 a6|a6 e3 a2 7d) mtppr32 r13
+#pass
- .section ".text"
+ .text
power7:
lxvd2x 3,4,5
lxvd2x 43,4,5
or 29,29,29
mdoom
or 30,30,30
+ mfppr 10
+ mfppr32 11
+ mtppr 12
+ mtppr32 13
if { [istarget powerpc*-*-*] } then {
run_dump_test "simpshft"
- run_dump_test "machine"
run_dump_test "regnames"
+ if { [is_elf_format] } then {
+ run_dump_test "machine"
+ run_dump_test "common"
+ run_dump_test "476"
+ run_dump_test "a2"
+ if { ![istarget powerpc*le-*-*] } then {
+ run_dump_test "vle"
+ run_dump_test "vle-reloc"
+ run_dump_test "vle-simple-1"
+ run_dump_test "vle-simple-2"
+ run_dump_test "vle-simple-3"
+ run_dump_test "vle-simple-4"
+ run_dump_test "vle-simple-5"
+ run_dump_test "vle-simple-6"
+ }
+ }
if { [istarget powerpc-*-*aix*] } then {
run_dump_test "altivec_xcoff"
run_dump_test "altivec_xcoff64"
} else {
run_dump_test "altivec"
+ run_dump_test "altivec2"
run_dump_test "altivec_and_spe"
run_dump_test "booke"
run_dump_test "e500"
run_dump_test "e500mc64_nop"
run_dump_test "e5500_nop"
run_dump_test "e6500_nop"
- run_dump_test "a2"
run_dump_test "cell"
- run_dump_test "common"
run_dump_test "power4_32"
run_dump_test "power6"
run_dump_test "power7"
run_dump_test "vsx"
- run_dump_test "476"
run_dump_test "titan"
- run_dump_test "vle"
- run_dump_test "vle-reloc"
- run_dump_test "vle-simple-1"
- run_dump_test "vle-simple-2"
- run_dump_test "vle-simple-3"
- run_dump_test "vle-simple-4"
- run_dump_test "vle-simple-5"
- run_dump_test "vle-simple-6"
}
}
#objdump: -dr -Mppcps
#name: PPC750CL paired single tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+0000000 <start>:
- 0: e0 03 d0 04 psq_l f0,4\(r3\),1,5
- 4: e4 22 30 08 psq_lu f1,8\(r2\),0,3
- 8: 10 45 25 4c psq_lux f2,r5,r4,1,2
- c: 10 62 22 8c psq_lx f3,r2,r4,0,5
- 10: f0 62 30 08 psq_st f3,8\(r2\),0,3
- 14: f4 62 70 08 psq_stu f3,8\(r2\),0,7
- 18: 10 43 22 ce psq_stux f2,r3,r4,0,5
- 1c: 10 c7 46 0e psq_stx f6,r7,r8,1,4
- 20: 10 a0 3a 10 ps_abs f5,f7
- 24: 10 a0 3a 11 ps_abs. f5,f7
- 28: 10 22 18 2a ps_add f1,f2,f3
- 2c: 10 22 18 2b ps_add. f1,f2,f3
- 30: 11 82 20 40 ps_cmpo0 cr3,f2,f4
- 34: 11 82 20 c0 ps_cmpo1 cr3,f2,f4
- 38: 11 82 20 00 ps_cmpu0 cr3,f2,f4
- 3c: 11 82 20 80 ps_cmpu1 cr3,f2,f4
- 40: 10 44 30 24 ps_div f2,f4,f6
- 44: 10 44 30 25 ps_div. f2,f4,f6
- 48: 10 01 18 ba ps_madd f0,f1,f2,f3
- 4c: 10 01 18 bb ps_madd. f0,f1,f2,f3
- 50: 10 22 20 dc ps_madds0 f1,f2,f3,f4
- 54: 10 22 20 dd ps_madds0. f1,f2,f3,f4
- 58: 10 22 20 de ps_madds1 f1,f2,f3,f4
- 5c: 10 22 20 df ps_madds1. f1,f2,f3,f4
- 60: 10 44 34 20 ps_merge00 f2,f4,f6
- 64: 10 44 34 21 ps_merge00. f2,f4,f6
- 68: 10 44 34 60 ps_merge01 f2,f4,f6
- 6c: 10 44 34 61 ps_merge01. f2,f4,f6
- 70: 10 44 34 a0 ps_merge10 f2,f4,f6
- 74: 10 44 34 a1 ps_merge10. f2,f4,f6
- 78: 10 44 34 e0 ps_merge11 f2,f4,f6
- 7c: 10 44 34 e1 ps_merge11. f2,f4,f6
- 80: 10 60 28 90 ps_mr f3,f5
- 84: 10 60 28 91 ps_mr. f3,f5
- 88: 10 44 41 b8 ps_msub f2,f4,f6,f8
- 8c: 10 44 41 b9 ps_msub. f2,f4,f6,f8
- 90: 10 43 01 72 ps_mul f2,f3,f5
- 94: 10 43 01 73 ps_mul. f2,f3,f5
- 98: 10 64 01 d8 ps_muls0 f3,f4,f7
- 9c: 10 64 01 d9 ps_muls0. f3,f4,f7
- a0: 10 64 01 da ps_muls1 f3,f4,f7
- a4: 10 64 01 db ps_muls1. f3,f4,f7
- a8: 10 20 29 10 ps_nabs f1,f5
- ac: 10 20 29 11 ps_nabs. f1,f5
- b0: 10 20 28 50 ps_neg f1,f5
- b4: 10 20 28 51 ps_neg. f1,f5
- b8: 10 23 39 7e ps_nmadd f1,f3,f5,f7
- bc: 10 23 39 7f ps_nmadd. f1,f3,f5,f7
- c0: 10 23 39 7c ps_nmsub f1,f3,f5,f7
- c4: 10 23 39 7d ps_nmsub. f1,f3,f5,f7
- c8: 11 20 18 30 ps_res f9,f3
- cc: 11 20 18 31 ps_res. f9,f3
- d0: 11 20 18 34 ps_rsqrte f9,f3
- d4: 11 20 18 35 ps_rsqrte. f9,f3
- d8: 10 22 20 ee ps_sel f1,f2,f3,f4
- dc: 10 22 20 ef ps_sel. f1,f2,f3,f4
- e0: 10 ab 10 28 ps_sub f5,f11,f2
- e4: 10 ab 10 29 ps_sub. f5,f11,f2
- e8: 10 45 52 54 ps_sum0 f2,f5,f9,f10
- ec: 10 45 52 55 ps_sum0. f2,f5,f9,f10
- f0: 10 45 52 56 ps_sum1 f2,f5,f9,f10
- f4: 10 45 52 57 ps_sum1. f2,f5,f9,f10
- f8: 10 03 2f ec dcbz_l r3,r5
+ 0: (e0 03 d0 04|04 d0 03 e0) psq_l f0,4\(r3\),1,5
+ 4: (e4 22 30 08|08 30 22 e4) psq_lu f1,8\(r2\),0,3
+ 8: (10 45 25 4c|4c 25 45 10) psq_lux f2,r5,r4,1,2
+ c: (10 62 22 8c|8c 22 62 10) psq_lx f3,r2,r4,0,5
+ 10: (f0 62 30 08|08 30 62 f0) psq_st f3,8\(r2\),0,3
+ 14: (f4 62 70 08|08 70 62 f4) psq_stu f3,8\(r2\),0,7
+ 18: (10 43 22 ce|ce 22 43 10) psq_stux f2,r3,r4,0,5
+ 1c: (10 c7 46 0e|0e 46 c7 10) psq_stx f6,r7,r8,1,4
+ 20: (10 a0 3a 10|10 3a a0 10) ps_abs f5,f7
+ 24: (10 a0 3a 11|11 3a a0 10) ps_abs. f5,f7
+ 28: (10 22 18 2a|2a 18 22 10) ps_add f1,f2,f3
+ 2c: (10 22 18 2b|2b 18 22 10) ps_add. f1,f2,f3
+ 30: (11 82 20 40|40 20 82 11) ps_cmpo0 cr3,f2,f4
+ 34: (11 82 20 c0|c0 20 82 11) ps_cmpo1 cr3,f2,f4
+ 38: (11 82 20 00|00 20 82 11) ps_cmpu0 cr3,f2,f4
+ 3c: (11 82 20 80|80 20 82 11) ps_cmpu1 cr3,f2,f4
+ 40: (10 44 30 24|24 30 44 10) ps_div f2,f4,f6
+ 44: (10 44 30 25|25 30 44 10) ps_div. f2,f4,f6
+ 48: (10 01 18 ba|ba 18 01 10) ps_madd f0,f1,f2,f3
+ 4c: (10 01 18 bb|bb 18 01 10) ps_madd. f0,f1,f2,f3
+ 50: (10 22 20 dc|dc 20 22 10) ps_madds0 f1,f2,f3,f4
+ 54: (10 22 20 dd|dd 20 22 10) ps_madds0. f1,f2,f3,f4
+ 58: (10 22 20 de|de 20 22 10) ps_madds1 f1,f2,f3,f4
+ 5c: (10 22 20 df|df 20 22 10) ps_madds1. f1,f2,f3,f4
+ 60: (10 44 34 20|20 34 44 10) ps_merge00 f2,f4,f6
+ 64: (10 44 34 21|21 34 44 10) ps_merge00. f2,f4,f6
+ 68: (10 44 34 60|60 34 44 10) ps_merge01 f2,f4,f6
+ 6c: (10 44 34 61|61 34 44 10) ps_merge01. f2,f4,f6
+ 70: (10 44 34 a0|a0 34 44 10) ps_merge10 f2,f4,f6
+ 74: (10 44 34 a1|a1 34 44 10) ps_merge10. f2,f4,f6
+ 78: (10 44 34 e0|e0 34 44 10) ps_merge11 f2,f4,f6
+ 7c: (10 44 34 e1|e1 34 44 10) ps_merge11. f2,f4,f6
+ 80: (10 60 28 90|90 28 60 10) ps_mr f3,f5
+ 84: (10 60 28 91|91 28 60 10) ps_mr. f3,f5
+ 88: (10 44 41 b8|b8 41 44 10) ps_msub f2,f4,f6,f8
+ 8c: (10 44 41 b9|b9 41 44 10) ps_msub. f2,f4,f6,f8
+ 90: (10 43 01 72|72 01 43 10) ps_mul f2,f3,f5
+ 94: (10 43 01 73|73 01 43 10) ps_mul. f2,f3,f5
+ 98: (10 64 01 d8|d8 01 64 10) ps_muls0 f3,f4,f7
+ 9c: (10 64 01 d9|d9 01 64 10) ps_muls0. f3,f4,f7
+ a0: (10 64 01 da|da 01 64 10) ps_muls1 f3,f4,f7
+ a4: (10 64 01 db|db 01 64 10) ps_muls1. f3,f4,f7
+ a8: (10 20 29 10|10 29 20 10) ps_nabs f1,f5
+ ac: (10 20 29 11|11 29 20 10) ps_nabs. f1,f5
+ b0: (10 20 28 50|50 28 20 10) ps_neg f1,f5
+ b4: (10 20 28 51|51 28 20 10) ps_neg. f1,f5
+ b8: (10 23 39 7e|7e 39 23 10) ps_nmadd f1,f3,f5,f7
+ bc: (10 23 39 7f|7f 39 23 10) ps_nmadd. f1,f3,f5,f7
+ c0: (10 23 39 7c|7c 39 23 10) ps_nmsub f1,f3,f5,f7
+ c4: (10 23 39 7d|7d 39 23 10) ps_nmsub. f1,f3,f5,f7
+ c8: (11 20 18 30|30 18 20 11) ps_res f9,f3
+ cc: (11 20 18 31|31 18 20 11) ps_res. f9,f3
+ d0: (11 20 18 34|34 18 20 11) ps_rsqrte f9,f3
+ d4: (11 20 18 35|35 18 20 11) ps_rsqrte. f9,f3
+ d8: (10 22 20 ee|ee 20 22 10) ps_sel f1,f2,f3,f4
+ dc: (10 22 20 ef|ef 20 22 10) ps_sel. f1,f2,f3,f4
+ e0: (10 ab 10 28|28 10 ab 10) ps_sub f5,f11,f2
+ e4: (10 ab 10 29|29 10 ab 10) ps_sub. f5,f11,f2
+ e8: (10 45 52 54|54 52 45 10) ps_sum0 f2,f5,f9,f10
+ ec: (10 45 52 55|55 52 45 10) ps_sum0. f2,f5,f9,f10
+ f0: (10 45 52 56|56 52 45 10) ps_sum1 f2,f5,f9,f10
+ f4: (10 45 52 57|57 52 45 10) ps_sum1. f2,f5,f9,f10
+ f8: (10 03 2f ec|ec 2f 03 10) dcbz_l r3,r5
+#pass
# PowerPC 750 paired single precision tests
- .section ".text"
+ .text
start:
psq_l 0, 4(3), 1, 5
psq_lu 1, 8(2), 0, 3
.*
Contents of section \.text:
- 0000 4fbdcb82 88850004 .*
+ 0000 (4fbdcb82|82cbbd4f) (88850004|04008588) .*
-#objdump: -s -j .text
+#objdump: -d -Mppc64
#as: -mppc64
#name: PowerPC test 3, simplified shifts
.*
-Contents of section \.text:
- 0000 78640fe0 7883f80e 78a545e4 78640020 xd..x...x.E.xd.
- 0010 54640ffe 5083f800 54a5402e 5464043e Td..P...T.@.Td.>
- 0020 78640004 786407e4 7864f806 7864ffe6 xd..xd..xd..xd..
- 0030 7864f842 7864ffe2 7864000c 7864080c xd.Bxd..xd..xd..
- 0040 78640fac 786407ec 78640000 78640800 xd..xd..xd..xd..
- 0050 7864f802 78640000 7864f802 78640800 xd..xd..xd..xd..
- 0060 78652010 786407e4 7864f806 78640000 xe .xd..xd..xd..
- 0070 7864f842 78640fe0 78640000 78640040 xd.Bxd..xd..xd.@
- 0080 786407e0 786407e4 786407a4 78640004 xd..xd..xd..xd..
- 0090 78640008 78640048 786407e8 78640fa8 xd..xd.Hxd..xd..
- 00a0 7864f80a 54640000 5464003e 5464f800 xd..Td..Td.>Td..
- 00b0 5464f83e 5464f87e 5464fffe 50640000 Td.>Td.~Td..Pd..
- 00c0 5064003e 50640ffe 5064f800 5064003e Pd.>Pd..Pd..Pd.>
- 00d0 506407fe 5464003e 5464083e 5464f83e Pd..Td.>Td.>Td.>
- 00e0 5464003e 5464f83e 5464083e 5c65203e Td.>Td.>Td.>\\e >
- 00f0 5464003e 5464083c 5464f800 5464003e Td.>Td.<Td..Td.>
- 0100 5464f87e 54640ffe 5464003e 5464007e Td.~Td..Td.>Td.~
- 0110 546407fe 5464003e 5464003c 54640000 Td..Td.>Td.<Td..
- 0120 5464003e 5464007e 546407fe 54640fbc Td.>Td.~Td..Td..
- 0130 5464f800 00000000 Td......
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
+ 4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0
+ 8: (e4 45 a5 78|78 a5 45 e4) rldicr r5,r5,8,55
+ c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32
+ 10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0
+ 18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23
+ 1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16
+ 20: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
+ 24: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
+ 28: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
+ 2c: (e6 ff 64 78|78 64 ff e6) rldicr r4,r3,63,63
+ 30: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
+ 34: (e2 ff 64 78|78 64 ff e2) rldicl r4,r3,63,63
+ 38: (0c 00 64 78|78 64 00 0c) rldimi r4,r3,0,0
+ 3c: (0c 08 64 78|78 64 08 0c) rldimi r4,r3,1,0
+ 40: (ac 0f 64 78|78 64 0f ac) rldimi r4,r3,1,62
+ 44: (ec 07 64 78|78 64 07 ec) rldimi r4,r3,0,63
+ 48: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
+ 4c: (00 08 64 78|78 64 08 00) rotldi r4,r3,1
+ 50: (02 f8 64 78|78 64 f8 02) rotldi r4,r3,63
+ 54: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
+ 58: (02 f8 64 78|78 64 f8 02) rotldi r4,r3,63
+ 5c: (00 08 64 78|78 64 08 00) rotldi r4,r3,1
+ 60: (10 20 65 78|78 65 20 10) rotld r5,r3,r4
+ 64: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
+ 68: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0
+ 6c: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
+ 70: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1
+ 74: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
+ 78: (00 00 64 78|78 64 00 00) rotldi r4,r3,0
+ 7c: (40 00 64 78|78 64 00 40) clrldi r4,r3,1
+ 80: (e0 07 64 78|78 64 07 e0) clrldi r4,r3,63
+ 84: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63
+ 88: (a4 07 64 78|78 64 07 a4) rldicr r4,r3,0,62
+ 8c: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0
+ 90: (08 00 64 78|78 64 00 08) rldic r4,r3,0,0
+ 94: (48 00 64 78|78 64 00 48) rldic r4,r3,0,1
+ 98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63
+ 9c: (a8 0f 64 78|78 64 0f a8) rldic r4,r3,1,62
+ a0: (0a f8 64 78|78 64 f8 0a) rldic r4,r3,63,0
+ a4: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ a8: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ ac: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ b0: (3e f8 64 54|54 64 f8 3e) rotlwi r4,r3,31
+ b4: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
+ b8: (fe ff 64 54|54 64 ff fe) rlwinm r4,r3,31,31,31
+ bc: (00 00 64 50|50 64 00 00) rlwimi r4,r3,0,0,0
+ c0: (3e 00 64 50|50 64 00 3e) rlwimi r4,r3,0,0,31
+ c4: (fe 0f 64 50|50 64 0f fe) rlwimi r4,r3,1,31,31
+ c8: (00 f8 64 50|50 64 f8 00) rlwimi r4,r3,31,0,0
+ cc: (3e 00 64 50|50 64 00 3e) rlwimi r4,r3,0,0,31
+ d0: (fe 07 64 50|50 64 07 fe) rlwimi r4,r3,0,31,31
+ d4: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ d8: (3e 08 64 54|54 64 08 3e) rotlwi r4,r3,1
+ dc: (3e f8 64 54|54 64 f8 3e) rotlwi r4,r3,31
+ e0: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ e4: (3e f8 64 54|54 64 f8 3e) rotlwi r4,r3,31
+ e8: (3e 08 64 54|54 64 08 3e) rotlwi r4,r3,1
+ ec: (3e 20 65 5c|5c 65 20 3e) rotlw r5,r3,r4
+ f0: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ f4: (3c 08 64 54|54 64 08 3c) rlwinm r4,r3,1,0,30
+ f8: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ fc: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ 100: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
+ 104: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 108: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ 10c: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
+ 110: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
+ 114: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ 118: (3c 00 64 54|54 64 00 3c) rlwinm r4,r3,0,0,30
+ 11c: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ 120: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
+ 124: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
+ 128: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
+ 12c: (bc 0f 64 54|54 64 0f bc) rlwinm r4,r3,1,30,30
+ 130: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+#pass
#objdump: -Drx
#name: PowerPC Test 1, 32 bit elf
-.*: +file format elf32-powerpc
+.*
.*
architecture: powerpc:common, flags 0x00000011:
HAS_RELOC, HAS_SYMS
Disassembly of section \.text:
0+0000 <\.text>:
- 0: 80 63 00 00 lwz r3,0\(r3\)
- 2: R_PPC_ADDR16_LO \.data
- 4: 80 63 00 04 lwz r3,4\(r3\)
- 6: R_PPC_ADDR16_LO \.data\+0x4
- 8: 80 63 00 04 lwz r3,4\(r3\)
- a: R_PPC_ADDR16_LO \.data\+0x4
- c: 80 63 00 08 lwz r3,8\(r3\)
- e: R_PPC_ADDR16_LO \.data\+0x8
- 10: 80 63 00 00 lwz r3,0\(r3\)
- 12: R_PPC_ADDR16_LO esym0
- 14: 80 63 00 00 lwz r3,0\(r3\)
- 16: R_PPC_ADDR16_LO esym1
- 18: 38 60 00 04 li r3,4
- 1c: 38 60 ff fc li r3,-4
- 20: 38 60 00 04 li r3,4
- 24: 38 60 ff fc li r3,-4
- 28: 38 60 ff fc li r3,-4
- 2c: 38 60 00 04 li r3,4
- 30: 38 60 00 00 li r3,0
- 32: R_PPC_ADDR16_LO \.data
- 34: 38 60 00 00 li r3,0
- 36: R_PPC_ADDR16_HI \.data
- 38: 38 60 00 00 li r3,0
- 3a: R_PPC_ADDR16_HA \.data
- 3c: 38 60 ff fc li r3,-4
- 40: 38 60 ff ff li r3,-1
- 44: 38 60 00 00 li r3,0
- 48: 80 64 00 04 lwz r3,4\(r4\)
- 4c: 80 60 00 00 lwz r3,0\(0\)
- 4e: R_PPC_ADDR16_LO \.text
+ 0: (80 63 00 00|00 00 63 80) lwz r3,0\(r3\)
+ (2|0): R_PPC_ADDR16_LO \.data
+ 4: (80 63 00 0.|0. 00 63 80) lwz r3,.\(r3\)
+ (6|4): R_PPC_ADDR16_LO \.data\+0x4
+ 8: (80 63 00 0.|0. 00 63 80) lwz r3,.\(r3\)
+ (a|8): R_PPC_ADDR16_LO \.data\+0x4
+ c: (80 63 00 0.|0. 00 63 80) lwz r3,.\(r3\)
+ (e|c): R_PPC_ADDR16_LO \.data\+0x8
+ 10: (80 63 00 00|00 00 63 80) lwz r3,0\(r3\)
+ (12|10): R_PPC_ADDR16_LO esym0
+ 14: (80 63 00 00|00 00 63 80) lwz r3,0\(r3\)
+ (16|14): R_PPC_ADDR16_LO esym1
+ 18: (38 60 00 04|04 00 60 38) li r3,4
+ 1c: (38 60 ff fc|fc ff 60 38) li r3,-4
+ 20: (38 60 00 04|04 00 60 38) li r3,4
+ 24: (38 60 ff fc|fc ff 60 38) li r3,-4
+ 28: (38 60 ff fc|fc ff 60 38) li r3,-4
+ 2c: (38 60 00 04|04 00 60 38) li r3,4
+ 30: (38 60 00 00|00 00 60 38) li r3,0
+ (32|30): R_PPC_ADDR16_LO \.data
+ 34: (38 60 00 00|00 00 60 38) li r3,0
+ (36|34): R_PPC_ADDR16_HI \.data
+ 38: (38 60 00 00|00 00 60 38) li r3,0
+ (3a|38): R_PPC_ADDR16_HA \.data
+ 3c: (38 60 ff fc|fc ff 60 38) li r3,-4
+ 40: (38 60 ff ff|ff ff 60 38) li r3,-1
+ 44: (38 60 00 00|00 00 60 38) li r3,0
+ 48: (80 64 00 04|04 00 64 80) lwz r3,4\(r4\)
+ 4c: (80 60 00 00|00 00 60 80) lwz r3,0\(0\)
+ (4e|4c): R_PPC_ADDR16_LO \.text
Disassembly of section \.data:
0+0000 <dsym0>:
- 0: de ad be ef stfdu f21,-16657\(r13\)
+ 0: (de ad be ef|ef be ad de) stfdu f21,-16657\(r13\)
0+0004 <dsym1>:
- 4: ca fe ba be lfd f23,-17730\(r30\)
+ 4: (ca fe ba be|be ba fe ca) lfd f23,-17730\(r30\)
0+0008 <datpt>:
- 8: 00 98 96 80 \.long 0x989680
+ 8: 00 00 00 00 \.long 0x0
8: R_PPC_REL32 jk\+0x989680
0+000c <dat0>:
- c: ff ff ff fc fnmsub f31,f31,f31,f31
+ c: 00 00 00 00 \.long 0x0
c: R_PPC_REL32 jk-0x4
0+0010 <dat1>:
10: R_PPC_REL32 jk
0+0014 <dat2>:
- 14: 00 00 00 04 \.long 0x4
+ 14: 00 00 00 00 \.long 0x0
14: R_PPC_REL32 jk\+0x4
#objdump: -Drx
#name: PowerPC Test 1, 64 bit elf
-.*: +file format elf64-powerpc
+.*
.*
architecture: powerpc:common64, flags 0x00000011:
HAS_RELOC, HAS_SYMS
Disassembly of section \.text:
0000000000000000 <\.text>:
- 0: e8 63 00 00 ld r3,0\(r3\)
- 2: R_PPC64_ADDR16_LO_DS \.data
- 4: e8 63 00 08 ld r3,8\(r3\)
- 6: R_PPC64_ADDR16_LO_DS \.data\+0x8
- 8: e8 63 00 08 ld r3,8\(r3\)
- a: R_PPC64_ADDR16_LO_DS \.data\+0x8
- c: e8 63 00 10 ld r3,16\(r3\)
- e: R_PPC64_ADDR16_LO_DS \.data\+0x10
- 10: e8 63 00 00 ld r3,0\(r3\)
- 12: R_PPC64_ADDR16_LO_DS esym0
- 14: e8 63 00 00 ld r3,0\(r3\)
- 16: R_PPC64_ADDR16_LO_DS esym1
- 18: e8 62 00 00 ld r3,0\(r2\)
- 1a: R_PPC64_TOC16_DS \.toc
- 1c: e8 62 00 08 ld r3,8\(r2\)
- 1e: R_PPC64_TOC16_DS \.toc\+0x8
- 20: e8 62 00 10 ld r3,16\(r2\)
- 22: R_PPC64_TOC16_DS \.toc\+0x10
- 24: e8 62 00 18 ld r3,24\(r2\)
- 26: R_PPC64_TOC16_DS \.toc\+0x18
- 28: e8 62 00 20 ld r3,32\(r2\)
- 2a: R_PPC64_TOC16_DS \.toc\+0x20
- 2c: e8 62 00 28 ld r3,40\(r2\)
- 2e: R_PPC64_TOC16_DS \.toc\+0x28
- 30: 3c 80 00 28 lis r4,40
- 32: R_PPC64_TOC16_HA \.toc\+0x28
- 34: e8 62 00 28 ld r3,40\(r2\)
- 36: R_PPC64_TOC16_LO_DS \.toc\+0x28
- 38: 38 60 00 08 li r3,8
- 3c: 38 60 ff f8 li r3,-8
- 40: 38 60 00 08 li r3,8
- 44: 38 60 ff f8 li r3,-8
- 48: 38 60 ff f8 li r3,-8
- 4c: 38 60 00 08 li r3,8
- 50: 38 60 00 00 li r3,0
- 52: R_PPC64_ADDR16_LO \.data
- 54: 38 60 00 00 li r3,0
- 56: R_PPC64_ADDR16_HI \.data
- 58: 38 60 00 00 li r3,0
- 5a: R_PPC64_ADDR16_HA \.data
- 5c: 38 60 00 00 li r3,0
- 5e: R_PPC64_ADDR16_HIGHER \.data
- 60: 38 60 00 00 li r3,0
- 62: R_PPC64_ADDR16_HIGHERA \.data
- 64: 38 60 00 00 li r3,0
- 66: R_PPC64_ADDR16_HIGHEST \.data
- 68: 38 60 00 00 li r3,0
- 6a: R_PPC64_ADDR16_HIGHESTA \.data
- 6c: 38 60 ff f8 li r3,-8
- 70: 38 60 ff ff li r3,-1
- 74: 38 60 00 00 li r3,0
- 78: 38 60 ff ff li r3,-1
- 7c: 38 60 00 00 li r3,0
- 80: 38 60 ff ff li r3,-1
- 84: 38 60 00 00 li r3,0
- 88: e8 64 00 08 ld r3,8\(r4\)
- 8c: e8 60 00 00 ld r3,0\(0\)
- 8e: R_PPC64_ADDR16_LO_DS \.text
+ 0: (e8 63 00 00|00 00 63 e8) ld r3,0\(r3\)
+ (2|0): R_PPC64_ADDR16_LO_DS \.data
+ 4: (e8 63 00 0.|0. 00 63 e8) ld r3,.\(r3\)
+ (6|4): R_PPC64_ADDR16_LO_DS \.data\+0x8
+ 8: (e8 63 00 0.|0. 00 63 e8) ld r3,.\(r3\)
+ (a|8): R_PPC64_ADDR16_LO_DS \.data\+0x8
+ c: (e8 63 00 .0|.0 00 63 e8) ld r3,.*\(r3\)
+ (e|c): R_PPC64_ADDR16_LO_DS \.data\+0x10
+ 10: (e8 63 00 00|00 00 63 e8) ld r3,0\(r3\)
+ 1(0|2): R_PPC64_ADDR16_LO_DS esym0
+ 14: (e8 63 00 00|00 00 63 e8) ld r3,0\(r3\)
+ 1(6|4): R_PPC64_ADDR16_LO_DS esym1
+ 18: (e8 62 00 00|00 00 62 e8) ld r3,0\(r2\)
+ 1(a|8): R_PPC64_TOC16_DS \.toc
+ 1c: (e8 62 00 0.|0. 00 62 e8) ld r3,.\(r2\)
+ 1(e|c): R_PPC64_TOC16_DS \.toc\+0x8
+ 20: (e8 62 00 .0|.0 00 62 e8) ld r3,.*\(r2\)
+ 2(2|0): R_PPC64_TOC16_DS \.toc\+0x10
+ 24: (e8 62 00 ..|.. 00 62 e8) ld r3,.*\(r2\)
+ 2(6|4): R_PPC64_TOC16_DS \.toc\+0x18
+ 28: (e8 62 00 .0|.0 00 62 e8) ld r3,.*\(r2\)
+ 2(a|8): R_PPC64_TOC16_DS \.toc\+0x20
+ 2c: (e8 62 00 ..|.. 00 62 e8) ld r3,.*\(r2\)
+ 2(e|c): R_PPC64_TOC16_DS \.toc\+0x28
+ 30: (3c 80 00 ..|.. 00 80 3c) lis r4,.*
+ 3(2|0): R_PPC64_TOC16_HA \.toc\+0x28
+ 34: (e8 62 00 ..|.. 00 62 e8) ld r3,.*\(r2\)
+ 3(6|4): R_PPC64_TOC16_LO_DS \.toc\+0x28
+ 38: (38 60 00 08|08 00 60 38) li r3,8
+ 3c: (38 60 ff f8|f8 ff 60 38) li r3,-8
+ 40: (38 60 00 08|08 00 60 38) li r3,8
+ 44: (38 60 ff f8|f8 ff 60 38) li r3,-8
+ 48: (38 60 ff f8|f8 ff 60 38) li r3,-8
+ 4c: (38 60 00 08|08 00 60 38) li r3,8
+ 50: (38 60 00 00|00 00 60 38) li r3,0
+ 5(2|0): R_PPC64_ADDR16_LO \.data
+ 54: (38 60 00 00|00 00 60 38) li r3,0
+ 5(6|4): R_PPC64_ADDR16_HI \.data
+ 58: (38 60 00 00|00 00 60 38) li r3,0
+ 5(a|8): R_PPC64_ADDR16_HA \.data
+ 5c: (38 60 00 00|00 00 60 38) li r3,0
+ 5(e|c): R_PPC64_ADDR16_HIGHER \.data
+ 60: (38 60 00 00|00 00 60 38) li r3,0
+ 6(2|0): R_PPC64_ADDR16_HIGHERA \.data
+ 64: (38 60 00 00|00 00 60 38) li r3,0
+ 6(6|4): R_PPC64_ADDR16_HIGHEST \.data
+ 68: (38 60 00 00|00 00 60 38) li r3,0
+ 6(a|8): R_PPC64_ADDR16_HIGHESTA \.data
+ 6c: (38 60 ff f8|f8 ff 60 38) li r3,-8
+ 70: (38 60 ff ff|ff ff 60 38) li r3,-1
+ 74: (38 60 00 00|00 00 60 38) li r3,0
+ 78: (38 60 ff ff|ff ff 60 38) li r3,-1
+ 7c: (38 60 00 00|00 00 60 38) li r3,0
+ 80: (38 60 ff ff|ff ff 60 38) li r3,-1
+ 84: (38 60 00 00|00 00 60 38) li r3,0
+ 88: (e8 64 00 08|08 00 64 e8) ld r3,8\(r4\)
+ 8c: (e8 60 00 00|00 00 60 e8) ld r3,0\(0\)
+ 8(e|c): R_PPC64_ADDR16_LO_DS \.text
Disassembly of section \.data:
0000000000000000 <dsym0>:
- 0: 00 00 00 00 \.long 0x0
- 4: de ad be ef stfdu f21,-16657\(r13\)
+ 0: (00 00 00 00|ef be ad de) .*
+ 4: (de ad be ef|00 00 00 00) .*
0000000000000008 <dsym1>:
- 8: 00 00 00 00 \.long 0x0
- c: ca fe ba be lfd f23,-17730\(r30\)
+ 8: (00 00 00 00|be ba fe ca) .*
+ c: (ca fe ba be|00 00 00 00) .*
0000000000000010 <datpt>:
- 10: 00 98 96 80 \.long 0x989680
+ 10: 00 00 00 00 .*
10: R_PPC64_REL32 jk\+0x989680
0000000000000014 <dat0>:
- 14: ff ff ff fc fnmsub f31,f31,f31,f31
+ 14: 00 00 00 00 .*
14: R_PPC64_REL32 jk-0x4
0000000000000018 <dat1>:
- 18: 00 00 00 00 \.long 0x0
+ 18: 00 00 00 00 .*
18: R_PPC64_REL32 jk
000000000000001c <dat2>:
- 1c: 00 00 00 04 \.long 0x4
+ 1c: 00 00 00 00 .*
1c: R_PPC64_REL32 jk\+0x4
0000000000000020 <dat3>:
- 20: 00 00 00 00 \.long 0x0
+ \.\.\.
20: R_PPC64_REL64 jk\+0x8
- 24: 00 00 00 08 \.long 0x8
0000000000000028 <dat4>:
- 28: 00 00 00 00 \.long 0x0
+ \.\.\.
28: R_PPC64_REL64 jk\+0x10
- 2c: 00 00 00 10 \.long 0x10
Disassembly of section \.toc:
0000000000000000 <\.toc>:
- \.\.\.
+#...
0: R_PPC64_ADDR64 \.data
+#...
8: R_PPC64_ADDR64 \.data\+0x8
- c: 00 00 00 08 \.long 0x8
- 10: 00 00 00 00 \.long 0x0
+#...
10: R_PPC64_ADDR64 \.data\+0x8
- 14: 00 00 00 08 \.long 0x8
- 18: 00 00 00 00 \.long 0x0
+#...
18: R_PPC64_ADDR64 \.data\+0x10
- 1c: 00 00 00 10 \.long 0x10
- \.\.\.
+#...
20: R_PPC64_ADDR64 esym0
28: R_PPC64_ADDR64 esym1
#objdump: -dr -Mtitan
#name: AppliedMicro Titan tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+0000000 <start>:
- 0: 4e 80 00 20 blr
- 4: 0c 81 00 00 tweqi r1,0
- 8: 10 41 01 58 macchw r2,r1,r0
- c: 10 41 01 59 macchw\. r2,r1,r0
- 10: 10 41 05 58 macchwo r2,r1,r0
- 14: 10 41 05 59 macchwo\. r2,r1,r0
- 18: 10 41 01 d8 macchws r2,r1,r0
- 1c: 10 41 01 d9 macchws\. r2,r1,r0
- 20: 10 41 05 d8 macchwso r2,r1,r0
- 24: 10 41 05 d9 macchwso\. r2,r1,r0
- 28: 10 41 01 98 macchwsu r2,r1,r0
- 2c: 10 41 01 99 macchwsu\. r2,r1,r0
- 30: 10 41 05 98 macchwsuo r2,r1,r0
- 34: 10 41 05 99 macchwsuo\. r2,r1,r0
- 38: 10 41 01 18 macchwu r2,r1,r0
- 3c: 10 41 01 19 macchwu\. r2,r1,r0
- 40: 10 41 05 18 macchwuo r2,r1,r0
- 44: 10 41 05 19 macchwuo\. r2,r1,r0
- 48: 10 41 00 58 machhw r2,r1,r0
- 4c: 10 41 00 59 machhw\. r2,r1,r0
- 50: 10 41 04 58 machhwo r2,r1,r0
- 54: 10 41 04 59 machhwo\. r2,r1,r0
- 58: 10 41 00 d8 machhws r2,r1,r0
- 5c: 10 41 00 d9 machhws\. r2,r1,r0
- 60: 10 41 04 d8 machhwso r2,r1,r0
- 64: 10 41 04 d9 machhwso\. r2,r1,r0
- 68: 10 41 00 98 machhwsu r2,r1,r0
- 6c: 10 41 00 99 machhwsu\. r2,r1,r0
- 70: 10 41 04 98 machhwsuo r2,r1,r0
- 74: 10 41 04 99 machhwsuo\. r2,r1,r0
- 78: 10 41 00 18 machhwu r2,r1,r0
- 7c: 10 41 00 19 machhwu\. r2,r1,r0
- 80: 10 41 04 18 machhwuo r2,r1,r0
- 84: 10 41 04 19 machhwuo\. r2,r1,r0
- 88: 10 41 03 58 maclhw r2,r1,r0
- 8c: 10 41 03 59 maclhw\. r2,r1,r0
- 90: 10 41 07 58 maclhwo r2,r1,r0
- 94: 10 41 07 59 maclhwo\. r2,r1,r0
- 98: 10 41 03 d8 maclhws r2,r1,r0
- 9c: 10 41 03 d9 maclhws\. r2,r1,r0
- a0: 10 41 07 d8 maclhwso r2,r1,r0
- a4: 10 41 07 d9 maclhwso\. r2,r1,r0
- a8: 10 41 03 98 maclhwsu r2,r1,r0
- ac: 10 41 03 99 maclhwsu\. r2,r1,r0
- b0: 10 41 07 98 maclhwsuo r2,r1,r0
- b4: 10 41 07 99 maclhwsuo\. r2,r1,r0
- b8: 10 41 03 18 maclhwu r2,r1,r0
- bc: 10 41 03 19 maclhwu\. r2,r1,r0
- c0: 10 41 07 18 maclhwuo r2,r1,r0
- c4: 10 41 07 19 maclhwuo\. r2,r1,r0
- c8: 10 41 01 5c nmacchw r2,r1,r0
- cc: 10 41 01 5d nmacchw\. r2,r1,r0
- d0: 10 41 05 5c nmacchwo r2,r1,r0
- d4: 10 41 05 5d nmacchwo\. r2,r1,r0
- d8: 10 41 01 dc nmacchws r2,r1,r0
- dc: 10 41 01 dd nmacchws\. r2,r1,r0
- e0: 10 41 05 dc nmacchwso r2,r1,r0
- e4: 10 41 05 dd nmacchwso\. r2,r1,r0
- e8: 10 41 00 5c nmachhw r2,r1,r0
- ec: 10 41 00 5d nmachhw\. r2,r1,r0
- f0: 10 41 04 5c nmachhwo r2,r1,r0
- f4: 10 41 04 5d nmachhwo\. r2,r1,r0
- f8: 10 41 00 dc nmachhws r2,r1,r0
- fc: 10 41 00 dd nmachhws\. r2,r1,r0
- 100: 10 41 04 dc nmachhwso r2,r1,r0
- 104: 10 41 04 dd nmachhwso\. r2,r1,r0
- 108: 10 41 03 5c nmaclhw r2,r1,r0
- 10c: 10 41 03 5d nmaclhw\. r2,r1,r0
- 110: 10 41 07 5c nmaclhwo r2,r1,r0
- 114: 10 41 07 5d nmaclhwo\. r2,r1,r0
- 118: 10 41 03 dc nmaclhws r2,r1,r0
- 11c: 10 41 03 dd nmaclhws\. r2,r1,r0
- 120: 10 41 07 dc nmaclhwso r2,r1,r0
- 124: 10 41 07 dd nmaclhwso\. r2,r1,r0
- 128: 10 41 01 50 mulchw r2,r1,r0
- 12c: 10 41 01 51 mulchw\. r2,r1,r0
- 130: 10 41 01 10 mulchwu r2,r1,r0
- 134: 10 41 01 11 mulchwu\. r2,r1,r0
- 138: 10 41 00 50 mulhhw r2,r1,r0
- 13c: 10 41 00 51 mulhhw\. r2,r1,r0
- 140: 10 41 00 10 mulhhwu r2,r1,r0
- 144: 10 41 00 11 mulhhwu\. r2,r1,r0
- 148: 10 41 03 50 mullhw r2,r1,r0
- 14c: 10 41 03 51 mullhw\. r2,r1,r0
- 150: 10 41 03 10 mullhwu r2,r1,r0
- 154: 10 41 03 11 mullhwu\. r2,r1,r0
- 158: 7c 22 00 9c dlmzb r2,r1,r0
- 15c: 7c 22 00 9d dlmzb\. r2,r1,r0
- 160: 7c 02 0b 8c dccci r2,r1
- 164: 7c 02 0f 8c iccci r2,r1
- 168: 7c 02 0b 0c dcblc r2,r1
- 16c: 7c 02 0b 0c dcblc r2,r1
- 170: 7c 22 0b 0c dcblc 1,r2,r1
- 174: 7c 02 09 4c dcbtls r2,r1
- 178: 7c 02 09 4c dcbtls r2,r1
- 17c: 7c 22 09 4c dcbtls 1,r2,r1
- 180: 7c 02 09 0c dcbtstls r2,r1
- 184: 7c 02 09 0c dcbtstls r2,r1
- 188: 7c 22 09 0c dcbtstls 1,r2,r1
- 18c: 7c 02 09 cc icblc r2,r1
- 190: 7c 02 09 cc icblc r2,r1
- 194: 7c 22 09 cc icblc 1,r2,r1
- 198: 7c 02 0b cc icbtls r2,r1
- 19c: 7c 02 0b cc icbtls r2,r1
- 1a0: 7c 22 0b cc icbtls 1,r2,r1
- 1a4: 7c 41 02 8c dcread r2,r1,r0
- 1a8: 7c 02 0f cc icread r2,r1
- 1ac: 7c 41 02 9c mfpmr r2,1
- 1b0: 7c 22 02 9c mfpmr r1,2
- 1b4: 7c 81 02 a6 mfxer r4
- 1b8: 7c 81 02 a6 mfxer r4
- 1bc: 7c 88 02 a6 mflr r4
- 1c0: 7c 88 02 a6 mflr r4
- 1c4: 7c 89 02 a6 mfctr r4
- 1c8: 7c 89 02 a6 mfctr r4
- 1cc: 7c 96 02 a6 mfdec r4
- 1d0: 7c 96 02 a6 mfdec r4
- 1d4: 7c 9a 02 a6 mfsrr0 r4
- 1d8: 7c 9a 02 a6 mfsrr0 r4
- 1dc: 7c 9b 02 a6 mfsrr1 r4
- 1e0: 7c 9b 02 a6 mfsrr1 r4
- 1e4: 7c 90 0a a6 mfpid r4
- 1e8: 7c 90 0a a6 mfpid r4
- 1ec: 7c 9a 0a a6 mfcsrr0 r4
- 1f0: 7c 9a 0a a6 mfcsrr0 r4
- 1f4: 7c 9b 0a a6 mfcsrr1 r4
- 1f8: 7c 9b 0a a6 mfcsrr1 r4
- 1fc: 7c 9d 0a a6 mfdear r4
- 200: 7c 9d 0a a6 mfdear r4
- 204: 7c 9e 0a a6 mfesr r4
- 208: 7c 9e 0a a6 mfesr r4
- 20c: 7c 9f 0a a6 mfivpr r4
- 210: 7c 9f 0a a6 mfivpr r4
- 214: 7c 80 42 a6 mfusprg0 r4
- 218: 7c 80 42 a6 mfusprg0 r4
- 21c: 7c 84 42 a6 mfsprg r4,4
- 220: 7c 84 42 a6 mfsprg r4,4
- 224: 7c 85 42 a6 mfsprg r4,5
- 228: 7c 85 42 a6 mfsprg r4,5
- 22c: 7c 86 42 a6 mfsprg r4,6
- 230: 7c 86 42 a6 mfsprg r4,6
- 234: 7c 87 42 a6 mfsprg r4,7
- 238: 7c 87 42 a6 mfsprg r4,7
- 23c: 7c 8c 42 a6 mftb r4
- 240: 7c 8c 42 a6 mftb r4
- 244: 7c 8c 42 a6 mftb r4
- 248: 7c 8d 42 a6 mftbu r4
- 24c: 7c 8d 42 a6 mftbu r4
- 250: 7c 90 42 a6 mfsprg r4,0
- 254: 7c 90 42 a6 mfsprg r4,0
- 258: 7c 91 42 a6 mfsprg r4,1
- 25c: 7c 91 42 a6 mfsprg r4,1
- 260: 7c 92 42 a6 mfsprg r4,2
- 264: 7c 92 42 a6 mfsprg r4,2
- 268: 7c 93 42 a6 mfsprg r4,3
- 26c: 7c 93 42 a6 mfsprg r4,3
- 270: 7c 9e 42 a6 mfpir r4
- 274: 7c 9e 42 a6 mfpir r4
- 278: 7c 9f 42 a6 mfpvr r4
- 27c: 7c 9f 42 a6 mfpvr r4
- 280: 7c 90 4a a6 mfdbsr r4
- 284: 7c 90 4a a6 mfdbsr r4
- 288: 7c 94 4a a6 mfdbcr0 r4
- 28c: 7c 94 4a a6 mfdbcr0 r4
- 290: 7c 95 4a a6 mfdbcr1 r4
- 294: 7c 95 4a a6 mfdbcr1 r4
- 298: 7c 96 4a a6 mfdbcr2 r4
- 29c: 7c 96 4a a6 mfdbcr2 r4
- 2a0: 7c 98 4a a6 mfiac1 r4
- 2a4: 7c 98 4a a6 mfiac1 r4
- 2a8: 7c 99 4a a6 mfiac2 r4
- 2ac: 7c 99 4a a6 mfiac2 r4
- 2b0: 7c 9a 4a a6 mfiac3 r4
- 2b4: 7c 9a 4a a6 mfiac3 r4
- 2b8: 7c 9b 4a a6 mfiac4 r4
- 2bc: 7c 9b 4a a6 mfiac4 r4
- 2c0: 7c 9c 4a a6 mfdac1 r4
- 2c4: 7c 9c 4a a6 mfdac1 r4
- 2c8: 7c 9d 4a a6 mfdac2 r4
- 2cc: 7c 9d 4a a6 mfdac2 r4
- 2d0: 7c 9e 4a a6 mfdvc1 r4
- 2d4: 7c 9e 4a a6 mfdvc1 r4
- 2d8: 7c 9f 4a a6 mfdvc2 r4
- 2dc: 7c 9f 4a a6 mfdvc2 r4
- 2e0: 7c 90 52 a6 mftsr r4
- 2e4: 7c 90 52 a6 mftsr r4
- 2e8: 7c 94 52 a6 mftcr r4
- 2ec: 7c 94 52 a6 mftcr r4
- 2f0: 7c 90 62 a6 mfivor0 r4
- 2f4: 7c 90 62 a6 mfivor0 r4
- 2f8: 7c 91 62 a6 mfivor1 r4
- 2fc: 7c 91 62 a6 mfivor1 r4
- 300: 7c 92 62 a6 mfivor2 r4
- 304: 7c 92 62 a6 mfivor2 r4
- 308: 7c 93 62 a6 mfivor3 r4
- 30c: 7c 93 62 a6 mfivor3 r4
- 310: 7c 94 62 a6 mfivor4 r4
- 314: 7c 94 62 a6 mfivor4 r4
- 318: 7c 95 62 a6 mfivor5 r4
- 31c: 7c 95 62 a6 mfivor5 r4
- 320: 7c 96 62 a6 mfivor6 r4
- 324: 7c 96 62 a6 mfivor6 r4
- 328: 7c 97 62 a6 mfivor7 r4
- 32c: 7c 97 62 a6 mfivor7 r4
- 330: 7c 98 62 a6 mfivor8 r4
- 334: 7c 98 62 a6 mfivor8 r4
- 338: 7c 99 62 a6 mfivor9 r4
- 33c: 7c 99 62 a6 mfivor9 r4
- 340: 7c 9a 62 a6 mfivor10 r4
- 344: 7c 9a 62 a6 mfivor10 r4
- 348: 7c 9b 62 a6 mfivor11 r4
- 34c: 7c 9b 62 a6 mfivor11 r4
- 350: 7c 9c 62 a6 mfivor12 r4
- 354: 7c 9c 62 a6 mfivor12 r4
- 358: 7c 9d 62 a6 mfivor13 r4
- 35c: 7c 9d 62 a6 mfivor13 r4
- 360: 7c 9e 62 a6 mfivor14 r4
- 364: 7c 9e 62 a6 mfivor14 r4
- 368: 7c 9f 62 a6 mfivor15 r4
- 36c: 7c 9f 62 a6 mfivor15 r4
- 370: 7c 93 82 a6 mfivor35 r4
- 374: 7c 93 82 a6 mfivor35 r4
- 378: 7c 9a 8a a6 mfdc_dat r4
- 37c: 7c 9a 8a a6 mfdc_dat r4
- 380: 7c 9b 8a a6 mfmcsrr1 r4
- 384: 7c 9b 8a a6 mfmcsrr1 r4
- 388: 7c 9c 8a a6 mfmcsr r4
- 38c: 7c 9c 8a a6 mfmcsr r4
- 390: 7c 90 da a6 mfivndx r4
- 394: 7c 90 da a6 mfivndx r4
- 398: 7c 91 da a6 mfdvndx r4
- 39c: 7c 91 da a6 mfdvndx r4
- 3a0: 7c 92 da a6 mfivlim r4
- 3a4: 7c 92 da a6 mfivlim r4
- 3a8: 7c 93 da a6 mfdvlim r4
- 3ac: 7c 93 da a6 mfdvlim r4
- 3b0: 7c 94 da a6 mfclcsr r4
- 3b4: 7c 94 da a6 mfclcsr r4
- 3b8: 7c 98 da a6 mfccr1 r4
- 3bc: 7c 98 da a6 mfccr1 r4
- 3c0: 7c 9b e2 a6 mfrstcfg r4
- 3c4: 7c 9b e2 a6 mfrstcfg r4
- 3c8: 7c 9c e2 a6 mfdcdbtrl r4
- 3cc: 7c 9c e2 a6 mfdcdbtrl r4
- 3d0: 7c 9d e2 a6 mfdcdbtrh r4
- 3d4: 7c 9d e2 a6 mfdcdbtrh r4
- 3d8: 7c 9f e2 a6 mficdbtr r4
- 3dc: 7c 9f e2 a6 mficdbtr r4
- 3e0: 7c 92 ea a6 mfmmucr r4
- 3e4: 7c 92 ea a6 mfmmucr r4
- 3e8: 7c 93 ea a6 mfccr0 r4
- 3ec: 7c 93 ea a6 mfccr0 r4
- 3f0: 7c 93 f2 a6 mficdbdr r4
- 3f4: 7c 93 f2 a6 mficdbdr r4
- 3f8: 7c 93 fa a6 mfdbdr r4
- 3fc: 7c 93 fa a6 mfdbdr r4
- 400: 7c 96 0b a6 mtdecar r4
- 404: 7c 96 0b a6 mtdecar r4
+ 0: (4e 80 00 20|20 00 80 4e) blr
+ 4: (0c 81 00 00|00 00 81 0c) tweqi r1,0
+ 8: (10 41 01 58|58 01 41 10) macchw r2,r1,r0
+ c: (10 41 01 59|59 01 41 10) macchw\. r2,r1,r0
+ 10: (10 41 05 58|58 05 41 10) macchwo r2,r1,r0
+ 14: (10 41 05 59|59 05 41 10) macchwo\. r2,r1,r0
+ 18: (10 41 01 d8|d8 01 41 10) macchws r2,r1,r0
+ 1c: (10 41 01 d9|d9 01 41 10) macchws\. r2,r1,r0
+ 20: (10 41 05 d8|d8 05 41 10) macchwso r2,r1,r0
+ 24: (10 41 05 d9|d9 05 41 10) macchwso\. r2,r1,r0
+ 28: (10 41 01 98|98 01 41 10) macchwsu r2,r1,r0
+ 2c: (10 41 01 99|99 01 41 10) macchwsu\. r2,r1,r0
+ 30: (10 41 05 98|98 05 41 10) macchwsuo r2,r1,r0
+ 34: (10 41 05 99|99 05 41 10) macchwsuo\. r2,r1,r0
+ 38: (10 41 01 18|18 01 41 10) macchwu r2,r1,r0
+ 3c: (10 41 01 19|19 01 41 10) macchwu\. r2,r1,r0
+ 40: (10 41 05 18|18 05 41 10) macchwuo r2,r1,r0
+ 44: (10 41 05 19|19 05 41 10) macchwuo\. r2,r1,r0
+ 48: (10 41 00 58|58 00 41 10) machhw r2,r1,r0
+ 4c: (10 41 00 59|59 00 41 10) machhw\. r2,r1,r0
+ 50: (10 41 04 58|58 04 41 10) machhwo r2,r1,r0
+ 54: (10 41 04 59|59 04 41 10) machhwo\. r2,r1,r0
+ 58: (10 41 00 d8|d8 00 41 10) machhws r2,r1,r0
+ 5c: (10 41 00 d9|d9 00 41 10) machhws\. r2,r1,r0
+ 60: (10 41 04 d8|d8 04 41 10) machhwso r2,r1,r0
+ 64: (10 41 04 d9|d9 04 41 10) machhwso\. r2,r1,r0
+ 68: (10 41 00 98|98 00 41 10) machhwsu r2,r1,r0
+ 6c: (10 41 00 99|99 00 41 10) machhwsu\. r2,r1,r0
+ 70: (10 41 04 98|98 04 41 10) machhwsuo r2,r1,r0
+ 74: (10 41 04 99|99 04 41 10) machhwsuo\. r2,r1,r0
+ 78: (10 41 00 18|18 00 41 10) machhwu r2,r1,r0
+ 7c: (10 41 00 19|19 00 41 10) machhwu\. r2,r1,r0
+ 80: (10 41 04 18|18 04 41 10) machhwuo r2,r1,r0
+ 84: (10 41 04 19|19 04 41 10) machhwuo\. r2,r1,r0
+ 88: (10 41 03 58|58 03 41 10) maclhw r2,r1,r0
+ 8c: (10 41 03 59|59 03 41 10) maclhw\. r2,r1,r0
+ 90: (10 41 07 58|58 07 41 10) maclhwo r2,r1,r0
+ 94: (10 41 07 59|59 07 41 10) maclhwo\. r2,r1,r0
+ 98: (10 41 03 d8|d8 03 41 10) maclhws r2,r1,r0
+ 9c: (10 41 03 d9|d9 03 41 10) maclhws\. r2,r1,r0
+ a0: (10 41 07 d8|d8 07 41 10) maclhwso r2,r1,r0
+ a4: (10 41 07 d9|d9 07 41 10) maclhwso\. r2,r1,r0
+ a8: (10 41 03 98|98 03 41 10) maclhwsu r2,r1,r0
+ ac: (10 41 03 99|99 03 41 10) maclhwsu\. r2,r1,r0
+ b0: (10 41 07 98|98 07 41 10) maclhwsuo r2,r1,r0
+ b4: (10 41 07 99|99 07 41 10) maclhwsuo\. r2,r1,r0
+ b8: (10 41 03 18|18 03 41 10) maclhwu r2,r1,r0
+ bc: (10 41 03 19|19 03 41 10) maclhwu\. r2,r1,r0
+ c0: (10 41 07 18|18 07 41 10) maclhwuo r2,r1,r0
+ c4: (10 41 07 19|19 07 41 10) maclhwuo\. r2,r1,r0
+ c8: (10 41 01 5c|5c 01 41 10) nmacchw r2,r1,r0
+ cc: (10 41 01 5d|5d 01 41 10) nmacchw\. r2,r1,r0
+ d0: (10 41 05 5c|5c 05 41 10) nmacchwo r2,r1,r0
+ d4: (10 41 05 5d|5d 05 41 10) nmacchwo\. r2,r1,r0
+ d8: (10 41 01 dc|dc 01 41 10) nmacchws r2,r1,r0
+ dc: (10 41 01 dd|dd 01 41 10) nmacchws\. r2,r1,r0
+ e0: (10 41 05 dc|dc 05 41 10) nmacchwso r2,r1,r0
+ e4: (10 41 05 dd|dd 05 41 10) nmacchwso\. r2,r1,r0
+ e8: (10 41 00 5c|5c 00 41 10) nmachhw r2,r1,r0
+ ec: (10 41 00 5d|5d 00 41 10) nmachhw\. r2,r1,r0
+ f0: (10 41 04 5c|5c 04 41 10) nmachhwo r2,r1,r0
+ f4: (10 41 04 5d|5d 04 41 10) nmachhwo\. r2,r1,r0
+ f8: (10 41 00 dc|dc 00 41 10) nmachhws r2,r1,r0
+ fc: (10 41 00 dd|dd 00 41 10) nmachhws\. r2,r1,r0
+ 100: (10 41 04 dc|dc 04 41 10) nmachhwso r2,r1,r0
+ 104: (10 41 04 dd|dd 04 41 10) nmachhwso\. r2,r1,r0
+ 108: (10 41 03 5c|5c 03 41 10) nmaclhw r2,r1,r0
+ 10c: (10 41 03 5d|5d 03 41 10) nmaclhw\. r2,r1,r0
+ 110: (10 41 07 5c|5c 07 41 10) nmaclhwo r2,r1,r0
+ 114: (10 41 07 5d|5d 07 41 10) nmaclhwo\. r2,r1,r0
+ 118: (10 41 03 dc|dc 03 41 10) nmaclhws r2,r1,r0
+ 11c: (10 41 03 dd|dd 03 41 10) nmaclhws\. r2,r1,r0
+ 120: (10 41 07 dc|dc 07 41 10) nmaclhwso r2,r1,r0
+ 124: (10 41 07 dd|dd 07 41 10) nmaclhwso\. r2,r1,r0
+ 128: (10 41 01 50|50 01 41 10) mulchw r2,r1,r0
+ 12c: (10 41 01 51|51 01 41 10) mulchw\. r2,r1,r0
+ 130: (10 41 01 10|10 01 41 10) mulchwu r2,r1,r0
+ 134: (10 41 01 11|11 01 41 10) mulchwu\. r2,r1,r0
+ 138: (10 41 00 50|50 00 41 10) mulhhw r2,r1,r0
+ 13c: (10 41 00 51|51 00 41 10) mulhhw\. r2,r1,r0
+ 140: (10 41 00 10|10 00 41 10) mulhhwu r2,r1,r0
+ 144: (10 41 00 11|11 00 41 10) mulhhwu\. r2,r1,r0
+ 148: (10 41 03 50|50 03 41 10) mullhw r2,r1,r0
+ 14c: (10 41 03 51|51 03 41 10) mullhw\. r2,r1,r0
+ 150: (10 41 03 10|10 03 41 10) mullhwu r2,r1,r0
+ 154: (10 41 03 11|11 03 41 10) mullhwu\. r2,r1,r0
+ 158: (7c 22 00 9c|9c 00 22 7c) dlmzb r2,r1,r0
+ 15c: (7c 22 00 9d|9d 00 22 7c) dlmzb\. r2,r1,r0
+ 160: (7c 02 0b 8c|8c 0b 02 7c) dccci r2,r1
+ 164: (7c 02 0f 8c|8c 0f 02 7c) iccci r2,r1
+ 168: (7c 02 0b 0c|0c 0b 02 7c) dcblc r2,r1
+ 16c: (7c 02 0b 0c|0c 0b 02 7c) dcblc r2,r1
+ 170: (7c 22 0b 0c|0c 0b 22 7c) dcblc 1,r2,r1
+ 174: (7c 02 09 4c|4c 09 02 7c) dcbtls r2,r1
+ 178: (7c 02 09 4c|4c 09 02 7c) dcbtls r2,r1
+ 17c: (7c 22 09 4c|4c 09 22 7c) dcbtls 1,r2,r1
+ 180: (7c 02 09 0c|0c 09 02 7c) dcbtstls r2,r1
+ 184: (7c 02 09 0c|0c 09 02 7c) dcbtstls r2,r1
+ 188: (7c 22 09 0c|0c 09 22 7c) dcbtstls 1,r2,r1
+ 18c: (7c 02 09 cc|cc 09 02 7c) icblc r2,r1
+ 190: (7c 02 09 cc|cc 09 02 7c) icblc r2,r1
+ 194: (7c 22 09 cc|cc 09 22 7c) icblc 1,r2,r1
+ 198: (7c 02 0b cc|cc 0b 02 7c) icbtls r2,r1
+ 19c: (7c 02 0b cc|cc 0b 02 7c) icbtls r2,r1
+ 1a0: (7c 22 0b cc|cc 0b 22 7c) icbtls 1,r2,r1
+ 1a4: (7c 41 02 8c|8c 02 41 7c) dcread r2,r1,r0
+ 1a8: (7c 02 0f cc|cc 0f 02 7c) icread r2,r1
+ 1ac: (7c 41 02 9c|9c 02 41 7c) mfpmr r2,1
+ 1b0: (7c 22 02 9c|9c 02 22 7c) mfpmr r1,2
+ 1b4: (7c 81 02 a6|a6 02 81 7c) mfxer r4
+ 1b8: (7c 81 02 a6|a6 02 81 7c) mfxer r4
+ 1bc: (7c 88 02 a6|a6 02 88 7c) mflr r4
+ 1c0: (7c 88 02 a6|a6 02 88 7c) mflr r4
+ 1c4: (7c 89 02 a6|a6 02 89 7c) mfctr r4
+ 1c8: (7c 89 02 a6|a6 02 89 7c) mfctr r4
+ 1cc: (7c 96 02 a6|a6 02 96 7c) mfdec r4
+ 1d0: (7c 96 02 a6|a6 02 96 7c) mfdec r4
+ 1d4: (7c 9a 02 a6|a6 02 9a 7c) mfsrr0 r4
+ 1d8: (7c 9a 02 a6|a6 02 9a 7c) mfsrr0 r4
+ 1dc: (7c 9b 02 a6|a6 02 9b 7c) mfsrr1 r4
+ 1e0: (7c 9b 02 a6|a6 02 9b 7c) mfsrr1 r4
+ 1e4: (7c 90 0a a6|a6 0a 90 7c) mfpid r4
+ 1e8: (7c 90 0a a6|a6 0a 90 7c) mfpid r4
+ 1ec: (7c 9a 0a a6|a6 0a 9a 7c) mfcsrr0 r4
+ 1f0: (7c 9a 0a a6|a6 0a 9a 7c) mfcsrr0 r4
+ 1f4: (7c 9b 0a a6|a6 0a 9b 7c) mfcsrr1 r4
+ 1f8: (7c 9b 0a a6|a6 0a 9b 7c) mfcsrr1 r4
+ 1fc: (7c 9d 0a a6|a6 0a 9d 7c) mfdear r4
+ 200: (7c 9d 0a a6|a6 0a 9d 7c) mfdear r4
+ 204: (7c 9e 0a a6|a6 0a 9e 7c) mfesr r4
+ 208: (7c 9e 0a a6|a6 0a 9e 7c) mfesr r4
+ 20c: (7c 9f 0a a6|a6 0a 9f 7c) mfivpr r4
+ 210: (7c 9f 0a a6|a6 0a 9f 7c) mfivpr r4
+ 214: (7c 80 42 a6|a6 42 80 7c) mfusprg0 r4
+ 218: (7c 80 42 a6|a6 42 80 7c) mfusprg0 r4
+ 21c: (7c 84 42 a6|a6 42 84 7c) mfsprg r4,4
+ 220: (7c 84 42 a6|a6 42 84 7c) mfsprg r4,4
+ 224: (7c 85 42 a6|a6 42 85 7c) mfsprg r4,5
+ 228: (7c 85 42 a6|a6 42 85 7c) mfsprg r4,5
+ 22c: (7c 86 42 a6|a6 42 86 7c) mfsprg r4,6
+ 230: (7c 86 42 a6|a6 42 86 7c) mfsprg r4,6
+ 234: (7c 87 42 a6|a6 42 87 7c) mfsprg r4,7
+ 238: (7c 87 42 a6|a6 42 87 7c) mfsprg r4,7
+ 23c: (7c 8c 42 a6|a6 42 8c 7c) mftb r4
+ 240: (7c 8c 42 a6|a6 42 8c 7c) mftb r4
+ 244: (7c 8c 42 a6|a6 42 8c 7c) mftb r4
+ 248: (7c 8d 42 a6|a6 42 8d 7c) mftbu r4
+ 24c: (7c 8d 42 a6|a6 42 8d 7c) mftbu r4
+ 250: (7c 90 42 a6|a6 42 90 7c) mfsprg r4,0
+ 254: (7c 90 42 a6|a6 42 90 7c) mfsprg r4,0
+ 258: (7c 91 42 a6|a6 42 91 7c) mfsprg r4,1
+ 25c: (7c 91 42 a6|a6 42 91 7c) mfsprg r4,1
+ 260: (7c 92 42 a6|a6 42 92 7c) mfsprg r4,2
+ 264: (7c 92 42 a6|a6 42 92 7c) mfsprg r4,2
+ 268: (7c 93 42 a6|a6 42 93 7c) mfsprg r4,3
+ 26c: (7c 93 42 a6|a6 42 93 7c) mfsprg r4,3
+ 270: (7c 9e 42 a6|a6 42 9e 7c) mfpir r4
+ 274: (7c 9e 42 a6|a6 42 9e 7c) mfpir r4
+ 278: (7c 9f 42 a6|a6 42 9f 7c) mfpvr r4
+ 27c: (7c 9f 42 a6|a6 42 9f 7c) mfpvr r4
+ 280: (7c 90 4a a6|a6 4a 90 7c) mfdbsr r4
+ 284: (7c 90 4a a6|a6 4a 90 7c) mfdbsr r4
+ 288: (7c 94 4a a6|a6 4a 94 7c) mfdbcr0 r4
+ 28c: (7c 94 4a a6|a6 4a 94 7c) mfdbcr0 r4
+ 290: (7c 95 4a a6|a6 4a 95 7c) mfdbcr1 r4
+ 294: (7c 95 4a a6|a6 4a 95 7c) mfdbcr1 r4
+ 298: (7c 96 4a a6|a6 4a 96 7c) mfdbcr2 r4
+ 29c: (7c 96 4a a6|a6 4a 96 7c) mfdbcr2 r4
+ 2a0: (7c 98 4a a6|a6 4a 98 7c) mfiac1 r4
+ 2a4: (7c 98 4a a6|a6 4a 98 7c) mfiac1 r4
+ 2a8: (7c 99 4a a6|a6 4a 99 7c) mfiac2 r4
+ 2ac: (7c 99 4a a6|a6 4a 99 7c) mfiac2 r4
+ 2b0: (7c 9a 4a a6|a6 4a 9a 7c) mfiac3 r4
+ 2b4: (7c 9a 4a a6|a6 4a 9a 7c) mfiac3 r4
+ 2b8: (7c 9b 4a a6|a6 4a 9b 7c) mfiac4 r4
+ 2bc: (7c 9b 4a a6|a6 4a 9b 7c) mfiac4 r4
+ 2c0: (7c 9c 4a a6|a6 4a 9c 7c) mfdac1 r4
+ 2c4: (7c 9c 4a a6|a6 4a 9c 7c) mfdac1 r4
+ 2c8: (7c 9d 4a a6|a6 4a 9d 7c) mfdac2 r4
+ 2cc: (7c 9d 4a a6|a6 4a 9d 7c) mfdac2 r4
+ 2d0: (7c 9e 4a a6|a6 4a 9e 7c) mfdvc1 r4
+ 2d4: (7c 9e 4a a6|a6 4a 9e 7c) mfdvc1 r4
+ 2d8: (7c 9f 4a a6|a6 4a 9f 7c) mfdvc2 r4
+ 2dc: (7c 9f 4a a6|a6 4a 9f 7c) mfdvc2 r4
+ 2e0: (7c 90 52 a6|a6 52 90 7c) mftsr r4
+ 2e4: (7c 90 52 a6|a6 52 90 7c) mftsr r4
+ 2e8: (7c 94 52 a6|a6 52 94 7c) mftcr r4
+ 2ec: (7c 94 52 a6|a6 52 94 7c) mftcr r4
+ 2f0: (7c 90 62 a6|a6 62 90 7c) mfivor0 r4
+ 2f4: (7c 90 62 a6|a6 62 90 7c) mfivor0 r4
+ 2f8: (7c 91 62 a6|a6 62 91 7c) mfivor1 r4
+ 2fc: (7c 91 62 a6|a6 62 91 7c) mfivor1 r4
+ 300: (7c 92 62 a6|a6 62 92 7c) mfivor2 r4
+ 304: (7c 92 62 a6|a6 62 92 7c) mfivor2 r4
+ 308: (7c 93 62 a6|a6 62 93 7c) mfivor3 r4
+ 30c: (7c 93 62 a6|a6 62 93 7c) mfivor3 r4
+ 310: (7c 94 62 a6|a6 62 94 7c) mfivor4 r4
+ 314: (7c 94 62 a6|a6 62 94 7c) mfivor4 r4
+ 318: (7c 95 62 a6|a6 62 95 7c) mfivor5 r4
+ 31c: (7c 95 62 a6|a6 62 95 7c) mfivor5 r4
+ 320: (7c 96 62 a6|a6 62 96 7c) mfivor6 r4
+ 324: (7c 96 62 a6|a6 62 96 7c) mfivor6 r4
+ 328: (7c 97 62 a6|a6 62 97 7c) mfivor7 r4
+ 32c: (7c 97 62 a6|a6 62 97 7c) mfivor7 r4
+ 330: (7c 98 62 a6|a6 62 98 7c) mfivor8 r4
+ 334: (7c 98 62 a6|a6 62 98 7c) mfivor8 r4
+ 338: (7c 99 62 a6|a6 62 99 7c) mfivor9 r4
+ 33c: (7c 99 62 a6|a6 62 99 7c) mfivor9 r4
+ 340: (7c 9a 62 a6|a6 62 9a 7c) mfivor10 r4
+ 344: (7c 9a 62 a6|a6 62 9a 7c) mfivor10 r4
+ 348: (7c 9b 62 a6|a6 62 9b 7c) mfivor11 r4
+ 34c: (7c 9b 62 a6|a6 62 9b 7c) mfivor11 r4
+ 350: (7c 9c 62 a6|a6 62 9c 7c) mfivor12 r4
+ 354: (7c 9c 62 a6|a6 62 9c 7c) mfivor12 r4
+ 358: (7c 9d 62 a6|a6 62 9d 7c) mfivor13 r4
+ 35c: (7c 9d 62 a6|a6 62 9d 7c) mfivor13 r4
+ 360: (7c 9e 62 a6|a6 62 9e 7c) mfivor14 r4
+ 364: (7c 9e 62 a6|a6 62 9e 7c) mfivor14 r4
+ 368: (7c 9f 62 a6|a6 62 9f 7c) mfivor15 r4
+ 36c: (7c 9f 62 a6|a6 62 9f 7c) mfivor15 r4
+ 370: (7c 93 82 a6|a6 82 93 7c) mfivor35 r4
+ 374: (7c 93 82 a6|a6 82 93 7c) mfivor35 r4
+ 378: (7c 9a 8a a6|a6 8a 9a 7c) mfdc_dat r4
+ 37c: (7c 9a 8a a6|a6 8a 9a 7c) mfdc_dat r4
+ 380: (7c 9b 8a a6|a6 8a 9b 7c) mfmcsrr1 r4
+ 384: (7c 9b 8a a6|a6 8a 9b 7c) mfmcsrr1 r4
+ 388: (7c 9c 8a a6|a6 8a 9c 7c) mfmcsr r4
+ 38c: (7c 9c 8a a6|a6 8a 9c 7c) mfmcsr r4
+ 390: (7c 90 da a6|a6 da 90 7c) mfivndx r4
+ 394: (7c 90 da a6|a6 da 90 7c) mfivndx r4
+ 398: (7c 91 da a6|a6 da 91 7c) mfdvndx r4
+ 39c: (7c 91 da a6|a6 da 91 7c) mfdvndx r4
+ 3a0: (7c 92 da a6|a6 da 92 7c) mfivlim r4
+ 3a4: (7c 92 da a6|a6 da 92 7c) mfivlim r4
+ 3a8: (7c 93 da a6|a6 da 93 7c) mfdvlim r4
+ 3ac: (7c 93 da a6|a6 da 93 7c) mfdvlim r4
+ 3b0: (7c 94 da a6|a6 da 94 7c) mfclcsr r4
+ 3b4: (7c 94 da a6|a6 da 94 7c) mfclcsr r4
+ 3b8: (7c 98 da a6|a6 da 98 7c) mfccr1 r4
+ 3bc: (7c 98 da a6|a6 da 98 7c) mfccr1 r4
+ 3c0: (7c 9b e2 a6|a6 e2 9b 7c) mfrstcfg r4
+ 3c4: (7c 9b e2 a6|a6 e2 9b 7c) mfrstcfg r4
+ 3c8: (7c 9c e2 a6|a6 e2 9c 7c) mfdcdbtrl r4
+ 3cc: (7c 9c e2 a6|a6 e2 9c 7c) mfdcdbtrl r4
+ 3d0: (7c 9d e2 a6|a6 e2 9d 7c) mfdcdbtrh r4
+ 3d4: (7c 9d e2 a6|a6 e2 9d 7c) mfdcdbtrh r4
+ 3d8: (7c 9f e2 a6|a6 e2 9f 7c) mficdbtr r4
+ 3dc: (7c 9f e2 a6|a6 e2 9f 7c) mficdbtr r4
+ 3e0: (7c 92 ea a6|a6 ea 92 7c) mfmmucr r4
+ 3e4: (7c 92 ea a6|a6 ea 92 7c) mfmmucr r4
+ 3e8: (7c 93 ea a6|a6 ea 93 7c) mfccr0 r4
+ 3ec: (7c 93 ea a6|a6 ea 93 7c) mfccr0 r4
+ 3f0: (7c 93 f2 a6|a6 f2 93 7c) mficdbdr r4
+ 3f4: (7c 93 f2 a6|a6 f2 93 7c) mficdbdr r4
+ 3f8: (7c 93 fa a6|a6 fa 93 7c) mfdbdr r4
+ 3fc: (7c 93 fa a6|a6 fa 93 7c) mfdbdr r4
+ 400: (7c 96 0b a6|a6 0b 96 7c) mtdecar r4
+ 404: (7c 96 0b a6|a6 0b 96 7c) mtdecar r4
# AppliedMicro Titan tests
- .section ".text"
+ .text
start:
blr
tweqi 1, 0
- .section .text
+ .text
se_b sub1
se_bl sub1
se_bc 0,1,sub2
- .section .text
+ .text
target0:
se_beq target3
- .section .text
+ .text
target0:
e_bdnz target1
- .section .text
+ .text
trap:
trap
twlt 1, 2
- .section .text
+ .text
subtract:
sub 1, 2, 3
- .section .text
+ .text
e_extlwi 2, 2, 1, 0
e_extrwi 2, 3, 10, 5
- .section .text
+ .text
mtmas1 5
# Freescale PowerPC VLE instruction tests
#as: -mvle
- .section .text
+ .text
.extern extern_subr
.equ UI8,0x37
.equ SCI0,UI8<<0
#objdump: -d -Mvsx
#name: VSX tests
-.*: +file format elf(32)?(64)?-powerpc.*
+.*
Disassembly of section \.text:
0+00 <start>:
- 0: 7d 0a a4 99 lxsdx vs40,r10,r20
- 4: 7d 0a a6 99 lxvd2x vs40,r10,r20
- 8: 7d 0a a2 99 lxvdsx vs40,r10,r20
- c: 7d 0a a6 19 lxvw4x vs40,r10,r20
- 10: 7d 0a a5 99 stxsdx vs40,r10,r20
- 14: 7d 0a a7 99 stxvd2x vs40,r10,r20
- 18: 7d 0a a7 19 stxvw4x vs40,r10,r20
- 1c: f1 00 e5 67 xsabsdp vs40,vs60
- 20: f1 12 e1 07 xsadddp vs40,vs50,vs60
- 24: f0 92 e1 5e xscmpodp cr1,vs50,vs60
- 28: f0 92 e1 1e xscmpudp cr1,vs50,vs60
- 2c: f1 12 e5 87 xscpsgndp vs40,vs50,vs60
- 30: f1 00 e4 27 xscvdpsp vs40,vs60
- 34: f1 00 e5 63 xscvdpsxds vs40,vs60
- 38: f1 00 e1 63 xscvdpsxws vs40,vs60
- 3c: f1 00 e5 23 xscvdpuxds vs40,vs60
- 40: f1 00 e1 23 xscvdpuxws vs40,vs60
- 44: f1 00 e5 27 xscvspdp vs40,vs60
- 48: f1 00 e5 e3 xscvsxddp vs40,vs60
- 4c: f1 00 e5 a3 xscvuxddp vs40,vs60
- 50: f1 12 e1 c7 xsdivdp vs40,vs50,vs60
- 54: f1 12 e1 0f xsmaddadp vs40,vs50,vs60
- 58: f1 12 e1 4f xsmaddmdp vs40,vs50,vs60
- 5c: f1 12 e5 07 xsmaxdp vs40,vs50,vs60
- 60: f1 12 e5 47 xsmindp vs40,vs50,vs60
- 64: f1 12 e1 8f xsmsubadp vs40,vs50,vs60
- 68: f1 12 e1 cf xsmsubmdp vs40,vs50,vs60
- 6c: f1 12 e1 87 xsmuldp vs40,vs50,vs60
- 70: f1 00 e5 a7 xsnabsdp vs40,vs60
- 74: f1 00 e5 e7 xsnegdp vs40,vs60
- 78: f1 12 e5 0f xsnmaddadp vs40,vs50,vs60
- 7c: f1 12 e5 4f xsnmaddmdp vs40,vs50,vs60
- 80: f1 12 e5 8f xsnmsubadp vs40,vs50,vs60
- 84: f1 12 e5 cf xsnmsubmdp vs40,vs50,vs60
- 88: f1 00 e1 27 xsrdpi vs40,vs60
- 8c: f1 00 e1 af xsrdpic vs40,vs60
- 90: f1 00 e1 e7 xsrdpim vs40,vs60
- 94: f1 00 e1 a7 xsrdpip vs40,vs60
- 98: f1 00 e1 67 xsrdpiz vs40,vs60
- 9c: f1 00 e1 6b xsredp vs40,vs60
- a0: f1 00 e1 2b xsrsqrtedp vs40,vs60
- a4: f1 00 e1 2f xssqrtdp vs40,vs60
- a8: f1 12 e1 47 xssubdp vs40,vs50,vs60
- ac: f0 92 e1 ee xstdivdp cr1,vs50,vs60
- b0: f0 80 e1 aa xstsqrtdp cr1,vs60
- b4: f1 00 e7 67 xvabsdp vs40,vs60
- b8: f1 00 e6 67 xvabssp vs40,vs60
- bc: f1 12 e3 07 xvadddp vs40,vs50,vs60
- c0: f1 12 e2 07 xvaddsp vs40,vs50,vs60
- c4: f1 12 e3 1f xvcmpeqdp vs40,vs50,vs60
- c8: f1 12 e7 1f xvcmpeqdp\. vs40,vs50,vs60
- cc: f1 12 e2 1f xvcmpeqsp vs40,vs50,vs60
- d0: f1 12 e6 1f xvcmpeqsp\. vs40,vs50,vs60
- d4: f1 12 e3 9f xvcmpgedp vs40,vs50,vs60
- d8: f1 12 e7 9f xvcmpgedp\. vs40,vs50,vs60
- dc: f1 12 e2 9f xvcmpgesp vs40,vs50,vs60
- e0: f1 12 e6 9f xvcmpgesp\. vs40,vs50,vs60
- e4: f1 12 e3 5f xvcmpgtdp vs40,vs50,vs60
- e8: f1 12 e7 5f xvcmpgtdp\. vs40,vs50,vs60
- ec: f1 12 e2 5f xvcmpgtsp vs40,vs50,vs60
- f0: f1 12 e6 5f xvcmpgtsp\. vs40,vs50,vs60
- f4: f1 12 e7 87 xvcpsgndp vs40,vs50,vs60
- f8: f1 1c e7 87 xvmovdp vs40,vs60
- fc: f1 1c e7 87 xvmovdp vs40,vs60
- 100: f1 12 e6 87 xvcpsgnsp vs40,vs50,vs60
- 104: f1 1c e6 87 xvmovsp vs40,vs60
- 108: f1 1c e6 87 xvmovsp vs40,vs60
- 10c: f1 00 e6 27 xvcvdpsp vs40,vs60
- 110: f1 00 e7 63 xvcvdpsxds vs40,vs60
- 114: f1 00 e3 63 xvcvdpsxws vs40,vs60
- 118: f1 00 e7 23 xvcvdpuxds vs40,vs60
- 11c: f1 00 e3 23 xvcvdpuxws vs40,vs60
- 120: f1 00 e7 27 xvcvspdp vs40,vs60
- 124: f1 00 e6 63 xvcvspsxds vs40,vs60
- 128: f1 00 e2 63 xvcvspsxws vs40,vs60
- 12c: f1 00 e6 23 xvcvspuxds vs40,vs60
- 130: f1 00 e2 23 xvcvspuxws vs40,vs60
- 134: f1 00 e7 e3 xvcvsxddp vs40,vs60
- 138: f1 00 e6 e3 xvcvsxdsp vs40,vs60
- 13c: f1 00 e3 e3 xvcvsxwdp vs40,vs60
- 140: f1 00 e2 e3 xvcvsxwsp vs40,vs60
- 144: f1 00 e7 a3 xvcvuxddp vs40,vs60
- 148: f1 00 e6 a3 xvcvuxdsp vs40,vs60
- 14c: f1 00 e3 a3 xvcvuxwdp vs40,vs60
- 150: f1 00 e2 a3 xvcvuxwsp vs40,vs60
- 154: f1 12 e3 c7 xvdivdp vs40,vs50,vs60
- 158: f1 12 e2 c7 xvdivsp vs40,vs50,vs60
- 15c: f1 12 e3 0f xvmaddadp vs40,vs50,vs60
- 160: f1 12 e3 4f xvmaddmdp vs40,vs50,vs60
- 164: f1 12 e2 0f xvmaddasp vs40,vs50,vs60
- 168: f1 12 e2 4f xvmaddmsp vs40,vs50,vs60
- 16c: f1 12 e7 07 xvmaxdp vs40,vs50,vs60
- 170: f1 12 e6 07 xvmaxsp vs40,vs50,vs60
- 174: f1 12 e7 47 xvmindp vs40,vs50,vs60
- 178: f1 12 e6 47 xvminsp vs40,vs50,vs60
- 17c: f1 12 e3 8f xvmsubadp vs40,vs50,vs60
- 180: f1 12 e3 cf xvmsubmdp vs40,vs50,vs60
- 184: f1 12 e2 8f xvmsubasp vs40,vs50,vs60
- 188: f1 12 e2 cf xvmsubmsp vs40,vs50,vs60
- 18c: f1 12 e3 87 xvmuldp vs40,vs50,vs60
- 190: f1 12 e2 87 xvmulsp vs40,vs50,vs60
- 194: f1 00 e7 a7 xvnabsdp vs40,vs60
- 198: f1 00 e6 a7 xvnabssp vs40,vs60
- 19c: f1 00 e7 e7 xvnegdp vs40,vs60
- 1a0: f1 00 e6 e7 xvnegsp vs40,vs60
- 1a4: f1 12 e7 0f xvnmaddadp vs40,vs50,vs60
- 1a8: f1 12 e7 4f xvnmaddmdp vs40,vs50,vs60
- 1ac: f1 12 e6 0f xvnmaddasp vs40,vs50,vs60
- 1b0: f1 12 e6 4f xvnmaddmsp vs40,vs50,vs60
- 1b4: f1 12 e7 8f xvnmsubadp vs40,vs50,vs60
- 1b8: f1 12 e7 cf xvnmsubmdp vs40,vs50,vs60
- 1bc: f1 12 e6 8f xvnmsubasp vs40,vs50,vs60
- 1c0: f1 12 e6 cf xvnmsubmsp vs40,vs50,vs60
- 1c4: f1 00 e3 27 xvrdpi vs40,vs60
- 1c8: f1 00 e3 af xvrdpic vs40,vs60
- 1cc: f1 00 e3 e7 xvrdpim vs40,vs60
- 1d0: f1 00 e3 a7 xvrdpip vs40,vs60
- 1d4: f1 00 e3 67 xvrdpiz vs40,vs60
- 1d8: f1 00 e3 6b xvredp vs40,vs60
- 1dc: f1 00 e2 6b xvresp vs40,vs60
- 1e0: f1 00 e2 27 xvrspi vs40,vs60
- 1e4: f1 00 e2 af xvrspic vs40,vs60
- 1e8: f1 00 e2 e7 xvrspim vs40,vs60
- 1ec: f1 00 e2 a7 xvrspip vs40,vs60
- 1f0: f1 00 e2 67 xvrspiz vs40,vs60
- 1f4: f1 00 e3 2b xvrsqrtedp vs40,vs60
- 1f8: f1 00 e2 2b xvrsqrtesp vs40,vs60
- 1fc: f1 00 e3 2f xvsqrtdp vs40,vs60
- 200: f1 00 e2 2f xvsqrtsp vs40,vs60
- 204: f1 12 e3 47 xvsubdp vs40,vs50,vs60
- 208: f1 12 e2 47 xvsubsp vs40,vs50,vs60
- 20c: f0 92 e3 ee xvtdivdp cr1,vs50,vs60
- 210: f0 92 e2 ee xvtdivsp cr1,vs50,vs60
- 214: f0 80 e3 aa xvtsqrtdp cr1,vs60
- 218: f0 80 e2 aa xvtsqrtsp cr1,vs60
- 21c: f1 12 e4 17 xxland vs40,vs50,vs60
- 220: f1 12 e4 57 xxlandc vs40,vs50,vs60
- 224: f1 12 e5 17 xxlnor vs40,vs50,vs60
- 228: f1 12 e4 97 xxlor vs40,vs50,vs60
- 22c: f1 12 e4 d7 xxlxor vs40,vs50,vs60
- 230: f1 12 e0 97 xxmrghw vs40,vs50,vs60
- 234: f1 12 e1 97 xxmrglw vs40,vs50,vs60
- 238: f1 12 e0 57 xxmrghd vs40,vs50,vs60
- 23c: f1 12 e1 57 xxpermdi vs40,vs50,vs60,1
- 240: f1 12 e2 57 xxpermdi vs40,vs50,vs60,2
- 244: f1 12 e3 57 xxmrgld vs40,vs50,vs60
- 248: f1 12 90 57 xxspltd vs40,vs50,0
- 24c: f1 12 90 57 xxspltd vs40,vs50,0
- 250: f1 12 93 57 xxspltd vs40,vs50,1
- 254: f1 12 93 57 xxspltd vs40,vs50,1
- 258: f1 12 e0 57 xxmrghd vs40,vs50,vs60
- 25c: f1 12 e0 57 xxmrghd vs40,vs50,vs60
- 260: f1 12 e3 57 xxmrgld vs40,vs50,vs60
- 264: f1 12 92 57 xxswapd vs40,vs50
- 268: f1 12 92 57 xxswapd vs40,vs50
- 26c: f1 12 e7 bf xxsel vs40,vs50,vs60,vs62
- 270: f1 12 e2 17 xxsldwi vs40,vs50,vs60,2
- 274: f1 02 e2 93 xxspltw vs40,vs60,2
+ 0: (7d 0a a4 99|99 a4 0a 7d) lxsdx vs40,r10,r20
+ 4: (7d 0a a6 99|99 a6 0a 7d) lxvd2x vs40,r10,r20
+ 8: (7d 0a a2 99|99 a2 0a 7d) lxvdsx vs40,r10,r20
+ c: (7d 0a a6 19|19 a6 0a 7d) lxvw4x vs40,r10,r20
+ 10: (7d 0a a5 99|99 a5 0a 7d) stxsdx vs40,r10,r20
+ 14: (7d 0a a7 99|99 a7 0a 7d) stxvd2x vs40,r10,r20
+ 18: (7d 0a a7 19|19 a7 0a 7d) stxvw4x vs40,r10,r20
+ 1c: (f1 00 e5 67|67 e5 00 f1) xsabsdp vs40,vs60
+ 20: (f1 12 e1 07|07 e1 12 f1) xsadddp vs40,vs50,vs60
+ 24: (f0 92 e1 5e|5e e1 92 f0) xscmpodp cr1,vs50,vs60
+ 28: (f0 92 e1 1e|1e e1 92 f0) xscmpudp cr1,vs50,vs60
+ 2c: (f1 12 e5 87|87 e5 12 f1) xscpsgndp vs40,vs50,vs60
+ 30: (f1 00 e4 27|27 e4 00 f1) xscvdpsp vs40,vs60
+ 34: (f1 00 e5 63|63 e5 00 f1) xscvdpsxds vs40,vs60
+ 38: (f1 00 e1 63|63 e1 00 f1) xscvdpsxws vs40,vs60
+ 3c: (f1 00 e5 23|23 e5 00 f1) xscvdpuxds vs40,vs60
+ 40: (f1 00 e1 23|23 e1 00 f1) xscvdpuxws vs40,vs60
+ 44: (f1 00 e5 27|27 e5 00 f1) xscvspdp vs40,vs60
+ 48: (f1 00 e5 e3|e3 e5 00 f1) xscvsxddp vs40,vs60
+ 4c: (f1 00 e5 a3|a3 e5 00 f1) xscvuxddp vs40,vs60
+ 50: (f1 12 e1 c7|c7 e1 12 f1) xsdivdp vs40,vs50,vs60
+ 54: (f1 12 e1 0f|0f e1 12 f1) xsmaddadp vs40,vs50,vs60
+ 58: (f1 12 e1 4f|4f e1 12 f1) xsmaddmdp vs40,vs50,vs60
+ 5c: (f1 12 e5 07|07 e5 12 f1) xsmaxdp vs40,vs50,vs60
+ 60: (f1 12 e5 47|47 e5 12 f1) xsmindp vs40,vs50,vs60
+ 64: (f1 12 e1 8f|8f e1 12 f1) xsmsubadp vs40,vs50,vs60
+ 68: (f1 12 e1 cf|cf e1 12 f1) xsmsubmdp vs40,vs50,vs60
+ 6c: (f1 12 e1 87|87 e1 12 f1) xsmuldp vs40,vs50,vs60
+ 70: (f1 00 e5 a7|a7 e5 00 f1) xsnabsdp vs40,vs60
+ 74: (f1 00 e5 e7|e7 e5 00 f1) xsnegdp vs40,vs60
+ 78: (f1 12 e5 0f|0f e5 12 f1) xsnmaddadp vs40,vs50,vs60
+ 7c: (f1 12 e5 4f|4f e5 12 f1) xsnmaddmdp vs40,vs50,vs60
+ 80: (f1 12 e5 8f|8f e5 12 f1) xsnmsubadp vs40,vs50,vs60
+ 84: (f1 12 e5 cf|cf e5 12 f1) xsnmsubmdp vs40,vs50,vs60
+ 88: (f1 00 e1 27|27 e1 00 f1) xsrdpi vs40,vs60
+ 8c: (f1 00 e1 af|af e1 00 f1) xsrdpic vs40,vs60
+ 90: (f1 00 e1 e7|e7 e1 00 f1) xsrdpim vs40,vs60
+ 94: (f1 00 e1 a7|a7 e1 00 f1) xsrdpip vs40,vs60
+ 98: (f1 00 e1 67|67 e1 00 f1) xsrdpiz vs40,vs60
+ 9c: (f1 00 e1 6b|6b e1 00 f1) xsredp vs40,vs60
+ a0: (f1 00 e1 2b|2b e1 00 f1) xsrsqrtedp vs40,vs60
+ a4: (f1 00 e1 2f|2f e1 00 f1) xssqrtdp vs40,vs60
+ a8: (f1 12 e1 47|47 e1 12 f1) xssubdp vs40,vs50,vs60
+ ac: (f0 92 e1 ee|ee e1 92 f0) xstdivdp cr1,vs50,vs60
+ b0: (f0 80 e1 aa|aa e1 80 f0) xstsqrtdp cr1,vs60
+ b4: (f1 00 e7 67|67 e7 00 f1) xvabsdp vs40,vs60
+ b8: (f1 00 e6 67|67 e6 00 f1) xvabssp vs40,vs60
+ bc: (f1 12 e3 07|07 e3 12 f1) xvadddp vs40,vs50,vs60
+ c0: (f1 12 e2 07|07 e2 12 f1) xvaddsp vs40,vs50,vs60
+ c4: (f1 12 e3 1f|1f e3 12 f1) xvcmpeqdp vs40,vs50,vs60
+ c8: (f1 12 e7 1f|1f e7 12 f1) xvcmpeqdp\. vs40,vs50,vs60
+ cc: (f1 12 e2 1f|1f e2 12 f1) xvcmpeqsp vs40,vs50,vs60
+ d0: (f1 12 e6 1f|1f e6 12 f1) xvcmpeqsp\. vs40,vs50,vs60
+ d4: (f1 12 e3 9f|9f e3 12 f1) xvcmpgedp vs40,vs50,vs60
+ d8: (f1 12 e7 9f|9f e7 12 f1) xvcmpgedp\. vs40,vs50,vs60
+ dc: (f1 12 e2 9f|9f e2 12 f1) xvcmpgesp vs40,vs50,vs60
+ e0: (f1 12 e6 9f|9f e6 12 f1) xvcmpgesp\. vs40,vs50,vs60
+ e4: (f1 12 e3 5f|5f e3 12 f1) xvcmpgtdp vs40,vs50,vs60
+ e8: (f1 12 e7 5f|5f e7 12 f1) xvcmpgtdp\. vs40,vs50,vs60
+ ec: (f1 12 e2 5f|5f e2 12 f1) xvcmpgtsp vs40,vs50,vs60
+ f0: (f1 12 e6 5f|5f e6 12 f1) xvcmpgtsp\. vs40,vs50,vs60
+ f4: (f1 12 e7 87|87 e7 12 f1) xvcpsgndp vs40,vs50,vs60
+ f8: (f1 1c e7 87|87 e7 1c f1) xvmovdp vs40,vs60
+ fc: (f1 1c e7 87|87 e7 1c f1) xvmovdp vs40,vs60
+ 100: (f1 12 e6 87|87 e6 12 f1) xvcpsgnsp vs40,vs50,vs60
+ 104: (f1 1c e6 87|87 e6 1c f1) xvmovsp vs40,vs60
+ 108: (f1 1c e6 87|87 e6 1c f1) xvmovsp vs40,vs60
+ 10c: (f1 00 e6 27|27 e6 00 f1) xvcvdpsp vs40,vs60
+ 110: (f1 00 e7 63|63 e7 00 f1) xvcvdpsxds vs40,vs60
+ 114: (f1 00 e3 63|63 e3 00 f1) xvcvdpsxws vs40,vs60
+ 118: (f1 00 e7 23|23 e7 00 f1) xvcvdpuxds vs40,vs60
+ 11c: (f1 00 e3 23|23 e3 00 f1) xvcvdpuxws vs40,vs60
+ 120: (f1 00 e7 27|27 e7 00 f1) xvcvspdp vs40,vs60
+ 124: (f1 00 e6 63|63 e6 00 f1) xvcvspsxds vs40,vs60
+ 128: (f1 00 e2 63|63 e2 00 f1) xvcvspsxws vs40,vs60
+ 12c: (f1 00 e6 23|23 e6 00 f1) xvcvspuxds vs40,vs60
+ 130: (f1 00 e2 23|23 e2 00 f1) xvcvspuxws vs40,vs60
+ 134: (f1 00 e7 e3|e3 e7 00 f1) xvcvsxddp vs40,vs60
+ 138: (f1 00 e6 e3|e3 e6 00 f1) xvcvsxdsp vs40,vs60
+ 13c: (f1 00 e3 e3|e3 e3 00 f1) xvcvsxwdp vs40,vs60
+ 140: (f1 00 e2 e3|e3 e2 00 f1) xvcvsxwsp vs40,vs60
+ 144: (f1 00 e7 a3|a3 e7 00 f1) xvcvuxddp vs40,vs60
+ 148: (f1 00 e6 a3|a3 e6 00 f1) xvcvuxdsp vs40,vs60
+ 14c: (f1 00 e3 a3|a3 e3 00 f1) xvcvuxwdp vs40,vs60
+ 150: (f1 00 e2 a3|a3 e2 00 f1) xvcvuxwsp vs40,vs60
+ 154: (f1 12 e3 c7|c7 e3 12 f1) xvdivdp vs40,vs50,vs60
+ 158: (f1 12 e2 c7|c7 e2 12 f1) xvdivsp vs40,vs50,vs60
+ 15c: (f1 12 e3 0f|0f e3 12 f1) xvmaddadp vs40,vs50,vs60
+ 160: (f1 12 e3 4f|4f e3 12 f1) xvmaddmdp vs40,vs50,vs60
+ 164: (f1 12 e2 0f|0f e2 12 f1) xvmaddasp vs40,vs50,vs60
+ 168: (f1 12 e2 4f|4f e2 12 f1) xvmaddmsp vs40,vs50,vs60
+ 16c: (f1 12 e7 07|07 e7 12 f1) xvmaxdp vs40,vs50,vs60
+ 170: (f1 12 e6 07|07 e6 12 f1) xvmaxsp vs40,vs50,vs60
+ 174: (f1 12 e7 47|47 e7 12 f1) xvmindp vs40,vs50,vs60
+ 178: (f1 12 e6 47|47 e6 12 f1) xvminsp vs40,vs50,vs60
+ 17c: (f1 12 e3 8f|8f e3 12 f1) xvmsubadp vs40,vs50,vs60
+ 180: (f1 12 e3 cf|cf e3 12 f1) xvmsubmdp vs40,vs50,vs60
+ 184: (f1 12 e2 8f|8f e2 12 f1) xvmsubasp vs40,vs50,vs60
+ 188: (f1 12 e2 cf|cf e2 12 f1) xvmsubmsp vs40,vs50,vs60
+ 18c: (f1 12 e3 87|87 e3 12 f1) xvmuldp vs40,vs50,vs60
+ 190: (f1 12 e2 87|87 e2 12 f1) xvmulsp vs40,vs50,vs60
+ 194: (f1 00 e7 a7|a7 e7 00 f1) xvnabsdp vs40,vs60
+ 198: (f1 00 e6 a7|a7 e6 00 f1) xvnabssp vs40,vs60
+ 19c: (f1 00 e7 e7|e7 e7 00 f1) xvnegdp vs40,vs60
+ 1a0: (f1 00 e6 e7|e7 e6 00 f1) xvnegsp vs40,vs60
+ 1a4: (f1 12 e7 0f|0f e7 12 f1) xvnmaddadp vs40,vs50,vs60
+ 1a8: (f1 12 e7 4f|4f e7 12 f1) xvnmaddmdp vs40,vs50,vs60
+ 1ac: (f1 12 e6 0f|0f e6 12 f1) xvnmaddasp vs40,vs50,vs60
+ 1b0: (f1 12 e6 4f|4f e6 12 f1) xvnmaddmsp vs40,vs50,vs60
+ 1b4: (f1 12 e7 8f|8f e7 12 f1) xvnmsubadp vs40,vs50,vs60
+ 1b8: (f1 12 e7 cf|cf e7 12 f1) xvnmsubmdp vs40,vs50,vs60
+ 1bc: (f1 12 e6 8f|8f e6 12 f1) xvnmsubasp vs40,vs50,vs60
+ 1c0: (f1 12 e6 cf|cf e6 12 f1) xvnmsubmsp vs40,vs50,vs60
+ 1c4: (f1 00 e3 27|27 e3 00 f1) xvrdpi vs40,vs60
+ 1c8: (f1 00 e3 af|af e3 00 f1) xvrdpic vs40,vs60
+ 1cc: (f1 00 e3 e7|e7 e3 00 f1) xvrdpim vs40,vs60
+ 1d0: (f1 00 e3 a7|a7 e3 00 f1) xvrdpip vs40,vs60
+ 1d4: (f1 00 e3 67|67 e3 00 f1) xvrdpiz vs40,vs60
+ 1d8: (f1 00 e3 6b|6b e3 00 f1) xvredp vs40,vs60
+ 1dc: (f1 00 e2 6b|6b e2 00 f1) xvresp vs40,vs60
+ 1e0: (f1 00 e2 27|27 e2 00 f1) xvrspi vs40,vs60
+ 1e4: (f1 00 e2 af|af e2 00 f1) xvrspic vs40,vs60
+ 1e8: (f1 00 e2 e7|e7 e2 00 f1) xvrspim vs40,vs60
+ 1ec: (f1 00 e2 a7|a7 e2 00 f1) xvrspip vs40,vs60
+ 1f0: (f1 00 e2 67|67 e2 00 f1) xvrspiz vs40,vs60
+ 1f4: (f1 00 e3 2b|2b e3 00 f1) xvrsqrtedp vs40,vs60
+ 1f8: (f1 00 e2 2b|2b e2 00 f1) xvrsqrtesp vs40,vs60
+ 1fc: (f1 00 e3 2f|2f e3 00 f1) xvsqrtdp vs40,vs60
+ 200: (f1 00 e2 2f|2f e2 00 f1) xvsqrtsp vs40,vs60
+ 204: (f1 12 e3 47|47 e3 12 f1) xvsubdp vs40,vs50,vs60
+ 208: (f1 12 e2 47|47 e2 12 f1) xvsubsp vs40,vs50,vs60
+ 20c: (f0 92 e3 ee|ee e3 92 f0) xvtdivdp cr1,vs50,vs60
+ 210: (f0 92 e2 ee|ee e2 92 f0) xvtdivsp cr1,vs50,vs60
+ 214: (f0 80 e3 aa|aa e3 80 f0) xvtsqrtdp cr1,vs60
+ 218: (f0 80 e2 aa|aa e2 80 f0) xvtsqrtsp cr1,vs60
+ 21c: (f1 12 e4 17|17 e4 12 f1) xxland vs40,vs50,vs60
+ 220: (f1 12 e4 57|57 e4 12 f1) xxlandc vs40,vs50,vs60
+ 224: (f1 12 e5 17|17 e5 12 f1) xxlnor vs40,vs50,vs60
+ 228: (f1 12 e4 97|97 e4 12 f1) xxlor vs40,vs50,vs60
+ 22c: (f1 12 e4 d7|d7 e4 12 f1) xxlxor vs40,vs50,vs60
+ 230: (f1 12 e0 97|97 e0 12 f1) xxmrghw vs40,vs50,vs60
+ 234: (f1 12 e1 97|97 e1 12 f1) xxmrglw vs40,vs50,vs60
+ 238: (f1 12 e0 57|57 e0 12 f1) xxmrghd vs40,vs50,vs60
+ 23c: (f1 12 e1 57|57 e1 12 f1) xxpermdi vs40,vs50,vs60,1
+ 240: (f1 12 e2 57|57 e2 12 f1) xxpermdi vs40,vs50,vs60,2
+ 244: (f1 12 e3 57|57 e3 12 f1) xxmrgld vs40,vs50,vs60
+ 248: (f1 12 90 57|57 90 12 f1) xxspltd vs40,vs50,0
+ 24c: (f1 12 90 57|57 90 12 f1) xxspltd vs40,vs50,0
+ 250: (f1 12 93 57|57 93 12 f1) xxspltd vs40,vs50,1
+ 254: (f1 12 93 57|57 93 12 f1) xxspltd vs40,vs50,1
+ 258: (f1 12 e0 57|57 e0 12 f1) xxmrghd vs40,vs50,vs60
+ 25c: (f1 12 e0 57|57 e0 12 f1) xxmrghd vs40,vs50,vs60
+ 260: (f1 12 e3 57|57 e3 12 f1) xxmrgld vs40,vs50,vs60
+ 264: (f1 12 92 57|57 92 12 f1) xxswapd vs40,vs50
+ 268: (f1 12 92 57|57 92 12 f1) xxswapd vs40,vs50
+ 26c: (f1 12 e7 bf|bf e7 12 f1) xxsel vs40,vs50,vs60,vs62
+ 270: (f1 12 e2 17|17 e2 12 f1) xxsldwi vs40,vs50,vs60,2
+ 274: (f1 02 e2 93|93 e2 02 f1) xxspltw vs40,vs60,2
- .section ".text"
+ .text
start:
lxsdx 40,10,20
lxvd2x 40,10,20
prev_fix = frchp->fix_tail;
}
}
- gas_assert (prev_frag->fr_type != 0);
- gas_assert (prev_frag != &dummy);
+ gas_assert (prev_frag != &dummy
+ && prev_frag->fr_type != 0);
prev_frag->fr_next = 0;
return prev_frag;
}
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2012-11-23 Alan Modra <amodra@gmail.com>
+ * ppc.h (ppc_parse_cpu): Update prototype.
+
2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
Maciej W. Rozycki <macro@codesourcery.com>
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
-extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
+extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
#endif /* PPC_H */
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2013-01-08 Alan Modra <amodra@gmail.com>
+ * emultempl/elf32.em (gld${EMULATION_NAME}_check_ld_so_conf): Replace
+ "name" param with a bfd_link_needed_link pointer. Update caller.
+ (gld${EMULATION_NAME}_check_ld_elf_hints): Likewise.
+
+ 2012-12-17 Alan Modra <amodra@gmail.com>
+ PR ld/14962
+ * ldexp.h (struct ldexp_control): Add "assign_name".
+ * ldexp.c (fold_name <NAME>): Compare and clear assign_name on match.
+ (exp_fold_tree_1): Remove existing code testing for self assignment.
+ Instead set and test expld.assign_name.
+ * ldlang.c (scan_for_self_assignment): Delete.
+ (print_assignment): Instead set and test expld.assign_name.
+
+ 2012-12-05 H.J. Lu <hongjiu.lu@intel.com>
+ PR ld/14915
+ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Also
+ check DT_NEEDED entries when creating shared object with
+ --copy-dt-needed-entries.
+
+ 2012-12-03 H.J. Lu <hongjiu.lu@intel.com>
+ PR ld/14904
+ * ldmain.c (main): Don't check plugin_load_plugins return.
+ * lexsup.c (parse_args): Don't check plugin_opt_plugin return.
+ * plugin.c (dlerror): New. Defined if HAVE_DLFCN_H isn't
+ defined.
+ (plugin_opt_plugin): Change return type to void. Stop on
+ dlopen error and report error with dlerror ().
+ (plugin_load_plugins): Change return type to void. Stop on
+ dlsym error and report error with dlerror (). Don't use
+ set_plugin_error.
+ (plugin_call_cleanup): Issue an error for each plugin.
+ * plugin.h (plugin_opt_plugin): Change return type to void.
+ (plugin_load_plugins): Likewise.
+
+ 2012-11-01 Alan Modra <amodra@gmail.com>
+ * ldlang.c (insert_pad): Correct output section size calculation.
+ (lang_size_sections_1): Likewise for lang_data_statement and
+ lang_reloc_statement.
+
+ 2012-10-22 Alan Modra <amodra@gmail.com>
+ * plugin.c (plugin_load_plugins): Warning fix.
+
2012-12-18 Roland McGrath <mcgrathr@google.com>
* ld.texinfo (Options): Describe -Trodata-segment.
#endif
static bfd_boolean
-gld${EMULATION_NAME}_check_ld_elf_hints (const char *name, int force)
+gld${EMULATION_NAME}_check_ld_elf_hints (const struct bfd_link_needed_list *l,
+ int force)
{
static bfd_boolean initialized;
static char *ld_elf_hints;
if (ld_elf_hints == NULL)
return FALSE;
- needed.by = NULL;
- needed.name = name;
- return gld${EMULATION_NAME}_search_needed (ld_elf_hints, & needed,
- force);
+ needed.by = l->by;
+ needed.name = l->name;
+ return gld${EMULATION_NAME}_search_needed (ld_elf_hints, &needed, force);
}
EOF
# FreeBSD
}
static bfd_boolean
-gld${EMULATION_NAME}_check_ld_so_conf (const char *name, int force)
+gld${EMULATION_NAME}_check_ld_so_conf (const struct bfd_link_needed_list *l,
+ int force)
{
static bfd_boolean initialized;
static char *ld_so_conf;
return FALSE;
- needed.by = NULL;
- needed.name = name;
+ needed.by = l->by;
+ needed.name = l->name;
return gld${EMULATION_NAME}_search_needed (ld_so_conf, &needed, force);
}
special action by the person doing the link. Note that the
needed list can actually grow while we are stepping through this
loop. */
- if (!link_info.executable)
- return;
needed = bfd_elf_get_needed_list (link_info.output_bfd, &link_info);
for (l = needed; l != NULL; l = l->next)
{
int force;
/* If the lib that needs this one was --as-needed and wasn't
- found to be needed, then this lib isn't needed either. */
+ found to be needed, then this lib isn't needed either. Skip
+ the lib when creating a shared object unless we are copying
+ DT_NEEDED entres. */
if (l->by != NULL
- && (bfd_elf_get_dyn_lib_class (l->by) & DYN_AS_NEEDED) != 0)
+ && ((bfd_elf_get_dyn_lib_class (l->by) & DYN_AS_NEEDED) != 0
+ || (!link_info.executable
+ && bfd_elf_get_dyn_lib_class (l->by) & DYN_NO_ADD_NEEDED) != 0))
continue;
/* If we've already seen this file, skip it. */
case ${target} in
*-*-freebsd* | *-*-dragonfly*)
fragment <<EOF
- if (gld${EMULATION_NAME}_check_ld_elf_hints (l->name, force))
+ if (gld${EMULATION_NAME}_check_ld_elf_hints (l, force))
break;
EOF
# FreeBSD
*-*-linux-* | *-*-k*bsd*-* | *-*-gnu*)
# Linux
fragment <<EOF
- if (gld${EMULATION_NAME}_check_ld_so_conf (l->name, force))
+ if (gld${EMULATION_NAME}_check_ld_so_conf (l, force))
break;
EOF
break;
case NAME:
+ if (expld.assign_name != NULL
+ && strcmp (expld.assign_name, tree->name.name) == 0)
+ expld.assign_name = NULL;
if (expld.phase == lang_first_phase_enum)
;
else if (tree->name.name[0] == '.' && tree->name.name[1] == 0)
}
else
{
- etree_type *name;
-
struct bfd_link_hash_entry *h = NULL;
if (tree->type.node_class == etree_provide)
}
}
- name = tree->assign.src;
- if (name->type.node_class == etree_trinary)
- {
- exp_fold_tree_1 (name->trinary.cond);
- if (expld.result.valid_p)
- name = (expld.result.value
- ? name->trinary.lhs : name->trinary.rhs);
- }
-
- if (name->type.node_class == etree_name
- && name->type.node_code == NAME
- && strcmp (tree->assign.dst, name->name.name) == 0)
- /* Leave it alone. Do not replace a symbol with its own
- output address, in case there is another section sizing
- pass. Folding does not preserve input sections. */
- break;
-
+ expld.assign_name = tree->assign.dst;
exp_fold_tree_1 (tree->assign.src);
- if (expld.result.valid_p
+ /* expld.assign_name remaining equal to tree->assign.dst
+ below indicates the evaluation of tree->assign.src did
+ not use the value of tree->assign.dst. We don't allow
+ self assignment until the final phase for two reasons:
+ 1) Expressions are evaluated multiple times. With
+ relaxation, the number of times may vary.
+ 2) Section relative symbol values cannot be correctly
+ converted to absolute values, as is required by many
+ expressions, until final section sizing is complete. */
+ if ((expld.result.valid_p
+ && (expld.phase == lang_final_phase_enum
+ || expld.assign_name != NULL))
|| (expld.phase <= lang_mark_phase_enum
&& tree->type.node_class == etree_assign
&& tree->assign.defsym))
&& h->type == bfd_link_hash_new)
h->type = bfd_link_hash_undefined;
}
+ expld.assign_name = NULL;
}
break;
/* Principally used for diagnostics. */
bfd_boolean assigning_to_dot;
+ /* If evaluating an assignment, the destination. Cleared if an
+ etree_name NAME matches this, to signal a self-assignment.
+ Note that an etree_name DEFINED does not clear this field, nor
+ does the false branch of a trinary expression. */
+ const char *assign_name;
/* Working results. */
etree_value_type result;
output_section_statement);
}
-/* Scan for the use of the destination in the right hand side
- of an expression. In such cases we will not compute the
- correct expression, since the value of DST that is used on
- the right hand side will be its final value, not its value
- just before this expression is evaluated. */
-
-static bfd_boolean
-scan_for_self_assignment (const char * dst, etree_type * rhs)
-{
- if (rhs == NULL || dst == NULL)
- return FALSE;
-
- switch (rhs->type.node_class)
- {
- case etree_binary:
- return (scan_for_self_assignment (dst, rhs->binary.lhs)
- || scan_for_self_assignment (dst, rhs->binary.rhs));
-
- case etree_trinary:
- return (scan_for_self_assignment (dst, rhs->trinary.lhs)
- || scan_for_self_assignment (dst, rhs->trinary.rhs));
-
- case etree_assign:
- case etree_provided:
- case etree_provide:
- if (strcmp (dst, rhs->assign.dst) == 0)
- return TRUE;
- return scan_for_self_assignment (dst, rhs->assign.src);
-
- case etree_unary:
- return scan_for_self_assignment (dst, rhs->unary.child);
-
- case etree_value:
- if (rhs->value.str)
- return strcmp (dst, rhs->value.str) == 0;
- return FALSE;
-
- case etree_name:
- if (rhs->name.name)
- return strcmp (dst, rhs->name.name) == 0;
- return FALSE;
-
- default:
- break;
- }
-
- return FALSE;
-}
-
-
static void
print_assignment (lang_assignment_statement_type *assignment,
lang_output_section_statement_type *output_section)
{
unsigned int i;
bfd_boolean is_dot;
- bfd_boolean computation_is_valid = TRUE;
etree_type *tree;
asection *osec;
{
is_dot = FALSE;
tree = assignment->exp->assert_s.child;
- computation_is_valid = TRUE;
}
else
{
const char *dst = assignment->exp->assign.dst;
is_dot = (dst[0] == '.' && dst[1] == 0);
+ expld.assign_name = dst;
tree = assignment->exp->assign.src;
- computation_is_valid = is_dot || !scan_for_self_assignment (dst, tree);
}
osec = output_section->bfd_section;
{
bfd_vma value;
- if (computation_is_valid)
+ if (assignment->exp->type.node_class == etree_assert
+ || is_dot
+ || expld.assign_name != NULL)
{
value = expld.result.value;
minfo (" ");
#endif
}
+ expld.assign_name = NULL;
minfo (" ");
exp_print_tree (assignment->exp);
}
pad->padding_statement.output_offset = dot - output_section->vma;
pad->padding_statement.size = alignment_needed;
- output_section->size += alignment_needed;
+ output_section->size = TO_SIZE (dot + TO_ADDR (alignment_needed)
+ - output_section->vma);
}
/* Work out how much this section will move the dot point. */
if (size < TO_SIZE ((unsigned) 1))
size = TO_SIZE ((unsigned) 1);
dot += TO_ADDR (size);
- output_section_statement->bfd_section->size += size;
+ output_section_statement->bfd_section->size
+ = TO_SIZE (dot - output_section_statement->bfd_section->vma);
+
}
break;
output_section_statement->bfd_section;
size = bfd_get_reloc_size (s->reloc_statement.howto);
dot += TO_ADDR (size);
- output_section_statement->bfd_section->size += size;
+ output_section_statement->bfd_section->size
+ = TO_SIZE (dot - output_section_statement->bfd_section->vma);
}
break;
#ifdef ENABLE_PLUGINS
/* Now all the plugin arguments have been gathered, we can load them. */
- if (plugin_load_plugins ())
- einfo (_("%P%F: %s: error loading plugin\n"), plugin_error_plugin ());
+ plugin_load_plugins ();
#endif /* ENABLE_PLUGINS */
ldemul_set_symbols ();
break;
#ifdef ENABLE_PLUGINS
case OPTION_PLUGIN:
- if (plugin_opt_plugin (optarg))
- einfo (_("%P%F: %s: error loading plugin\n"),
- plugin_error_plugin ());
+ plugin_opt_plugin (optarg);
break;
case OPTION_PLUGIN_OPT:
if (plugin_opt_plugin_arg (optarg))
#endif /* !defined (HAVE_DLFCN_H) && defined (HAVE_WINDOWS_H) */
+#ifndef HAVE_DLFCN_H
+static const char *
+dlerror (void)
+{
+ return "";
+}
+#endif
+
/* Helper function for exiting with error status. */
static int
set_plugin_error (const char *plugin)
}
/* Handle -plugin arg: find and load plugin, or return error. */
-int
+void
plugin_opt_plugin (const char *plugin)
{
plugin_t *newplug;
newplug->name = plugin;
newplug->dlhandle = dlopen (plugin, RTLD_NOW);
if (!newplug->dlhandle)
- return set_plugin_error (plugin);
+ einfo (_("%P%F: %s: error loading plugin: %s\n"), plugin, dlerror ());
/* Chain on end, so when we run list it is in command-line order. */
*plugins_tail_chain_ptr = newplug;
/* Record it as current plugin for receiving args. */
last_plugin = newplug;
last_plugin_args_tail_chain_ptr = &newplug->args;
- return 0;
}
/* Accumulate option arguments for last-loaded plugin, or return
}
/* Load up and initialise all plugins after argument parsing. */
-int
+void
plugin_load_plugins (void)
{
struct ld_plugin_tv *my_tv;
/* If there are no plugins, we need do nothing this run. */
if (!curplug)
- return 0;
+ return;
/* First pass over plugins to find max # args needed so that we
can size and allocate the tv array. */
while (curplug)
{
enum ld_plugin_status rv;
- ld_plugin_onload onloadfn = dlsym (curplug->dlhandle, "onload");
+ ld_plugin_onload onloadfn;
+
+ onloadfn = (ld_plugin_onload) dlsym (curplug->dlhandle, "onload");
if (!onloadfn)
- onloadfn = dlsym (curplug->dlhandle, "_onload");
+ onloadfn = (ld_plugin_onload) dlsym (curplug->dlhandle, "_onload");
if (!onloadfn)
- return set_plugin_error (curplug->name);
+ einfo (_("%P%F: %s: error loading plugin: %s\n"),
+ curplug->name, dlerror ());
set_tv_plugin_args (curplug, &my_tv[tv_header_size]);
called_plugin = curplug;
rv = (*onloadfn) (my_tv);
called_plugin = NULL;
if (rv != LDPS_OK)
- return set_plugin_error (curplug->name);
+ einfo (_("%P%F: %s: plugin error: %d\n"), curplug->name, rv);
curplug = curplug->next;
}
plugin_callbacks.notice = &plugin_notice;
link_info.notice_all = TRUE;
link_info.callbacks = &plugin_callbacks;
-
- return 0;
}
/* Call 'claim file' hook for all plugins. */
rv = (*curplug->cleanup_handler) ();
called_plugin = NULL;
if (rv != LDPS_OK)
- set_plugin_error (curplug->name);
+ info_msg (_("%P: %s: error in plugin cleanup: %d (ignored)\n"),
+ curplug->name, rv);
dlclose (curplug->dlhandle);
}
curplug = curplug->next;
}
- if (plugin_error_p ())
- info_msg (_("%P: %s: error in plugin cleanup (ignored)\n"),
- plugin_error_plugin ());
}
/* To determine which symbols should be resolved LDPR_PREVAILING_DEF
to include the plugin-api.h header in order to use this file. */
struct ld_plugin_input_file;
-/* Handle -plugin arg: find and load plugin, or return error. */
-extern int plugin_opt_plugin (const char *plugin);
+/* Handle -plugin arg: find and load plugin. */
+extern void plugin_opt_plugin (const char *plugin);
/* Accumulate option arguments for last-loaded plugin, or return
error if none. */
extern bfd_boolean plugin_active_plugins_p (void);
/* Load up and initialise all plugins after argument parsing. */
-extern int plugin_load_plugins (void);
+extern void plugin_load_plugins (void);
/* Return name of plugin which caused an error in any of the above. */
extern const char *plugin_error_plugin (void);
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2013-01-15 Alan Modra <amodra@gmail.com>
+ * ld-powerpc/tlsso.d: Adjust for plt-thread-safe stubs.
+ * ld-powerpc/tlsso.g: Likewise.
+ * ld-powerpc/tlsso.r: Likewise.
+ * ld-powerpc/tlstocso.d: Likewise.
+ * ld-powerpc/tlstocso.g: Likewise.
+
+ 2012-12-03 H.J. Lu <hongjiu.lu@intel.com>
+ PR ld/14904
+ * ld-plugin/plugin-2.d: Update expected error message.
+ * ld-plugin/plugin-4.d: Likewise.
+
+ 2012-11-23 Alan Modra <amodra@gmail.com>
+ * ld-powerpc/plt1.d: Update for default "at" branch hints.
+ * ld-powerpc/tlsexe.d: Likewise.
+ * ld-powerpc/tlsexetoc.d: Likewise.
+ * ld-powerpc/tlsopt1.d: Likewise.
+ * ld-powerpc/tlsopt1_32.d: Likewise.
+ * ld-powerpc/tlsopt2.d: Likewise.
+ * ld-powerpc/tlsopt2_32.d: Likewise.
+ * ld-powerpc/tlsopt4.d: Likewise.
+ * ld-powerpc/tlsopt4_32.d: Likewise.
+ * ld-powerpc/tlsso.d: Likewise.
+ * ld-powerpc/tlstocso.d: Likewise.
+
+ 2012-10-29 Alan Modra <amodra@gmail.com>
+ * ld-powerpc/powerpc.exp: Modify emulation option passed to ld
+ when little-endian.
+ * ld-powerpc/apuinfo-nul.rd: Update for le output.
+ * ld-powerpc/apuinfo.rd: Likewise.
+ * ld-powerpc/plt1.d: Likewise.
+ * ld-powerpc/relax.d: Likewise.
+ * ld-powerpc/relaxr.d: Likewise.
+ * ld-powerpc/sdadyn.d: Likewise.
+ * ld-powerpc/tls.d: Likewise.
+ * ld-powerpc/tls.g: Likewise.
+ * ld-powerpc/tls.t: Likewise.
+ * ld-powerpc/tls32.d: Likewise.
+ * ld-powerpc/tls32.g: Likewise.
+ * ld-powerpc/tls32.t: Likewise.
+ * ld-powerpc/tlsexe.d: Likewise.
+ * ld-powerpc/tlsexe.g: Likewise.
+ * ld-powerpc/tlsexe.r: Likewise.
+ * ld-powerpc/tlsexe.t: Likewise.
+ * ld-powerpc/tlsexe32.d: Likewise.
+ * ld-powerpc/tlsexe32.g: Likewise.
+ * ld-powerpc/tlsexe32.r: Likewise.
+ * ld-powerpc/tlsexe32.t: Likewise.
+ * ld-powerpc/tlsexetoc.d: Likewise.
+ * ld-powerpc/tlsexetoc.g: Likewise.
+ * ld-powerpc/tlsexetoc.r: Likewise.
+ * ld-powerpc/tlsexetoc.t: Likewise.
+ * ld-powerpc/tlsmark.d: Likewise.
+ * ld-powerpc/tlsmark32.d: Likewise.
+ * ld-powerpc/tlsopt1.d: Likewise.
+ * ld-powerpc/tlsopt1_32.d: Likewise.
+ * ld-powerpc/tlsopt2.d: Likewise.
+ * ld-powerpc/tlsopt2_32.d: Likewise.
+ * ld-powerpc/tlsopt3.d: Likewise.
+ * ld-powerpc/tlsopt3_32.d: Likewise.
+ * ld-powerpc/tlsopt4.d: Likewise.
+ * ld-powerpc/tlsopt4_32.d: Likewise.
+ * ld-powerpc/tlsso.d: Likewise.
+ * ld-powerpc/tlsso.g: Likewise.
+ * ld-powerpc/tlsso.r: Likewise.
+ * ld-powerpc/tlsso.t: Likewise.
+ * ld-powerpc/tlsso32.d: Likewise.
+ * ld-powerpc/tlsso32.g: Likewise.
+ * ld-powerpc/tlsso32.r: Likewise.
+ * ld-powerpc/tlsso32.t: Likewise.
+ * ld-powerpc/tlstoc.d: Likewise.
+ * ld-powerpc/tlstoc.g: Likewise.
+ * ld-powerpc/tlstoc.t: Likewise.
+ * ld-powerpc/tlstocso.d: Likewise.
+ * ld-powerpc/tlstocso.g: Likewise.
+ * ld-powerpc/tlstocso.t: Likewise.
+ * ld-powerpc/tocopt.out: Likewise.
+
+ 2012-08-01 James Lemke <jwlemke@codesourcery.com>
+ * ld-gc/pr13683.d: XFAIL for powerpc*-*-eabivle.
+
2012-12-21 H.J. Lu <hongjiu.lu@intel.com>
PR ld/14980
#source: dummy.s
#ld: --gc-sections -e main --defsym foo=foo2 tmpdir/pr13683.o
#nm: --format=bsd
-#xfail: sh64*-*-* iq2000-*-* lm32-*-* epiphany-*-* mips64vr-*-* frv-*-* m32c-*-* rl78-*-* rx-*-* sh-*-*
+#xfail: sh64*-*-* iq2000-*-* lm32-*-* epiphany-*-* mips64vr-*-* frv-*-* m32c-*-* rl78-*-* rx-*-* sh-*-* powerpc*-*-eabivle
# Note - look for both "foo" and "foo2" being defined, non-zero function symbols
.*: LDPT_OPTION 'failonload'
.*: LDPT_NULL value 0x0 \(0\)
#...
-.*ld.*:.*ldtestplug.*: error loading plugin
+.*ld.*:.*ldtestplug.*: plugin error: 3
#...
.*: LDPT_NULL value 0x0 \(0\)
#...
hook called: cleanup.
-.*ld.*:.*ldtestplug.*: error in plugin cleanup \(ignored\)
+.*ld.*:.*ldtestplug.*: error in plugin cleanup: 3 \(ignored\)
#...
#target: powerpc-eabi*
Hex dump of section '.PPC.EMB.apuinfo':
- 0x00000000 00000008 00000000 00000002 41505569 ............APUi
+ 0x00000000 (00000008|08000000) 00000000 (00000002|02000000) 41505569 .*APUi
0x00000010 6e666f00 nfo.
#target: powerpc-eabi*
Hex dump of section '.PPC.EMB.apuinfo':
- 0x00000000 00000008 00000020 00000002 41505569 ....... ....APUi
- 0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A..
- 0x00000020 01020001 01010001 00400001 01040001 .........@......
- 0x00000030 01000001 ....$
+ 0x00000000 (00000008|08000000) (00000020|20000000) (00000002|02000000) 41505569 .*APUi
+ 0x00000010 6e666f00 (00420001|01004200) (00430001|01004300) (00410001|01004100) nfo.*
+ 0x00000020 (01020001|01000201) (01010001|01000101) (00400001|01004000) (01040001|01000401) .*
+ 0x00000030 01000001 .*
#objdump: -dr
#target: powerpc*-*-*
-.*: file format elf32-powerpc
+.*
Disassembly of section .text:
0+ <_start>:
- 0: 42 9f 00 05 bcl- 20,4\*cr7\+so,4 .*
- 4: 7f c8 02 a6 mflr r30
- 8: 3f de 00 00 addis r30,r30,0
- a: R_PPC_REL16_HA _GLOBAL_OFFSET_TABLE_\+0x6
- c: 3b de 00 0a addi r30,r30,10
- e: R_PPC_REL16_LO _GLOBAL_OFFSET_TABLE_\+0xa
- 10: 48 00 00 01 bl 10 .*
+ 0: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,4 .*
+ 4: (7f c8 02 a6|a6 02 c8 7f) mflr r30
+ 8: (3f de 00 00|00 00 de 3f) addis r30,r30,0
+ (a|8): R_PPC_REL16_HA _GLOBAL_OFFSET_TABLE_\+0x(6|4)
+ c: (3b de 00 0.|0. 00 de 3b) addi r30,r30,.*
+ (e|c): R_PPC_REL16_LO _GLOBAL_OFFSET_TABLE_\+0x(a|8)
+ 10: (48 00 00 01|01 00 00 48) bl 10 .*
10: R_PPC_PLTREL24 _exit
- 14: 48 00 00 00 b 14 .*
+ 14: (48 00 00 00|00 00 00 48) b 14 .*
14: R_PPC_REL24 _start
{{objdump "-Mvle -d" vle-reloc-3.d}} "vle-reloc-3"}
}
+if [istarget "powerpc*le*-*-*"] then {
+ set options_regsub(ld) {-melf32ppc -melf32lppc}
+
+ for {set i 0} {$i < [llength $ppcelftests]} {incr i} {
+ set line [lindex $ppcelftests $i]
+ set ld_options [lindex $line 1]
+ regsub -all elf32ppc $ld_options elf32lppc ld_options
+ set line [lreplace $line 1 1 $ld_options]
+ set ppcelftests [lreplace $ppcelftests $i $i $line]
+ }
+
+ if [ supports_ppc64 ] then {
+ for {set i 0} {$i < [llength $ppc64elftests]} {incr i} {
+ set line [lindex $ppcelftests $i]
+ set ld_options [lindex $line 1]
+ regsub -all elf64ppc $ld_options elf64lppc ld_options
+ set line [lreplace $line 1 1 $ld_options]
+ set ppc64elftests [lreplace $ppc64elftests $i $i $line]
+ }
+ }
+}
run_ld_link_tests $ppcelftests
Disassembly of section .text:
00000000 <_start>:
- 0: 48 00 43 21 bl 4320 <near>
- 4: 48 00 00 11 bl 14 <_start\+0x14>
- 8: 48 00 43 19 bl 4320 <near>
- c: 48 00 00 09 bl 14 <_start\+0x14>
- 10: 4b ff ff f0 b 0 <.*>
- 14: 3d 80 80 00 lis r12,-32768
- 18: 39 8c 12 34 addi r12,r12,4660
- 1c: 7d 89 03 a6 mtctr r12
- 20: 4e 80 04 20 bctr
+ 0: (48 00 43 21|21 43 00 48) bl 4320 <near>
+ 4: (48 00 00 11|11 00 00 48) bl 14 <_start\+0x14>
+ 8: (48 00 43 19|19 43 00 48) bl 4320 <near>
+ c: (48 00 00 09|09 00 00 48) bl 14 <_start\+0x14>
+ 10: (4b ff ff f0|f0 ff ff 4b) b 0 <.*>
+ 14: (3d 80 80 00|00 80 80 3d) lis r12,-32768
+ 18: (39 8c 12 34|34 12 8c 39) addi r12,r12,4660
+ 1c: (7d 89 03 a6|a6 03 89 7d) mtctr r12
+ 20: (4e 80 04 20|20 04 80 4e) bctr
Disassembly of section .text:
00000000 <_start>:
- 0: 48 00 00 15 bl 14 <_start\+0x14>
- 4: 48 00 00 21 bl 24 <_start\+0x24>
- 8: 48 00 00 0d bl 14 <_start\+0x14>
+ 0: (48 00 00 15|15 00 00 48) bl 14 <_start\+0x14>
+ 4: (48 00 00 21|21 00 00 48) bl 24 <_start\+0x24>
+ 8: (48 00 00 0d|0d 00 00 48) bl 14 <_start\+0x14>
8: R_PPC_NONE \*ABS\*
- c: 48 00 00 19 bl 24 <_start\+0x24>
+ c: (48 00 00 19|19 00 00 48) bl 24 <_start\+0x24>
c: R_PPC_NONE \*ABS\*
- 10: 48 00 00 00 b 10 <_start\+0x10>
+ 10: (48 00 00 00|00 00 00 48) b 10 <_start\+0x10>
10: R_PPC_REL24 _start
- 14: 3d 80 00 00 lis r12,0
- 16: R_PPC_ADDR16_HA near
- 18: 39 8c 00 00 addi r12,r12,0
- 1a: R_PPC_ADDR16_LO near
- 1c: 7d 89 03 a6 mtctr r12
- 20: 4e 80 04 20 bctr
- 24: 3d 80 00 00 lis r12,0
- 26: R_PPC_ADDR16_HA far
- 28: 39 8c 00 00 addi r12,r12,0
- 2a: R_PPC_ADDR16_LO far
- 2c: 7d 89 03 a6 mtctr r12
- 30: 4e 80 04 20 bctr
+ 14: (3d 80 00 00|00 00 80 3d) lis r12,0
+ 1(6|4): R_PPC_ADDR16_HA near
+ 18: (39 8c 00 00|00 00 8c 39) addi r12,r12,0
+ 1(a|8): R_PPC_ADDR16_LO near
+ 1c: (7d 89 03 a6|a6 03 89 7d) mtctr r12
+ 20: (4e 80 04 20|20 04 80 4e) bctr
+ 24: (3d 80 00 00|00 00 80 3d) lis r12,0
+ 2(6|4): R_PPC_ADDR16_HA far
+ 28: (39 8c 00 00|00 00 8c 39) addi r12,r12,0
+ 2(a|8): R_PPC_ADDR16_LO far
+ 2c: (7d 89 03 a6|a6 03 89 7d) mtctr r12
+ 30: (4e 80 04 20|20 04 80 4e) bctr
-.*: +file format elf32-powerpc
+.*
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
#source: tls.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0+100000e8 <_start>:
- 100000e8: 3c 6d 00 00 addis r3,r13,0
- 100000ec: 60 00 00 00 nop
- 100000f0: 38 63 90 78 addi r3,r3,-28552
- 100000f4: 3c 6d 00 00 addis r3,r13,0
- 100000f8: 60 00 00 00 nop
- 100000fc: 38 63 10 00 addi r3,r3,4096
- 10000100: 3c 6d 00 00 addis r3,r13,0
- 10000104: 60 00 00 00 nop
- 10000108: 38 63 90 40 addi r3,r3,-28608
- 1000010c: 3c 6d 00 00 addis r3,r13,0
- 10000110: 60 00 00 00 nop
- 10000114: 38 63 10 00 addi r3,r3,4096
- 10000118: 39 23 80 48 addi r9,r3,-32696
- 1000011c: 3d 23 00 00 addis r9,r3,0
- 10000120: 81 49 80 50 lwz r10,-32688\(r9\)
- 10000124: e9 22 80 10 ld r9,-32752\(r2\)
- 10000128: 7d 49 18 2a ldx r10,r9,r3
- 1000012c: 3d 2d 00 00 addis r9,r13,0
- 10000130: a1 49 90 60 lhz r10,-28576\(r9\)
- 10000134: 89 4d 90 68 lbz r10,-28568\(r13\)
- 10000138: 3d 2d 00 00 addis r9,r13,0
- 1000013c: 99 49 90 70 stb r10,-28560\(r9\)
- 10000140: 3c 6d 00 00 addis r3,r13,0
- 10000144: 60 00 00 00 nop
- 10000148: 38 63 90 00 addi r3,r3,-28672
- 1000014c: 3c 6d 00 00 addis r3,r13,0
- 10000150: 60 00 00 00 nop
- 10000154: 38 63 10 00 addi r3,r3,4096
- 10000158: f9 43 80 08 std r10,-32760\(r3\)
- 1000015c: 3d 23 00 00 addis r9,r3,0
- 10000160: 91 49 80 10 stw r10,-32752\(r9\)
- 10000164: e9 22 80 08 ld r9,-32760\(r2\)
- 10000168: 7d 49 19 2a stdx r10,r9,r3
- 1000016c: 3d 2d 00 00 addis r9,r13,0
- 10000170: b1 49 90 60 sth r10,-28576\(r9\)
- 10000174: e9 4d 90 2a lwa r10,-28632\(r13\)
- 10000178: 3d 2d 00 00 addis r9,r13,0
- 1000017c: a9 49 90 30 lha r10,-28624\(r9\)
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 78|78 90 63 38) addi r3,r3,-28552
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 40|40 90 63 38) addi r3,r3,-28608
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (39 23 80 48|48 80 23 39) addi r9,r3,-32696
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (81 49 80 50|50 80 49 81) lwz r10,-32688\(r9\)
+.*: (e9 22 80 10|10 80 22 e9) ld r9,-32752\(r2\)
+.*: (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.*: (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.*: (a1 49 90 60|60 90 49 a1) lhz r10,-28576\(r9\)
+.*: (89 4d 90 68|68 90 4d 89) lbz r10,-28568\(r13\)
+.*: (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.*: (99 49 90 70|70 90 49 99) stb r10,-28560\(r9\)
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
+.*: (e9 22 80 08|08 80 22 e9) ld r9,-32760\(r2\)
+.*: (7d 49 19 2a|2a 19 49 7d) stdx r10,r9,r3
+.*: (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.*: (b1 49 90 60|60 90 49 b1) sth r10,-28576\(r9\)
+.*: (e9 4d 90 2a|2a 90 4d e9) lwa r10,-28632\(r13\)
+.*: (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.*: (a9 49 90 30|30 90 49 a9) lha r10,-28624\(r9\)
0+10000180 <\.__tls_get_addr>:
- 10000180: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
#source: tls.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -sj.got
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.got:
- 100101e0 00000000 100181e0 ffffffff ffff8018 .*
- 100101f0 ffffffff ffff8058 .*
+ 100101e0 (00000000|e0810110) (100181e0|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff) .*
+ 100101f0 (ffffffff|5880ffff) (ffff8058|ffffffff) .*
#source: tls.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -sj.tdata
#target: powerpc64*-*-*
.*: +file format elf64-powerpc
Contents of section \.tdata:
-.* 12345678 9abcdef0 23456789 abcdef01 .*
-.* 3456789a bcdef012 456789ab cdef0123 .*
-.* 56789abc def01234 6789abcd ef012345 .*
-.* 789abcde f0123456 00c0ffee .*
+.* (12345678|f0debc9a) (9abcdef0|78563412) (23456789|01efcdab) (abcdef01|89674523) .*
+.* (3456789a|12f0debc) (bcdef012|9a785634) (456789ab|2301efcd) (cdef0123|ab896745) .*
+.* (56789abc|3412f0de) (def01234|bc9a7856) (6789abcd|452301ef) (ef012345|cdab8967) .*
+.* (789abcde|563412f0) (f0123456|debc9a78) (00c0ffee|eeffc000) .*
#source: tls32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <_start>:
- 1800094: 3c 62 00 00 addis r3,r2,0
- 1800098: 38 63 90 3c addi r3,r3,-28612
- 180009c: 3c 62 00 00 addis r3,r2,0
- 18000a0: 38 63 10 00 addi r3,r3,4096
- 18000a4: 3c 62 00 00 addis r3,r2,0
- 18000a8: 38 63 90 20 addi r3,r3,-28640
- 18000ac: 3c 62 00 00 addis r3,r2,0
- 18000b0: 38 63 10 00 addi r3,r3,4096
- 18000b4: 39 23 80 24 addi r9,r3,-32732
- 18000b8: 3d 23 00 00 addis r9,r3,0
- 18000bc: 81 49 80 28 lwz r10,-32728\(r9\)
- 18000c0: 3d 22 00 00 addis r9,r2,0
- 18000c4: a1 49 90 30 lhz r10,-28624\(r9\)
- 18000c8: 89 42 90 34 lbz r10,-28620\(r2\)
- 18000cc: 3d 22 00 00 addis r9,r2,0
- 18000d0: 99 49 90 38 stb r10,-28616\(r9\)
- 18000d4: 3c 62 00 00 addis r3,r2,0
- 18000d8: 38 63 90 00 addi r3,r3,-28672
- 18000dc: 3c 62 00 00 addis r3,r2,0
- 18000e0: 38 63 10 00 addi r3,r3,4096
- 18000e4: 91 43 80 04 stw r10,-32764\(r3\)
- 18000e8: 3d 23 00 00 addis r9,r3,0
- 18000ec: 91 49 80 08 stw r10,-32760\(r9\)
- 18000f0: 3d 22 00 00 addis r9,r2,0
- 18000f4: b1 49 90 30 sth r10,-28624\(r9\)
- 18000f8: a1 42 90 14 lhz r10,-28652\(r2\)
- 18000fc: 3d 22 00 00 addis r9,r2,0
- 1800100: a9 49 90 18 lha r10,-28648\(r9\)
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 3c|3c 90 63 38) addi r3,r3,-28612
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 20|20 90 63 38) addi r3,r3,-28640
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (39 23 80 24|24 80 23 39) addi r9,r3,-32732
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (81 49 80 28|28 80 49 81) lwz r10,-32728\(r9\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (a1 49 90 30|30 90 49 a1) lhz r10,-28624\(r9\)
+.*: (89 42 90 34|34 90 42 89) lbz r10,-28620\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (99 49 90 38|38 90 49 99) stb r10,-28616\(r9\)
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\)
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (b1 49 90 30|30 90 49 b1) sth r10,-28624\(r9\)
+.*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (a9 49 90 18|18 90 49 a9) lha r10,-28648\(r9\)
0+1800104 <__tls_get_addr>:
- 1800104: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.got:
0+1810128 <_GLOBAL_OFFSET_TABLE_-0x4>:
- 1810128: 4e 80 00 21 blrl
+.*: (4e 80 00 21|21 00 80 4e) blrl
0+181012c <_GLOBAL_OFFSET_TABLE_>:
\.\.\.
#source: tls32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -sj.got
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.got:
- 1810128 4e800021 00000000 00000000 00000000 .*
+ 1810128 (4e800021|2100804e) 00000000 00000000 00000000 .*
#source: tls32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -sj.tdata
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.tdata:
- 1810108 12345678 23456789 3456789a 456789ab .*
- 1810118 56789abc 6789abcd 789abcde 00c0ffee .*
+ 1810108 (12345678|78563412) (23456789|89674523) (3456789a|9a785634) (456789ab|ab896745) .*
+ 1810118 (56789abc|bc9a7856) (6789abcd|cdab8967) (789abcde|debc9a78) (00c0ffee|eeffc000) .*
#source: tls.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
-.* e9 63 00 00 ld r11,0\(r3\)
-.* e9 83 00 08 ld r12,8\(r3\)
-.* 7c 60 1b 78 mr r0,r3
-.* 2c 2b 00 00 cmpdi r11,0
-.* 7c 6c 6a 14 add r3,r12,r13
-.* 4d 82 00 20 beqlr
-.* 7c 03 03 78 mr r3,r0
-.* 7d 68 02 a6 mflr r11
-.* f9 61 00 20 std r11,32\(r1\)
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 62 80 48 ld r11,-32696\(r2\)
-.* 7d 69 03 a6 mtctr r11
-.* e8 42 80 50 ld r2,-32688\(r2\)
-.* 4e 80 04 21 bctrl
-.* e9 61 00 20 ld r11,32\(r1\)
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 7d 68 03 a6 mtlr r11
-.* 4e 80 00 20 blr
+.* (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
+.* (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
+.* (7c 60 1b 78|78 1b 60 7c) mr r0,r3
+.* (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
+.* (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
+.* (4d 82 00 20|20 00 82 4d) beqlr
+.* (7c 03 03 78|78 03 03 7c) mr r3,r0
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
+.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
+.* (e9 62 80 48|48 80 62 e9) ld r11,-32696\(r2\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e8 42 80 50|50 80 42 e8) ld r2,-32688\(r2\)
+.* (4e 80 04 21|21 04 80 4e) bctrl
+.* (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (7d 68 03 a6|a6 03 68 7d) mtlr r11
+.* (4e 80 00 20|20 00 80 4e) blr
.* <_start>:
-.* e8 62 80 10 ld r3,-32752\(r2\)
-.* 60 00 00 00 nop
-.* 7c 63 6a 14 add r3,r3,r13
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff a9 bl .*
-.* 60 00 00 00 nop
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 90 38 addi r3,r3,-28616
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 28 ld r9,-32728\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 58 lhz r10,-28584\(r9\)
-.* 89 4d 90 60 lbz r10,-28576\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 68 stb r10,-28568\(r9\)
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 90 00 addi r3,r3,-28672
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* f9 43 80 08 std r10,-32760\(r3\)
-.* 3d 23 00 00 addis r9,r3,0
-.* 91 49 80 10 stw r10,-32752\(r9\)
-.* e9 22 80 08 ld r9,-32760\(r2\)
-.* 7d 49 19 2a stdx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* b1 49 90 58 sth r10,-28584\(r9\)
-.* e9 4d 90 2a lwa r10,-28632\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* a9 49 90 30 lha r10,-28624\(r9\)
-.* 00 00 00 00 .*
-.* 00 01 02 00 .*
+.* (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\)
+.* (60 00 00 00|00 00 00 60) nop
+.* (7c 63 6a 14|14 6a 63 7c) add r3,r3,r13
+.* (38 62 80 18|18 80 62 38) addi r3,r2,-32744
+.* (4b ff ff a9|a9 ff ff 4b) bl .*
+.* (60 00 00 00|00 00 00 60) nop
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 90 38|38 90 63 38) addi r3,r3,-28616
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
+.* (e9 22 80 28|28 80 22 e9) ld r9,-32728\(r2\)
+.* (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (a1 49 90 58|58 90 49 a1) lhz r10,-28584\(r9\)
+.* (89 4d 90 60|60 90 4d 89) lbz r10,-28576\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (99 49 90 68|68 90 49 99) stb r10,-28568\(r9\)
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.* (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
+.* (e9 22 80 08|08 80 22 e9) ld r9,-32760\(r2\)
+.* (7d 49 19 2a|2a 19 49 7d) stdx r10,r9,r3
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (b1 49 90 58|58 90 49 b1) sth r10,-28584\(r9\)
+.* (e9 4d 90 2a|2a 90 4d e9) lwa r10,-28632\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (a9 49 90 30|30 90 49 a9) lha r10,-28624\(r9\)
+.* (00 00 00 00|00 02 01 00) .*
+.* (00 01 02 00|00 00 00 00) .*
.* <__glink_PLTresolve>:
-.* 7d 88 02 a6 mflr r12
-.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
-.* 7d 68 02 a6 mflr r11
-.* e8 4b ff f0 ld r2,-16\(r11\)
-.* 7d 88 03 a6 mtlr r12
-.* 7d 82 5a 14 add r12,r2,r11
-.* e9 6c 00 00 ld r11,0\(r12\)
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
-.* 4e 80 04 20 bctr
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 38 00 00 00 li r0,0
-.* 4b ff ff c4 b .*
+.* (7d 88 02 a6|a6 02 88 7d) mflr r12
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
+.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
+.* (7d 82 5a 14|14 5a 82 7d) add r12,r2,r11
+.* (e9 6c 00 00|00 00 6c e9) ld r11,0\(r12\)
+.* (e8 4c 00 08|08 00 4c e8) ld r2,8\(r12\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e9 6c 00 10|10 00 6c e9) ld r11,16\(r12\)
+.* (4e 80 04 20|20 04 80 4e) bctr
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 00 00 00|00 00 00 38) li r0,0
+.* (4b ff ff c4|c4 ff ff 4b) b .*
#source: tls.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -sj.got
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.got:
-.* 00000000 10018620 ffffffff ffff8018 .*
+.* (00000000|20860110) (10018620|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff) .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
#source: tls.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#readelf: -WSsrl
#target: powerpc64*-*-*
#source: tls.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -sj.tdata
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.tdata:
- .* 12345678 9abcdef0 23456789 abcdef01 .*
- .* 3456789a bcdef012 456789ab cdef0123 .*
- .* 56789abc def01234 6789abcd ef012345 .*
- .* 789abcde f0123456 .*
+ .* (12345678|f0debc9a) (9abcdef0|78563412) (23456789|01efcdab) (abcdef01|89674523) .*
+ .* (3456789a|12f0debc) (bcdef012|9a785634) (456789ab|2301efcd) (cdef0123|ab896745) .*
+ .* (56789abc|3412f0de) (def01234|bc9a7856) (6789abcd|452301ef) (ef012345|cdab8967) .*
+ .* (789abcde|563412f0) (f0123456|debc9a78) .*
#source: tls32.s
#as: -a32
-#ld: -melf32ppc tmpdir/libtlslib32.so
+#ld: tmpdir/libtlslib32.so
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
.* <_start>:
-.*: 80 7f ff f0 lwz r3,-16\(r31\)
-.*: 7c 63 12 14 add r3,r3,r2
-.*: 38 7f ff f4 addi r3,r31,-12
-.*: 48 01 01 85 bl .*<__tls_get_addr_opt@plt>
-.*: 3c 62 00 00 addis r3,r2,0
-.*: 38 63 90 1c addi r3,r3,-28644
-.*: 3c 62 00 00 addis r3,r2,0
-.*: 38 63 10 00 addi r3,r3,4096
-.*: 39 23 80 20 addi r9,r3,-32736
-.*: 3d 23 00 00 addis r9,r3,0
-.*: 81 49 80 24 lwz r10,-32732\(r9\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: a1 49 90 2c lhz r10,-28628\(r9\)
-.*: 89 42 90 30 lbz r10,-28624\(r2\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: 99 49 90 34 stb r10,-28620\(r9\)
-.*: 3c 62 00 00 addis r3,r2,0
-.*: 38 63 90 00 addi r3,r3,-28672
-.*: 3c 62 00 00 addis r3,r2,0
-.*: 38 63 10 00 addi r3,r3,4096
-.*: 91 43 80 04 stw r10,-32764\(r3\)
-.*: 3d 23 00 00 addis r9,r3,0
-.*: 91 49 80 08 stw r10,-32760\(r9\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: b1 49 90 2c sth r10,-28628\(r9\)
-.*: a1 42 90 14 lhz r10,-28652\(r2\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: a9 49 90 18 lha r10,-28648\(r9\)
+.*: (80 7f ff f0|f0 ff 7f 80) lwz r3,-16\(r31\)
+.*: (7c 63 12 14|14 12 63 7c) add r3,r3,r2
+.*: (38 7f ff f4|f4 ff 7f 38) addi r3,r31,-12
+.*: (48 01 01 85|85 01 01 48) bl .*<__tls_get_addr_opt@plt>
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 1c|1c 90 63 38) addi r3,r3,-28644
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (39 23 80 20|20 80 23 39) addi r9,r3,-32736
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (81 49 80 24|24 80 49 81) lwz r10,-32732\(r9\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (a1 49 90 2c|2c 90 49 a1) lhz r10,-28628\(r9\)
+.*: (89 42 90 30|30 90 42 89) lbz r10,-28624\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (99 49 90 34|34 90 49 99) stb r10,-28620\(r9\)
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\)
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (b1 49 90 2c|2c 90 49 b1) sth r10,-28628\(r9\)
+.*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (a9 49 90 18|18 90 49 a9) lha r10,-28648\(r9\)
Disassembly of section \.got:
.* <_GLOBAL_OFFSET_TABLE_-0x10>:
\.\.\.
-.*: 4e 80 00 21 blrl
+.*: (4e 80 00 21|21 00 80 4e) blrl
.* <_GLOBAL_OFFSET_TABLE_>:
-.*: 01 81 02 b8 00 00 00 00 00 00 00 00 .*
+.*: (01 81 02 b8|b8 02 81 01) 00 00 00 00 00 00 00 00 .*
#source: tls32.s
#as: -a32
-#ld: -melf32ppc tmpdir/libtlslib32.so
+#ld: tmpdir/libtlslib32.so
#objdump: -sj.got
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.got:
-.* 00000000 00000000 00000000 4e800021 .*
-.* 018102b8 00000000 00000000 .*
+.* 00000000 00000000 00000000 (4e800021|2100804e) .*
+.* (018102b8|b8028101) 00000000 00000000 .*
#source: tls32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#readelf: -WSsrl
#target: powerpc*-*-*
#source: tls32.s
#as: -a32
-#ld: -melf32ppc tmpdir/libtlslib32.so
+#ld: tmpdir/libtlslib32.so
#objdump: -sj.tdata
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.tdata:
-.* 12345678 23456789 3456789a 456789ab .*
-.* 56789abc 6789abcd 789abcde .*
+.* (12345678|78563412) (23456789|89674523) (3456789a|9a785634) (456789ab|ab896745) .*
+.* (56789abc|bc9a7856) (6789abcd|cdab8967) (789abcde|debc9a78) .*
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
-.* e9 63 00 00 ld r11,0\(r3\)
-.* e9 83 00 08 ld r12,8\(r3\)
-.* 7c 60 1b 78 mr r0,r3
-.* 2c 2b 00 00 cmpdi r11,0
-.* 7c 6c 6a 14 add r3,r12,r13
-.* 4d 82 00 20 beqlr
-.* 7c 03 03 78 mr r3,r0
-.* 7d 68 02 a6 mflr r11
-.* f9 61 00 20 std r11,32\(r1\)
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 62 80 70 ld r11,-32656\(r2\)
-.* 7d 69 03 a6 mtctr r11
-.* e8 42 80 78 ld r2,-32648\(r2\)
-.* 4e 80 04 21 bctrl
-.* e9 61 00 20 ld r11,32\(r1\)
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 7d 68 03 a6 mtlr r11
-.* 4e 80 00 20 blr
+.* (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
+.* (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
+.* (7c 60 1b 78|78 1b 60 7c) mr r0,r3
+.* (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
+.* (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
+.* (4d 82 00 20|20 00 82 4d) beqlr
+.* (7c 03 03 78|78 03 03 7c) mr r3,r0
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
+.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
+.* (e9 62 80 70|70 80 62 e9) ld r11,-32656\(r2\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e8 42 80 78|78 80 42 e8) ld r2,-32648\(r2\)
+.* (4e 80 04 21|21 04 80 4e) bctrl
+.* (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (7d 68 03 a6|a6 03 68 7d) mtlr r11
+.* (4e 80 00 20|20 00 80 4e) blr
.* <_start>:
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff b5 bl .*
-.* 60 00 00 00 nop
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff a9 bl .*
-.* 60 00 00 00 nop
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 90 38 addi r3,r3,-28616
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 58 lhz r10,-28584\(r9\)
-.* 89 4d 90 60 lbz r10,-28576\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 68 stb r10,-28568\(r9\)
-.* 00 00 00 00 .*
-.* 00 01 02 28 .*
+.* (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.* (4b ff ff b5|b5 ff ff 4b) bl .*
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 62 80 18|18 80 62 38) addi r3,r2,-32744
+.* (4b ff ff a9|a9 ff ff 4b) bl .*
+.* (60 00 00 00|00 00 00 60) nop
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 90 38|38 90 63 38) addi r3,r3,-28616
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
+.* (e9 22 80 48|48 80 22 e9) ld r9,-32696\(r2\)
+.* (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (a1 49 90 58|58 90 49 a1) lhz r10,-28584\(r9\)
+.* (89 4d 90 60|60 90 4d 89) lbz r10,-28576\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (99 49 90 68|68 90 49 99) stb r10,-28568\(r9\)
+.* (00 00 00 00|28 02 01 00) .*
+.* (00 01 02 28|00 00 00 00) .*
.* <__glink_PLTresolve>:
-.* 7d 88 02 a6 mflr r12
-.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
-.* 7d 68 02 a6 mflr r11
-.* e8 4b ff f0 ld r2,-16\(r11\)
-.* 7d 88 03 a6 mtlr r12
-.* 7d 82 5a 14 add r12,r2,r11
-.* e9 6c 00 00 ld r11,0\(r12\)
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
-.* 4e 80 04 20 bctr
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 38 00 00 00 li r0,0
-.* 4b ff ff c4 b .*
+.* (7d 88 02 a6|a6 02 88 7d) mflr r12
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
+.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
+.* (7d 82 5a 14|14 5a 82 7d) add r12,r2,r11
+.* (e9 6c 00 00|00 00 6c e9) ld r11,0\(r12\)
+.* (e8 4c 00 08|08 00 4c e8) ld r2,8\(r12\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e9 6c 00 10|10 00 6c e9) ld r11,16\(r12\)
+.* (4e 80 04 20|20 04 80 4e) bctr
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 00 00 00|00 00 00 38) li r0,0
+.* (4b ff ff c4|c4 ff ff 4b) b .*
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -sj.got
#target: powerpc64*-*-*
.*: +file format elf64-powerpc
Contents of section \.got:
-.* 00000000 100185c0 00000000 00000000 .*
+.* (00000000|c0850110) (100185c0|00000000) 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
-.* 00000000 00000000 00000000 00000001 .*
-.* 00000000 00000000 00000000 00000001 .*
-.* 00000000 00000000 ffffffff ffff8050 .*
+.* 00000000 00000000 (00000000|01000000) (00000001|00000000) .*
+.* 00000000 00000000 (00000000|01000000) (00000001|00000000) .*
+.* 00000000 00000000 (ffffffff|5080ffff) (ffff8050|ffffffff) .*
.* 00000000 00000000 .*
#source: tlslib.s
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#readelf: -WSsrl
#target: powerpc64*-*-*
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc tmpdir/libtlslib.so
+#ld: tmpdir/libtlslib.so
#objdump: -sj.tdata
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.tdata:
-.* 12345678 9abcdef0 23456789 abcdef01 .*
-.* 3456789a bcdef012 456789ab cdef0123 .*
-.* 56789abc def01234 6789abcd ef012345 .*
-.* 789abcde f0123456 .*
+.* (12345678|f0debc9a) (9abcdef0|78563412) (23456789|01efcdab) (abcdef01|89674523) .*
+.* (3456789a|12f0debc) (bcdef012|9a785634) (456789ab|2301efcd) (cdef0123|ab896745) .*
+.* (56789abc|3412f0de) (def01234|bc9a7856) (6789abcd|452301ef) (ef012345|cdab8967) .*
+.* (789abcde|563412f0) (f0123456|debc9a78) .*
#source: tlsmark.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0+100000e8 <_start>:
- 100000e8: 48 00 00 18 b 10000100 <_start\+0x18>
- 100000ec: 60 00 00 00 nop
- 100000f0: 38 63 90 00 addi r3,r3,-28672
- 100000f4: e8 83 00 00 ld r4,0\(r3\)
- 100000f8: 3c 6d 00 00 addis r3,r13,0
- 100000fc: 48 00 00 0c b 10000108 <_start\+0x20>
- 10000100: 3c 6d 00 00 addis r3,r13,0
- 10000104: 4b ff ff e8 b 100000ec <_start\+0x4>
- 10000108: 60 00 00 00 nop
- 1000010c: 38 63 10 00 addi r3,r3,4096
- 10000110: e8 83 80 00 ld r4,-32768\(r3\)
- 10000114: 3c 6d 00 00 addis r3,r13,0
- 10000118: 48 00 00 0c b 10000124 <_start\+0x3c>
- 1000011c: 3c 6d 00 00 addis r3,r13,0
- 10000120: 48 00 00 14 b 10000134 <_start\+0x4c>
- 10000124: 60 00 00 00 nop
- 10000128: 38 63 90 04 addi r3,r3,-28668
- 1000012c: e8 a3 00 00 ld r5,0\(r3\)
- 10000130: 4b ff ff ec b 1000011c <_start\+0x34>
- 10000134: 60 00 00 00 nop
- 10000138: 38 63 10 00 addi r3,r3,4096
- 1000013c: e8 a3 80 04 ld r5,-32764\(r3\)
+.*: (48 00 00 18|18 00 00 48) b 10000100 <_start\+0x18>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.*: (e8 83 00 00|00 00 83 e8) ld r4,0\(r3\)
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (48 00 00 0c|0c 00 00 48) b 10000108 <_start\+0x20>
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (4b ff ff e8|e8 ff ff 4b) b 100000ec <_start\+0x4>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (e8 83 80 00|00 80 83 e8) ld r4,-32768\(r3\)
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (48 00 00 0c|0c 00 00 48) b 10000124 <_start\+0x3c>
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (48 00 00 14|14 00 00 48) b 10000134 <_start\+0x4c>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 04|04 90 63 38) addi r3,r3,-28668
+.*: (e8 a3 00 00|00 00 a3 e8) ld r5,0\(r3\)
+.*: (4b ff ff ec|ec ff ff 4b) b 1000011c <_start\+0x34>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (e8 a3 80 04|04 80 a3 e8) ld r5,-32764\(r3\)
0+10000140 <\.__tls_get_addr>:
- 10000140: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
#source: tlsmark32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <_start>:
- 1800094: 48 00 00 14 b 18000a8 <_start\+0x14>
- 1800098: 38 63 90 00 addi r3,r3,-28672
- 180009c: 80 83 00 00 lwz r4,0\(r3\)
- 18000a0: 3c 62 00 00 addis r3,r2,0
- 18000a4: 48 00 00 0c b 18000b0 <_start\+0x1c>
- 18000a8: 3c 62 00 00 addis r3,r2,0
- 18000ac: 4b ff ff ec b 1800098 <_start\+0x4>
- 18000b0: 38 63 10 00 addi r3,r3,4096
- 18000b4: 80 83 80 00 lwz r4,-32768\(r3\)
+.*: (48 00 00 14|14 00 00 48) b 18000a8 <_start\+0x14>
+.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
+.*: (80 83 00 00|00 00 83 80) lwz r4,0\(r3\)
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (48 00 00 0c|0c 00 00 48) b 18000b0 <_start\+0x1c>
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (4b ff ff ec|ec ff ff 4b) b 1800098 <_start\+0x4>
+.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.*: (80 83 80 00|00 80 83 80) lwz r4,-32768\(r3\)
0+18000b8 <__tls_get_addr>:
- 18000b8: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
#pass
\ No newline at end of file
#source: tlsopt1.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0+100000e8 <\.__tls_get_addr>:
- 100000e8: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt1:
0+100000ec <\.no_opt1>:
- 100000ec: 38 62 80 08 addi r3,r2,-32760
- 100000f0: 2c 24 00 00 cmpdi r4,0
- 100000f4: 41 82 00 10 beq- .*
- 100000f8: 4b ff ff f1 bl 100000e8 <\.__tls_get_addr>
- 100000fc: 60 00 00 00 nop
- 10000100: 48 00 00 0c b .*
- 10000104: 4b ff ff e5 bl 100000e8 <\.__tls_get_addr>
- 10000108: 60 00 00 00 nop
+.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
+.*: (41 82 00 10|10 00 82 41) beq .*
+.*: (4b ff ff f1|f1 ff ff 4b) bl 100000e8 <\.__tls_get_addr>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (4b ff ff e5|e5 ff ff 4b) bl 100000e8 <\.__tls_get_addr>
+.*: (60 00 00 00|00 00 00 60) nop
#source: tlsopt1_32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <__tls_get_addr>:
- 1800094: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt1:
0+1800098 <\.no_opt1>:
- 1800098: 38 6d ff f4 addi r3,r13,-12
- 180009c: 2c 04 00 00 cmpwi r4,0
- 18000a0: 41 82 00 0c beq- .*
- 18000a4: 4b ff ff f1 bl 1800094 <__tls_get_addr>
- 18000a8: 48 00 00 08 b .*
- 18000ac: 4b ff ff e9 bl 1800094 <__tls_get_addr>
+.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
+.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
+.*: (41 82 00 0c|0c 00 82 41) beq .*
+.*: (4b ff ff f1|f1 ff ff 4b) bl 1800094 <__tls_get_addr>
+.*: (48 00 00 08|08 00 00 48) b .*
+.*: (4b ff ff e9|e9 ff ff 4b) bl 1800094 <__tls_get_addr>
#pass
#source: tlsopt2.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0+100000e8 <\.__tls_get_addr>:
- 100000e8: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt2:
0+100000ec <\.no_opt2>:
- 100000ec: 38 62 80 08 addi r3,r2,-32760
- 100000f0: 2c 24 00 00 cmpdi r4,0
- 100000f4: 41 82 00 08 beq- .*
- 100000f8: 38 62 80 08 addi r3,r2,-32760
- 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr>
- 10000100: 60 00 00 00 nop
+.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
+.*: (41 82 00 08|08 00 82 41) beq .*
+.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.*: (4b ff ff ed|ed ff ff 4b) bl 100000e8 <\.__tls_get_addr>
+.*: (60 00 00 00|00 00 00 60) nop
#source: tlsopt2_32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <__tls_get_addr>:
- 1800094: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt2:
0+1800098 <\.no_opt2>:
- 1800098: 38 6d ff f4 addi r3,r13,-12
- 180009c: 2c 04 00 00 cmpwi r4,0
- 18000a0: 41 82 00 08 beq- .*
- 18000a4: 38 6d ff f4 addi r3,r13,-12
- 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr>
+.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
+.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
+.*: (41 82 00 08|08 00 82 41) beq .*
+.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
+.*: (4b ff ff ed|ed ff ff 4b) bl 1800094 <__tls_get_addr>
#pass
#source: tlsopt3.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
00000000100000e8 <\.__tls_get_addr>:
- 100000e8: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt3:
00000000100000ec <\.no_opt3>:
- 100000ec: 38 62 80 08 addi r3,r2,-32760
- 100000f0: 48 00 00 0c b .*
- 100000f4: 38 62 80 18 addi r3,r2,-32744
- 100000f8: 48 00 00 10 b .*
- 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr>
- 10000100: 60 00 00 00 nop
- 10000104: 48 00 00 0c b .*
- 10000108: 4b ff ff e1 bl 100000e8 <\.__tls_get_addr>
- 1000010c: 60 00 00 00 nop
+.*: (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (38 62 80 18|18 80 62 38) addi r3,r2,-32744
+.*: (48 00 00 10|10 00 00 48) b .*
+.*: (4b ff ff ed|ed ff ff 4b) bl 100000e8 <\.__tls_get_addr>
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (4b ff ff e1|e1 ff ff 4b) bl 100000e8 <\.__tls_get_addr>
+.*: (60 00 00 00|00 00 00 60) nop
#source: tlsopt3_32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <__tls_get_addr>:
- 1800094: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.no_opt3:
0+1800098 <\.no_opt3>:
- 1800098: 38 6d ff ec addi r3,r13,-20
- 180009c: 48 00 00 0c b .*
- 18000a0: 38 6d ff f4 addi r3,r13,-12
- 18000a4: 48 00 00 0c b .*
- 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr>
- 18000ac: 48 00 00 08 b .*
- 18000b0: 4b ff ff e5 bl 1800094 <__tls_get_addr>
+.*: (38 6d ff ec|ec ff 6d 38) addi r3,r13,-20
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (38 6d ff f4|f4 ff 6d 38) addi r3,r13,-12
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (4b ff ff ed|ed ff ff 4b) bl 1800094 <__tls_get_addr>
+.*: (48 00 00 08|08 00 00 48) b .*
+.*: (4b ff ff e5|e5 ff ff 4b) bl 1800094 <__tls_get_addr>
#pass
#source: tlsopt4.s
#source: tlslib.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
0+100000e8 <\.__tls_get_addr>:
- 100000e8: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.opt1:
0+100000ec <\.opt1>:
- 100000ec: 3c 6d 00 00 addis r3,r13,0
- 100000f0: 2c 24 00 00 cmpdi r4,0
- 100000f4: 41 82 00 10 beq- .*
- 100000f8: 60 00 00 00 nop
- 100000fc: 38 63 90 10 addi r3,r3,-28656
- 10000100: 48 00 00 0c b .*
- 10000104: 60 00 00 00 nop
- 10000108: 38 63 90 10 addi r3,r3,-28656
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
+.*: (41 82 00 10|10 00 82 41) beq .*
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Disassembly of section \.opt2:
0+1000010c <\.opt2>:
- 1000010c: 3c 6d 00 00 addis r3,r13,0
- 10000110: 2c 24 00 00 cmpdi r4,0
- 10000114: 41 82 00 08 beq- .*
- 10000118: 3c 6d 00 00 addis r3,r13,0
- 1000011c: 60 00 00 00 nop
- 10000120: 38 63 90 10 addi r3,r3,-28656
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
+.*: (41 82 00 08|08 00 82 41) beq .*
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Disassembly of section \.opt3:
0+10000124 <\.opt3>:
- 10000124: 3c 6d 00 00 addis r3,r13,0
- 10000128: 48 00 00 0c b .*
- 1000012c: 3c 6d 00 00 addis r3,r13,0
- 10000130: 48 00 00 10 b .*
- 10000134: 60 00 00 00 nop
- 10000138: 38 63 90 10 addi r3,r3,-28656
- 1000013c: 48 00 00 0c b .*
- 10000140: 60 00 00 00 nop
- 10000144: 38 63 90 08 addi r3,r3,-28664
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.*: (48 00 00 10|10 00 00 48) b .*
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (38 63 90 08|08 90 63 38) addi r3,r3,-28664
#source: tlsopt4_32.s
#source: tlslib32.s
#as: -a32
-#ld: -melf32ppc
+#ld:
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
0+1800094 <__tls_get_addr>:
- 1800094: 4e 80 00 20 blr
+.*: (4e 80 00 20|20 00 80 4e) blr
Disassembly of section \.opt1:
0+1800098 <\.opt1>:
- 1800098: 3c 62 00 00 addis r3,r2,0
- 180009c: 2c 04 00 00 cmpwi r4,0
- 18000a0: 41 82 00 0c beq- .*
- 18000a4: 38 63 90 10 addi r3,r3,-28656
- 18000a8: 48 00 00 08 b .*
- 18000ac: 38 63 90 10 addi r3,r3,-28656
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
+.*: (41 82 00 0c|0c 00 82 41) beq .*
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
+.*: (48 00 00 08|08 00 00 48) b .*
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Disassembly of section \.opt2:
0+18000b0 <\.opt2>:
- 18000b0: 3c 62 00 00 addis r3,r2,0
- 18000b4: 2c 04 00 00 cmpwi r4,0
- 18000b8: 41 82 00 08 beq- .*
- 18000bc: 3c 62 00 00 addis r3,r2,0
- 18000c0: 38 63 90 10 addi r3,r3,-28656
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
+.*: (41 82 00 08|08 00 82 41) beq .*
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
Disassembly of section \.opt3:
0+18000c4 <\.opt3>:
- 18000c4: 3c 62 00 00 addis r3,r2,0
- 18000c8: 48 00 00 0c b .*
- 18000cc: 3c 62 00 00 addis r3,r2,0
- 18000d0: 48 00 00 0c b .*
- 18000d4: 38 63 90 10 addi r3,r3,-28656
- 18000d8: 48 00 00 08 b .*
- 18000dc: 38 63 90 08 addi r3,r3,-28664
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
+.*: (48 00 00 0c|0c 00 00 48) b .*
+.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
+.*: (48 00 00 08|08 00 00 48) b .*
+.*: (38 63 90 08|08 90 63 38) addi r3,r3,-28664
#pass
#source: tls.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -dr
#target: powerpc64*-*-*
Disassembly of section \.text:
.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 62 80 78 ld r11,-32648\(r2\)
-.* 7d 69 03 a6 mtctr r11
-.* e8 42 80 80 ld r2,-32640\(r2\)
-.* 4e 80 04 20 bctr
+.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
+.* (e9 62 80 78|78 80 62 e9) ld r11,-32648\(r2\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e8 42 80 80|80 80 42 e8) ld r2,-32640\(r2\)
+.* (28 22 00 00|00 00 22 28) cmpldi r2,0
+.* (4c e2 04 20|20 04 e2 4c) bnectr\+
+.* (48 00 00 ..|.. 00 00 48) b .* <__glink_PLTresolve\+0x38>
.* <_start>:
-.* 38 62 80 20 addi r3,r2,-32736
-.* 4b ff ff e9 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 50 addi r3,r2,-32688
-.* 4b ff ff dd bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 38 addi r3,r2,-32712
-.* 4b ff ff d1 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 50 addi r3,r2,-32688
-.* 4b ff ff c5 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 30 ld r9,-32720\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 6a 2e lhzx r10,r9,r13
-.* 89 4d 00 00 lbz r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 00 00 stb r10,0\(r9\)
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff 91 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 50 addi r3,r2,-32688
-.* 4b ff ff 85 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* f9 43 80 08 std r10,-32760\(r3\)
-.* 3d 23 00 00 addis r9,r3,0
-.* 91 49 80 10 stw r10,-32752\(r9\)
-.* e9 22 80 18 ld r9,-32744\(r2\)
-.* 7d 49 19 2a stdx r10,r9,r3
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 6b 2e sthx r10,r9,r13
-.* e9 4d 00 02 lwa r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* a9 49 00 00 lha r10,0\(r9\)
-.* 60 00 00 00 nop
-.* 00 00 00 00 .*
-.* 00 01 02 20 .*
+.* (38 62 80 20|20 80 62 38) addi r3,r2,-32736
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 50|50 80 62 38) addi r3,r2,-32688
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 38|38 80 62 38) addi r3,r2,-32712
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 50|50 80 62 38) addi r3,r2,-32688
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
+.* (e9 22 80 30|30 80 22 e9) ld r9,-32720\(r2\)
+.* (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.* (e9 22 80 48|48 80 22 e9) ld r9,-32696\(r2\)
+.* (7d 49 6a 2e|2e 6a 49 7d) lhzx r10,r9,r13
+.* (89 4d 00 00|00 00 4d 89) lbz r10,0\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (99 49 00 00|00 00 49 99) stb r10,0\(r9\)
+.* (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 50|50 80 62 38) addi r3,r2,-32688
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
+.* (e9 22 80 18|18 80 22 e9) ld r9,-32744\(r2\)
+.* (7d 49 19 2a|2a 19 49 7d) stdx r10,r9,r3
+.* (e9 22 80 48|48 80 22 e9) ld r9,-32696\(r2\)
+.* (7d 49 6b 2e|2e 6b 49 7d) sthx r10,r9,r13
+.* (e9 4d 00 02|02 00 4d e9) lwa r10,0\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (a9 49 00 00|00 00 49 a9) lha r10,0\(r9\)
+.* (60 00 00 00|00 00 00 60) nop
+.* (00 00 00 00|20 02 01 00) .*
+.* (00 01 02 20|00 00 00 00) .*
.* <__glink_PLTresolve>:
-.* 7d 88 02 a6 mflr r12
-.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
-.* 7d 68 02 a6 mflr r11
-.* e8 4b ff f0 ld r2,-16\(r11\)
-.* 7d 88 03 a6 mtlr r12
-.* 7d 82 5a 14 add r12,r2,r11
-.* e9 6c 00 00 ld r11,0\(r12\)
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
-.* 4e 80 04 20 bctr
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 38 00 00 00 li r0,0
-.* 4b ff ff c4 b .*
+.* (7d 88 02 a6|a6 02 88 7d) mflr r12
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
+.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
+.* (7d 82 5a 14|14 5a 82 7d) add r12,r2,r11
+.* (e9 6c 00 00|00 00 6c e9) ld r11,0\(r12\)
+.* (e8 4c 00 08|08 00 4c e8) ld r2,8\(r12\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e9 6c 00 10|10 00 6c e9) ld r11,16\(r12\)
+.* (4e 80 04 20|20 04 80 4e) bctr
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 00 00 00|00 00 00 38) li r0,0
+.* (4b ff ff c4|c4 ff ff 4b) b .*
#source: tls.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -sj.got
#target: powerpc64*-*-*
.*: +file format elf64-powerpc
Contents of section \.got:
-.* 00000000 00018780 00000000 00000000 .*
+ 10788 (00000000|88870100) (00018788|00000000) 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
#source: tls.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#readelf: -WSsrl
#target: powerpc64*-*-*
[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
-[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f8 \.tdata \+ 28
-[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f8 \.tdata \+ 30
-[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f8 \.tdata \+ 30
+[0-9a-f ]+R_PPC64_TPREL16_DS +[0-9a-f]+ \.tdata \+ 28
+[0-9a-f ]+R_PPC64_TPREL16_HA +[0-9a-f]+ \.tdata \+ 30
+[0-9a-f ]+R_PPC64_TPREL16_LO +[0-9a-f]+ \.tdata \+ 30
[0-9a-f ]+R_PPC64_DTPMOD64 +0
[0-9a-f ]+R_PPC64_DTPREL64 +0
[0-9a-f ]+R_PPC64_DTPREL64 +18
#source: tls.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -sj.tdata
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.tdata:
-.* 12345678 9abcdef0 23456789 abcdef01 .*
-.* 3456789a bcdef012 456789ab cdef0123 .*
-.* 56789abc def01234 6789abcd ef012345 .*
-.* 789abcde f0123456 .*
+.* (12345678|f0debc9a) (9abcdef0|78563412) (23456789|01efcdab) (abcdef01|89674523) .*
+.* (3456789a|12f0debc) (bcdef012|9a785634) (456789ab|2301efcd) (cdef0123|ab896745) .*
+.* (56789abc|3412f0de) (def01234|bc9a7856) (6789abcd|452301ef) (ef012345|cdab8967) .*
+.* (789abcde|563412f0) (f0123456|debc9a78) .*
#source: tls32.s
#as: -a32
-#ld: -shared -melf32ppc
+#ld: -shared
#objdump: -dr
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Disassembly of section \.text:
.* <_start>:
-.*: 38 7f ff e0 addi r3,r31,-32
-.*: 48 00 00 01 bl .*
-.*: 38 7f ff f4 addi r3,r31,-12
-.*: 48 00 00 01 bl .*
-.*: 38 7f ff e8 addi r3,r31,-24
-.*: 48 01 01 95 bl .*<__tls_get_addr@plt>
-.*: 38 7f ff f4 addi r3,r31,-12
-.*: 48 01 01 8d bl .*<__tls_get_addr@plt>
-.*: 39 23 80 20 addi r9,r3,-32736
-.*: 3d 23 00 00 addis r9,r3,0
-.*: 81 49 80 24 lwz r10,-32732\(r9\)
-.*: 81 3f ff f0 lwz r9,-16\(r31\)
-.*: 7d 49 12 2e lhzx r10,r9,r2
-.*: 89 42 00 00 lbz r10,0\(r2\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: 99 49 00 00 stb r10,0\(r9\)
-.*: 38 7e ff d8 addi r3,r30,-40
-.*: 48 00 00 01 bl .*
-.*: 38 7e ff f4 addi r3,r30,-12
-.*: 48 00 00 01 bl .*
-.*: 91 43 80 04 stw r10,-32764\(r3\)
-.*: 3d 23 00 00 addis r9,r3,0
-.*: 91 49 80 08 stw r10,-32760\(r9\)
-.*: 81 3e ff f0 lwz r9,-16\(r30\)
-.*: 7d 49 13 2e sthx r10,r9,r2
-.*: a1 42 00 00 lhz r10,0\(r2\)
-.*: 3d 22 00 00 addis r9,r2,0
-.*: a9 49 00 00 lha r10,0\(r9\)
+.*: (38 7f ff e0|e0 ff 7f 38) addi r3,r31,-32
+.*: (48 00 00 01|01 00 00 48) bl .*
+.*: (38 7f ff f4|f4 ff 7f 38) addi r3,r31,-12
+.*: (48 00 00 01|01 00 00 48) bl .*
+.*: (38 7f ff e8|e8 ff 7f 38) addi r3,r31,-24
+.*: (48 01 01 95|95 01 01 48) bl .*<__tls_get_addr@plt>
+.*: (38 7f ff f4|f4 ff 7f 38) addi r3,r31,-12
+.*: (48 01 01 8d|8d 01 01 48) bl .*<__tls_get_addr@plt>
+.*: (39 23 80 20|20 80 23 39) addi r9,r3,-32736
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (81 49 80 24|24 80 49 81) lwz r10,-32732\(r9\)
+.*: (81 3f ff f0|f0 ff 3f 81) lwz r9,-16\(r31\)
+.*: (7d 49 12 2e|2e 12 49 7d) lhzx r10,r9,r2
+.*: (89 42 00 00|00 00 42 89) lbz r10,0\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (99 49 00 00|00 00 49 99) stb r10,0\(r9\)
+.*: (38 7e ff d8|d8 ff 7e 38) addi r3,r30,-40
+.*: (48 00 00 01|01 00 00 48) bl .*
+.*: (38 7e ff f4|f4 ff 7e 38) addi r3,r30,-12
+.*: (48 00 00 01|01 00 00 48) bl .*
+.*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\)
+.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\)
+.*: (81 3e ff f0|f0 ff 3e 81) lwz r9,-16\(r30\)
+.*: (7d 49 13 2e|2e 13 49 7d) sthx r10,r9,r2
+.*: (a1 42 00 00|00 00 42 a1) lhz r10,0\(r2\)
+.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
+.*: (a9 49 00 00|00 00 49 a9) lha r10,0\(r9\)
Disassembly of section \.got:
.* <_GLOBAL_OFFSET_TABLE_-0x28>:
#...
-.*: 4e 80 00 21 blrl
+.*: (4e 80 00 21|21 00 80 4e) blrl
.* <_GLOBAL_OFFSET_TABLE_>:
-.*: 00 01 03 ec .*
+.*: (00 01 03 ec|ec 03 01 00) .*
#pass
#source: tls32.s
#as: -a32
-#ld: -shared -melf32ppc
+#ld: -shared
#objdump: -sj.got
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.got:
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
-.* 00000000 4e800021 000103ec 00000000 .*
+.* 00000000 (4e800021|2100804e) (000103ec|ec030100) 00000000 .*
.* 00000000 .*
#source: tls32.s
#as: -a32
-#ld: -shared -melf32ppc
+#ld: -shared
#readelf: -WSsrl
#target: powerpc*-*-*
#source: tls32.s
#as: -a32
-#ld: -shared -melf32ppc
+#ld: -shared
#objdump: -sj.tdata
#target: powerpc*-*-*
-.*: +file format elf32-powerpc
+.*
Contents of section \.tdata:
-.* 12345678 23456789 3456789a 456789ab .*
-.* 56789abc 6789abcd 789abcde .*
+.* (12345678|78563412) (23456789|89674523) (3456789a|9a785634) (456789ab|ab896745) .*
+.* (56789abc|bc9a7856) (6789abcd|cdab8967) (789abcde|debc9a78) .*
#source: tlslib.s
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -dr
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Disassembly of section \.text:
.* <\.__tls_get_addr>:
-.* 4e 80 00 20 blr
+.* (4e 80 00 20|20 00 80 4e) blr
.* <_start>:
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 90 40 addi r3,r3,-28608
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 90 48 addi r3,r3,-28600
-.* 3c 6d 00 00 addis r3,r13,0
-.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 50 addi r9,r3,-32688
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 58 lwz r10,-32680\(r9\)
-.* e9 22 80 40 ld r9,-32704\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 68 lhz r10,-28568\(r9\)
-.* 89 4d 90 70 lbz r10,-28560\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 78 stb r10,-28552\(r9\)
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 90 40|40 90 63 38) addi r3,r3,-28608
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 90 48|48 90 63 38) addi r3,r3,-28600
+.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
+.* (39 23 80 50|50 80 23 39) addi r9,r3,-32688
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (81 49 80 58|58 80 49 81) lwz r10,-32680\(r9\)
+.* (e9 22 80 40|40 80 22 e9) ld r9,-32704\(r2\)
+.* (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (a1 49 90 68|68 90 49 a1) lhz r10,-28568\(r9\)
+.* (89 4d 90 70|70 90 4d 89) lbz r10,-28560\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (99 49 90 78|78 90 49 99) stb r10,-28552\(r9\)
#source: tlslib.s
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -sj.got
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.got:
- 100101a0 00000000 00000001 00000000 00000000 .*
- 100101b0 00000000 00000001 00000000 00000000 .*
- 100101c0 00000000 00000001 00000000 00000000 .*
- 100101d0 00000000 00000001 00000000 00000000 .*
- 100101e0 ffffffff ffff8060 00000000 00000000 .*
+ 100101a0 (00000000|01000000) (00000001|00000000) 00000000 00000000 .*
+ 100101b0 (00000000|01000000) (00000001|00000000) 00000000 00000000 .*
+ 100101c0 (00000000|01000000) (00000001|00000000) 00000000 00000000 .*
+ 100101d0 (00000000|01000000) (00000001|00000000) 00000000 00000000 .*
+ 100101e0 (ffffffff|6080ffff) (ffff8060|ffffffff) 00000000 00000000 .*
#source: tlslib.s
#source: tlstoc.s
#as: -a64
-#ld: -melf64ppc
+#ld:
#objdump: -sj.tdata
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.tdata:
- 10010148 00c0ffee 00000000 12345678 9abcdef0 .*
- 10010158 23456789 abcdef01 3456789a bcdef012 .*
- 10010168 456789ab cdef0123 56789abc def01234 .*
- 10010178 6789abcd ef012345 789abcde f0123456 .*
+ 10010148 (00c0ffee|eeffc000) 00000000 (12345678|78563412) (9abcdef0|f0debc9a) .*
+ 10010158 (23456789|89674523) (abcdef01|01efcdab) (3456789a|9a785634) (bcdef012|12f0debc) .*
+ 10010168 (456789ab|ab896745) (cdef0123|2301efcd) (56789abc|bc9a7856) (def01234|3412f0de) .*
+ 10010178 (6789abcd|cdab8967) (ef012345|452301ef) (789abcde|debc9a78) (f0123456|563412f0) .*
#source: tlstoc.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -dr
#target: powerpc64*-*-*
Disassembly of section \.text:
.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 62 80 70 ld r11,-32656\(r2\)
-.* 7d 69 03 a6 mtctr r11
-.* e8 42 80 78 ld r2,-32648\(r2\)
-.* 4e 80 04 20 bctr
+.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
+.* (e9 62 80 70|70 80 62 e9) ld r11,-32656\(r2\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e8 42 80 78|78 80 42 e8) ld r2,-32648\(r2\)
+.* (28 22 00 00|00 00 22 28) cmpldi r2,0
+.* (4c e2 04 20|20 04 e2 4c) bnectr\+
+.* (48 00 00 ..|.. 00 00 48) b .* <__glink_PLTresolve\+0x38>
.* <_start>:
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff e9 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff dd bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 28 addi r3,r2,-32728
-.* 4b ff ff d1 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 38 addi r3,r2,-32712
-.* 4b ff ff c5 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* e9 22 80 50 ld r9,-32688\(r2\)
-.* 7d 49 6a 2e lhzx r10,r9,r13
-.* 89 4d 00 00 lbz r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 00 00 stb r10,0\(r9\)
-.* 60 00 00 00 nop
-.* 00 00 00 00 .*
-.* 00 01 02 18 .*
+.* (38 62 80 08|08 80 62 38) addi r3,r2,-32760
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 18|18 80 62 38) addi r3,r2,-32744
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 28|28 80 62 38) addi r3,r2,-32728
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (38 62 80 38|38 80 62 38) addi r3,r2,-32712
+.* (4b ff ff ..|.. ff ff 4b) bl .*plt_call.__tls_get_addr.*
+.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
+.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
+.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
+.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
+.* (e9 22 80 48|48 80 22 e9) ld r9,-32696\(r2\)
+.* (7d 49 18 2a|2a 18 49 7d) ldx r10,r9,r3
+.* (e9 22 80 50|50 80 22 e9) ld r9,-32688\(r2\)
+.* (7d 49 6a 2e|2e 6a 49 7d) lhzx r10,r9,r13
+.* (89 4d 00 00|00 00 4d 89) lbz r10,0\(r13\)
+.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
+.* (99 49 00 00|00 00 49 99) stb r10,0\(r9\)
+.* (60 00 00 00|00 00 00 60) nop
+.* (00 00 00 00|18 02 01 00) .*
+.* (00 01 02 18|00 00 00 00) .*
.* <__glink_PLTresolve>:
-.* 7d 88 02 a6 mflr r12
-.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
-.* 7d 68 02 a6 mflr r11
-.* e8 4b ff f0 ld r2,-16\(r11\)
-.* 7d 88 03 a6 mtlr r12
-.* 7d 82 5a 14 add r12,r2,r11
-.* e9 6c 00 00 ld r11,0\(r12\)
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
-.* 4e 80 04 20 bctr
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 60 00 00 00 nop
-.* 38 00 00 00 li r0,0
-.* 4b ff ff c4 b .*
+.* (7d 88 02 a6|a6 02 88 7d) mflr r12
+.* (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.*
+.* (7d 68 02 a6|a6 02 68 7d) mflr r11
+.* (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
+.* (7d 88 03 a6|a6 03 88 7d) mtlr r12
+.* (7d 82 5a 14|14 5a 82 7d) add r12,r2,r11
+.* (e9 6c 00 00|00 00 6c e9) ld r11,0\(r12\)
+.* (e8 4c 00 08|08 00 4c e8) ld r2,8\(r12\)
+.* (7d 69 03 a6|a6 03 69 7d) mtctr r11
+.* (e9 6c 00 10|10 00 6c e9) ld r11,16\(r12\)
+.* (4e 80 04 20|20 04 80 4e) bctr
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (60 00 00 00|00 00 00 60) nop
+.* (38 00 00 00|00 00 00 38) li r0,0
+.* (4b ff ff c4|c4 ff ff 4b) b .*
#source: tlstoc.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -sj.got
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.got:
-.* 00000000 000186c0 00000000 00000000 .*
+ 106c8 00000000 (000186c8|c8860100) 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
#source: tlstoc.s
#as: -a64
-#ld: -shared -melf64ppc
+#ld: -shared
#objdump: -sj.tdata
#target: powerpc64*-*-*
-.*: +file format elf64-powerpc
+.*
Contents of section \.tdata:
-.* 12345678 9abcdef0 23456789 abcdef01 .*
-.* 3456789a bcdef012 456789ab cdef0123 .*
-.* 56789abc def01234 6789abcd ef012345 .*
-.* 789abcde f0123456 .*
+.* (12345678|78563412) (9abcdef0|f0debc9a) (23456789|89674523) (abcdef01|01efcdab) .*
+.* (3456789a|9a785634) (bcdef012|12f0debc) (456789ab|ab896745) (cdef0123|2301efcd) .*
+.* (56789abc|bc9a7856) (def01234|3412f0de) (6789abcd|cdab8967) (ef012345|452301ef) .*
+.* (789abcde|debc9a78) (f0123456|563412f0) .*
.*
-\(\.text\+0x14\): .* 0x3fa00000 .*
+\(\.text\+0x14\): .*
.*
-\(\.text\+0x34\): .* 0x3fa00010 .*
+\(\.text\+0x34\): .*
+2013-01-22 Alan Modra <amodra@gmail.com>
+
+ Apply mainline patches
+ 2012-12-13 Alan Modra <amodra@gmail.com>
+ PR binutils/14950
+ * ppc-opc.c (insert_sci8, extract_sci8): Rewrite.
+ (insert_sci8n, extract_sci8n): Likewise.
+
+ 2012-11-23 Alan Modra <amodra@gmail.com>
+ * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
+ set from ppc_opts.sticky in it. Delete "retain_mask".
+ (powerpc_init_dialect): Choose default dialect from info->mach
+ before parsing -M options. Handle more bfd_mach_ppc variants.
+ Update common default to power7.
+
+ 2012-10-26 Alan Modra <amodra@gmail.com>
+ * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
+
+ 2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
+ * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
+
+ 2012-10-05 Peter Bergner <bergner@vnet.ibm.com>
+ * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
+ * ppc-opc.c (VBA): New define.
+ (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
+ mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
+
2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
| PPC_OPCODE_A2),
0 },
{ "altivec", (PPC_OPCODE_PPC),
- PPC_OPCODE_ALTIVEC },
+ PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
{ "any", 0,
PPC_OPCODE_ANY },
{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
/* Handle -m and -M options that set cpu type, and .machine arg. */
ppc_cpu_t
-ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
+ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
{
- const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
- | PPC_OPCODE_SPE | PPC_OPCODE_ANY
- | PPC_OPCODE_VLE | PPC_OPCODE_PMR);
- /* Sticky bits. */
- ppc_cpu_t retain_flags = ppc_cpu & retain_mask;
unsigned int i;
for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
{
if (ppc_opts[i].sticky)
{
- retain_flags |= ppc_opts[i].sticky;
- if ((ppc_cpu & ~retain_mask) != 0)
+ *sticky |= ppc_opts[i].sticky;
+ if ((ppc_cpu & ~*sticky) != 0)
break;
}
ppc_cpu = ppc_opts[i].cpu;
if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
return 0;
- ppc_cpu |= retain_flags;
+ ppc_cpu |= *sticky;
return ppc_cpu;
}
powerpc_init_dialect (struct disassemble_info *info)
{
ppc_cpu_t dialect = 0;
+ ppc_cpu_t sticky = 0;
char *arg;
struct dis_private *priv = calloc (sizeof (*priv), 1);
if (priv == NULL)
priv = &private;
+ switch (info->mach)
+ {
+ case bfd_mach_ppc_403:
+ case bfd_mach_ppc_403gc:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403);
+ break;
+ case bfd_mach_ppc_405:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405);
+ break;
+ case bfd_mach_ppc_601:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601);
+ break;
+ case bfd_mach_ppc_a35:
+ case bfd_mach_ppc_rs64ii:
+ case bfd_mach_ppc_rs64iii:
+ dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64);
+ break;
+ case bfd_mach_ppc_e500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
+ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500);
+ break;
+ case bfd_mach_ppc_e500mc:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC);
+ break;
+ case bfd_mach_ppc_e500mc64:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
+ | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_e5500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_e6500:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
+ | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
+ break;
+ case bfd_mach_ppc_titan:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
+ | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN);
+ break;
+ case bfd_mach_ppc_vle:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
+ break;
+ default:
+ dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
+ | PPC_OPCODE_ANY);
+ }
+
arg = info->disassembler_options;
while (arg != NULL)
{
if (end != NULL)
*end = 0;
- if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
+ if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
dialect = new_cpu;
else if (strcmp (arg, "32") == 0)
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
arg = end;
}
- if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
- {
- if (info->mach == bfd_mach_ppc64)
- dialect |= PPC_OPCODE_64;
- else
- dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
- if (info->mach == bfd_mach_ppc_vle)
- dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
- else
- /* Choose a reasonable default. */
- dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
- | PPC_OPCODE_ALTIVEC);
- }
-
info->private_data = priv;
POWERPC_DIALECT(info) = dialect;
}
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
#define BBA BB + 1
+ /* The VB field in a VX form instruction when it must be the same
+ as the VA field in the same instruction. */
+#define VBA BBA
{ 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
/* The BD field in a B form instruction. The lower two bits are
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg)
{
- int fill = 0;
- int scale_factor = 0;
- long ui8 = value;
+ unsigned int fill_scale = 0;
+ unsigned long ui8 = value;
- if ((value & 0xff000000) == (unsigned int) value)
- {
- scale_factor = 3;
- ui8 = value >> 24;
- fill = 0;
- }
- else if ((value & 0xff0000) == (unsigned int) value)
+ if ((ui8 & 0xffffff00) == 0)
+ ;
+ else if ((ui8 & 0xffffff00) == 0xffffff00)
+ fill_scale = 0x400;
+ else if ((ui8 & 0xffff00ff) == 0)
{
- scale_factor = 2;
- ui8 = value >> 16;
- fill = 0;
+ fill_scale = 1 << 8;
+ ui8 >>= 8;
}
- else if ((value & 0xff00) == (unsigned int) value)
+ else if ((ui8 & 0xffff00ff) == 0xffff00ff)
{
- scale_factor = 1;
- ui8 = value >> 8;
- fill = 0;
+ fill_scale = 0x400 | (1 << 8);
+ ui8 >>= 8;
}
- else if ((value & 0xff) == value)
+ else if ((ui8 & 0xff00ffff) == 0)
{
- scale_factor = 0;
- ui8 = value;
- fill = 0;
+ fill_scale = 2 << 8;
+ ui8 >>= 16;
}
- else if ((value & 0xffffff00) == 0xffffff00)
+ else if ((ui8 & 0xff00ffff) == 0xff00ffff)
{
- scale_factor = 0;
- ui8 = (value & 0xff);
- fill = 1;
+ fill_scale = 0x400 | (2 << 8);
+ ui8 >>= 16;
}
- else if ((value & 0xffff00ff) == 0xffff00ff)
+ else if ((ui8 & 0x00ffffff) == 0)
{
- scale_factor = 1;
- ui8 = (value & 0xff00) >> 8;
- fill = 1;
+ fill_scale = 3 << 8;
+ ui8 >>= 24;
}
- else if ((value & 0xff00ffff) == 0xff00ffff)
+ else if ((ui8 & 0x00ffffff) == 0x00ffffff)
{
- scale_factor = 2;
- ui8 = (value & 0xff0000) >> 16;
- fill = 1;
+ fill_scale = 0x400 | (3 << 8);
+ ui8 >>= 24;
}
- else if ((value & 0x00ffffff) == 0x00ffffff)
+ else
{
- scale_factor = 3;
- ui8 = (value & 0xff000000) >> 24;
- fill = 1;
+ *errmsg = _("illegal immediate value");
+ ui8 = 0;
}
- else
- *errmsg = _("illegal immediate value");
- return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff);
+ return insn | fill_scale | (ui8 & 0xff);
}
static long
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid ATTRIBUTE_UNUSED)
{
- int scale_factor, fill;
- scale_factor = (insn & 0x300) >> 8;
- fill = (insn & 0x00000400) >> 10;
-
- if (fill == 0)
- return (insn & 0xff) << (scale_factor << 3);
-
- /* Fill is one. */
- if (scale_factor == 0)
- return (insn & 0xff) | 0xffffff00;
- else if (scale_factor == 1)
- return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3));
- else if (scale_factor == 2)
- return 0xff00ffff | (insn & 0xff << (scale_factor << 3));
- else /* scale_factor 3 */
- return 0x00ffffff | (insn & 0xff << (scale_factor << 3));
+ int fill = insn & 0x400;
+ int scale_factor = (insn & 0x300) >> 5;
+ long value = (insn & 0xff) << scale_factor;
+
+ if (fill != 0)
+ value |= ~((long) 0xff << scale_factor);
+ return value;
}
static unsigned long
insert_sci8n (unsigned long insn,
long value,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect,
const char **errmsg)
{
- insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg);
- /* Set the F bit. */
- return insn | 0x400;
+ return insert_sci8 (insn, -value, dialect, errmsg);
}
static long
extract_sci8n (unsigned long insn,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
+ ppc_cpu_t dialect,
+ int *invalid)
{
- int scale_factor;
- scale_factor = (insn & 0x300) >> 8;
- return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3);
+ return -extract_sci8 (insn, dialect, invalid);
}
static unsigned long
{"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
{"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
{"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vnot", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
{"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}},
{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}},
{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}},
+{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, PPCNONE, {RT}},
+{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, PPCNONE, {RT}},
{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}},
{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}},
{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}},
{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}},
{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}},
{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}},
+{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, PPCNONE, {RS}},
+{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, PPCNONE, {RS}},
{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
-{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, D, RA0}},
+{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}},
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, D, RA0}},
+{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}},
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
projects / thirdparty / binutils-gdb.git / commitdiff
