--- /dev/null
+From 7c97bc0128b2eecc703106112679a69d446d1a12 Mon Sep 17 00:00:00 2001
+From: Doug Berger <opendmb@gmail.com>
+Date: Wed, 22 Jun 2022 20:02:04 -0700
+Subject: net: dsa: bcm_sf2: force pause link settings
+
+From: Doug Berger <opendmb@gmail.com>
+
+commit 7c97bc0128b2eecc703106112679a69d446d1a12 upstream.
+
+The pause settings reported by the PHY should also be applied to the GMII port
+status override otherwise the switch will not generate pause frames towards the
+link partner despite the advertisement saying otherwise.
+
+Fixes: 246d7f773c13 ("net: dsa: add Broadcom SF2 switch driver")
+Signed-off-by: Doug Berger <opendmb@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20220623030204.1966851-1-f.fainelli@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/dsa/bcm_sf2.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -600,7 +600,9 @@ static void bcm_sf2_sw_adjust_link(struc
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ struct ethtool_eee *p = &priv->port_sts[port].eee;
+ u32 id_mode_dis = 0, port_mode;
++ u16 lcl_adv = 0, rmt_adv = 0;
+ const char *str = NULL;
++ u8 flowctrl = 0;
+ u32 reg;
+
+ switch (phydev->interface) {
+@@ -667,10 +669,27 @@ force_link:
+ break;
+ }
+
++ if (phydev->duplex == DUPLEX_FULL &&
++ phydev->autoneg == AUTONEG_ENABLE) {
++ if (phydev->pause)
++ rmt_adv = LPA_PAUSE_CAP;
++ if (phydev->asym_pause)
++ rmt_adv |= LPA_PAUSE_ASYM;
++ if (phydev->advertising & ADVERTISED_Pause)
++ lcl_adv = ADVERTISE_PAUSE_CAP;
++ if (phydev->advertising & ADVERTISED_Asym_Pause)
++ lcl_adv |= ADVERTISE_PAUSE_ASYM;
++ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
++ }
++
+ if (phydev->link)
+ reg |= LINK_STS;
+ if (phydev->duplex == DUPLEX_FULL)
+ reg |= DUPLX_MODE;
++ if (flowctrl & FLOW_CTRL_TX)
++ reg |= TXFLOW_CNTL;
++ if (flowctrl & FLOW_CTRL_RX)
++ reg |= RXFLOW_CNTL;
+
+ core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
+