]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/panelreplay: Panel Replay capability DPCD register definitions
authorJouni Högander <jouni.hogander@intel.com>
Mon, 26 May 2025 12:05:01 +0000 (15:05 +0300)
committerJouni Högander <jouni.hogander@intel.com>
Thu, 29 May 2025 05:13:38 +0000 (08:13 +0300)
Add new definition for size of Panel Replay DPCD capability registers
area. Rename existing definitions to group capability registers together.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-2-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
include/drm/display/drm_dp.h

index cd833b63ea6b759ed365cbe315030348946720c8..0cfdeff268f97fbb5f08e9ec6ed18e7443df50e9 100644 (file)
@@ -516,7 +516,7 @@ static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.sink_panel_replay_su_support)
                drm_dp_dpcd_readb(&intel_dp->aux,
-                                 DP_PANEL_PANEL_REPLAY_CAPABILITY,
+                                 DP_PANEL_REPLAY_CAP_CAPABILITY,
                                  &su_capability);
        else
                su_capability = intel_dp->psr_dpcd[1];
@@ -528,7 +528,7 @@ static unsigned int
 intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
 {
        return intel_dp->psr.sink_panel_replay_su_support ?
-               DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
+               DP_PANEL_REPLAY_CAP_X_GRANULARITY :
                DP_PSR2_SU_X_GRANULARITY;
 }
 
@@ -536,7 +536,7 @@ static unsigned int
 intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
 {
        return intel_dp->psr.sink_panel_replay_su_support ?
-               DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
+               DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
                DP_PSR2_SU_Y_GRANULARITY;
 }
 
@@ -676,7 +676,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 {
        drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
                         sizeof(intel_dp->psr_dpcd));
-       drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
+       drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
                          &intel_dp->pr_dpcd);
 
        if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
index 3001c0b6e7bb355970ee8b77655f9aa03cbf1e98..3371e2edd9e9ea5b24914c41fdeca0c444d93ed6 100644 (file)
 /* DFP Capability Extension */
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT    0x0a3   /* 2.0 */
 
-#define DP_PANEL_REPLAY_CAP                            0x0b0  /* DP 2.0 */
+#define DP_PANEL_REPLAY_CAP_SUPPORT                    0x0b0  /* DP 2.0 */
 # define DP_PANEL_REPLAY_SUPPORT                       (1 << 0)
 # define DP_PANEL_REPLAY_SU_SUPPORT                    (1 << 1)
 # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT       (1 << 2) /* eDP 1.5 */
 
-#define DP_PANEL_PANEL_REPLAY_CAPABILITY               0xb1
-# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5)
+#define DP_PANEL_REPLAY_CAP_SIZE       7
 
-#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY            0xb2
-#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY            0xb4
+#define DP_PANEL_REPLAY_CAP_CAPABILITY                 0xb1
+# define DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED       (1 << 5)
+
+#define DP_PANEL_REPLAY_CAP_X_GRANULARITY              0xb2
+#define DP_PANEL_REPLAY_CAP_Y_GRANULARITY              0xb4
 
 /* Link Configuration */
 #define        DP_LINK_BW_SET                      0x100