arm64: dts: qcom: sm8350: Add CPU topology and idle-states

Add CPU topology and define the idle states for the silver and gold
cores as well as the cluster.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210825221600.1498939-1-bjorn.andersson@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 28669e0f93e9f0ee701a0ef3021af816f7cf7ad0..d134280e29390f3d6d163618bd13d8ba6a6286f7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -47,6 +47,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
+                       power-domains = <&CPU_PD0>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                              compatible = "cache";
@@ -64,6 +66,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
+                       power-domains = <&CPU_PD1>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                              compatible = "cache";
@@ -78,6 +82,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
+                       power-domains = <&CPU_PD2>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                              compatible = "cache";
@@ -92,6 +98,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
+                       power-domains = <&CPU_PD3>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                              compatible = "cache";
@@ -106,6 +114,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
+                       power-domains = <&CPU_PD4>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                              compatible = "cache";
@@ -120,6 +130,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
+                       power-domains = <&CPU_PD5>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                              compatible = "cache";
@@ -135,6 +147,8 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
+                       power-domains = <&CPU_PD6>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                              compatible = "cache";
@@ -149,12 +163,86 @@
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
                        qcom,freq-domain = <&cpufreq_hw 2>;
+                       power-domains = <&CPU_PD7>;
+                       power-domain-names = "psci";
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
                        };
                };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&CPU0>;
+                               };
+
+                               core1 {
+                                       cpu = <&CPU1>;
+                               };
+
+                               core2 {
+                                       cpu = <&CPU2>;
+                               };
+
+                               core3 {
+                                       cpu = <&CPU3>;
+                               };
+
+                               core4 {
+                                       cpu = <&CPU4>;
+                               };
+
+                               core5 {
+                                       cpu = <&CPU5>;
+                               };
+
+                               core6 {
+                                       cpu = <&CPU6>;
+                               };
+
+                               core7 {
+                                       cpu = <&CPU7>;
+                               };
+                       };
+               };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+                               compatible = "arm,idle-state";
+                               idle-state-name = "silver-rail-power-collapse";
+                               arm,psci-suspend-param = <0x40000004>;
+                               entry-latency-us = <355>;
+                               exit-latency-us = <909>;
+                               min-residency-us = <3934>;
+                               local-timer-stop;
+                       };
+
+                       BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+                               compatible = "arm,idle-state";
+                               idle-state-name = "gold-rail-power-collapse";
+                               arm,psci-suspend-param = <0x40000004>;
+                               entry-latency-us = <241>;
+                               exit-latency-us = <1461>;
+                               min-residency-us = <4488>;
+                               local-timer-stop;
+                       };
+               };
+
+               domain-idle-states {
+                       CLUSTER_SLEEP_0: cluster-sleep-0 {
+                               compatible = "domain-idle-state";
+                               idle-state-name = "cluster-power-collapse";
+                               arm,psci-suspend-param = <0x4100c344>;
+                               entry-latency-us = <3263>;
+                               exit-latency-us = <6562>;
+                               min-residency-us = <9987>;
+                               local-timer-stop;
+                       };
+               };
        };
 
        firmware {
@@ -178,6 +266,59 @@
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
+
+               CPU_PD0: cpu0 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+               };
+
+               CPU_PD1: cpu1 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+               };
+
+               CPU_PD2: cpu2 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+               };
+
+               CPU_PD3: cpu3 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+               };
+
+               CPU_PD4: cpu4 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+               };
+
+               CPU_PD5: cpu5 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+               };
+
+               CPU_PD6: cpu6 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+               };
+
+               CPU_PD7: cpu7 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+               };
+
+               CLUSTER_PD: cpu-cluster0 {
+                       #power-domain-cells = <0>;
+                       domain-idle-states = <&CLUSTER_SLEEP_0>;
+               };
        };
 
        reserved_memory: reserved-memory {