clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5

Add asynchronous core clocks and module clocks for SCI channels 1
through 5 on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812171720.3245851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 704d14d31e871463b14cf1b3a7a61b96180a72c9..1fdd764f9b91331f88c03ad1187d15f21dc4cdf7 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -46,8 +46,13 @@
 #define DIVCA55C2      CONF_PACK(SCKCR2, 10, 1)
 #define DIVCA55C3      CONF_PACK(SCKCR2, 11, 1)
 #define DIVCA55S       CONF_PACK(SCKCR2, 12, 1)
+#define DIVSCI5ASYNC   CONF_PACK(SCKCR2, 18, 2)
 
 #define DIVSCI0ASYNC   CONF_PACK(SCKCR3, 6, 2)
+#define DIVSCI1ASYNC   CONF_PACK(SCKCR3, 8, 2)
+#define DIVSCI2ASYNC   CONF_PACK(SCKCR3, 10, 2)
+#define DIVSCI3ASYNC   CONF_PACK(SCKCR3, 12, 2)
+#define DIVSCI4ASYNC   CONF_PACK(SCKCR3, 14, 2)
 
 #define SEL_PLL                CONF_PACK(SCKCR, 22, 1)
 
@@ -84,6 +89,11 @@ enum clk_ids {
        CLK_SEL_CLK_PLL4,
        CLK_PLL4D1,
        CLK_SCI0ASYNC,
+       CLK_SCI1ASYNC,
+       CLK_SCI2ASYNC,
+       CLK_SCI3ASYNC,
+       CLK_SCI4ASYNC,
+       CLK_SCI5ASYNC,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -133,6 +143,16 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
        DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
        DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
                dtable_24_25_30_32),
+       DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
+               dtable_24_25_30_32),
+       DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
+               dtable_24_25_30_32),
+       DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
+               dtable_24_25_30_32),
+       DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
+               dtable_24_25_30_32),
+       DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
+               dtable_24_25_30_32),
 
        /* Core output clk */
        DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
@@ -155,9 +175,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
 
 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
        DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
+       DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC),
+       DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC),
+       DEF_MOD("sci3fck", 11, CLK_SCI3ASYNC),
+       DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
        DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
        DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
        DEF_MOD("usb", 408, R9A09G077_CLK_PCLKAM),
+       DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
        DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
        DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
        DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),