drm/amd/display: Update dc_tiling_info union to structure

[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is currently in use.

[HOW]
Updated the `dc_tiling_info` union to include a new field that
explicitly indicates the currently used GFX format.
This allows the system to determine the active GFX format
and take the correct programming path accordingly.

[Description]
The union `dc_tiling_info` has been updated to support multiple
GFX formats by adding a new field for identifying the active format.
This update ensures that the correct programming path is followed
based on the selected format. All references to `dc_tiling_info`
in the codebase have been updated to reflect the new structure.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 1ec4e4b9ea94551c2be45fca65068206ec6e094a..db8c55cc865e51b88751de246ce5dff9cd7762be 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -177,7 +177,7 @@ static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier
        return AMD_FMT_MOD_GET(TILE, modifier);
 }
 
-static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
+static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,
                                                             uint64_t tiling_flags)
 {
        /* Fill GFX8 params */
@@ -210,7 +210,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_inf
 }
 
 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
-                                                             union dc_tiling_info *tiling_info)
+                                                             struct dc_tiling_info *tiling_info)
 {
        /* Fill GFX9 params */
        tiling_info->gfx9.num_pipes =
@@ -231,7 +231,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgp
 }
 
 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
-                                                               union dc_tiling_info *tiling_info,
+                                                               struct dc_tiling_info *tiling_info,
                                                                uint64_t modifier)
 {
        unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
@@ -261,7 +261,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amd
 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
                                        const enum surface_pixel_format format,
                                        const enum dc_rotation_angle rotation,
-                                       const union dc_tiling_info *tiling_info,
+                                       const struct dc_tiling_info *tiling_info,
                                        const struct dc_plane_dcc_param *dcc,
                                        const struct dc_plane_address *address,
                                        const struct plane_size *plane_size)
@@ -308,7 +308,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg
                                                                     const enum surface_pixel_format format,
                                                                     const enum dc_rotation_angle rotation,
                                                                     const struct plane_size *plane_size,
-                                                                    union dc_tiling_info *tiling_info,
+                                                                    struct dc_tiling_info *tiling_info,
                                                                     struct dc_plane_dcc_param *dcc,
                                                                     struct dc_plane_address *address)
 {
@@ -358,7 +358,7 @@ static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amd
                                                                      const enum surface_pixel_format format,
                                                                      const enum dc_rotation_angle rotation,
                                                                      const struct plane_size *plane_size,
-                                                                     union dc_tiling_info *tiling_info,
+                                                                     struct dc_tiling_info *tiling_info,
                                                                      struct dc_plane_dcc_param *dcc,
                                                                      struct dc_plane_address *address)
 {
@@ -834,7 +834,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
                             const enum surface_pixel_format format,
                             const enum dc_rotation_angle rotation,
                             const uint64_t tiling_flags,
-                            union dc_tiling_info *tiling_info,
+                            struct dc_tiling_info *tiling_info,
                             struct plane_size *plane_size,
                             struct dc_plane_dcc_param *dcc,
                             struct dc_plane_address *address,

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
index 2eef13b1c05a4b80d1b85cf9038c47977ec5f542..615d2ab2b8034643476f81f576ca4aae976aec17 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
@@ -47,7 +47,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
                                 const enum surface_pixel_format format,
                                 const enum dc_rotation_angle rotation,
                                 const uint64_t tiling_flags,
-                                union dc_tiling_info *tiling_info,
+                                struct dc_tiling_info *tiling_info,
                                 struct plane_size *plane_size,
                                 struct dc_plane_dcc_param *dcc,
                                 struct dc_plane_address *address,

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f99f84406374353e4d8cc4f708703040761b734f..08d35d9da4431875d94fb82ee0567764bd15ef46 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2555,7 +2555,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc,
 
 
        if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
-                       sizeof(union dc_tiling_info)) != 0) {
+                       sizeof(struct dc_tiling_info)) != 0) {
                update_flags->bits.swizzle_change = 1;
                elevate_update_type(&update_type, UPDATE_TYPE_MED);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9db51b359de03fe05d570144c1cc01012b93a42d..2e4200d5145f7c23cbd3630c4c379df44443dbfb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1306,7 +1306,7 @@ struct dc_plane_state {
        struct rect clip_rect;
 
        struct plane_size plane_size;
-       union dc_tiling_info tiling_info;
+       struct dc_tiling_info tiling_info;
 
        struct dc_plane_dcc_param dcc;
 
@@ -1377,7 +1377,7 @@ struct dc_plane_state {
 
 struct dc_plane_info {
        struct plane_size plane_size;
-       union dc_tiling_info tiling_info;
+       struct dc_tiling_info tiling_info;
        struct dc_plane_dcc_param dcc;
        enum surface_pixel_format format;
        enum dc_rotation_angle rotation;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 8a6e3dfa42305c8b1eb9aa52a8bc0d58fd4d2882..5ac55601a6da1798ff83c7949403e727a5d1a74c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -341,89 +341,101 @@ enum swizzle_mode_addr3_values {
        DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX
 };
 
-union dc_tiling_info {
-
-       struct {
-               /* Specifies the number of memory banks for tiling
-                *      purposes.
-                * Only applies to 2D and 3D tiling modes.
-                *      POSSIBLE VALUES: 2,4,8,16
-                */
-               unsigned int num_banks;
-               /* Specifies the number of tiles in the x direction
-                *      to be incorporated into the same bank.
-                * Only applies to 2D and 3D tiling modes.
-                *      POSSIBLE VALUES: 1,2,4,8
-                */
-               unsigned int bank_width;
-               unsigned int bank_width_c;
-               /* Specifies the number of tiles in the y direction to
-                *      be incorporated into the same bank.
-                * Only applies to 2D and 3D tiling modes.
-                *      POSSIBLE VALUES: 1,2,4,8
-                */
-               unsigned int bank_height;
-               unsigned int bank_height_c;
-               /* Specifies the macro tile aspect ratio. Only applies
-                * to 2D and 3D tiling modes.
-                */
-               unsigned int tile_aspect;
-               unsigned int tile_aspect_c;
-               /* Specifies the number of bytes that will be stored
-                *      contiguously for each tile.
-                * If the tile data requires more storage than this
-                *      amount, it is split into multiple slices.
-                * This field must not be larger than
-                *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-                * Only applies to 2D and 3D tiling modes.
-                * For color render targets, TILE_SPLIT >= 256B.
-                */
-               enum tile_split_values tile_split;
-               enum tile_split_values tile_split_c;
-               /* Specifies the addressing within a tile.
-                *      0x0 - DISPLAY_MICRO_TILING
-                *      0x1 - THIN_MICRO_TILING
-                *      0x2 - DEPTH_MICRO_TILING
-                *      0x3 - ROTATED_MICRO_TILING
-                */
-               enum tile_mode_values tile_mode;
-               enum tile_mode_values tile_mode_c;
-               /* Specifies the number of pipes and how they are
-                *      interleaved in the surface.
-                * Refer to memory addressing document for complete
-                *      details and constraints.
-                */
-               unsigned int pipe_config;
-               /* Specifies the tiling mode of the surface.
-                * THIN tiles use an 8x8x1 tile size.
-                * THICK tiles use an 8x8x4 tile size.
-                * 2D tiling modes rotate banks for successive Z slices
-                * 3D tiling modes rotate pipes and banks for Z slices
-                * Refer to memory addressing document for complete
-                *      details and constraints.
-                */
-               enum array_mode_values array_mode;
-       } gfx8;
+enum dc_gfxversion {
+       DcGfxVersion7 = 0,
+       DcGfxVersion8,
+       DcGfxVersion9,
+       DcGfxVersion10,
+       DcGfxVersion11,
+       DcGfxAddr3,
+       DcGfxVersionUnknown
+};
+
+ struct dc_tiling_info {
+       unsigned int gfxversion;     // Specifies which part of the union to use. Must use DalGfxVersion enum
+       union {
+               struct {
+                       /* Specifies the number of memory banks for tiling
+                        *      purposes.
+                        * Only applies to 2D and 3D tiling modes.
+                        *      POSSIBLE VALUES: 2,4,8,16
+                        */
+                       unsigned int num_banks;
+                       /* Specifies the number of tiles in the x direction
+                        *      to be incorporated into the same bank.
+                        * Only applies to 2D and 3D tiling modes.
+                        *      POSSIBLE VALUES: 1,2,4,8
+                        */
+                       unsigned int bank_width;
+                       unsigned int bank_width_c;
+                       /* Specifies the number of tiles in the y direction to
+                        *      be incorporated into the same bank.
+                        * Only applies to 2D and 3D tiling modes.
+                        *      POSSIBLE VALUES: 1,2,4,8
+                        */
+                       unsigned int bank_height;
+                       unsigned int bank_height_c;
+                       /* Specifies the macro tile aspect ratio. Only applies
+                        * to 2D and 3D tiling modes.
+                        */
+                       unsigned int tile_aspect;
+                       unsigned int tile_aspect_c;
+                       /* Specifies the number of bytes that will be stored
+                        *      contiguously for each tile.
+                        * If the tile data requires more storage than this
+                        *      amount, it is split into multiple slices.
+                        * This field must not be larger than
+                        *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
+                        * Only applies to 2D and 3D tiling modes.
+                        * For color render targets, TILE_SPLIT >= 256B.
+                        */
+                       enum tile_split_values tile_split;
+                       enum tile_split_values tile_split_c;
+                       /* Specifies the addressing within a tile.
+                        *      0x0 - DISPLAY_MICRO_TILING
+                        *      0x1 - THIN_MICRO_TILING
+                        *      0x2 - DEPTH_MICRO_TILING
+                        *      0x3 - ROTATED_MICRO_TILING
+                        */
+                       enum tile_mode_values tile_mode;
+                       enum tile_mode_values tile_mode_c;
+                       /* Specifies the number of pipes and how they are
+                        *      interleaved in the surface.
+                        * Refer to memory addressing document for complete
+                        *      details and constraints.
+                        */
+                       unsigned int pipe_config;
+                       /* Specifies the tiling mode of the surface.
+                        * THIN tiles use an 8x8x1 tile size.
+                        * THICK tiles use an 8x8x4 tile size.
+                        * 2D tiling modes rotate banks for successive Z slices
+                        * 3D tiling modes rotate pipes and banks for Z slices
+                        * Refer to memory addressing document for complete
+                        *      details and constraints.
+                        */
+                       enum array_mode_values array_mode;
+               } gfx8;
 
-       struct {
-               enum swizzle_mode_values swizzle;
-               unsigned int num_pipes;
-               unsigned int max_compressed_frags;
-               unsigned int pipe_interleave;
-
-               unsigned int num_banks;
-               unsigned int num_shader_engines;
-               unsigned int num_rb_per_se;
-               bool shaderEnable;
-
-               bool meta_linear;
-               bool rb_aligned;
-               bool pipe_aligned;
-               unsigned int num_pkrs;
-       } gfx9;/*gfx9, gfx10 and above*/
-       struct {
-               enum swizzle_mode_addr3_values swizzle;
-       } gfx_addr3;/*gfx with addr3 and above*/
+               struct {
+                       enum swizzle_mode_values swizzle;
+                       unsigned int num_pipes;
+                       unsigned int max_compressed_frags;
+                       unsigned int pipe_interleave;
+
+                       unsigned int num_banks;
+                       unsigned int num_shader_engines;
+                       unsigned int num_rb_per_se;
+                       bool shaderEnable;
+
+                       bool meta_linear;
+                       bool rb_aligned;
+                       bool pipe_aligned;
+                       unsigned int num_pkrs;
+               } gfx9;/*gfx9, gfx10 and above*/
+               struct {
+                       enum swizzle_mode_addr3_values swizzle;
+               } gfx_addr3;/*gfx with addr3 and above*/
+       };
 };
 
 /* Rotation angle */

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index ebd174be5786b14f93f581341b287e10977b2486..1c2009e38aa125f67c0b72c18d7236abb9640fda 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -98,7 +98,7 @@ static enum mi_bits_per_pixel get_mi_bpp(
 }
 
 static enum mi_tiling_format get_mi_tiling(
-               union dc_tiling_info *tiling_info)
+               struct dc_tiling_info *tiling_info)
 {
        switch (tiling_info->gfx8.array_mode) {
        case DC_ARRAY_1D_TILED_THIN1:
@@ -133,7 +133,7 @@ static bool is_vert_scan(enum dc_rotation_angle rotation)
 static void dce_mi_program_pte_vm(
                struct mem_input *mi,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                enum dc_rotation_angle rotation)
 {
        struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
@@ -430,7 +430,7 @@ static void dce120_mi_program_display_marks(struct mem_input *mi,
 }
 
 static void program_tiling(
-       struct dce_mem_input *dce_mi, const union dc_tiling_info *info)
+       struct dce_mem_input *dce_mi, const struct dc_tiling_info *info)
 {
        if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
                REG_UPDATE_6(GRPH_CONTROL,
@@ -650,7 +650,7 @@ static void dce_mi_clear_tiling(
 static void dce_mi_program_surface_config(
        struct mem_input *mi,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,
@@ -670,7 +670,7 @@ static void dce_mi_program_surface_config(
 static void dce60_mi_program_surface_config(
        struct mem_input *mi,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation, /* not used in DCE6 */
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 8a3fbf95c48f2a1473bca3609468aee18eeab3ee..2c43c24226385d4cbd6911d75f69192c027811bb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -162,7 +162,7 @@ static void enable(struct dce_mem_input *mem_input110)
 
 static void program_tiling(
        struct dce_mem_input *mem_input110,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
        uint32_t value = 0;
@@ -523,7 +523,7 @@ static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
 
 /* Helper to get table entry from surface info */
 static const unsigned int *get_dvmm_hw_setting(
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                enum surface_pixel_format format,
                bool chroma)
 {
@@ -563,7 +563,7 @@ static const unsigned int *get_dvmm_hw_setting(
 static void dce_mem_input_v_program_pte_vm(
                struct mem_input *mem_input,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                enum dc_rotation_angle rotation)
 {
        struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
@@ -636,7 +636,7 @@ static void dce_mem_input_v_program_pte_vm(
 static void dce_mem_input_v_program_surface_config(
        struct mem_input *mem_input,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index f0ba944553df596cd2550cd107d06557b095d95e..8364c9f9231a403d6b2443ed03c9a8b49fda57bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -140,7 +140,7 @@ void hubp1_vready_workaround(struct hubp *hubp,
 
 void hubp1_program_tiling(
        struct hubp *hubp,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -549,7 +549,7 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
 void hubp1_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
index 631350cd4f2ed6963d53dcced67f2edda1c60024..a85dc3be786f7846bb6b1b1a8ac0f90300bb7337 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
@@ -706,7 +706,7 @@ struct dcn10_hubp {
 void hubp1_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,
@@ -739,7 +739,7 @@ void hubp1_program_rotation(
 
 void hubp1_program_tiling(
        struct hubp *hubp,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format);
 
 void hubp1_dcc_control(struct hubp *hubp,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index 200194544bf0c25c0b36c4aa87f2cb9ea181d5f2..c74f6a3313a27c470feebe92ca294afe875c1f27 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -310,7 +310,7 @@ void hubp2_setup_interdependent(
  */
 static void hubp2_program_tiling(
        struct dcn20_hubp *hubp2,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
        REG_UPDATE_3(DCSURF_ADDR_CONFIG,
@@ -550,7 +550,7 @@ void hubp2_program_pixel_format(
 void hubp2_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
index 7fd9240868c3441fe84b07a031557e8106d88d57..6968087a36052ff487971ce49a4ad9129bdb4d27 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
@@ -382,7 +382,7 @@ void hubp2_program_pixel_format(
 void hubp2_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
index d910e4a54c34abedc9d9431d6951527b0eadaf0b..65c628078ca2ab2547d3aeaeb8198ad69537c449 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
@@ -42,7 +42,7 @@
 static void hubp201_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
index 3b16c3cda2c3e7ab4d13f8a9da2e970ffc9466f1..12b282ed7067b48a0cc2fb32cc39a71acab8364e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
@@ -318,7 +318,7 @@ bool hubp3_program_surface_flip_and_addr(
 
 void hubp3_program_tiling(
        struct dcn20_hubp *hubp2,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
        REG_UPDATE_4(DCSURF_ADDR_CONFIG,
@@ -411,7 +411,7 @@ void hubp3_dmdata_set_attributes(
 void hubp3_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
index cfb01bf340a1a6db449deaa94e3f87bc7b75edf4..b7d7adf0b58cd4350ed2161d091653f5f1455b60 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
@@ -264,7 +264,7 @@ bool hubp3_program_surface_flip_and_addr(
 void hubp3_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,
@@ -280,7 +280,7 @@ void hubp3_setup(
 
 void hubp3_program_tiling(
                struct dcn20_hubp *hubp2,
-               const union dc_tiling_info *info,
+               const struct dc_tiling_info *info,
                const enum surface_pixel_format pixel_format);
 
 void hubp3_dcc_control(struct hubp *hubp, bool enable,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
index eb62042dfafc2d5fcb445ad3c8d0b0a6324fe12b..faf37febc6fb86b77395edfcd637ad3f8aa51b12 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
@@ -172,7 +172,7 @@ void hubp35_program_pixel_format(
 void hubp35_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
index 586b43aa5834174bb46bce04961cb94af21a9368..d913f80b3130de40e9980501fbd2bcd2f879e06d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
@@ -65,7 +65,7 @@ void hubp35_program_pixel_format(
 void hubp35_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 09f730cfbf8e2af4b6298a046ff744fb694c4544..d38e3f3a1107c09b9edebb318b261528acf793c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -532,7 +532,7 @@ void hubp401_dcc_control(struct hubp *hubp,
 
 void hubp401_program_tiling(
        struct dcn20_hubp *hubp2,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
        /* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x
@@ -580,7 +580,7 @@ void hubp401_program_size(
 void hubp401_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
index 9b200a55bf9d36b30c9f2ef73c2ec95b67e913ee..9e2cf8b5e344da0af66790a0be93d8ab3cf51665 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
@@ -290,7 +290,7 @@ void hubp401_dcc_control(struct hubp *hubp,
 
 void hubp401_program_tiling(
        struct dcn20_hubp *hubp2,
-       const union dc_tiling_info *info,
+       const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format);
 
 void hubp401_program_size(
@@ -302,7 +302,7 @@ void hubp401_program_size(
 void hubp401_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
-       union dc_tiling_info *tiling_info,
+       struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index d0878fc0cc948b7fcfa1eb6c6d6a3b3ccff467aa..93529dc196c0a16b62719ea36c8a4a7fe4cf97df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -165,7 +165,7 @@ struct hubp_funcs {
        void (*hubp_program_pte_vm)(
                struct hubp *hubp,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                enum dc_rotation_angle rotation);
 
        void (*hubp_set_vm_system_aperture_settings)(
@@ -179,7 +179,7 @@ struct hubp_funcs {
        void (*hubp_program_surface_config)(
                struct hubp *hubp,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                struct plane_size *plane_size,
                enum dc_rotation_angle rotation,
                struct dc_plane_dcc_param *dcc,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 4f5d102455cac2151c2ee085f44f6b322a7ea902..42fbc70f7056abbe82dc7a352fe2ff2604c9a8f9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -150,7 +150,7 @@ struct mem_input_funcs {
        void (*mem_input_program_pte_vm)(
                struct mem_input *mem_input,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                enum dc_rotation_angle rotation);
 
        void (*mem_input_set_vm_system_aperture_settings)(
@@ -164,7 +164,7 @@ struct mem_input_funcs {
        void (*mem_input_program_surface_config)(
                struct mem_input *mem_input,
                enum surface_pixel_format format,
-               union dc_tiling_info *tiling_info,
+               struct dc_tiling_info *tiling_info,
                struct plane_size *plane_size,
                enum dc_rotation_angle rotation,
                struct dc_plane_dcc_param *dcc,