DONE;
})
+(define_expand "isnormal<mode>2"
+ [(use (match_operand:SI 0 "gpc_reg_operand"))
+ (use (match_operand:IEEE_FP 1 "<fp_register_op>"))]
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)"
+{
+ rtx tmp = gen_reg_rtx (SImode);
+ /* It is neither NAN, infinite, zero, nor denormal. */
+ int mask = VSX_TEST_DATA_CLASS_NAN
+ | VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF
+ | VSX_TEST_DATA_CLASS_POS_ZERO | VSX_TEST_DATA_CLASS_NEG_ZERO
+ | VSX_TEST_DATA_CLASS_POS_DENORMAL
+ | VSX_TEST_DATA_CLASS_NEG_DENORMAL;
+ emit_insn (gen_xststdc_<mode> (tmp, operands[1], GEN_INT (mask)));
+ emit_insn (gen_xorsi3 (operands[0], tmp, const1_rtx));
+ DONE;
+})
+
;; The VSX Scalar Test Negative Quad-Precision
(define_expand "xststdcnegqp_<mode>"
[(set (match_dup 2)
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target powerpc_vsx } */
+
+int test1 (double x)
+{
+ return __builtin_isnormal (x);
+}
+
+int test2 (float x)
+{
+ return __builtin_isnormal (x);
+}
+
+/* { dg-final { scan-assembler-not {\mfcmp} } } */
+/* { dg-final { scan-assembler-times {\mxststdcsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxststdcdp\M} 1 } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target ppc_float128_hw } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -mabi=ieeelongdouble -Wno-psabi" } */
+/* { dg-require-effective-target powerpc_vsx } */
+
+int test1 (long double x)
+{
+ return __builtin_isnormal (x);
+}
+
+/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
+/* { dg-final { scan-assembler {\mxststdcqp\M} } } */