drm/xe: Skip L2 / TDF cache flushes if primary GT is disabled

If the primary GT is disabled via configfs, GT-side L2 and TD cache
flushes are unnecessary since nothing is using/filling these caches.

Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://lore.kernel.org/r/20251013200944.2499947-34-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 6f8f72fd1b133a60e624ef27b1d3ebc5ba0ecfe9..e2aa79a78938950373f18c4eae7082fd1c226564 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1062,6 +1062,8 @@ void xe_device_l2_flush(struct xe_device *xe)
        unsigned int fw_ref;
 
        gt = xe_root_mmio_gt(xe);
+       if (!gt)
+               return;
 
        if (!XE_GT_WA(gt, 16023588340))
                return;
@@ -1107,6 +1109,9 @@ void xe_device_td_flush(struct xe_device *xe)
                return;
 
        root_gt = xe_root_mmio_gt(xe);
+       if (!root_gt)
+               return;
+
        if (XE_GT_WA(root_gt, 16023588340)) {
                /* A transient flush is not sufficient: flush the L2 */
                xe_device_l2_flush(xe);