net: stmmac: add support for reading inband SGMII status

Report the link, speed and duplex for SGMII links, read from the
SGMII, RGMII and SMII status and control register.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1w2tPZ-0000000DYAj-1MdI@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index 9fe639fb06bb3f61179e967b663927cce50ff3ca..1de1f929d61cdd244279a82dfb31eb4b320903c6 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -70,18 +70,8 @@ enum power_event {
 #define GMAC_RGSMIIIS          0x000000d8      /* RGMII/SMII status */
 
 /* SGMII/RGMII status register */
-#define GMAC_RGSMIIIS_LNKMODE          BIT(0)
-#define GMAC_RGSMIIIS_SPEED            GENMASK(2, 1)
-#define GMAC_RGSMIIIS_LNKSTS           BIT(3)
-#define GMAC_RGSMIIIS_JABTO            BIT(4)
-#define GMAC_RGSMIIIS_FALSECARDET      BIT(5)
+#define GMAC_RSGMIIIS_MASK             GENMASK(15, 0)
 #define GMAC_RGSMIIIS_SMIDRXS          BIT(16)
-/* LNKMOD */
-#define GMAC_RGSMIIIS_LNKMOD_MASK      0x1
-/* LNKSPEED */
-#define GMAC_RGSMIIIS_SPEED_125                0x2
-#define GMAC_RGSMIIIS_SPEED_25         0x1
-#define GMAC_RGSMIIIS_SPEED_2_5                0x0
 
 /* GMAC Configuration defines */
 #define GMAC_CONTROL_2K 0x08000000     /* IEEE 802.3as 2K packets */

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index c851e3b88ce5627d733d81f80694d3a0b445b011..caac85fc08f1b60397d9ed345b91ad41be95f05f 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -24,6 +24,8 @@
 
 static const struct stmmac_pcs_info dwmac1000_pcs_info = {
        .pcs_offset = GMAC_PCS_BASE,
+       .rgsmii_offset = GMAC_RGSMIIIS,
+       .rgsmii_status_mask = GMAC_RSGMIIIS_MASK,
        .int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN,
 };
 

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index d797d936aee16e1a05a50e8d7f6e8d5a1c302db2..ffcd036d4c024f2fbbe846de7a5f4cbabe3bd403 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -470,15 +470,7 @@ static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
 #define GMAC_PHYIF_CTRLSTATUS_TC               BIT(0)
 #define GMAC_PHYIF_CTRLSTATUS_LUD              BIT(1)
 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS          BIT(4)
-#define GMAC_PHYIF_CTRLSTATUS_LNKMOD           BIT(16)
-#define GMAC_PHYIF_CTRLSTATUS_SPEED            GENMASK(18, 17)
-#define GMAC_PHYIF_CTRLSTATUS_LNKSTS           BIT(19)
-#define GMAC_PHYIF_CTRLSTATUS_JABTO            BIT(20)
-#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET      BIT(21)
-/* LNKSPEED */
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_125                0x2
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_25         0x1
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5                0x0
+#define GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK      GENMASK(31, 16)
 
 extern const struct stmmac_dma_ops dwmac4_dma_ops;
 extern const struct stmmac_dma_ops dwmac410_dma_ops;

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index ba5393beb7bba7bb54989a06d9557037debed6fa..c6fcfae27c3d0eb2ca3269c9be2f4333dc1546a8 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -24,6 +24,8 @@
 
 static const struct stmmac_pcs_info dwmac4_pcs_info = {
        .pcs_offset = GMAC_PCS_BASE,
+       .rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS,
+       .rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
        .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
 };
 

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 2695e0b9ed03c72ef86b5fe8de432c28066e10b2..df72f7c5a6a7b6fa0b87881e829a8aa006f237d9 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -16,6 +16,16 @@
 #define GMAC_ANE_LPA   0x0c    /* ANE link partener ability */
 #define GMAC_TBI       0x14    /* TBI extend status */
 
+/*
+ * RGSMII status bitfield definitions.
+ */
+#define GMAC_RGSMII_LNKMOD             BIT(0)
+#define GMAC_RGSMII_SPEED_MASK         GENMASK(2, 1)
+#define GMAC_RGSMII_SPEED_125          2
+#define GMAC_RGSMII_SPEED_25           1
+#define GMAC_RGSMII_SPEED_2_5          0
+#define GMAC_RGSMII_LNKSTS             BIT(3)
+
 static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
 {
        struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -36,7 +46,42 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
                                           unsigned int neg_mode,
                                           struct phylink_link_state *state)
 {
-       state->link = false;
+       struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+       u32 status, rgsmii;
+
+       status = readl(spcs->base + GMAC_AN_STATUS);
+
+       if (phy_interface_mode_is_8023z(state->interface)) {
+               state->link = false;
+       } else {
+               rgsmii = field_get(spcs->rgsmii_status_mask,
+                                  readl(spcs->rgsmii));
+
+               state->link = status & BMSR_LSTATUS &&
+                             rgsmii & GMAC_RGSMII_LNKSTS;
+
+               if (state->link && neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+                       state->duplex = rgsmii & GMAC_RGSMII_LNKMOD ?
+                                       DUPLEX_FULL : DUPLEX_HALF;
+                       switch (FIELD_GET(GMAC_RGSMII_SPEED_MASK, rgsmii)) {
+                       case GMAC_RGSMII_SPEED_2_5:
+                               state->speed = SPEED_10;
+                               break;
+
+                       case GMAC_RGSMII_SPEED_25:
+                               state->speed = SPEED_100;
+                               break;
+
+                       case GMAC_RGSMII_SPEED_125:
+                               state->speed = SPEED_1000;
+                               break;
+
+                       default:
+                               state->link = false;
+                               break;
+                       }
+               }
+       }
 }
 
 static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
@@ -101,6 +146,8 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
 
        spcs->priv = priv;
        spcs->base = priv->ioaddr + pcs_info->pcs_offset;
+       spcs->rgsmii = priv->ioaddr + pcs_info->rgsmii_offset;
+       spcs->rgsmii_status_mask = pcs_info->rgsmii_status_mask;
        spcs->int_mask = pcs_info->int_mask;
        spcs->pcs.ops = &dwmac_integrated_pcs_ops;
 

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index f1ee473d8e3e4bec4c652f536a9387400361b876..09e609f111b1b167b6c69ab0ff63ba15dbee45fc 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -29,12 +29,16 @@ struct stmmac_priv;
 
 struct stmmac_pcs_info {
        unsigned int pcs_offset;
+       unsigned int rgsmii_offset;
+       u32 rgsmii_status_mask;
        u32 int_mask;
 };
 
 struct stmmac_pcs {
        struct stmmac_priv *priv;
        void __iomem *base;
+       void __iomem *rgsmii;
+       u32 rgsmii_status_mask;
        u32 int_mask;
        struct phylink_pcs pcs;
 };