* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
+2003-10-06 Dave Brolley <brolley@redhat.com>
+
+ * sim/frv/fr550: New subdirectory.
+ * sim/frv/fr400/*.cgs: Add fr550 as appropriate.
+ * sim/frv/fr500/*.cgs: Add fr550 as appropriate.
+ * sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
+ * sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
+
2003-09-19 Michael Snyder <msnyder@redhat.com>
* sim/frv/nldqi.cgs: Remove. This insn was never implemented
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "frv fr500 fr400"
+ set all_machs "frv fr500 fr550 fr400"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
# frv parallel testcase for branching
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv parallel testcase for call $label24
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfabss $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfitos $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmpb $GRi,$GRj,$ICCi_1
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for cmpba $GRi,$GRj,$ICCi_1
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for dcef @(GRi,GRj),a
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for dcei @(GRi,GRj),a
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for fabss $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fadds $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fcmps $GRi,$GRj,$FCCi_2
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdadds $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdcmps $FRi,$FRj,$FCCi_2
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdivs $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdmulcs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdmuls $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdsads $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fdsubs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fitos $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fmas $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fmovs $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fmss $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fmuls $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fnegs $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fnop
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
--- /dev/null
+# frv testcase for addss $GRi,$GRj,$GRk
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global add
+add_nosaturate:
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ addss gr7,gr8,gr8
+ test_gr_immed 3,gr8
+add_saturate_pos:
+ set_gr_limmed 0x7fff,0xffff,gr7
+ set_gr_immed 1,gr8
+ addss gr7,gr8,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+
+ set_gr_limmed 0x4000,0x0000,gr7
+ set_gr_limmed 0x4000,0x0000,gr8
+ addss gr7,gr8,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+
+add_saturate_neg:
+ set_gr_limmed 0x8000,0x0000,gr7
+ set_gr_limmed 0xffff,0xffff,gr8
+ addss gr7,gr8,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+
+ set_gr_limmed 0x8000,0x0001,gr7
+ set_gr_limmed 0x8000,0x0001,gr8
+ addss gr7,gr8,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+
+ pass
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "fr400"
+ set all_machs "fr400 fr550"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
--- /dev/null
+# frv testcase for movgs $GRj,iacc0[hl]
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global movgs
+IACC0H:
+ set_gr_limmed 0xdead,0xbeef,gr8
+ and_spr_immed 0,iacc0h
+ movgs gr8,iacc0h
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0h
+SPR280:
+ ; try alternate names for iacc0h
+ and_spr_immed 0,280
+ movgs gr8,spr[280] ; iacc0h is spr number 280
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[280]
+
+IACC0L:
+ set_gr_limmed 0xdead,0xbeef,gr8
+ and_spr_immed 0,iacc0l
+ movgs gr8,iacc0l
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0l
+SPR281:
+ ; try alternate names for iacc0l
+ and_spr_immed 0,281
+ movgs gr8,spr[281] ; iacc0l is spr number 281
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[281]
+
+IACC0L_SPR281:
+ ; try crossing between iacc0l and spr[281]
+ and_spr_immed 0,281
+ and_spr_immed 0,iacc0l
+ movgs gr8,spr[281] ; iacc0l is spr number 281
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0l
+
+SPR280_IACC0H:
+ and_spr_immed 0,280
+ and_spr_immed 0,iacc0h
+ movgs gr8,iacc0h ; iacc0h is spr number 280
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[280]
+
+ pass
--- /dev/null
+# frv testcase for movsg iacc0[hl],$GRj
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global movsg
+Iacc0h:
+ set_spr_limmed 0xdead,0xbeef,iacc0h
+ set_gr_limmed 0,0,gr8
+ movsg iacc0h,gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0h
+Iacc0l:
+ set_spr_limmed 0xdead,0xbeef,iacc0l
+ set_gr_limmed 0,0,gr8
+ movsg iacc0l,gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0l
+
+Spr280:
+ set_spr_limmed 0xdead,0xbeef,spr[280]
+ set_gr_limmed 0,0,gr8
+ movsg spr[280],gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[280]
+Spr281:
+ set_spr_limmed 0xdead,0xbeef,spr[281]
+ set_gr_limmed 0,0,gr8
+ movsg spr[281],gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[281]
+
+Iacc0h_spr280:
+ set_spr_limmed 0xdead,0xbeef,spr[280]
+ set_spr_limmed 0xdead,0xbeef,iacc0h
+ set_gr_limmed 0,0,gr8
+ movsg iacc0h,gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[280]
+Iacc0l_spr281:
+ set_spr_limmed 0xdead,0xbeef,spr[281]
+ set_spr_limmed 0xdead,0xbeef,iacc0l
+ set_gr_limmed 0,0,gr8
+ movsg iacc0l,gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,spr[281]
+
+Spr280_iacc0h:
+ set_spr_limmed 0xdead,0xbeef,spr[280]
+ set_spr_limmed 0xdead,0xbeef,iacc0h
+ set_gr_limmed 0,0,gr8
+ movsg spr[280],gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0h
+Spr281_iacc0l:
+ set_spr_limmed 0xdead,0xbeef,spr[281]
+ set_spr_limmed 0xdead,0xbeef,iacc0l
+ set_gr_limmed 0,0,gr8
+ movsg spr[281],gr8
+ test_gr_limmed 0xdead,0xbeef,gr8
+ test_spr_limmed 0xdead,0xbeef,iacc0l
+
+ pass
--- /dev/null
+# frv testcase for scutss $FRj,$FRk
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global scutss
+scutss:
+ set_spr_immed 0xffffffe7,iacc0h
+ set_spr_immed 0x89abcdef,iacc0l
+
+ set_gr_immed 0,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffe7,gr11
+
+ set_gr_immed 1,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffcf,gr11
+
+ set_gr_immed 2,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xff9e,gr11
+
+ set_gr_immed 3,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xff3c,gr11
+
+ set_gr_immed 4,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfe78,gr11
+
+ set_gr_immed 5,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfcf1,gr11
+
+ set_gr_immed 6,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xf9e2,gr11
+
+ set_gr_immed 7,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xf3c4,gr11
+
+ set_gr_immed 8,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xe789,gr11
+
+ set_gr_immed 9,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xcf13,gr11
+
+ set_gr_immed 10,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0x9e26,gr11
+
+ set_gr_immed 11,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0x3c4d,gr11
+
+ set_gr_immed 12,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfffe,0x789a,gr11
+
+ set_gr_immed 13,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfffc,0xf135,gr11
+
+ set_gr_immed 14,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfff9,0xe26a,gr11
+
+ set_gr_immed 15,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfff3,0xc4d5,gr11
+
+ set_gr_immed 16,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffe7,0x89ab,gr11
+
+ set_gr_immed 17,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffcf,0x1357,gr11
+
+ set_gr_immed 18,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xff9e,0x26af,gr11
+
+ set_gr_immed 19,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xff3c,0x4d5e,gr11
+
+ set_gr_immed 20,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfe78,0x9abc,gr11
+
+ set_gr_immed 21,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfcf1,0x3579,gr11
+
+ set_gr_immed 22,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xf9e2,0x6af3,gr11
+
+ set_gr_immed 23,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xf3c4,0xd5e6,gr11
+
+ set_gr_immed 24,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xe789,0xabcd,gr11
+
+ set_gr_immed 25,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xcf13,0x579b,gr11
+
+ set_gr_immed 26,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x9e26,0xaf37,gr11
+
+ set_gr_immed 27,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 28,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 29,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 30,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 31,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 32,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 33,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 34,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 35,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 36,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 37,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 38,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 39,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 40,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 41,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 42,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 43,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 44,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 45,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 46,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 47,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 48,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 49,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 50,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 51,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 52,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 53,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 54,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 55,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 56,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 57,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 58,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 59,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 60,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 61,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 62,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 63,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11
+
+ set_gr_immed 64,gr10 ; same as -64
+ scutss gr10,gr11
+ test_gr_immed -1,gr11
+
+ set_gr_immed 128,gr10 ; same as 0
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffe7,gr11
+
+ .global scutss2
+scutss2:
+ set_spr_immed 0xe789abcd,iacc0h
+ set_spr_immed 0xefa5a5a5,iacc0l
+
+ set_gr_limmed 0xffff,0xffff,gr10 ; -1
+ scutss gr10,gr11
+ test_gr_limmed 0xf3c4,0xd5e6,gr11
+
+ set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter)
+ scutss gr10,gr11
+ test_gr_limmed 0xf9e2,0x6af3,gr11
+
+ set_gr_immed -3,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfcf1,0x3579,gr11
+
+ set_gr_immed -4,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfe78,0x9abc,gr11
+
+ set_gr_immed -5,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xff3c,0x4d5e,gr11
+
+ set_gr_immed -6,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xff9e,0x26af,gr11
+
+ set_gr_immed -7,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffcf,0x1357,gr11
+
+ set_gr_immed -8,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffe7,0x89ab,gr11
+
+ set_gr_immed -9,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfff3,0xc4d5,gr11
+
+ set_gr_immed -10,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfff9,0xe26a,gr11
+
+ set_gr_immed -11,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfffc,0xf135,gr11
+
+ set_gr_immed -12,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfffe,0x789a,gr11
+
+ set_gr_immed -13,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0x3c4d,gr11
+
+ set_gr_immed -14,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0x9e26,gr11
+
+ set_gr_immed -15,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xcf13,gr11
+
+ set_gr_immed -16,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xe789,gr11
+
+ set_gr_immed -17,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xf3c4,gr11
+
+ set_gr_immed -18,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xf9e2,gr11
+
+ set_gr_immed -19,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfcf1,gr11
+
+ set_gr_immed -20,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfe78,gr11
+
+ set_gr_immed -21,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xff3c,gr11
+
+ set_gr_immed -22,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xff9e,gr11
+
+ set_gr_immed -23,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffcf,gr11
+
+ set_gr_immed -24,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffe7,gr11
+
+ set_gr_immed -25,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfff3,gr11
+
+ set_gr_immed -26,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfff9,gr11
+
+ set_gr_immed -27,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfffc,gr11
+
+ set_gr_immed -28,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xfffe,gr11
+
+ set_gr_immed -29,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffff,gr11
+
+ set_gr_immed -30,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffff,gr11
+
+ set_gr_immed -31,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffff,gr11
+
+ set_gr_immed -32,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffff,gr11
+
+ set_gr_limmed 0,64,gr10 ; same as -32
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffff,gr11
+
+ set_spr_immed 0x6789abcd,iacc0h
+ set_spr_immed 0xefa5a5a5,iacc0l
+
+ set_gr_limmed 0xffff,0xffff,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x33c4,0xd5e6,gr11
+
+ set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter)
+ scutss gr10,gr11
+ test_gr_limmed 0x19e2,0x6af3,gr11
+
+ set_gr_immed -3,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0cf1,0x3579,gr11
+
+ set_gr_immed -4,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0678,0x9abc,gr11
+
+ set_gr_immed -5,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x033c,0x4d5e,gr11
+
+ set_gr_immed -6,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x019e,0x26af,gr11
+
+ set_gr_immed -7,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x00cf,0x1357,gr11
+
+ set_gr_immed -8,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0067,0x89ab,gr11
+
+ set_gr_immed -9,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0033,0xc4d5,gr11
+
+ set_gr_immed -10,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0019,0xe26a,gr11
+
+ set_gr_immed -11,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x000c,0xf135,gr11
+
+ set_gr_immed -12,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0006,0x789a,gr11
+
+ set_gr_immed -13,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0003,0x3c4d,gr11
+
+ set_gr_immed -14,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0001,0x9e26,gr11
+
+ set_gr_immed -15,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0xcf13,gr11
+
+ set_gr_immed -16,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x6789,gr11
+
+ set_gr_immed -17,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x33c4,gr11
+
+ set_gr_immed -18,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x19e2,gr11
+
+ set_gr_immed -19,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0cf1,gr11
+
+ set_gr_immed -20,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0678,gr11
+
+ set_gr_immed -21,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x033c,gr11
+
+ set_gr_immed -22,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x019e,gr11
+
+ set_gr_immed -23,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x00cf,gr11
+
+ set_gr_immed -24,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0067,gr11
+
+ set_gr_immed -25,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0033,gr11
+
+ set_gr_immed -26,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0019,gr11
+
+ set_gr_immed -27,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x000c,gr11
+
+ set_gr_immed -28,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0006,gr11
+
+ set_gr_immed -29,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0003,gr11
+
+ set_gr_immed -30,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0001,gr11
+
+ set_gr_immed -31,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0000,gr11
+
+ set_gr_immed -32,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0000,gr11
+
+ set_gr_immed 64,gr10 ; same as -32
+ scutss gr10,gr11
+ test_gr_limmed 0x0000,0x0000,gr11
+
+ ; Examples from the customer (modified for iacc0)
+ set_spr_immed 0xffffffff,iacc0h
+ set_spr_immed 0xffe00000,iacc0l
+
+ set_gr_limmed 0,16,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffe0,gr11
+
+ set_gr_limmed 0,17,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xffc0,gr11
+
+ set_gr_limmed 0,18,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xffff,0xff80,gr11
+
+ set_spr_immed 0,iacc0h
+ set_spr_immed 0x003fffff,iacc0l
+
+ set_gr_limmed 0,40,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x3fff,0xff00,gr11
+
+ set_gr_limmed 0,41,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xfe00,gr11
+
+ set_spr_immed 0x7f,iacc0h
+ set_spr_immed 0xffe00000,iacc0l
+
+ set_gr_limmed 0,40,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
+
+ set_gr_limmed 0,41,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
+
+ set_gr_limmed 0,42,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
+
+ set_spr_immed 0x08,iacc0h
+ set_spr_immed 0x003fffff,iacc0l
+
+ set_gr_limmed 0,40,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
+
+ set_gr_limmed 0,41,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
+
+ set_spr_immed 0xffffffff,iacc0h
+ set_spr_immed 0xefe00000,iacc0l
+
+ set_gr_limmed 0,40,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11 ; saturated
+
+ set_gr_limmed 0,41,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11 ; saturated
+
+ set_gr_limmed 0,42,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11 ; saturated
+
+ set_spr_immed 0x80000000,iacc0h
+ set_spr_immed 0x003fffff,iacc0l
+
+ set_gr_limmed 0,16,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11 ; saturated
+
+ set_gr_limmed 0,17,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x8000,0x0000,gr11 ; saturated
+
+ set_spr_immed 0xaf5a5a5a,iacc0h
+ set_spr_immed 0x5a5a5a5a,iacc0l
+
+ set_gr_limmed 0xffff,0xfffc,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0xfaf5,0xa5a5,gr11
+
+ set_spr_immed 0x2f5a5a5a,iacc0h
+ set_spr_immed 0x5a5a5a5a,iacc0l
+
+ set_gr_limmed 0xffff,0xfff9,gr10
+ scutss gr10,gr11
+ test_gr_limmed 0x005e,0xb4b4,gr11
+
+ pass
--- /dev/null
+# frv testcase for slass $GRi,$GRj,$GRk
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global sll
+slass0:
+ set_gr_immed 0,gr7 ; Shift by 0
+ set_gr_immed 2,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed 2,gr8
+ test_gr_immed 0,gr7
+ test_gr_immed 2,gr6
+slass1:
+ set_gr_immed 1,gr7 ; Shift by 1
+ set_gr_immed 2,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed 2,gr8
+ test_gr_immed 1,gr7
+ test_gr_immed 4,gr6
+
+slass2:
+ set_gr_immed 31,gr7 ; Shift 1 by 31
+ set_gr_immed 1,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed 1,gr8
+ test_gr_immed 31,gr7
+ test_gr_limmed 0x7fff,0xffff,gr6
+
+slass3:
+ set_gr_immed 31,gr7 ; Shift -1 by 31
+ set_gr_immed -1,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed -1,gr8
+ test_gr_immed 31,gr7
+ test_gr_limmed 0x8000,0x0000,gr6
+
+slass4:
+ set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14
+ set_gr_limmed 0xffff,0x0000,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0xffff,0x0000,gr8
+ test_gr_immed 14,gr7
+ test_gr_limmed 0xc000,0x0000,gr6
+
+slass5:
+ set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15
+ set_gr_limmed 0xffff,0x0000,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0xffff,0x0000,gr8
+ test_gr_immed 15,gr7
+ test_gr_limmed 0x8000,0x0000,gr6
+
+slass6:
+ set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20
+ set_gr_limmed 0xffff,0x0000,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0xffff,0x0000,gr8
+ test_gr_immed 20,gr7
+ test_gr_limmed 0x8000,0x0000,gr6
+
+slass7:
+ set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14
+ set_gr_limmed 0x0000,0xffff,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0x0000,0xffff,gr8
+ test_gr_immed 14,gr7
+ test_gr_limmed 0x3fff,0xc000,gr6
+
+slass8:
+ set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15
+ set_gr_limmed 0x0000,0xffff,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0x0000,0xffff,gr8
+ test_gr_immed 15,gr7
+ test_gr_limmed 0x7fff,0x8000,gr6
+
+slass9:
+ set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20
+ set_gr_limmed 0x0000,0xffff,gr8
+ slass gr8,gr7,gr6
+ test_gr_limmed 0x0000,0xffff,gr8
+ test_gr_immed 20,gr7
+ test_gr_limmed 0x7fff,0xffff,gr6
+
+slass10:
+ set_gr_immed 30,gr7 ; Shift 1 by 30
+ set_gr_immed 1,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed 1,gr8
+ test_gr_immed 30,gr7
+ test_gr_limmed 0x4000,0x0000,gr6
+
+slass11:
+ set_gr_immed 30,gr7 ; Shift -1 by 30
+ set_gr_immed -1,gr8
+ slass gr8,gr7,gr6
+ test_gr_immed -1,gr8
+ test_gr_immed 30,gr7
+ test_gr_limmed 0xc000,0000,gr6
+
+ pass
--- /dev/null
+# frv testcase for smass $GRi,$GRj
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global smass
+smass1:
+ ; Positive operands
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 3,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 7,iacc0l ; result 3*2+1
+ test_spr_immed 0,iacc0h
+smass2:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 1,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 3,iacc0l ; result 1*2+1
+ test_spr_immed 0,iacc0h
+smass3:
+ set_gr_immed 2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 3,iacc0l ; result 2*1+1
+ test_spr_immed 0,iacc0h
+smass4:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 1,iacc0l ; result 0*2+1
+ test_spr_immed 0,iacc0h
+smass5:
+ set_gr_immed 2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 1,iacc0l ; result 2*0+1
+ test_spr_immed 0,iacc0h
+smass6:
+ set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x3fff,0xffff,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1
+ test_spr_immed 0,iacc0h
+smass7:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1
+ test_spr_immed 0,iacc0h
+smass8:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed 4,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_immed 1,iacc0l ; 40000000*4+1
+ test_spr_immed 1,iacc0h
+smass9:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1
+ test_spr_limmed 0x3fff,0xffff,iacc0h
+smass10:
+ ; Mixed operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed -5,iacc0l ; -3*2+1
+ test_spr_immed -1,iacc0h
+smass11:
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 3,gr7
+ test_spr_immed -5,iacc0l ; 3*-2+1
+ test_spr_immed -1,iacc0h
+smass12:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 1,gr7
+ test_spr_immed -1,iacc0l ; 1*-2+1
+ test_spr_immed -1,iacc0h
+smass13:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed -1,iacc0l ; -2*1+1
+ test_spr_immed -1,iacc0h
+smass14:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 1,iacc0l ; 0*-2+1
+ test_spr_immed 0,iacc0h
+smass15:
+ set_gr_immed -2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 1,iacc0l ; -2*0+1
+ test_spr_immed 0,iacc0h
+smass16:
+ set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x2000,0x0001,gr7
+ test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smass17:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smass18:
+ set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0001,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smass19:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed -4,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smass20:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1
+ test_spr_limmed 0xc000,0x0000,iacc0h
+smass21:
+ ; Negative operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed 7,iacc0l ; -3*-2+1
+ test_spr_immed 0,iacc0h
+smass22:
+ set_gr_immed -1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -1,gr7
+ test_spr_immed 3,iacc0l ; -1*-2+1
+ test_spr_immed 0,iacc0h
+smass23:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed -1,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 3,iacc0l ; -2*-1+1
+ test_spr_immed 0,iacc0h
+smass24:
+ set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0xc000,0x0001,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1
+ test_spr_immed 0,iacc0h
+smass25:
+ set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0xc000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1
+ test_spr_immed 0,iacc0h
+smass26:
+ set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
+ set_gr_immed -4,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_immed -4,gr8
+ test_gr_limmed 0xc000,0x0000,gr7
+ test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1
+ test_spr_immed 1,iacc0h
+smass27:
+ set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
+ set_gr_limmed 0x8000,0x0001,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0001,gr8
+ test_gr_limmed 0x8000,0x0001,gr7
+ test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1
+ test_spr_limmed 0x3fff,0xffff,iacc0h
+smass28:
+ set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x8000,0x0000,gr7
+ test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1
+ test_spr_limmed 0x4000,0x0000,iacc0h
+
+smass29:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0xffff,0xfffe,iacc0l
+ set_spr_limmed 0x4000,0x0000,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe
+
+smass30:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0xffff,0xffff,iacc0l
+ set_spr_limmed 0x4000,0x0000,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff
+
+smass31:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0xffff,0xffff,iacc0l
+ set_spr_limmed 0x7fff,0xffff,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff
+
+smass32:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0x8000,0x0000,iacc0l
+ set_spr_limmed 0xbfff,0xffff,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000
+
+smass33:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0x7fff,0xffff,iacc0l
+ set_spr_limmed 0xbfff,0xffff,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
+
+smass34:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0x0000,0x0000,iacc0l
+ set_spr_limmed 0x8000,0x0000,iacc0h
+ smass gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000
+
+ pass
--- /dev/null
+# frv testcase for smsss $GRi,$GRj
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global smsss
+smsss1:
+ ; Positive operands
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 7,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 3,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 1,iacc0l ; result 7-3*2
+ test_spr_immed 0,iacc0h
+smsss2:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 3,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 1,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 1,iacc0l ; result 3-1*2
+ test_spr_immed 0,iacc0h
+smsss3:
+ set_gr_immed 2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 3,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 1,iacc0l ; result 3-2*1
+ test_spr_immed 0,iacc0h
+smsss4:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed 2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 1,iacc0l ; result 1-0*2
+ test_spr_immed 0,iacc0h
+smsss5:
+ set_gr_immed 2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 1,iacc0l ; result 1-2*0
+ test_spr_immed 0,iacc0h
+smsss6:
+ set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
+ set_gr_immed 2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x3fff,0xffff,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2
+ test_spr_immed -1,iacc0h
+smsss7:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed 2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_limmed 0x8000,0x0001,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2
+ test_spr_immed -1,iacc0h
+smsss8:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed 4,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4
+ test_spr_immed -2,iacc0h
+smsss9:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0x7fff,0xffff,iacc0h
+ set_spr_immed -1,iacc0l
+ smsss gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff
+ test_spr_limmed 0x4000,0x0000,iacc0h
+smsss10:
+ ; Mixed operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -5,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed 1,iacc0l ; -5-(-3*2)
+ test_spr_immed 0,iacc0h
+smsss11:
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -5,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 3,gr7
+ test_spr_immed 1,iacc0l ; -5-(3*-2)
+ test_spr_immed 0,iacc0h
+smsss12:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 1,gr7
+ test_spr_immed 1,iacc0l ; -1-(1*-2)
+ test_spr_immed 0,iacc0h
+smsss13:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 1,iacc0l ; -1-(-2*1)
+ test_spr_immed 0,iacc0h
+smsss14:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 1,iacc0l ; 1-(0*-2)
+ test_spr_immed 0,iacc0h
+smsss15:
+ set_gr_immed -2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 1,iacc0l ; 1-(-2*0)
+ test_spr_immed 0,iacc0h
+smsss16:
+ set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_limmed 0x3fff,0xffff,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x2000,0x0000,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l
+ test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2
+smsss17:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2
+ test_spr_immed 0,iacc0h
+smsss18:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ set_spr_immed -1,iacc0h
+ set_spr_immed -1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l
+ test_spr_immed 0,iacc0h ; -1-40000000*-2
+smsss19:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed -4,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_immed 1,iacc0l ; 200000001-(40000000*-4)
+ test_spr_immed 1,iacc0h
+smsss20:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0xbfff,0xffff,iacc0h
+ set_spr_limmed 0x0000,0x0001,iacc0l
+ smsss gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff)
+ test_spr_limmed 0x8000,0x0000,iacc0h
+smsss21:
+ ; Negative operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 7,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed 1,iacc0l ; 7-(-3*-2)
+ test_spr_immed 0,iacc0h
+smsss22:
+ set_gr_immed -1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 3,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -1,gr7
+ test_spr_immed 1,iacc0l ; 3-(-1*-2)
+ test_spr_immed 0,iacc0h
+smsss23:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed -1,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_immed 3,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 1,iacc0l ; 3-(-2*-1)
+ test_spr_immed 0,iacc0h
+smsss24:
+ set_gr_immed -32768,gr7 ; 31 bit result
+ set_gr_immed -32768,gr8
+ set_spr_immed 0,iacc0h
+ set_spr_limmed 0xbfff,0xffff,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -32768,gr8
+ test_gr_immed -32768,gr7
+ test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2)
+ test_spr_immed 0,iacc0h
+smsss25:
+ set_gr_immed 0xffff,gr7 ; 32 bit result
+ set_gr_immed 0xffff,gr8
+ set_spr_immed 1,iacc0h
+ set_spr_limmed 0xfffe,0x0000,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 0xffff,gr8
+ test_gr_immed 0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff
+ test_spr_immed 0,iacc0h
+smsss26:
+ set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result
+ set_gr_limmed 0x0001,0x0000,gr8
+ set_spr_immed 2,iacc0h
+ set_spr_immed 1,iacc0l
+ smsss gr7,gr8
+ test_gr_limmed 0x0001,0x0000,gr8
+ test_gr_limmed 0x0001,0x0000,gr7
+ test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000
+ test_spr_immed 1,iacc0h
+smsss27:
+ set_gr_immed -2,gr7 ; almost max positive result
+ set_gr_immed -2,gr8
+ set_spr_limmed 0x7fff,0xffff,iacc0h
+ set_spr_limmed 0xffff,0xffff,iacc0l
+ smsss gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -2,gr7
+ test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2)
+ test_spr_limmed 0x7fff,0xffff,iacc0h
+smsss28:
+ set_gr_immed 0,gr7 ; max positive result
+ set_gr_immed 0,gr8
+ set_spr_limmed 0x7fff,0xffff,iacc0h
+ set_spr_limmed 0xffff,0xffff,iacc0l
+ smsss gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed 0,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0)
+ test_spr_limmed 0x7fff,0xffff,iacc0h
+smsss29:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0x4000,0x0000,iacc0h
+ set_spr_limmed 0x7fff,0xffff,iacc0l
+ smsss gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff -
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
+smsss30:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0x4000,0x0000,iacc0h
+ set_spr_limmed 0x8000,0x0000,iacc0l
+ smsss gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 -
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
+
+smsss31:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_spr_limmed 0xffff,0xffff,iacc0l
+ set_spr_limmed 0x7fff,0xffff,iacc0h
+ smsss gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff -
+ test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000
+smsss32:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_immed 1,iacc0l
+ set_spr_limmed 0xbfff,0xffff,iacc0h
+ smsss gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 -
+ test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff
+smsss33:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_immed 0,iacc0l
+ set_spr_limmed 0xbfff,0xffff,iacc0h
+ smsss gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
+ test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
+smsss34:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
+ set_gr_limmed 0x7fff,0xffff,gr8
+ set_spr_limmed 0x0000,0x0000,iacc0l
+ set_spr_limmed 0x8000,0x0000,iacc0h
+ smsss gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000-
+ test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+
+
+ pass
--- /dev/null
+# frv testcase for smu $GRi,$GRj
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global smu
+smu1:
+ ; Positive operands
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 3,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 6,iacc0l
+ test_spr_immed 0,iacc0h
+smu2:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 1,gr7
+ test_gr_immed 2,gr8
+ test_spr_immed 2,iacc0l
+ test_spr_immed 0,iacc0h
+smu3:
+ set_gr_immed 2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ smu gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 2,iacc0l
+ test_spr_immed 0,iacc0h
+smu4:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 0,iacc0l
+ test_spr_immed 0,iacc0h
+smu5:
+ set_gr_immed 2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ smu gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed 2,gr7
+ test_spr_immed 0,iacc0l
+ test_spr_immed 0,iacc0h
+smu6:
+ set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x3fff,0xffff,gr7
+ test_spr_limmed 0x7fff,0xfffe,iacc0l
+ test_spr_immed 0,iacc0h
+smu7:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0000,iacc0l
+ test_spr_immed 0,iacc0h
+smu8:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed 4,gr8
+ smu gr7,gr8
+ test_gr_immed 4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_immed 0,iacc0l
+ test_spr_immed 1,iacc0h
+smu9:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
+ set_gr_limmed 0x7fff,0xffff,gr8
+ smu gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_immed 0x00000001,iacc0l
+ test_spr_limmed 0x3fff,0xffff,iacc0h
+smu10:
+ ; Mixed operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed 2,gr8
+ smu gr7,gr8
+ test_gr_immed 2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed -6,iacc0l
+ test_spr_immed -1,iacc0h
+smu11:
+ set_gr_immed 3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 3,gr7
+ test_spr_immed -6,iacc0l
+ test_spr_immed -1,iacc0h
+smu12:
+ set_gr_immed 1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 1,gr7
+ test_spr_immed -2,iacc0l
+ test_spr_immed -1,iacc0h
+smu13:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed 1,gr8
+ smu gr7,gr8
+ test_gr_immed 1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed -2,iacc0l
+ test_spr_immed -1,iacc0h
+smu14:
+ set_gr_immed 0,gr7 ; multiply by 0
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed 0,gr7
+ test_spr_immed 0,iacc0l
+ test_spr_immed 0,iacc0h
+smu15:
+ set_gr_immed -2,gr7 ; multiply by 0
+ set_gr_immed 0,gr8
+ smu gr7,gr8
+ test_gr_immed 0,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 0,iacc0l
+ test_spr_immed 0,iacc0h
+smu16:
+ set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x2000,0x0001,gr7
+ test_spr_limmed 0xbfff,0xfffe,iacc0l
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smu17:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0000,iacc0l
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smu18:
+ set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0x4000,0x0001,gr7
+ test_spr_limmed 0x7fff,0xfffe,iacc0l
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smu19:
+ set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
+ set_gr_immed -4,gr8
+ smu gr7,gr8
+ test_gr_immed -4,gr8
+ test_gr_limmed 0x4000,0x0000,gr7
+ test_spr_limmed 0x0000,0x0000,iacc0l
+ test_spr_limmed 0xffff,0xffff,iacc0h
+smu20:
+ set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
+ set_gr_limmed 0x8000,0x0000,gr8
+ smu gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x7fff,0xffff,gr7
+ test_spr_limmed 0x8000,0x0000,iacc0l
+ test_spr_limmed 0xc000,0x0000,iacc0h
+smu21:
+ ; Negative operands
+ set_gr_immed -3,gr7 ; multiply small numbers
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -3,gr7
+ test_spr_immed 6,iacc0l
+ test_spr_immed 0,iacc0h
+smu22:
+ set_gr_immed -1,gr7 ; multiply by 1
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_immed -1,gr7
+ test_spr_immed 2,iacc0l
+ test_spr_immed 0,iacc0h
+smu23:
+ set_gr_immed -2,gr7 ; multiply by 1
+ set_gr_immed -1,gr8
+ smu gr7,gr8
+ test_gr_immed -1,gr8
+ test_gr_immed -2,gr7
+ test_spr_immed 2,iacc0l
+ test_spr_immed 0,iacc0h
+smu24:
+ set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0xc000,0x0001,gr7
+ test_spr_limmed 0x7fff,0xfffe,iacc0l
+ test_spr_immed 0,iacc0h
+smu25:
+ set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
+ set_gr_immed -2,gr8
+ smu gr7,gr8
+ test_gr_immed -2,gr8
+ test_gr_limmed 0xc000,0x0000,gr7
+ test_spr_limmed 0x8000,0x0000,iacc0l
+ test_spr_immed 0,iacc0h
+smu26:
+ set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
+ set_gr_immed -4,gr8
+ smu gr7,gr8
+ test_gr_immed -4,gr8
+ test_gr_limmed 0xc000,0x0000,gr7
+ test_spr_immed 0x00000000,iacc0l
+ test_spr_immed 1,iacc0h
+smu27:
+ set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
+ set_gr_limmed 0x8000,0x0001,gr8
+ smu gr7,gr8
+ test_gr_limmed 0x8000,0x0001,gr8
+ test_gr_limmed 0x8000,0x0001,gr7
+ test_spr_immed 0x00000001,iacc0l
+ test_spr_limmed 0x3fff,0xffff,iacc0h
+smu28:
+ set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
+ set_gr_limmed 0x8000,0x0000,gr8
+ smu gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+ test_gr_limmed 0x8000,0x0000,gr7
+ test_spr_immed 0x00000000,iacc0l
+ test_spr_limmed 0x4000,0x0000,iacc0h
+
+ pass
--- /dev/null
+# frv testcase for subss $GRi,$GRj,$GRk
+# mach: fr400
+
+ .include "../testutils.inc"
+
+ start
+
+ .global sub
+sub_no_saturate:
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ subss gr8,gr7,gr8
+ test_gr_immed 1,gr8
+
+ set_gr_immed 2,gr7
+ set_gr_immed 1,gr8
+ subss gr8,gr7,gr8
+ test_gr_limmed 0xffff,0xffff,gr8
+
+sub_saturate_neg:
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ subss gr8,gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+
+ set_gr_limmed 0x7fff,0xffff,gr7
+ set_gr_limmed 0xffff,0xfff0,gr8
+ subss gr8,gr7,gr8
+ test_gr_limmed 0x8000,0x0000,gr8
+
+sub_saturate_pos:
+ set_gr_limmed 0xffff,0xffff,gr7
+ set_gr_limmed 0x7fff,0xffff,gr8
+ subss gr8,gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+
+ set_gr_immed 0x0010,gr8
+ set_gr_limmed 0x8000,0x0000,gr7
+ subss gr8,gr7,gr8
+ test_gr_limmed 0x7fff,0xffff,gr8
+
+
+ pass
# frv testcase for udiv $GRi,$GRj,$GRk
-# mach: all
+# mach: fr400
.include "../testutils.inc"
# frv testcase for udivi $GRi,$s12,$GRk
-# mach: all
+# mach: fr400
.include "../testutils.inc"
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "frv fr500"
+ set all_machs "frv fr500 fr550"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# FRV testcase for dcpl GRi,GRj,lock
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# FRV testcase for dcul GRi
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for mqaddhss $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for mqaddhus $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for mqsubhss $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500
.include "../testutils.inc"
--- /dev/null
+# FRV simulator testsuite.
+
+if [istarget frv*-*] {
+ # load support procs (none yet)
+ # load_lib cgen.exp
+ # all machines
+ set all_machs "fr550"
+ set cpu_option -mcpu
+
+ # The .cgs suffix is for "cgen .s".
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
+}
--- /dev/null
+# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global maddhss
+maddhss:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x1233,0x5677,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc4,1
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc4,1
+ cmaddhss fr11,fr11,fr13,cc4,1
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x1233,0x5677,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc5,0
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc5,0
+ cmaddhss fr11,fr11,fr13,cc5,0
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc4,0
+ cmaddhss fr11,fr11,fr13,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc5,1
+ cmaddhss fr11,fr11,fr13,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc6,1
+ cmaddhss fr11,fr11,fr13,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+;
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhss fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhss fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmaddhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhss fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhss fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmaddhss.p fr10,fr10,fr12,cc7,1
+ cmaddhss fr11,fr11,fr13,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmaddhus
+cmaddhus:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x8000,0x7fff,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc4,1
+ cmaddhus fr11,fr11,fr13,cc4,1
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0xffff,0xffff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmaddhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x8000,0x7fff,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc5,0
+ cmaddhus fr11,fr11,fr13,cc5,0
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0xffff,0xffff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0x0000,fr10
+ set_fr_iimmed 0x0000,0xdead,fr11
+ cmaddhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc4,0
+ cmaddhus fr11,fr11,fr13,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0x0000,fr10
+ set_fr_iimmed 0x0000,0xdead,fr11
+ cmaddhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc5,1
+ cmaddhus fr11,fr11,fr13,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0x0000,fr10
+ set_fr_iimmed 0x0000,0xdead,fr11
+ cmaddhus fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc6,0
+ cmaddhus fr11,fr11,fr13,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0x0000,fr10
+ set_fr_iimmed 0x0000,0xdead,fr11
+ cmaddhus fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmaddhus fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmaddhus fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmaddhus fr10,fr11,fr12,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmaddhus fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ cmaddhus fr10,fr11,fr12,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmaddhus.p fr10,fr10,fr12,cc7,0
+ cmaddhus fr11,fr11,fr13,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmcpxiu
+cmcpxiu:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 26,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 5,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x7fff,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8001,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0x00010001,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0001,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0000,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0xfffe,0x0001,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,1
+ test_accg_immed 1,accg0
+ test_acc_immed 0xfffb0003,acc0
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,1
+ test_accg_immed 1,accg0
+ test_acc_immed 0xfffc0002,acc0
+
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 26,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 5,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x7fff,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8001,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0x00010001,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0001,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0000,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0xfffe,0x0001,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,0
+ test_accg_immed 1,accg0
+ test_acc_immed 0xfffb0003,acc0
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,0
+ test_accg_immed 1,accg0
+ test_acc_immed 0xfffc0002,acc0
+
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0x0001,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0x0001,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc2,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0x0001,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 3,5,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 1,3,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 0,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 0x0001,2,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 0x0001,4,fr8
+ cmcpxiu fr7,fr8,acc0,cc3,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x0000,0x8000,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0x0001,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxiu fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ pass
--- /dev/null
+# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmcpxru
+cmcpxru:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 14,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 1,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x7ffd,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0xffff,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0x0001ffff,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0001,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0000,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_accg_immed 0,accg0
+ test_acc_limmed 0xfffe,0x0001,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 14,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 1,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x7ffd,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0xffff,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0x0001ffff,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0001,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0000,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_accg_immed 0,accg0
+ test_acc_limmed 0xfffe,0x0001,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc0,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc1,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc2,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+;
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_fr_iimmed 4,2,fr7 ; multiply small numbers
+ set_fr_iimmed 5,3,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 3,1,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
+ set_fr_iimmed 4,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc3,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x0000,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
+ set_fr_iimmed 0xffff,0x0001,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmcpxru fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+
+ pass
--- /dev/null
+# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmmachs
+cmmachs:
+ set_spr_immed 0x1b1b,cccr
+
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0007,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0001,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0001,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xbffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xbffd,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x3ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x3ffd,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffd,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffd,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc003,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc003,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc005,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc005,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3ffec006,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x7ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x7ffec006,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+;;;;;;;;;;;;
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed -128,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed -128,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0 ; saturation
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0007,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0001,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0001,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xbffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xbffd,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x3ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x3ffd,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffd,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffd,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc003,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc003,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc005,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc005,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3ffec006,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x7ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x7ffec006,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+;
+ ; Positive operands
+ set_spr_immed 0x0,msr0
+ set_accg_immed 0x0,accg0
+ set_acc_immed 0x0,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x0,acc1
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ cmmachs fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachs fr7,fr8,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ cmmachs fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachs fr7,fr8,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ cmmachs fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ cmmachs fr7,fr8,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ cmmachs fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ cmmachs fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ cmmachs fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachs fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachs fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ cmmachs fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachs fr7,fr8,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ pass
--- /dev/null
+# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmmachu
+cmmachu:
+ set_spr_immed 0x1b1b,cccr
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x00020006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x00020006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x40010007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x40010007,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x8001,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x8001,0x0007,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x7fff,0x0008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x7fff,0x0008,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x00020006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x00020006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x40010007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x40010007,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x8001,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x8001,0x0007,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x7fff,0x0008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x7fff,0x0008,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+;
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ cmmachu fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ cmmachu fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ cmmachu fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ cmmachu fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ cmmachu fr7,fr8,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ cmmachu fr7,fr8,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+
+ pass
--- /dev/null
+# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmqaddhss
+cmqaddhss:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x1233,0x5677,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc4,1
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc4,1
+ cmqaddhss fr12,fr12,fr16,cc4,1
+ test_fr_limmed 0x0002,0x0002,fr14
+ test_fr_limmed 0xfffe,0xfffe,fr15
+ test_fr_limmed 0x7fff,0x0000,fr16
+ test_fr_limmed 0x0000,0x8000,fr17
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x1233,0x5677,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc5,0
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc5,0
+ cmqaddhss fr12,fr12,fr16,cc5,0
+ test_fr_limmed 0x0002,0x0002,fr14
+ test_fr_limmed 0xfffe,0xfffe,fr15
+ test_fr_limmed 0x7fff,0x0000,fr16
+ test_fr_limmed 0x0000,0x8000,fr17
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc4,0
+ cmqaddhss fr12,fr12,fr16,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc5,1
+ cmqaddhss fr12,fr12,fr16,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc2,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc6,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc6,1
+ cmqaddhss fr12,fr12,fr16,cc6,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+;
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhss fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhss fr10,fr12,fr14,cc3,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqaddhss fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ cmqaddhss fr10,fr12,fr14,cc7,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ cmqaddhss.p fr10,fr10,fr14,cc7,1
+ cmqaddhss fr12,fr12,fr16,cc7,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmqaddhus
+cmqaddhus:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc4,1
+ test_fr_limmed 0x8000,0x7fff,fr14
+ test_fr_limmed 0xffff,0xffff,fr15
+ test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc4,1
+ cmqaddhus fr12,fr12,fr16,cc4,1
+ test_fr_limmed 0x0004,0x0002,fr14
+ test_fr_limmed 0x0002,0x0002,fr15
+ test_fr_limmed 0xffff,0xffff,fr16
+ test_fr_limmed 0xffff,0xffff,fr17
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc5,0
+ test_fr_limmed 0x8000,0x7fff,fr14
+ test_fr_limmed 0xffff,0xffff,fr15
+ test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc5,0
+ cmqaddhus fr12,fr12,fr16,cc5,0
+ test_fr_limmed 0x0004,0x0002,fr14
+ test_fr_limmed 0x0002,0x0002,fr15
+ test_fr_limmed 0xffff,0xffff,fr16
+ test_fr_limmed 0xffff,0xffff,fr17
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc4,0
+ cmqaddhus fr12,fr12,fr16,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc5,1
+ cmqaddhus fr12,fr12,fr16,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc2,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc6,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc6,0
+ cmqaddhus fr12,fr12,fr16,cc6,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqaddhus fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqaddhus fr10,fr12,fr14,cc3,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ cmqaddhus fr10,fr12,fr14,cc7,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqaddhus.p fr10,fr10,fr14,cc7,0
+ cmqaddhus fr12,fr12,fr16,cc7,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmqmachs
+cmqmachs:
+ set_spr_immed 0x1b1b,cccr
+
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0,0x7ffe,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0,0x7ffe,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8008,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7fff,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7fff,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7ffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7ffd,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x3ffb,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x3ffb,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0002,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffb,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffb,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0008,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffd,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffd,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0009,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff0009,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fffbffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fffbffd,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0,0x7ffe,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0,0x7ffe,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8008,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7fff,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7fff,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7ffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7ffd,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x3ffb,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x3ffb,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0002,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffb,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffb,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0008,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffd,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffd,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0009,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff0009,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fffbffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fffbffd,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0x7f,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2 ; saturation
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0x7f,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2 ; saturation
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0x7f,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2 ; saturation
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+;
+ ; Positive operands
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ cmqmachs fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachs fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ cmqmachs fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ cmqmachs fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmqmachs fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachs fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0x7f,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ cmqmachs fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x80,accg0 ; saturation
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2 ; saturation
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ pass
+
+
--- /dev/null
+# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmqmachu
+cmqmachu:
+ set_spr_immed 0x1b1b,cccr
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 2,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 2,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8000,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc0,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x00018000,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x00018000,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff8007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff8007,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x4001,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x4001,0x8000,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x3ffd,0x8008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x3ffd,0x8008,acc1
+ test_accg_immed 1,accg2
+ test_acc_limmed 0x3fff,0x8001,acc2
+ test_accg_immed 1,accg3
+ test_acc_limmed 0x3fff,0x8001,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc4,1
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 2,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 2,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8000,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc1,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x00018000,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x00018000,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff8007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff8007,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x4001,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x4001,0x8000,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x3ffd,0x8008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x3ffd,0x8008,acc1
+ test_accg_immed 1,accg2
+ test_acc_limmed 0x3fff,0x8001,acc2
+ test_accg_immed 1,accg3
+ test_acc_limmed 0x3fff,0x8001,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc5,0
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc0,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc4,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc1,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc5,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc2,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc2,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc6,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc6,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+;
+ set_spr_immed 0,msr0
+ set_accg_immed 0x00000011,accg0
+ set_acc_immed 0x11111111,acc0
+ set_accg_immed 0x00000022,accg1
+ set_acc_immed 0x22222222,acc1
+ set_accg_immed 0x00000033,accg2
+ set_acc_immed 0x33333333,acc2
+ set_accg_immed 0x00000044,accg3
+ set_acc_immed 0x44444444,acc3
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ cmqmachu fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ cmqmachu fr8,fr10,acc0,cc3,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc3,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmqmachu fr8,fr10,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x00000011,accg0
+ test_acc_immed 0x11111111,acc0
+ test_accg_immed 0x00000022,accg1
+ test_acc_immed 0x22222222,acc1
+ test_accg_immed 0x00000033,accg2
+ test_acc_immed 0x33333333,acc2
+ test_accg_immed 0x00000044,accg3
+ test_acc_immed 0x44444444,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ cmqmachu fr8,fr10,acc0,cc7,0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmqmachu fr8,fr10,acc0,cc7,1
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0 ; saturation
+ test_acc_immed 0xffffffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xffffffff,acc1
+ test_accg_immed 0xff,accg2 ; saturation
+ test_acc_immed 0xffffffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_immed 0xffffffff,acc3
+
+ pass
--- /dev/null
+# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubhss
+msubhss:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0x4111,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x4111,0xdead,fr14
+ test_fr_limmed 0x0123,0x4567,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x1235,0x5679,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc4,1
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc4,1
+ cmqsubhss fr12,fr10,fr16,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x8000,0x8000,fr16
+ test_fr_limmed 0x8001,0x8001,fr17
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0x4111,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x4111,0xdead,fr14
+ test_fr_limmed 0x0123,0x4567,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x1235,0x5679,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc5,0
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc5,0
+ cmqsubhss fr12,fr10,fr16,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x8000,0x8000,fr16
+ test_fr_limmed 0x8001,0x8001,fr17
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc4,0
+ cmqsubhss fr12,fr10,fr16,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc5,1
+ cmqsubhss fr12,fr10,fr16,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc2,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc6,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc6,1
+ cmqsubhss fr12,fr10,fr16,cc6,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ cmqsubhss fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ cmqsubhss fr10,fr12,fr14,cc3,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ cmqsubhss fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhss fr10,fr12,fr14,cc7,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ cmqsubhss.p fr10,fr10,fr14,cc7,1
+ cmqsubhss fr12,fr10,fr16,cc7,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_fr_limmed 0x4444,0x4444,fr17
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmqsubhus
+cmqsubhus:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc0,1
+ test_fr_limmed 0x0123,0x4567,fr14
+ test_fr_limmed 0x7ffc,0x7ffd,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc4,1
+ cmqsubhus fr10,fr12,fr16,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x0001,0x0000,fr16
+ test_fr_limmed 0x0000,0x0000,fr17
+ test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc1,0
+ test_fr_limmed 0x0123,0x4567,fr14
+ test_fr_limmed 0x7ffc,0x7ffd,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc5,0
+ cmqsubhus fr10,fr12,fr16,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x0001,0x0000,fr16
+ test_fr_limmed 0x0000,0x0000,fr17
+ test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc0,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc4,0
+ cmqsubhus fr10,fr12,fr16,cc4,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_fr_limmed 0x4444,0x4444,fr17
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc1,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc5,1
+ cmqsubhus fr10,fr12,fr16,cc5,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_fr_limmed 0x4444,0x4444,fr17
+
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc2,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc2,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc6,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc6,0
+ cmqsubhus fr10,fr12,fr16,cc6,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_fr_limmed 0x4444,0x4444,fr17
+;
+ set_fr_iimmed 0x1111,0x1111,fr14
+ set_fr_iimmed 0x2222,0x2222,fr15
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ cmqsubhus fr10,fr12,fr14,cc3,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc3,0
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ cmqsubhus fr10,fr12,fr14,cc7,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x3333,0x3333,fr16
+ set_fr_iimmed 0x4444,0x4444,fr17
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ cmqsubhus.p fr10,fr10,fr14,cc7,0
+ cmqsubhus fr10,fr12,fr16,cc7,1
+ test_fr_limmed 0x1111,0x1111,fr14
+ test_fr_limmed 0x2222,0x2222,fr15
+ test_fr_limmed 0x3333,0x3333,fr16
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_fr_limmed 0x4444,0x4444,fr17
+
+ pass
--- /dev/null
+# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmsubhss
+cmsubhss:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xdead,0x4111,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x4111,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x1235,0x5679,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc4,1
+ cmsubhss fr11,fr10,fr13,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x8000,0x8000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xdead,0x4111,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x4111,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x1235,0x5679,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc5,0
+ cmsubhss fr11,fr10,fr13,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x8000,0x8000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc4,0
+ cmsubhss fr11,fr10,fr13,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc5,1
+ cmsubhss fr11,fr10,fr13,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc6,1
+ cmsubhss fr11,fr10,fr13,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+;
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ cmsubhss fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ cmsubhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhss fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ cmsubhss fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhss fr10,fr11,fr12,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhss fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ cmsubhss.p fr10,fr10,fr12,cc7,1
+ cmsubhss fr11,fr10,fr13,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global cmsubhus
+cmsubhus:
+ set_spr_immed 0x1b1b,cccr
+
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc0,1
+ test_fr_limmed 0x7ffc,0x7ffd,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc4,1
+ cmsubhus fr10,fr11,fr13,cc4,1
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x0000,0x0000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc1,0
+ test_fr_limmed 0x7ffc,0x7ffd,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc5,0
+ cmsubhus fr10,fr11,fr13,cc5,0
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x0000,0x0000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc0,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc4,0
+ cmsubhus fr10,fr11,fr13,cc4,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc1,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc5,1
+ cmsubhus fr10,fr11,fr13,cc5,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc2,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc2,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc6,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc6,0
+ cmsubhus fr10,fr11,fr13,cc6,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+;
+ set_fr_iimmed 0xdead,0xbeef,fr12
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ cmsubhus fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ cmsubhus fr10,fr11,fr12,cc3,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc3,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ cmsubhus fr10,fr11,fr12,cc7,0
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ cmsubhus fr10,fr11,fr12,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xbeef,0xdead,fr13
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ cmsubhus.p fr10,fr10,fr12,cc7,0
+ cmsubhus fr10,fr11,fr13,cc7,1
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_fr_limmed 0xbeef,0xdead,fr13
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ pass
--- /dev/null
+# FRV testcase for dcpl GRi,GRj,lock
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global dcpl
+dcpl:
+ or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
+
+ ; preload and lock all the lines in set 0 of the data cache
+ set_gr_immed 0x70000,gr10
+ dcpl gr10,gr0,1
+ set_mem_immed 0x11111111,gr10
+ test_mem_immed 0x11111111,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 1,gr11
+ dcpl gr10,gr11,1
+ set_mem_immed 0x22222222,gr10
+ test_mem_immed 0x22222222,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 63,gr11
+ dcpl gr10,gr11,1
+ set_mem_immed 0x33333333,gr10
+ test_mem_immed 0x33333333,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 64,gr11
+ dcpl gr10,gr11,1
+ set_mem_immed 0x44444444,gr10
+ test_mem_immed 0x44444444,gr10
+
+ ; Now write to another address which should be in the same set
+ ; the write should go through to memory, since all the lines in the
+ ; set are locked
+ inc_gr_immed 0x2000,gr10
+ set_mem_immed 0xdeadbeef,gr10
+ test_mem_immed 0xdeadbeef,gr10
+
+ ; Invalidate the data cache. Only the last value stored should have made
+ ; it through to memory
+ set_gr_immed 0x70000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0xdeadbeef,gr10
+
+ pass
--- /dev/null
+# FRV testcase for dcul GRi
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global dcul
+dcul:
+ or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
+
+ ; preload and lock all the lines in set 0 of the data cache
+ set_gr_immed 0x70000,gr10
+ lock_data_cache gr10
+ set_mem_immed 0x11111111,gr10
+ test_mem_immed 0x11111111,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 1,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x22222222,gr10
+ test_mem_immed 0x22222222,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 63,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x33333333,gr10
+ test_mem_immed 0x33333333,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 64,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x44444444,gr10
+ test_mem_immed 0x44444444,gr10
+
+ ; Now write to another address which should be in the same set
+ ; the write should go through to memory, since all the lines in the
+ ; set are locked
+ inc_gr_immed 0x2000,gr10
+ set_mem_immed 0xdeadbeef,gr10
+ test_mem_immed 0xdeadbeef,gr10
+
+ ; Invalidate the data cache. Only the last value stored should have made
+ ; it through to memory
+ set_gr_immed 0x70000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0,gr10
+
+ inc_gr_immed 0x2000,gr10
+ invalidate_data_cache gr10
+ test_mem_immed 0xdeadbeef,gr10
+
+ ; Now preload load and lock all the lines in set 0 of the data cache
+ ; again
+ set_gr_immed 0x70000,gr10
+ lock_data_cache gr10
+ set_mem_immed 0x11111111,gr10
+ test_mem_immed 0x11111111,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 1,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x22222222,gr10
+ test_mem_immed 0x22222222,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 63,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x33333333,gr10
+ test_mem_immed 0x33333333,gr10
+
+ inc_gr_immed 0x2000,gr10
+ set_gr_immed 64,gr11
+ lock_data_cache gr10
+ set_mem_immed 0x44444444,gr10
+ test_mem_immed 0x44444444,gr10
+
+ ; unlock one line
+ set_gr_immed 0x78000,gr10
+ dcul gr10
+
+ ; Now write to another address which should be in the same set.
+ set_gr_immed 0x7a000,gr10
+ set_mem_immed 0xbeefdead,gr10
+
+ ; All of the stored values should be retrievable
+
+ set_gr_immed 0x70000,gr10
+ test_mem_immed 0x11111111,gr10
+
+ inc_gr_immed 0x2000,gr10
+ test_mem_immed 0x22222222,gr10
+
+ inc_gr_immed 0x2000,gr10
+ test_mem_immed 0x33333333,gr10
+
+ inc_gr_immed 0x2000,gr10
+ test_mem_immed 0x44444444,gr10
+
+ inc_gr_immed 0x2000,gr10
+ test_mem_immed 0xdeadbeef,gr10
+
+ inc_gr_immed 0x2000,gr10
+ test_mem_immed 0xbeefdead,gr10
+
+ pass
--- /dev/null
+# frv testcase for mabshs $FRj,$FRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mabshs
+mabshs:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ mabshs fr10,fr11
+ test_fr_limmed 0x0000,0x0000,fr11
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0xffff,fr10
+ mabshs fr10,fr11
+ test_fr_limmed 0x0001,0x0001,fr11
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7fff,0x8001,fr10
+ mabshs fr10,fr11
+ test_fr_limmed 0x7fff,0x7fff,fr11
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7fff,0x8000,fr10
+ mabshs fr10,fr11
+ test_fr_limmed 0x7fff,0x7fff,fr11
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8000,0x7fff,fr10
+ mabshs fr10,fr11
+ test_fr_limmed 0x7fff,0x7fff,fr11
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7fff,0x8000,fr10
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ mabshs.p fr10,fr12
+ mabshs fr11,fr13
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for maddaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global maddaccs
+maddaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0xdead0000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x0000beef,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdead,0xbeef,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xbeef,0xdead,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x11111111,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x2345,0x6789,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg3
+ test_acc_limmed 0x1234,0x5677,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5677,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffe7ffe,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x00020001,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x80,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xfffffffe,acc1
+ maddaccs acc0,acc3
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg4
+ set_acc_immed 0x00000001,acc4
+ set_accg_immed 0x7f,accg5
+ set_acc_immed 0xffffffff,acc5
+ maddaccs.p acc0,acc1
+ maddaccs acc4,acc5
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0002,acc1
+ test_accg_immed 0x7f,accg5
+ test_acc_limmed 0xffff,0xffff,acc5
+
+ pass
--- /dev/null
+# frv testcase for maddhss $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global maddhss
+maddhss:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0x1233,0x5677,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ maddhss fr10,fr11,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ maddhss fr10,fr11,fr12
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ maddhss.p fr10,fr10,fr12
+ maddhss fr11,fr11,fr13
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for maddhus $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global maddhus
+maddhus:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0xbeef,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0x2345,0x6789,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0x8000,0x7fff,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xfffe,0xfffe,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ maddhus fr10,fr11,fr12
+ test_fr_limmed 0xffff,0xffff,fr12
+ test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ maddhus.p fr10,fr10,fr12
+ maddhus fr11,fr11,fr13
+ test_fr_limmed 0x0002,0x0002,fr12
+ test_fr_limmed 0xffff,0xffff,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for masaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global masaccs
+masaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0xdead0000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x0000beef,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0xdead,0xbeef,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdeac,0x4111,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0xbeef,0xdead,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0x4111,0xdead,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x11111111,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x2345,0x6789,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0123,0x4567,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 1,accg2
+ test_acc_limmed 0x1234,0x5677,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x1234,0x5677,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffe7ffe,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x00020001,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xfffc,0x7ffd,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x80,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xfffffffe,acc1
+ masaccs acc0,acc2
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x80,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0003,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg4
+ set_acc_immed 0x00000001,acc4
+ set_accg_immed 0x7f,accg5
+ set_acc_immed 0xffffffff,acc5
+ masaccs.p acc0,acc0
+ masaccs acc4,acc4
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0000,acc1
+ test_accg_immed 0x7f,accg4
+ test_acc_limmed 0xffff,0xffff,acc4
+ test_accg_immed 0x80,accg5
+ test_acc_limmed 0x0000,0x0002,acc5
+
+ pass
--- /dev/null
+# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mdaddaccs
+mdaddaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0xdead0000,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x0000beef,acc3
+ mdaddaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdead,0xbeef,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x11111111,acc3
+ mdaddaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0xbeef,0xdead,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x2345,0x6789,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ mdaddaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg2
+ test_acc_limmed 0x1234,0x5677,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5677,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffe7ffe,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x00020001,acc1
+ set_accg_immed 0x80,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xfffffffe,acc3
+ mdaddaccs acc0,acc2
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ mdaddaccs acc0,acc2
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0002,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ pass
--- /dev/null
+# frv testcase for mdasaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mdasaccs
+mdasaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0xdead0000,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x0000beef,acc3
+ mdasaccs acc0,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0000,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0000,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0xdead,0xbeef,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdeac,0x4111,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x11111111,acc3
+ mdasaccs acc0,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0xbeef,0xdead,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0x4111,0xdead,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x2345,0x6789,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0123,0x4567,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ mdasaccs acc0,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x1234,0x5677,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0x1234,0x5679,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x1234,0x5677,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffe7ffe,acc0
+ set_accg_immed 0x0,accg1
+ set_acc_immed 0x00020001,acc1
+ set_accg_immed 0x80,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xfffffffe,acc3
+ mdasaccs acc0,acc0
+ test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xfffc,0x7ffd,acc1
+ test_accg_immed 0x80,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0003,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ mdasaccs acc0,acc0
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0000,acc1
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0002,acc3
+
+ pass
--- /dev/null
+# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mdsubaccs
+mdsubaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0xdead0000,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x0000beef,acc3
+ mdsubaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdeac,0x4111,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x11111111,acc3
+ mdsubaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0x4111,0xdead,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0123,0x4567,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x12345678,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ mdsubaccs acc0,acc2
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0x1234,0x5679,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffffffe,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xfffffffe,acc1
+ set_accg_immed 0x80,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0,accg3
+ set_acc_immed 0x00000002,acc3
+ mdsubaccs acc0,acc2
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg2
+ set_acc_immed 0x00000001,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0x00000000,acc3
+ mdsubaccs acc0,acc2
+ test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0000,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ pass
--- /dev/null
+# frv testcase for mmachs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mmachs
+mmachs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0007,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x4000,0x0001,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x4000,0x0001,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xffff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xffff,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0xbffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0xbffd,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x3ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x3ffd,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffd,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffd,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc003,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc003,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xc005,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xc005,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3ffec006,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x7ffec006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x7ffec006,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ mmachs fr7,fr8,acc0
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmachs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ pass
+
+
--- /dev/null
+# frv testcase for mmachu $GRi,$GRj,$GRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mmachu
+mmachu:
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0001,0x0006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0001,0x0006,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x00020006,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x00020006,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x40010007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x40010007,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x8001,0x0007,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x8001,0x0007,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x7fff,0x0008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x7fff,0x0008,acc1
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0xffff,0x0000,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ mmachu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ pass
--- /dev/null
+# frv testcase for mmrdhs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mmrdhs
+mmrdhs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr7 ; multiply small numbers
+ set_fr_iimmed 3,2,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_immed -6,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed -6,acc1
+
+ set_fr_iimmed 0,1,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_immed -6,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed -6,acc1
+
+ set_fr_iimmed 2,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,2,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_immed -8,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed -8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0x7ffa,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0x7ffa,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xfffe,0xfffa,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xfffe,0xfffa,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xbfff,0xfff9,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xbfff,0xfff9,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xbfff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xbfff,0xffff,acc1
+
+ set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xc000,0x0001,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xc000,0x0001,acc1
+
+ set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xc000,0x0001,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xc000,0x0001,acc1
+
+ set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xc000,0x4003,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xc000,0x4003,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xc000,0xc003,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xc000,0xc003,acc1
+
+ set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x4003,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x4003,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x3ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x3ffd,acc1
+
+ set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x3ffb,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x3ffb,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_immed 0xc0013ffa,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0xc0013ffa,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg0
+ test_acc_immed 0x80013ffa,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_immed 0x80013ffa,acc1
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 0xffff,1,fr7
+ set_fr_iimmed 1,0xffff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_fr_iimmed 0x8000,0x0000,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0,1,fr7
+ set_fr_iimmed 1,1,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmrdhs fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ pass
+
+
--- /dev/null
+# frv testcase for mmrdhu $GRi,$GRj,$GRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mmrdhu
+mmrdhu:
+ set_accg_immed 0x80,accg0
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+
+ set_fr_iimmed 3,2,fr7 ; multiply small numbers
+ set_fr_iimmed 2,3,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_immed 0xfffffffa,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xfffffffa,acc1
+
+ set_fr_iimmed 1,2,fr7 ; multiply by 1
+ set_fr_iimmed 2,1,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_immed 0xfffffff8,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xfffffff8,acc1
+
+ set_fr_iimmed 0,2,fr7 ; multiply by 0
+ set_fr_iimmed 2,0,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_immed 0xfffffff8,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_immed 0xfffffff8,acc1
+
+ set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0x7ffa,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0x7ffa,acc1
+
+ set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xfffe,0xfffa,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xfffe,0xfffa,acc1
+
+ set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xfffd,0xfffa,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xfffd,0xfffa,acc1
+
+ set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xbffe,0xfff9,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xbffe,0xfff9,acc1
+
+ set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0x7ffe,0xfff9,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0x7ffe,0xfff9,acc1
+
+ set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0x7e,accg0
+ test_acc_limmed 0x8000,0xfff8,acc0
+ test_accg_immed 0x7e,accg1
+ test_acc_limmed 0x8000,0xfff8,acc1
+
+ set_accg_immed 0,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 1,1,fr7
+ set_fr_iimmed 1,1,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ set_fr_iimmed 0x0000,0xffff,fr7
+ set_fr_iimmed 0xffff,0xffff,fr8
+ mmrdhu fr7,fr8,acc0
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+
+ pass
--- /dev/null
+# frv testcase for mqaddhss $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqaddhss
+mqaddhss:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ mqaddhss fr10,fr12,fr14
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ mqaddhss fr10,fr12,fr14
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ mqaddhss fr10,fr12,fr14
+ test_fr_limmed 0x1233,0x5677,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0xffff,0xfffe,fr12
+ set_fr_iimmed 0xfffe,0xfffe,fr13
+ mqaddhss fr10,fr12,fr14
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x7fff,0x0000,fr12
+ set_fr_iimmed 0x0000,0x8000,fr13
+ mqaddhss.p fr10,fr10,fr14
+ mqaddhss fr12,fr12,fr16
+ test_fr_limmed 0x0002,0x0002,fr14
+ test_fr_limmed 0xfffe,0xfffe,fr15
+ test_fr_limmed 0x7fff,0x0000,fr16
+ test_fr_limmed 0x0000,0x8000,fr17
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for mqaddhus $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqaddhus
+mqaddhus:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ mqaddhus fr10,fr12,fr14
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ mqaddhus fr10,fr12,fr14
+ test_fr_limmed 0xbeef,0xdead,fr14
+ test_fr_limmed 0x2345,0x6789,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xfffe,fr11
+ set_fr_iimmed 0x0002,0x0001,fr12
+ set_fr_iimmed 0x0001,0x0002,fr13
+ mqaddhus fr10,fr12,fr14
+ test_fr_limmed 0x8000,0x7fff,fr14
+ test_fr_limmed 0xffff,0xffff,fr15
+ test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0002,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0xfffe,0xfffe,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ mqaddhus.p fr10,fr10,fr14
+ mqaddhus fr12,fr12,fr16
+ test_fr_limmed 0x0004,0x0002,fr14
+ test_fr_limmed 0x0002,0x0002,fr15
+ test_fr_limmed 0xffff,0xffff,fr16
+ test_fr_limmed 0xffff,0xffff,fr17
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for mqmachs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqmachs
+mqmachs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0,0x7ffe,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0,0x7ffe,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8008,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7fff,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7fff,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7ffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7ffd,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x3ffb,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x3ffb,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0002,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffb,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffb,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0008,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffd,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffd,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0009,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff0009,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fffbffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fffbffd,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ pass
+
+
--- /dev/null
+# frv testcase for mqmachu $GRi,$GRj,$GRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqmachu
+mqmachu:
+ set_fr_iimmed 3,2,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 1,2,fr9 ; multiply by 1
+ set_fr_iimmed 2,1,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 2,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 2,acc3
+
+ set_fr_iimmed 0,2,fr8 ; multiply by 0
+ set_fr_iimmed 2,0,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8000,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
+ set_fr_iimmed 2,0x8000,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8006,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8006,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x00018000,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x00018000,acc3
+
+ set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff8007,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff8007,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x4001,0x8000,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x4001,0x8000,acc3
+
+ set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
+ set_fr_iimmed 0xffff,0xffff,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 1,accg0
+ test_acc_limmed 0x3ffd,0x8008,acc0
+ test_accg_immed 1,accg1
+ test_acc_limmed 0x3ffd,0x8008,acc1
+ test_accg_immed 1,accg2
+ test_acc_limmed 0x3fff,0x8001,acc2
+ test_accg_immed 1,accg3
+ test_acc_limmed 0x3fff,0x8001,acc3
+
+ set_accg_immed 0xff,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0xff,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0xff,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 1,1,fr9
+ set_fr_iimmed 1,1,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_fr_iimmed 0xffff,0x0000,fr8
+ set_fr_iimmed 0xffff,0xffff,fr10
+ set_fr_iimmed 0x0000,0xffff,fr9
+ set_fr_iimmed 0xffff,0xffff,fr11
+ mqmachu fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ pass
--- /dev/null
+# frv testcase for mqmacxhs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqmacxhs
+mqmacxhs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 0,2,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 6,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 6,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 2,1,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 0x3fff,2,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 8,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 8,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0,0x7ffe,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0,0x7ffe,acc3
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 0x4000,2,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8008,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7fff,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7fff,acc3
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 2,0xfffd,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 0xfffe,1,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x7ffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x7ffd,acc3
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0xfffe,0,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0x2001,0xfffe,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x8002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x8002,acc1
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x3fff,0x3ffb,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x3fff,0x3ffb,acc3
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0x4000,0xfffe,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x7fff,0x8000,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0002,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0002,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffb,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffb,acc3
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffe,0xfffd,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x0000,0x0008,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0008,acc1
+ test_accg_immed 0xff,accg2
+ test_acc_limmed 0xffff,0xbffd,acc2
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0xffff,0xbffd,acc3
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fff0009,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fff0009,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fffbffd,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fffbffd,acc3
+
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 0xffff,1,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+
+ pass
+
+
--- /dev/null
+# frv testcase for mqsubhss $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubhss
+msubhss:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0x0000,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0xbeef,fr13
+ mqsubhss fr10,fr12,fr14
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0x4111,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0x1234,0x5678,fr11
+ set_fr_iimmed 0xbeef,0x0000,fr12
+ set_fr_iimmed 0x1111,0x1111,fr13
+ mqsubhss fr10,fr12,fr14
+ test_fr_limmed 0x4111,0xdead,fr14
+ test_fr_limmed 0x0123,0x4567,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0xfffe,0xffff,fr13
+ mqsubhss fr10,fr12,fr14
+ test_fr_limmed 0x1235,0x5679,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8001,0x8001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ mqsubhss fr10,fr12,fr14
+ test_fr_limmed 0x8000,0x8000,fr14
+ test_fr_limmed 0x8000,0x8000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ set_fr_iimmed 0x8000,0x8000,fr12
+ set_fr_iimmed 0x8000,0x8000,fr13
+ mqsubhss.p fr10,fr10,fr14
+ mqsubhss fr12,fr10,fr16
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x8000,0x8000,fr16
+ test_fr_limmed 0x8001,0x8001,fr17
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for msubhus $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubhus
+msubhus:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0xdead,0xbeef,fr11
+ set_fr_iimmed 0x0000,0x0000,fr12
+ set_fr_iimmed 0x0000,0x0000,fr13
+ mqsubhus fr10,fr12,fr14
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0xdead,0xbeef,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0x1111,0x1111,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ mqsubhus fr10,fr12,fr14
+ test_fr_limmed 0x0123,0x4567,fr14
+ test_fr_limmed 0x7ffc,0x7ffd,fr15
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0001,fr11
+ set_fr_iimmed 0x0001,0x0002,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ mqsubhus fr10,fr12,fr14
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ set_fr_iimmed 0x0000,0x0001,fr12
+ set_fr_iimmed 0x0002,0x0003,fr13
+ mqsubhus.p fr10,fr10,fr14
+ mqsubhus fr10,fr12,fr16
+ test_fr_limmed 0x0000,0x0000,fr14
+ test_fr_limmed 0x0000,0x0000,fr15
+ test_fr_limmed 0x0001,0x0000,fr16
+ test_fr_limmed 0x0000,0x0000,fr17
+ test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for mqxmachs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqxmachs
+mqxmachs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 3,2,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 2,0,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 6,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 6,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 1,2,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 2,0x3fff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_immed 8,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 8,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0,0x7ffe,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0,0x7ffe,acc1
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 2,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8008,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8008,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x7fff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x7fff,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,2,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 1,0xfffe,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8002,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x7ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x7ffd,acc1
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0,0xfffe,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0xfffe,0x2001,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8002,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x3ffb,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x3ffb,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0xfffe,0x4000,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x8000,0x7fff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0002,acc3
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffb,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffb,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffd,0xfffe,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0008,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0008,acc3
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffd,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffd,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fff0009,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fff0009,acc3
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fffbffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fffbffd,acc1
+
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 1,0xffff,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmachs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ pass
+
+
--- /dev/null
+# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mqxmacxhs
+mqxmacxhs:
+ ; Positive operands
+ set_fr_iimmed 2,3,fr8 ; multiply small numbers
+ set_fr_iimmed 2,3,fr10
+ set_fr_iimmed 0,1,fr9 ; multiply by 0
+ set_fr_iimmed 0,2,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0,acc1
+ test_accg_immed 0,accg2
+ test_acc_immed 6,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 6,acc3
+
+ set_fr_iimmed 2,1,fr8 ; multiply by 1
+ set_fr_iimmed 2,1,fr10
+ set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
+ set_fr_iimmed 0x3fff,2,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_immed 8,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 8,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0,0x7ffe,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0,0x7ffe,acc1
+
+ set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
+ set_fr_iimmed 0x4000,2,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8008,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8008,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x7fff,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x7fff,acc1
+
+ ; Mixed operands
+ set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 2,0xfffd,fr10
+ set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
+ set_fr_iimmed 0xfffe,1,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8002,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x7ffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x7ffd,acc1
+
+ set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
+ set_fr_iimmed 0xfffe,0,fr10
+ set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
+ set_fr_iimmed 0x2001,0xfffe,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x8002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x8002,acc3
+ test_accg_immed 0,accg0
+ test_acc_limmed 0x3fff,0x3ffb,acc0
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x3fff,0x3ffb,acc1
+
+ set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
+ set_fr_iimmed 0x4000,0xfffe,fr10
+ set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
+ set_fr_iimmed 0x7fff,0x8000,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0002,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0002,acc3
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffb,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffb,acc1
+
+ ; Negative operands
+ set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
+ set_fr_iimmed 0xfffe,0xfffd,fr10
+ set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
+ set_fr_iimmed 0xffff,0xfffe,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_limmed 0x0000,0x0008,acc2
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0008,acc3
+ test_accg_immed 0xff,accg0
+ test_acc_limmed 0xffff,0xbffd,acc0
+ test_accg_immed 0xff,accg1
+ test_acc_limmed 0xffff,0xbffd,acc1
+
+ set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
+ set_fr_iimmed 0x8000,0x8000,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg2
+ test_acc_immed 0x3fff0009,acc2
+ test_accg_immed 0,accg3
+ test_acc_immed 0x3fff0009,acc3
+ test_accg_immed 0,accg0
+ test_acc_immed 0x3fffbffd,acc0
+ test_accg_immed 0,accg1
+ test_acc_immed 0x3fffbffd,acc1
+
+ set_accg_immed 0x7f,accg2 ; saturation
+ set_acc_immed 0xffffffff,acc2
+ set_accg_immed 0x7f,accg3
+ set_acc_immed 0xffffffff,acc3
+ set_accg_immed 0x7f,accg0 ; saturation
+ set_acc_immed 0xffffffff,acc0
+ set_accg_immed 0x7f,accg1
+ set_acc_immed 0xffffffff,acc1
+ set_fr_iimmed 1,1,fr8
+ set_fr_iimmed 1,1,fr10
+ set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x7f,accg2
+ test_acc_limmed 0xffff,0xffff,acc2
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+ test_accg_immed 0x7f,accg0
+ test_acc_limmed 0xffff,0xffff,acc0
+ test_accg_immed 0x7f,accg1
+ test_acc_limmed 0xffff,0xffff,acc1
+
+ set_accg_immed 0x80,accg2 ; saturation
+ set_acc_immed 0,acc2
+ set_accg_immed 0x80,accg3
+ set_acc_immed 0,acc3
+ set_accg_immed 0x80,accg0 ; saturation
+ set_acc_immed 0,acc0
+ set_accg_immed 0x80,accg1
+ set_acc_immed 0,acc1
+ set_fr_iimmed 0xffff,0,fr8
+ set_fr_iimmed 0xffff,1,fr10
+ set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
+ set_fr_iimmed 0x7fff,0x7fff,fr11
+ mqxmacxhs fr8,fr10,acc0
+ test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
+ test_accg_immed 0x80,accg2
+ test_acc_immed 0,acc2
+ test_accg_immed 0x80,accg3
+ test_acc_immed 0,acc3
+ test_accg_immed 0x80,accg0
+ test_acc_immed 0,acc0
+ test_accg_immed 0x80,accg1
+ test_acc_immed 0,acc1
+
+ pass
+
+
--- /dev/null
+# frv testcase for msubaccs $ACC40Si,$ACC40Sk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubaccs
+msubaccs:
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000000,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0xdead0000,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x0000beef,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0xdeac,0x4111,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x0000dead,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xbeef0000,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0x4111,0xdead,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x11111111,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x0123,0x4567,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0xffffffff,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0xff,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_accg_immed 0,accg0
+ set_acc_immed 0x12345678,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xffffffff,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+ test_accg_immed 0,accg3
+ test_acc_limmed 0x1234,0x5679,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x7f,accg0
+ set_acc_immed 0xfffffffe,acc0
+ set_accg_immed 0xff,accg1
+ set_acc_immed 0xfffffffe,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x7f,accg3
+ test_acc_limmed 0xffff,0xffff,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0x80,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000002,acc1
+ msubaccs acc0,acc3
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0x80,accg3
+ test_acc_limmed 0x0000,0x0000,acc3
+
+ set_spr_immed 0,msr0
+ set_accg_immed 0,accg0
+ set_acc_immed 0x00000001,acc0
+ set_accg_immed 0,accg1
+ set_acc_immed 0x00000001,acc1
+ set_accg_immed 0,accg4
+ set_acc_immed 0x00000001,acc4
+ set_accg_immed 0x80,accg5
+ set_acc_immed 0x00000000,acc5
+ msubaccs.p acc0,acc1
+ msubaccs acc4,acc5
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ test_accg_immed 0,accg1
+ test_acc_limmed 0x0000,0x0000,acc1
+ test_accg_immed 0x7f,accg5
+ test_acc_limmed 0xffff,0xffff,acc5
+
+ pass
--- /dev/null
+# frv testcase for msubhss $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubhss
+msubhss:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0x0000,fr10
+ set_fr_iimmed 0x0000,0xbeef,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0xdead,0x4111,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0000,0xdead,fr10
+ set_fr_iimmed 0xbeef,0x0000,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x4111,0xdead,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0xffff,0xffff,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x1235,0x5679,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0xfffe,0xffff,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x7fff,0x7fff,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x8001,0x8001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ msubhss fr10,fr11,fr12
+ test_fr_limmed 0x8000,0x8000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x8000,0x8000,fr11
+ msubhss.p fr10,fr10,fr12
+ msubhss fr11,fr10,fr13
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x8000,0x8000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for msubhus $FRi,$FRj,$FRj
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global msubhus
+msubhus:
+ set_fr_iimmed 0x0000,0x0000,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0xdead,0xbeef,fr10
+ set_fr_iimmed 0x0000,0x0000,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0xdead,0xbeef,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x1111,0x1111,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0x0123,0x4567,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x7ffe,0x7ffe,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0x7ffc,0x7ffd,fr12
+ test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
+ test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
+ test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
+
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0001,0x0002,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0001,fr11
+ msubhus fr10,fr11,fr12
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x0001,0x0001,fr10
+ set_fr_iimmed 0x0002,0x0002,fr11
+ msubhus.p fr10,fr10,fr12
+ msubhus fr10,fr11,fr13
+ test_fr_limmed 0x0000,0x0000,fr12
+ test_fr_limmed 0x0000,0x0000,fr13
+ test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+
+ pass
--- /dev/null
+# frv testcase for mp_exception
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global mp_exception
+mpx:
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr7
+ inc_gr_immed 0x0e0,gr7 ; address of exception handler
+ set_bctrlr_0_0 gr7
+ set_spr_immed 128,lcr
+ set_spr_addr ok1,lr
+ set_psr_et 1
+ set_gr_immed 0,gr5
+
+ set_spr_immed 0,msr0
+ set_fr_iimmed 0x1234,0x5678,fr10
+ set_fr_iimmed 0x7ffe,0x7ffe,fr11
+ set_fr_iimmed 0xffff,0xffff,fr12
+ set_fr_iimmed 0x0002,0x0001,fr13
+ mqaddhss fr10,fr12,fr14
+ test_fr_limmed 0x1233,0x5677,fr14
+ test_fr_limmed 0x7fff,0x7fff,fr15
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ mtrap ; generate interrupt
+ test_gr_immed 1,gr5
+
+ and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields
+ mcmpsh fr10,fr11,fcc0 ; no exception
+ test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set
+ mtrap ; nop
+ test_gr_immed 1,gr5
+
+ pass
+
+; exception handler
+ok1:
+ test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
+ test_spr_bits 2,1,1,msr0 ; msr0.ovf set
+ test_spr_bits 1,0,1,msr0 ; msr0.aovf set
+ test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
+ inc_gr_immed 1,gr5
+ rett 0
+ fail
--- /dev/null
+# frv testcase for udiv $GRi,$GRj,$GRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global udiv
+udiv:
+ ; simple division 12 / 3
+ set_gr_immed 0x00000003,gr2
+ set_gr_immed 0x0000000c,gr3
+ udiv gr3,gr2,gr3
+ test_gr_immed 0x00000003,gr2
+ test_gr_immed 0x00000004,gr3
+
+ ; example 1 from udiv in the fr30 manual
+ set_gr_limmed 0x0123,0x4567,gr2
+ set_gr_limmed 0xfedc,0xba98,gr3
+ udiv gr3,gr2,gr3
+ test_gr_limmed 0x0123,0x4567,gr2
+ test_gr_immed 0x000000e0,gr3
+
+ ; set up exception handler
+ set_psr_et 1
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x170,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_gr_immed 0,gr15
+
+ ; divide by zero
+ set_spr_addr ok1,lr
+ set_gr_addr e1,gr17
+e1: udiv gr1,gr0,gr2 ; divide by zero
+ test_gr_immed 1,gr15
+
+ pass
+
+ok1: ; exception handler for divide by zero
+ test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set
+ test_spr_gr epcr0,gr17 ; return address set
+ test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
+ test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
+ inc_gr_immed 1,gr15
+ rett 0
+ fail
--- /dev/null
+# frv testcase for udivi $GRi,$s12,$GRk
+# mach: all
+
+ .include "../testutils.inc"
+
+ start
+
+ .global udivi
+udivi:
+ ; simple division 12 / 3
+ set_gr_immed 0x0000000c,gr3
+ udivi gr3,3,gr3
+ test_gr_immed 0x00000004,gr3
+
+ ; random example
+ set_gr_limmed 0xfedc,0xba98,gr3
+ udivi gr3,0x7ff,gr3
+ test_gr_limmed 0x001f,0xdf93,gr3
+
+ ; random example
+ set_gr_limmed 0xffff,0xffff,gr3
+ udivi gr3,-2048,gr3
+ test_gr_immed 1,gr3
+
+ ; set up exception handler
+ set_psr_et 1
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x170,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_gr_immed 0,gr15
+
+ ; divide by zero
+ set_spr_addr ok1,lr
+ set_gr_addr e1,gr17
+e1: udivi gr1,0,gr2 ; divide by zero
+ test_gr_immed 1,gr15
+
+ pass
+
+ok1: ; exception handler for divide by zero
+ test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set
+ test_spr_gr epcr0,gr17 ; return address set
+ test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
+ test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
+ inc_gr_immed 1,gr15
+ rett 0
+ fail
# frv testcase for fsqrts $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fstoi $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for fsubs $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for icei @(GRi,GRj),a
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "frv fr500 fr400"
+ set all_machs "frv fr500 fr550 fr400"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
# frv testcase
-# mach: fr500
+# mach: fr500
.include "testutils.inc"
--- /dev/null
+# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
+# mach: fr550
+ .include "testutils.inc"
+
+ start
+
+ .global align
+align:
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x100,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_psr_et 1
+ set_gr_immed 0xdeadbeef,gr17
+ set_gr_immed 0,gr15
+ inc_gr_immed 2,sp ; out of alignment
+
+ test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used)
+ sti gr17,@(sp,0) ; no exception
+ sti gr17,@(sp,4) ; no exception
+ ldi @(sp,0),gr18 ; stored at unaligned address
+ test_gr_immed 0xdeadbeef,gr18
+ ldi @(sp,0),gr19 ; no exception
+ test_gr_immed 0xdeadbeef,gr19
+
+ and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
+ sti gr17,@(sp,0) ; misaligned -- no exception
+ test_gr_immed 0,gr15
+
+ set_gr_gr sp,gr20
+ set_gr_immed 1,gr21
+ set_gr_immed 0x10101010,gr10
+ nop.p
+ ldu @(sp,gr21),gr10 ; misaligned read no exception
+ test_gr_immed 0,gr15 ; handler was not called
+ test_gr_immed 0xadbeefde,gr10 ; gr10 updated
+ test_gr_immed 1,gr21 ; gr21 not updated
+ inc_gr_immed 1,gr20
+ test_gr_gr gr20,sp ; sp updated
+
+ pass
--- /dev/null
+# frv testcase to generate compound exception
+# mach: fr550
+ .include "testutils.inc"
+
+ start
+
+ .global align
+align:
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x200,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_spr_addr ok1,lr
+ or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception
+ set_psr_et 1
+
+ set_gr_immed 0,gr15
+ set_fr_iimmed 0x7f7f,0xffff,fr0
+ set_fr_iimmed 0x0000,0x0000,fr1
+
+ and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned
+ set_gr_addr dividef,gr16
+ set_gr_addr dividei,gr17
+ set_gr_immed 0xdeadbeef,gr8
+ inc_gr_immed 2,sp ; misalign
+store: sti.p gr8,@(sp,0) ; misaligned - no exception
+dividef:fdivs.p fr0,fr1,fr2 ; fp_exception
+dividei:sdiv gr1,gr0,gr1 ; division exception
+ test_gr_immed 1,gr15
+
+ pass
+
+; exception handler
+ok1:
+ ; check fp_exception
+ test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active
+ test_spr_gr epcr2,gr16
+ test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid
+ test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set
+ test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear
+
+ ; check on fp_exception
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
+ test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
+ test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear
+
+ ; check interrupt on dividei
+ test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
+ test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
+
+ inc_gr_immed 1,gr15
+ rett 0
+ fail
--- /dev/null
+# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
+# mach: fr550
+# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
+ .include "testutils.inc"
+
+ start
+
+ .global dsr
+dsr:
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x140,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_psr_et 1
+
+ set_spr_addr ok0,lr
+ set_gr_immed 0,gr16
+
+ set_gr_immed 0xdeadbeef,gr15
+ set_gr_addr 0xfeff0600,gr17
+bad1: sti gr15,@(gr17,0) ; no interrupt
+ test_gr_immed 0,gr16
+
+ set_gr_immed 0xbeefdead,gr15
+ set_gr_addr 0xfeff7ffc,gr17
+bad2: sti gr15,@(gr17,0) ; no interrupt
+ test_gr_immed 0,gr16
+
+ set_gr_immed 0xbeefbeef,gr15
+ set_gr_addr 0xfe800000,gr17
+bad3: sti gr15,@(gr17,0) ; cause interrupt
+ test_gr_immed 1,gr16
+
+ set_gr_immed 0xdeaddead,gr15
+ set_gr_addr 0xfefefffc,gr17
+bad4: sti gr15,@(gr17,0) ; cause interrupt
+ test_gr_immed 2,gr16
+
+ sti gr0,@(sp,0) ; no interrupt
+ test_gr_immed 2,gr16
+
+ pass
+ok0:
+ ; check interrupts
+ test_spr_immed 0x4000,esfr1 ; esr14 is active
+ test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid
+ test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set
+ test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set
+
+ addi gr16,1,gr16
+ rett 0
+ fail
--- /dev/null
+# frv testcase to generate fp_exception
+# mach: fr550
+ .include "testutils.inc"
+
+ float_constants
+ start
+ load_float_constants
+
+ .global align
+align:
+ ; clear the packing bit if the insn at 'pack:'. We can't simply use
+ ; '.p' because the assembler will catch the error.
+ set_gr_mem pack,gr10
+ and_gr_immed 0x7fffffff,gr10
+ set_mem_gr gr10,pack
+ set_gr_addr pack,gr10
+ flush_data_cache gr10
+
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x070,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ inc_gr_immed 0x060,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_spr_addr ok1,lr
+ set_psr_et 1
+ inc_gr_immed -4,sp ; for alignment
+
+ set_gr_immed 0,gr20 ; PC increment
+ set_gr_immed 0,gr15
+
+ set_spr_addr ok3,lr
+ set_gr_immed 4,gr20 ; PC increment
+badst1: stdfi fr1,@(sp,0) ; misaligned reg -- slot I0
+ test_gr_immed 1,gr15
+
+ set_spr_addr ok4,lr
+ set_gr_immed 8,gr20 ; PC increment
+ nop.p
+badst2: lddfi @(sp,0),fr9 ; misaligned reg -- slot I1
+ test_gr_immed 2,gr15
+
+ set_spr_addr ok5,lr
+ set_gr_immed 20,gr20 ; PC increment
+ fnegs.p fr9,fr9
+ fnegs.p fr9,fr10
+ fnegs.p fr9,fr11
+pack: fnegs fr10,fr12
+ fnegs fr10,fr13 ; packing violation
+ test_gr_immed 3,gr15
+
+ set_spr_addr ok1,lr
+ set_gr_immed 4,gr20 ; PC increment
+bad: fmadds fr16,fr4,fr1 ; unimplemented
+ test_gr_immed 4,gr15
+
+ and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
+ set_fr_iimmed 0x7f7f,0xffff,fr0
+ set_fr_iimmed 0x0000,0x0000,fr1
+ fdivs fr0,fr1,fr2 ; div/0 -- no exception
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
+ test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
+ test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
+
+ set_spr_addr ok2,lr
+ set_gr_immed 0,gr20 ; PC increment
+ or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception
+ set_fr_iimmed 0xdead,0xbeef,fr2
+div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0
+ test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated
+ test_gr_immed 5,gr15
+
+ and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception
+ fsqrts fr32,fr2 ; inexact -- no exception
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
+ test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set
+ test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
+
+ set_fr_fr fr2,fr3 ; sqrt 2
+ set_fr_iimmed 0xdead,0xbeef,fr2
+ set_spr_addr ok6,lr
+ or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception
+inxt1: fsqrts fr32,fr2 ; fp_exception - inexact
+ test_gr_immed 6,gr15 ; handler called
+ test_fr_fr fr2,fr3 ; fr2 updated
+
+ set_fr_iimmed 0xdead,0xbeef,fr2
+ set_spr_addr ok7,lr
+inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again
+ test_gr_immed 7,gr15 ; handler called
+ test_fr_fr fr2,fr3 ; fr2 updated
+
+ pass
+
+; exception handler 1 -- illegal_instruction: bad insn
+ok1:
+ test_spr_immed 1,esfr1 ; esr0 active
+ test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
+ test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
+ bra ret
+
+; exception handler 2 - fp_exception: divide by 0
+ok2:
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
+ test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
+ test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
+
+ test_spr_immed 4,esfr1 ; esr2 active
+ test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
+ test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
+ test_spr_addr div0,epcr2 ; epcr2 is set
+ bra ret
+
+; exception handler 3 - illegal_instruction: register exception
+ok3:
+ test_spr_immed 1,esfr1 ; esr0 active
+ test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
+ test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
+ bra ret
+
+; exception handler 4 - illegal_instruction: register exception
+ok4:
+ test_spr_immed 1,esfr1 ; esr0 active
+ test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
+ test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
+ bra ret
+
+; exception handler 5 - illegal_instruction: sequence violation
+ok5:
+ test_spr_immed 1,esfr1 ; esr0 active
+ test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
+ test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
+ bra ret
+
+; exception handler 6 - fp_exception: inexact
+ok6:
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
+ test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
+ test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
+
+ test_spr_immed 4,esfr1 ; esr2 active
+ test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
+ test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
+ test_spr_addr inxt1,epcr2 ; epcr2 is set
+ bra ret
+
+; exception handler 7 - fp_exception: inexact again
+ok7:
+ test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
+ test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
+ test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
+
+ test_spr_immed 4,esfr1 ; esr2 active
+ test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
+ test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
+ test_spr_addr inxt2,epcr2 ; epcr2 is set
+ bra ret
+
+ret:
+ inc_gr_immed 1,gr15
+ movsg pcsr,gr60
+ add gr60,gr20,gr60
+ movgs gr60,pcsr
+ rett 0
+ fail
+
# FRV testcase
-# mach: fr500 fr400
+# mach: fr500 fr550 fr400
.include "testutils.inc"
ok0: test_spr_addr ill1,pcsr
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3f,0,0xb,esr0
+ movsg psr,gr28
+ srli gr28,28,gr28
+ subicc gr28,0x3,gr0,icc3 ; is fr550?
+ beq icc3,0,no_epcr
test_spr_addr ill1,epcr0
-
+no_epcr:
pass
--- /dev/null
+# frv testcase to generate insn_access_error interrupt
+# mach: fr550
+# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00
+ .include "testutils.inc"
+
+ start
+
+ .global dsr
+dsr:
+ and_spr_immed -4081,tbr ; clear tbr.tt
+ set_gr_spr tbr,gr17
+ inc_gr_immed 0x020,gr17 ; address of exception handler
+ set_bctrlr_0_0 gr17
+ set_spr_immed 128,lcr
+ set_psr_et 1
+
+ set_spr_addr handler,lr
+ set_gr_immed 0,gr16
+
+ set_gr_addr ok0,gr8
+ set_gr_addr 0xfe800000,gr17
+ jmpl @(gr17,gr0) ; cause interrupt
+ok0:
+ test_gr_immed 1,gr16
+
+ set_gr_addr ok1,gr8
+ set_gr_addr 0xfefffffc,gr17
+ jmpl @(gr17,gr0) ; cause interrupt
+ok1:
+ test_gr_immed 2,gr16
+
+ pass
+handler:
+ ; check interrupts
+ test_spr_immed 0x1,esfr1 ; esr0 is active
+; test_spr_gr epcr0,gr17 ; epcr0 is not used
+ test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
+ test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
+ test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
+
+ addi gr16,1,gr16
+ movgs gr8,pcsr
+ rett 0
+ fail
# frv testcase for mp_exception
-# mach: fr500 frv
+# mach: fr500 fr550 frv
# xerror:
# This program no longer assembles because the assembler
# frv testcase to generate reset interrupts
-# mach: fr500 fr400
+# mach: fr500 fr550 fr400
# sim: --memory-region 0xff000000,64
.include "testutils.inc"
# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj)
-# mach: fr500 fr400
+# mach: fr500 fr550 fr400
# sim: --timer 200,14
.include "testutils.inc"
# frv parallel testcase for lr branching
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for maddhss $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for maddhus $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mcplhi $FRi,$s6,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mcpli $FRi,$s6,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mdcutssi $ACC40i,$s6,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mdrotli $FRi,$s6,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhdseth $s5,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhdsets $u12,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhsethih $s5,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhsethis $u12,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhsetloh $s5,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mhsetlos $u12,$FRk
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for mmachs $GRi,$GRj,$ACCk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mmachu $GRi,$GRj,$GRk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mmrdhs $GRi,$GRj,$ACCk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mmrdhu $GRi,$GRj,$GRk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mqmachs $GRi,$GRj,$ACCk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mqmachu $GRi,$GRj,$GRk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mqsaths $FRi,$FRj,$FRj
-# mach: fr400
+# mach: fr400 fr550
.include "testutils.inc"
# frv testcase for msubhss $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for msubhus $FRi,$FRj,$FRj
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for mp_exception
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for nfadds $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdadds $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdivs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdmulcs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdmuls $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdsads $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfdsubs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfitos $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfmas $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfmss $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfmuls $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfsqrts $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfstoi $FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nfsubs $FRi,$FRj,$FRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nsdiv $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nsdivi $GRi,$s12,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nudiv $GRi,$GRj,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for nudivi $GRi,$s12,$GRk
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "frv fr500 fr400"
+ set all_machs "frv fr500 fr550 fr400"
set cpu_option -mcpu
# The .pcgs suffix is for "parallel cgen .s".
# frv parallel testcase for stdf $GRk,@($GRi,$GRj)
-# mach: fr500 frv
+# mach: fr500 fr550 frv
.include "testutils.inc"
# frv testcase for udiv $GRi,$GRj,$GRk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
# frv testcase for udivi $GRi,$s12,$GRk
-# mach: all
+# mach: frv fr500 fr400
.include "testutils.inc"
projects / thirdparty / binutils-gdb.git / commitdiff
