]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.2-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 8 Aug 2019 09:13:17 +0000 (11:13 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 8 Aug 2019 09:13:17 +0000 (11:13 +0200)
added patches:
drm-i915-vbt-fix-vbt-parsing-for-the-psr-section.patch
revert-mac80211-set-netif_f_lltx-when-using-intermediate-tx-queues.patch

queue-5.2/drm-i915-vbt-fix-vbt-parsing-for-the-psr-section.patch [new file with mode: 0644]
queue-5.2/revert-mac80211-set-netif_f_lltx-when-using-intermediate-tx-queues.patch [new file with mode: 0644]
queue-5.2/series

diff --git a/queue-5.2/drm-i915-vbt-fix-vbt-parsing-for-the-psr-section.patch b/queue-5.2/drm-i915-vbt-fix-vbt-parsing-for-the-psr-section.patch
new file mode 100644 (file)
index 0000000..c508ff1
--- /dev/null
@@ -0,0 +1,73 @@
+From 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Wed, 17 Jul 2019 15:34:51 -0700
+Subject: drm/i915/vbt: Fix VBT parsing for the PSR section
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+
+commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 upstream.
+
+A single 32-bit PSR2 training pattern field follows the sixteen element
+array of PSR table entries in the VBT spec. But, we incorrectly define
+this PSR2 field for each of the PSR table entries. As a result, the PSR1
+training pattern duration for any panel_type != 0 will be parsed
+incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
+version >= 226 will also be wrong.
+
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Cc: stable@vger.kernel.org
+Cc: stable@vger.kernel.org #v5.2
+Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Tested-by: François Guerraz <kubrick@fgv6.net>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com
+(cherry picked from commit b5ea9c9337007d6e700280c8a60b4e10d070fb53)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ drivers/gpu/drm/i915/intel_bios.c     |    2 +-
+ drivers/gpu/drm/i915/intel_vbt_defs.h |    6 +++---
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_bios.c
++++ b/drivers/gpu/drm/i915/intel_bios.c
+@@ -762,7 +762,7 @@ parse_psr(struct drm_i915_private *dev_p
+       }
+       if (bdb->version >= 226) {
+-              u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
++              u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
+               wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+               switch (wakeup_time) {
+--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
++++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
+@@ -772,13 +772,13 @@ struct psr_table {
+       /* TP wake up time in multiple of 100 */
+       u16 tp1_wakeup_time;
+       u16 tp2_tp3_wakeup_time;
+-
+-      /* PSR2 TP2/TP3 wakeup time for 16 panels */
+-      u32 psr2_tp2_tp3_wakeup_time;
+ } __packed;
+ struct bdb_psr {
+       struct psr_table psr_table[16];
++
++      /* PSR2 TP2/TP3 wakeup time for 16 panels */
++      u32 psr2_tp2_tp3_wakeup_time;
+ } __packed;
+ /*
diff --git a/queue-5.2/revert-mac80211-set-netif_f_lltx-when-using-intermediate-tx-queues.patch b/queue-5.2/revert-mac80211-set-netif_f_lltx-when-using-intermediate-tx-queues.patch
new file mode 100644 (file)
index 0000000..474739f
--- /dev/null
@@ -0,0 +1,33 @@
+From eef347f846ee8f7296a6f84e3866c057ca6bcce0 Mon Sep 17 00:00:00 2001
+From: Johannes Berg <johannes.berg@intel.com>
+Date: Tue, 30 Jul 2019 14:52:07 +0200
+Subject: Revert "mac80211: set NETIF_F_LLTX when using intermediate tx queues"
+
+From: Johannes Berg <johannes.berg@intel.com>
+
+commit eef347f846ee8f7296a6f84e3866c057ca6bcce0 upstream.
+
+Revert this for now, it has been reported multiple times that it
+completely breaks connectivity on various devices.
+
+Cc: stable@vger.kernel.org
+Fixes: 8dbb000ee73b ("mac80211: set NETIF_F_LLTX when using intermediate tx queues")
+Reported-by: Jean Delvare <jdelvare@suse.de>
+Reported-by: Peter Lebbing <peter@digitalbrains.com>
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ net/mac80211/iface.c |    1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/net/mac80211/iface.c
++++ b/net/mac80211/iface.c
+@@ -1222,7 +1222,6 @@ static void ieee80211_if_setup(struct ne
+ static void ieee80211_if_setup_no_queue(struct net_device *dev)
+ {
+       ieee80211_if_setup(dev);
+-      dev->features |= NETIF_F_LLTX;
+       dev->priv_flags |= IFF_NO_QUEUE;
+ }
index 51873f28d5e4274bf95f86299e5cfaab9f5f68c5..0bf445f80124eb9ad462b2a3dd0a5c4f114dce2a 100644 (file)
@@ -51,3 +51,5 @@ mlxsw-spectrum_buffers-further-reduce-pool-size-on-spectrum-2.patch
 net-mlx5-add-missing-rdma_rx-capabilities.patch
 net-mlx5e-fix-matching-of-speed-to-prm-link-modes.patch
 compat_ioctl-pppoe-fix-pppoeiocsfwd-handling.patch
+drm-i915-vbt-fix-vbt-parsing-for-the-psr-section.patch
+revert-mac80211-set-netif_f_lltx-when-using-intermediate-tx-queues.patch