RISC-V: Reconcile the existing test for vdivu.vx combine

Some existing vdiv related test need some adjust for the
asm check due to cost model.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adjust
	the asm check for vdivu.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
index 4685ed22a7845e45239d3d8a27cfca596629608d..a8be5edcc70c6f2d08ffd510485602398f065471 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
@@ -5,8 +5,8 @@
 
 /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
 /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
 
 /* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
 /* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 59c48d2d9bae06cbd3867861b2e2ff2fc808246f..7feee0ec154ad52b0aa00c1f9aac57ce5e538f7c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -5,8 +5,8 @@
 
 /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
 /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
 
 /* Division by constant is done by calculating a reciprocal and
    then multiplying.  Hence we do not expect 6 vfdivs.  */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
index b574dc42182cbe37bbbfcf7efcaae1dc56d314de..766b17fc37da7762d6f8d182c04d7df952d3183d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
@@ -5,8 +5,8 @@
 
 /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
 /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
 
 /* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
 /* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 9b46c6be0efb32269650e0088b2bcc453ad4ba92..c59c66439f8951d327dc16ad89c458f5dae8688d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -5,8 +5,8 @@
 
 /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
 /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
 
 /* Division by constant is done by calculating a reciprocal and
    then multiplying.  Hence we do not expect 6 vfdivs.  */