perf/x86/intel: Rename model-specific pebs_latency_data functions

The model-specific pebs_latency_data functions of ADL and MTL use the
"small" as a postfix to indicate the e-core. The postfix is too generic
for a model-specific function. It cannot provide useful information that
can directly map it to a specific uarch, which can facilitate the
development and maintenance.
Use the abbr of the uarch to rename the model-specific functions.

Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Ian Rogers <irogers@google.com>
Link: https://lkml.kernel.org/r/20240626143545.480761-5-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 224430e432bef149abf2157cc8f5280abf690754..35f2d52281ccf626bda915f2cc465884da6326f6 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6509,7 +6509,7 @@ __init int intel_pmu_init(void)
        case INTEL_ATOM_GRACEMONT:
                intel_pmu_init_grt(NULL);
                intel_pmu_pebs_data_source_grt();
-               x86_pmu.pebs_latency_data = adl_latency_data_small;
+               x86_pmu.pebs_latency_data = grt_latency_data;
                x86_pmu.get_event_constraints = tnt_get_event_constraints;
                td_attr = tnt_events_attrs;
                mem_attr = grt_mem_attrs;
@@ -6523,7 +6523,7 @@ __init int intel_pmu_init(void)
                intel_pmu_init_grt(NULL);
                x86_pmu.extra_regs = intel_cmt_extra_regs;
                intel_pmu_pebs_data_source_cmt();
-               x86_pmu.pebs_latency_data = mtl_latency_data_small;
+               x86_pmu.pebs_latency_data = cmt_latency_data;
                x86_pmu.get_event_constraints = cmt_get_event_constraints;
                td_attr = cmt_events_attrs;
                mem_attr = grt_mem_attrs;
@@ -6874,7 +6874,7 @@ __init int intel_pmu_init(void)
                 */
                intel_pmu_init_hybrid(hybrid_big_small);
 
-               x86_pmu.pebs_latency_data = adl_latency_data_small;
+               x86_pmu.pebs_latency_data = grt_latency_data;
                x86_pmu.get_event_constraints = adl_get_event_constraints;
                x86_pmu.hw_config = adl_hw_config;
                x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
@@ -6931,7 +6931,7 @@ __init int intel_pmu_init(void)
        case INTEL_METEORLAKE_L:
                intel_pmu_init_hybrid(hybrid_big_small);
 
-               x86_pmu.pebs_latency_data = mtl_latency_data_small;
+               x86_pmu.pebs_latency_data = cmt_latency_data;
                x86_pmu.get_event_constraints = mtl_get_event_constraints;
                x86_pmu.hw_config = adl_hw_config;
 

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 79e23dec6714fea2535091b0b13cd4562fe5b994..3581c2715b21172a7e663387a3f4ca840f5da2ed 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -257,8 +257,8 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
 }
 
 /* Retrieve the latency data for e-core of ADL */
-static u64 __adl_latency_data_small(struct perf_event *event, u64 status,
-                                    u8 dse, bool tlb, bool lock, bool blk)
+static u64 __grt_latency_data(struct perf_event *event, u64 status,
+                              u8 dse, bool tlb, bool lock, bool blk)
 {
        u64 val;
 
@@ -277,27 +277,27 @@ static u64 __adl_latency_data_small(struct perf_event *event, u64 status,
        return val;
 }
 
-u64 adl_latency_data_small(struct perf_event *event, u64 status)
+u64 grt_latency_data(struct perf_event *event, u64 status)
 {
        union intel_x86_pebs_dse dse;
 
        dse.val = status;
 
-       return __adl_latency_data_small(event, status, dse.ld_dse,
-                                       dse.ld_locked, dse.ld_stlb_miss,
-                                       dse.ld_data_blk);
+       return __grt_latency_data(event, status, dse.ld_dse,
+                                 dse.ld_locked, dse.ld_stlb_miss,
+                                 dse.ld_data_blk);
 }
 
 /* Retrieve the latency data for e-core of MTL */
-u64 mtl_latency_data_small(struct perf_event *event, u64 status)
+u64 cmt_latency_data(struct perf_event *event, u64 status)
 {
        union intel_x86_pebs_dse dse;
 
        dse.val = status;
 
-       return __adl_latency_data_small(event, status, dse.mtl_dse,
-                                       dse.mtl_stlb_miss, dse.mtl_locked,
-                                       dse.mtl_fwd_blk);
+       return __grt_latency_data(event, status, dse.mtl_dse,
+                                 dse.mtl_stlb_miss, dse.mtl_locked,
+                                 dse.mtl_fwd_blk);
 }
 
 static u64 load_latency_data(struct perf_event *event, u64 status)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index b7195eef4042dc54b5c020fda7986f31980449d1..fc2561959fede0420baf5fe97827ef76728e966a 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1548,9 +1548,9 @@ void intel_pmu_disable_bts(void);
 
 int intel_pmu_drain_bts_buffer(void);
 
-u64 adl_latency_data_small(struct perf_event *event, u64 status);
+u64 grt_latency_data(struct perf_event *event, u64 status);
 
-u64 mtl_latency_data_small(struct perf_event *event, u64 status);
+u64 cmt_latency_data(struct perf_event *event, u64 status);
 
 extern struct event_constraint intel_core2_pebs_event_constraints[];