PCI: rockchip-ep: Refactor endpoint link training enable

The function rockchip_pcie_init_port() enables link training for a
controller configured in EP mode. Enabling link training is again done
in rockchip_pcie_ep_probe() after that function executed
rockchip_pcie_init_port(). Enabling link training only needs to be done
once, and doing so at the probe stage before the controller is actually
started by the user serves no purpose.

Refactor this by removing the link training enablement from both
rockchip_pcie_init_port() and rockchip_pcie_ep_probe() and moving it to
the endpoint start operation defined with rockchip_pcie_ep_start().
Enabling the controller configuration using the PCIE_CLIENT_CONF_ENABLE
bit in the same PCIE_CLIENT_CONFIG register is also moved to
rockchip_pcie_ep_start() and both the controller configuration and link
training enable bits are set with a single call to
rockchip_pcie_write().

Link: https://lore.kernel.org/r/20241017015849.190271-11-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index a53ff16b16615fb8d03cc003fb45706161593c47..6c4169b7930e6b4a01048f4ed6eefe900113c977 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -467,6 +467,12 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc)
 
        rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
 
+       /* Enable configuration and start link training */
+       rockchip_pcie_write(rockchip,
+                           PCIE_CLIENT_LINK_TRAIN_ENABLE |
+                           PCIE_CLIENT_CONF_ENABLE,
+                           PCIE_CLIENT_CONFIG);
+
        return 0;
 }
 
@@ -656,16 +662,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
 
        rockchip_pcie_ep_hide_broken_msix_cap(rockchip);
 
-       /* Establish the link automatically */
-       rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
-                           PCIE_CLIENT_CONFIG);
-
        /* Only enable function 0 by default */
        rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
 
-       rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
-                           PCIE_CLIENT_CONFIG);
-
        pci_epc_init_notify(epc);
 
        return 0;

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index c07d7129f1c7c4e4b2de8edab757b98ebb998018..154e78819e6e8ca371ce87107ca2599787619d78 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -244,11 +244,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
                                    PCIE_CLIENT_CONFIG);
 
-       regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |
+       regs = PCIE_CLIENT_ARI_ENABLE |
               PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
 
        if (rockchip->is_rc)
-               regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
+               regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE |
+                       PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
        else
                regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;