Merge tag 'perf-tools-for-v6.16-1-2025-06-03' of git://git.kernel.org/pub/scm/linux...

Pull perf tools updates from Arnaldo Carvalho de Melo:
 "perf report/top/annotate TUI:

   - Accept the left arrow key as a Zoom out if done on the first column

   - Show if source code toggle status in title, to help spotting bugs
     with the various disassemblers (capstone, llvm, objdump)

   - Provide feedback on unhandled hotkeys

  Build:

   - Better inform when certain features are not available with warnings
     in the build process and in 'perf version --build-options' or 'perf -vv'

  perf record:

   - Improve the --off-cpu code by synthesizing events for switch-out ->
     switch-in intervals using a BPF program. This can be fine tuned
     using a --off-cpu-thresh knob

  perf report:

   - Add 'tgid' sort key

  perf mem/c2c:

   - Add 'op', 'cache', 'snoop', 'dtlb' output fields

   - Add support for 'ldlat' on AMD IBS (Instruction Based Sampling)

  perf ftrace:

   - Use process/session specific trace settings instead of messing with
     the global ftrace knobs

  perf trace:

   - Implement syscall summary in BPF

   - Support --summary-mode=cgroup

   - Always print return value for syscalls returning a pid

   - The rseq and set_robust_list don't return a pid, just -errno

  perf lock contention:

   - Symbolize zone->lock using BTF

   - Add -J/--inject-delay option to estimate impact on application
     performance by optimization of kernel locking behavior

  perf stat:

   - Improve hybrid support for the NMI watchdog warning

  Symbol resolution:

   - Handle 'u' and 'l' symbols in /proc/kallsyms, resolving some Rust
     symbols

   - Improve Rust demangler

  Hardware tracing:

  Intel PT:

   - Fix PEBS-via-PT data_src

   - Do not default to recording all switch events

   - Fix pattern matching with python3 on the SQL viewer script

  arm64:

   - Fixups for the hip08 hha PMU

  Vendor events:

   - Update Intel events/metrics files for alderlake, alderlaken,
     arrowlake, bonnell, broadwell, broadwellde, broadwellx,
     cascadelakex, clearwaterforest, elkhartlake, emeraldrapids,
     grandridge, graniterapids, haswell, haswellx, icelake, icelakex,
     ivybridge, ivytown, jaketown, lunarlake, meteorlake, nehalemep,
     nehalemex, rocketlake, sandybridge, sapphirerapids, sierraforest,
     skylake, skylakex, snowridgex, tigerlake, westmereep-dp,
     westmereep-sp, westmereep-sx

  python support:

   - Add support for event counts in the python binding, add a
     counting.py example

  perf list:

   - Display the PMU name associated with a perf metric in JSON

  perf test:

   - Hybrid improvements for metric value validation test

   - Fix LBR test by ignoring idle task

   - Add AMD IBS sw filter ana d'ldlat' tests

   - Add 'perf trace --summary-mode=cgroup' test

   - Add tests for the various language symbol demanglers

  Miscellaneous:

   - Allow specifying the cpu an event will be tied using '-e
     event/cpu=N/'

   - Sync various headers with the kernel sources

   - Add annotations to use clang's -Wthread-safety and fix some
     problems it detected

   - Make dump_stack() use perf's symbol resolution to provide better
     backtraces

   - Intel TPEBS support cleanups and fixes. TPEBS stands for Timed PEBS
     (Precision Event-Based Sampling), that adds timing info, the
     retirement latency of instructions

   - Various memory allocation (some detected by ASAN) and reference
     counting fixes

   - Add a 8-byte aligned PERF_RECORD_COMPRESSED2 to replace
     PERF_RECORD_COMPRESSED

   - Skip unsupported event types in perf.data files, don't stop when
     finding one

   - Improve lookups using hashmaps and binary searches"

* tag 'perf-tools-for-v6.16-1-2025-06-03' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (206 commits)
  perf callchain: Always populate the addr_location map when adding IP
  perf lock contention: Reject more than 10ms delays for safety
  perf trace: Set errpid to false for rseq and set_robust_list
  perf symbol: Move demangling code out of symbol-elf.c
  perf trace: Always print return value for syscalls returning a pid
  perf script: Print PERF_AUX_FLAG_COLLISION flag
  perf mem: Show absolute percent in mem_stat output
  perf mem: Display sort order only if it's available
  perf mem: Describe overhead calculation in brief
  perf record: Fix incorrect --user-regs comments
  Revert "perf thread: Ensure comm_lock held for comm_list"
  perf test trace_summary: Skip --bpf-summary tests if no libbpf
  perf test intel-pt: Skip jitdump test if no libelf
  perf intel-tpebs: Avoid race when evlist is being deleted
  perf test demangle-java: Don't segv if demangling fails
  perf symbol: Fix use-after-free in filename__read_build_id
  perf pmu: Avoid segv for missing name/alias_name in wildcarding
  perf machine: Factor creating a "live" machine out of dwarf-unwind
  perf test: Add AMD IBS sw filter test
  perf mem: Count L2 HITM for c2c statistic
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc tools/arch/x86/include/asm/cpufeatures.h
index 98c8931db4a56594128716b541f8054b6af40d3b,30144ef9ef02fb62e433bb5be7f86167c0a66a79..e02be2962a0181ec6de40aa5a6b617b600b206b0
--- 1/tools/arch/x86/include/asm/cpufeatures.h
--- 2/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@@ -477,11 -476,12 +477,12 @@@
  #define X86_FEATURE_CLEAR_BHB_LOOP    (21*32+ 1) /* Clear branch history at syscall entry using SW loop */
  #define X86_FEATURE_BHI_CTRL          (21*32+ 2) /* BHI_DIS_S HW control available */
  #define X86_FEATURE_CLEAR_BHB_HW      (21*32+ 3) /* BHI_DIS_S HW control enabled */
 -#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
 -#define X86_FEATURE_AMD_FAST_CPPC     (21*32 + 5) /* Fast CPPC */
 -#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
 -#define X86_FEATURE_AMD_WORKLOAD_CLASS        (21*32 + 7) /* Workload Classification */
 -#define X86_FEATURE_PREFER_YMM                (21*32 + 8) /* Avoid ZMM registers due to downclocking */
 -#define X86_FEATURE_INDIRECT_THUNK_ITS        (21*32 + 9) /* Use thunk for indirect branches in lower half of cacheline */
 +#define X86_FEATURE_CLEAR_BHB_VMEXIT  (21*32+ 4) /* Clear branch history at vmexit using SW loop */
 +#define X86_FEATURE_AMD_FAST_CPPC     (21*32+ 5) /* Fast CPPC */
 +#define X86_FEATURE_AMD_HTR_CORES     (21*32+ 6) /* Heterogeneous Core Topology */
 +#define X86_FEATURE_AMD_WORKLOAD_CLASS        (21*32+ 7) /* Workload Classification */
 +#define X86_FEATURE_PREFER_YMM                (21*32+ 8) /* Avoid ZMM registers due to downclocking */
++#define X86_FEATURE_INDIRECT_THUNK_ITS        (21*32+ 9) /* Use thunk for indirect branches in lower half of cacheline */
  
  /*
   * BUG word(s)
@@@ -528,10 -528,12 +529,12 @@@
  #define X86_BUG_TDX_PW_MCE            X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does partial write to TDX private memory */
  
  /* BUG word 2 */
 -#define X86_BUG_SRSO                  X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */
 -#define X86_BUG_DIV0                  X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
 -#define X86_BUG_RFDS                  X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
 -#define X86_BUG_BHI                   X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
 -#define X86_BUG_IBPB_NO_RET           X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
 -#define X86_BUG_SPECTRE_V2_USER               X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
 -#define X86_BUG_ITS                   X86_BUG(1*32 + 6) /* "its" CPU is affected by Indirect Target Selection */
 -#define X86_BUG_ITS_NATIVE_ONLY               X86_BUG(1*32 + 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
 +#define X86_BUG_SRSO                  X86_BUG( 1*32+ 0) /* "srso" AMD SRSO bug */
 +#define X86_BUG_DIV0                  X86_BUG( 1*32+ 1) /* "div0" AMD DIV0 speculation bug */
 +#define X86_BUG_RFDS                  X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
 +#define X86_BUG_BHI                   X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
 +#define X86_BUG_IBPB_NO_RET           X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */
 +#define X86_BUG_SPECTRE_V2_USER               X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
++#define X86_BUG_ITS                   X86_BUG( 1*32+ 6) /* "its" CPU is affected by Indirect Target Selection */
++#define X86_BUG_ITS_NATIVE_ONLY               X86_BUG( 1*32+ 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
  #endif /* _ASM_X86_CPUFEATURES_H */

diff --cc tools/perf/util/amd-sample-raw.c
Simple merge