drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCP

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_GCP register macro.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/36f0b90f07c7aa78e88fadb375359df39ecd0a77.1716808214.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 4557acdd8b3c2edfef18816cf203f4542a2b85e3..18a95d7f2771078da66516f0680a4080ac78aee6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -986,7 +986,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
                return false;
 
        if (HAS_DDI(dev_priv))
-               reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
+               reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
        else if (HAS_PCH_SPLIT(dev_priv))
@@ -1011,7 +1011,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
                return;
 
        if (HAS_DDI(dev_priv))
-               reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
+               reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
        else if (HAS_PCH_SPLIT(dev_priv))

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0331fdd61f331fd8b8856ae3e42ebf5d6b62ecbc..ff520171ac1696fa419fbcda30a1dfb10f3a23ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3476,7 +3476,7 @@
 #define _ICL_VIDEO_DIP_PPS_ECC_B       0x613D4
 
 #define HSW_TVIDEO_DIP_CTL(dev_priv, trans)            _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
-#define HSW_TVIDEO_DIP_GCP(trans)              _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
+#define HSW_TVIDEO_DIP_GCP(dev_priv, trans)            _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)      _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)       _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)      _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 027cd273d775b434db5b86cec87c97701cfa3a53..349578cc0fc85fb771384000c3178c0ee8d2e5a0 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1235,9 +1235,9 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(BXT_DSI_PLL_ENABLE);
        MMIO_D(GEN9_CLKGATE_DIS_0);
        MMIO_D(GEN9_CLKGATE_DIS_4);
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A));
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B));
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C));
        MMIO_D(RC6_CTX_BASE);
        MMIO_D(GEN8_PUSHBUS_CONTROL);
        MMIO_D(GEN8_PUSHBUS_ENABLE);