PCI: dwc: Add support for configuring lane equalization presets

PCIe equalization presets are predefined settings used to optimize signal
integrity by compensating for signal loss and distortion in high-speed data
transmission.

Based upon the number of lanes and the data rate supported, write the
preset data read from the device tree in to the lane equalization control
registers. These preset values will be used by the controller during the
LTSSM lane equalization procedure.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: reworded the commit message and comments in the driver]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250328-preset_v6-v9-5-22cfa0490518@oss.qualcomm.com

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index e8eccf6a1b2f98a6237d4fa3bb72d2683fa50ae7..b7faef26ed44050af492182f1c7ea37cf7886e5b 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -526,6 +526,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
        if (pci->num_lanes < 1)
                pci->num_lanes = dw_pcie_link_get_max_link_width(pci);
 
+       ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes);
+       if (ret)
+               goto err_free_msi;
+
        /*
         * Allocate the resource for MSG TLP before programming the iATU
         * outbound window in dw_pcie_setup_rc(). Since the allocation depends
@@ -831,6 +835,77 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
        return 0;
 }
 
+static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed)
+{
+       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+       u8 lane_eq_offset, lane_reg_size, cap_id;
+       u8 *presets;
+       u32 cap;
+       int i;
+
+       if (speed == PCIE_SPEED_8_0GT) {
+               presets = (u8 *)pp->presets.eq_presets_8gts;
+               lane_eq_offset =  PCI_SECPCI_LE_CTRL;
+               cap_id = PCI_EXT_CAP_ID_SECPCI;
+               /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/
+               lane_reg_size = 0x2;
+       } else if (speed == PCIE_SPEED_16_0GT) {
+               presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1];
+               lane_eq_offset = PCI_PL_16GT_LE_CTRL;
+               cap_id = PCI_EXT_CAP_ID_PL_16GT;
+               lane_reg_size = 0x1;
+       } else if (speed == PCIE_SPEED_32_0GT) {
+               presets =  pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_32GTS - 1];
+               lane_eq_offset = PCI_PL_32GT_LE_CTRL;
+               cap_id = PCI_EXT_CAP_ID_PL_32GT;
+               lane_reg_size = 0x1;
+       } else if (speed == PCIE_SPEED_64_0GT) {
+               presets =  pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_64GTS - 1];
+               lane_eq_offset = PCI_PL_64GT_LE_CTRL;
+               cap_id = PCI_EXT_CAP_ID_PL_64GT;
+               lane_reg_size = 0x1;
+       } else {
+               return;
+       }
+
+       if (presets[0] == PCI_EQ_RESV)
+               return;
+
+       cap = dw_pcie_find_ext_capability(pci, cap_id);
+       if (!cap)
+               return;
+
+       /*
+        * Write preset values to the registers byte-by-byte for the given
+        * number of lanes and register size.
+        */
+       for (i = 0; i < pci->num_lanes * lane_reg_size; i++)
+               dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]);
+}
+
+static void dw_pcie_config_presets(struct dw_pcie_rp *pp)
+{
+       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+       enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed];
+
+       /*
+        * Lane equalization settings need to be applied for all data rates the
+        * controller supports and for all supported lanes.
+        */
+
+       if (speed >= PCIE_SPEED_8_0GT)
+               dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT);
+
+       if (speed >= PCIE_SPEED_16_0GT)
+               dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT);
+
+       if (speed >= PCIE_SPEED_32_0GT)
+               dw_pcie_program_presets(pp, PCIE_SPEED_32_0GT);
+
+       if (speed >= PCIE_SPEED_64_0GT)
+               dw_pcie_program_presets(pp, PCIE_SPEED_64_0GT);
+}
+
 int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -884,6 +959,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
                PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
        dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 
+       dw_pcie_config_presets(pp);
        /*
         * If the platform provides its own child bus config accesses, it means
         * the platform uses its own address translation component rather than

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index dda788e3bd24ddc8b7d44498ba3aace6f8f2d187..7add69f13759f1bb70bc25867f3fbda11bb6c761 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -25,6 +25,8 @@
 #include <linux/pci-epc.h>
 #include <linux/pci-epf.h>
 
+#include "../../pci.h"
+
 /* DWC PCIe IP-core versions (native support since v4.70a) */
 #define DW_PCIE_VER_365A               0x3336352a
 #define DW_PCIE_VER_460A               0x3436302a
@@ -412,6 +414,7 @@ struct dw_pcie_rp {
        int                     msg_atu_index;
        struct resource         *msg_res;
        bool                    use_linkup_irq;
+       struct pci_eq_presets   presets;
 };
 
 struct dw_pcie_ep_ops {