mtd: spi-nor: Add USE_FSR flag for n25q* entries

Add USE_FSR flag to all variants of n25q entries that support Flag Status
Register.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: John Garry <john.garry@huawei.com> #for n25q128a13
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 77d29604d4dbfb0a09c1b9e84ad9355db8a8842d..e818fe405a48a434f35159bf568fe3ff36ea4c4f 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2476,16 +2476,21 @@ static const struct flash_info spi_nor_ids[] = {
        { "n25q032a",    INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
        { "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
-       { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
-       { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
+       { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K |
+                             USE_FSR | SPI_NOR_QUAD_READ) },
+       { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K |
+                             USE_FSR | SPI_NOR_QUAD_READ) },
        { "mt25ql256a",  INFO6(0x20ba19, 0x104400, 64 * 1024,  512,
                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
                               SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-       { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K |
+                             USE_FSR | SPI_NOR_DUAL_READ |
+                             SPI_NOR_QUAD_READ) },
        { "mt25qu256a",  INFO6(0x20bb19, 0x104400, 64 * 1024,  512,
                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
                               SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-       { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
+       { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K |
+                             USE_FSR | SPI_NOR_QUAD_READ) },
        { "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
                               SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
@@ -2494,7 +2499,7 @@ static const struct flash_info spi_nor_ids[] = {
                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
                               SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
        { "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
-                             SPI_NOR_QUAD_READ) },
+                             USE_FSR | SPI_NOR_QUAD_READ) },
        { "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
        { "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
        { "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,