arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy links

Marvell CN913x platforms use common phy framework for configuring and
linking serdes lanes according to their usage.
Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY
nodes.

CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1
respectively. Devicetree however wrongly links from these ports to the
comphy of CP0.

Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1,
cp1_eth2.

Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
index b1ea7dcaed17dc0205d1ae91d4178dd1f8313a5b..47234d0858dd2195bb1485f25768ad3c757b7ac2 100644 (file)
--- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
@@ -435,7 +435,7 @@
        managed = "in-band-status";
        phy-mode = "sgmii";
        phy = <&cp1_phy0>;
-       phys = <&cp0_comphy3 1>;
+       phys = <&cp1_comphy3 1>;
        status = "okay";
 };
 
@@ -444,7 +444,7 @@
        managed = "in-band-status";
        phy-mode = "sgmii";
        phy = <&cp1_phy1>;
-       phys = <&cp0_comphy5 2>;
+       phys = <&cp1_comphy5 2>;
        status = "okay";
 };