OPTIM: ring: use relaxed stores to release the threads

We don't care in what order the threads are released, so we can write
their sent value using relaxed atomic stores. This brings a 3-5% perf
boost on ARM with 80 cores, reaching 7.25M/s, and doesn't change
anything on x86 since it keeps using strict ordering.

diff --git a/src/ring.c b/src/ring.c
index 9f2be10fda9a2f0ad9d9342a8ce052aa13d7aaaf..8d46679cca65537f3fccfa4807c5f32fe9d392f5 100644 (file)
--- a/src/ring.c
+++ b/src/ring.c
@@ -411,7 +411,7 @@ ssize_t ring_write(struct ring *ring, size_t maxlen, const struct ist pfx[], siz
                /* now release */
                for (curr_cell = &cell; curr_cell; curr_cell = next_cell) {
                        next_cell = HA_ATOMIC_LOAD(&curr_cell->next);
-                       HA_ATOMIC_STORE(&curr_cell->next, curr_cell);
+                       _HA_ATOMIC_STORE(&curr_cell->next, curr_cell);
                }
 
                /* unlock the message area */
@@ -421,7 +421,7 @@ ssize_t ring_write(struct ring *ring, size_t maxlen, const struct ist pfx[], siz
                for (curr_cell = &cell; curr_cell; curr_cell = next_cell) {
                        next_cell = HA_ATOMIC_LOAD(&curr_cell->next);
                        HA_ATOMIC_STORE(&curr_cell->to_send_self, 0);
-                       HA_ATOMIC_STORE(&curr_cell->next, curr_cell);
+                       _HA_ATOMIC_STORE(&curr_cell->next, curr_cell);
                }
        }