pinctrl: cy8c95x0: Rename PWMSEL to SELPWM

There are two registers in the hardware, one, "Select PWM",
is per-port configuration enabling PWM function instead of GPIO.
The other one is "PWM Select" is per-PWM selector to configure
PWM itself. Original code uses abbreviation of the latter
to describe the former. Rename it to follow the datasheet.

Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/20250203131506.3318201-5-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c
index bfa16f70e29ce1e6d62f7c6acec8c1c8cd9b2c68..75100a9fb8e4cee80372d3bb08233528c587bb12 100644 (file)
--- a/drivers/pinctrl/pinctrl-cy8c95x0.c
+++ b/drivers/pinctrl/pinctrl-cy8c95x0.c
@@ -42,7 +42,7 @@
 #define CY8C95X0_PORTSEL       0x18
 /* Port settings, write PORTSEL first */
 #define CY8C95X0_INTMASK       0x19
-#define CY8C95X0_PWMSEL                0x1A
+#define CY8C95X0_SELPWM                0x1A
 #define CY8C95X0_INVERT                0x1B
 #define CY8C95X0_DIRECTION     0x1C
 /* Drive mode register change state on writing '1' */
@@ -369,8 +369,8 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
        case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
        case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
        case CY8C95X0_INTMASK:
+       case CY8C95X0_SELPWM:
        case CY8C95X0_INVERT:
-       case CY8C95X0_PWMSEL:
        case CY8C95X0_DIRECTION:
        case CY8C95X0_DRV_PU:
        case CY8C95X0_DRV_PD:
@@ -399,7 +399,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg)
 {
        switch (reg) {
        case CY8C95X0_INTMASK:
-       case CY8C95X0_PWMSEL:
+       case CY8C95X0_SELPWM:
        case CY8C95X0_INVERT:
        case CY8C95X0_DIRECTION:
        case CY8C95X0_DRV_PU:
@@ -797,7 +797,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
                reg = CY8C95X0_DIRECTION;
                break;
        case PIN_CONFIG_MODE_PWM:
-               reg = CY8C95X0_PWMSEL;
+               reg = CY8C95X0_SELPWM;
                break;
        case PIN_CONFIG_OUTPUT:
                reg = CY8C95X0_OUTPUT;
@@ -876,7 +876,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
                reg = CY8C95X0_DRV_PP_FAST;
                break;
        case PIN_CONFIG_MODE_PWM:
-               reg = CY8C95X0_PWMSEL;
+               reg = CY8C95X0_SELPWM;
                break;
        case PIN_CONFIG_OUTPUT_ENABLE:
                return cy8c95x0_pinmux_direction(chip, off, !arg);
@@ -1161,7 +1161,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *
        bitmap_zero(mask, MAX_LINE);
        __set_bit(pin, mask);
 
-       if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
+       if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) {
                seq_puts(s, "not available");
                return;
        }
@@ -1206,7 +1206,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bo
        u8 port = cypress_get_port(chip, off);
        u8 bit = cypress_get_pin_mask(chip, off);
 
-       return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
+       return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0);
 }
 
 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,