EDAC/qcom: Make irq configuration optional

On most modern qualcomm SoCs, the configuration necessary to enable the
Tag/Data RAM related irqs being propagated to the SoC irq controller is
already done in firmware (in DSF or 'DDR System Firmware')

On some like the x1e80100, these registers aren't even accesible to the
kernel causing a crash when edac device is probed.

Hence, make the irq configuration optional in the driver and mark x1e80100
as the SoC on which this should be avoided.

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reported-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240903101510.3452734-1-quic_rjendra@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
index d3cd4cc54ace9d31e8af583e8e75bd6d3cf5d81b..a9a8ba067007a9a2fc5bb7f473bc6f7783d62514 100644 (file)
--- a/drivers/edac/qcom_edac.c
+++ b/drivers/edac/qcom_edac.c
@@ -342,9 +342,11 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev)
        int ecc_irq;
        int rc;
 
-       rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);
-       if (rc)
-               return rc;
+       if (!llcc_driv_data->ecc_irq_configured) {
+               rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);
+               if (rc)
+                       return rc;
+       }
 
        /* Allocate edac control info */
        edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 8fa4ffd3a9b5921d95c20648048dcdfa20dde5db..28bcc65e91beb36c0cd38cdd02dae410ed2fb10d 100644 (file)
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -139,6 +139,7 @@ struct qcom_llcc_config {
        int size;
        bool need_llcc_cfg;
        bool no_edac;
+       bool irq_configured;
 };
 
 struct qcom_sct_config {
@@ -718,6 +719,7 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
                .need_llcc_cfg  = true,
                .reg_offset     = llcc_v2_1_reg_offset,
                .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+               .irq_configured = true,
        },
 };
 
@@ -1345,6 +1347,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
        drv_data->cfg = llcc_cfg;
        drv_data->cfg_size = sz;
        drv_data->edac_reg_offset = cfg->edac_reg_offset;
+       drv_data->ecc_irq_configured = cfg->irq_configured;
        mutex_init(&drv_data->lock);
        platform_set_drvdata(pdev, drv_data);
 

diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 9e9f528b13701fcf9df2f1369a1d365ed1f30c71..2f20281d4ad4352ef59e7b19148cd324c7991012 100644 (file)
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -125,6 +125,7 @@ struct llcc_edac_reg_offset {
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @ecc_irq: interrupt for llcc cache error detection and reporting
+ * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation
  * @version: Indicates the LLCC version
  */
 struct llcc_drv_data {
@@ -139,6 +140,7 @@ struct llcc_drv_data {
        u32 num_banks;
        unsigned long *bitmap;
        int ecc_irq;
+       bool ecc_irq_configured;
        u32 version;
 };