pinctrl: renesas: r8a779g0: FIX PWM suffixes

PWM channels 0, 2, 8, and 9 do not have alternate pins.
Remove their "_a" or "_b" suffixes to increase uniformity.

Fixes: c606c2fde2330547 ("pinctrl: renesas: r8a779g0: Add missing PWM")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/abb748e6e1e4e7d78beac7d96e7a0a3481b32e75.1717754960.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index f9f650f232e6e71e19b775b51d58d72bd3e67c4f..3228a61ea4098b93157600d0b7483ae6ebddc086 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -316,9 +316,9 @@
 #define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_B)             FM(SCK1_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_27_24   FM(HRTS0_N)             FM(RTS0_N)              FM(PWM9_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_31_28   FM(HSCK0)               FM(SCK0)                FM(PWM0_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24   FM(HRTS0_N)             FM(RTS0_N)              FM(PWM9)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28   FM(HSCK0)               FM(SCK0)                FM(PWM0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP2SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
 #define IP2SR1_3_0     FM(HRX0)                FM(RX0)                 F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -355,7 +355,7 @@
 #define IP1SR2_15_12   FM(CANFD0_RX)           FM(STPWT_EXTFXR)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_19_16   FM(CANFD2_TX)           FM(TPU0TO2)             F_(0, 0)                FM(TCLK3_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_23_20   FM(CANFD2_RX)           FM(TPU0TO3)             FM(PWM1_B)              FM(TCLK4_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_27_24   FM(CANFD3_TX)           F_(0, 0)                FM(PWM2_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24   FM(CANFD3_TX)           F_(0, 0)                FM(PWM2)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_31_28   FM(CANFD3_RX)           F_(0, 0)                FM(PWM3_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP2SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -827,15 +827,15 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP1SR1_23_20,  HCTS0_N),
        PINMUX_IPSR_GPSR(IP1SR1_23_20,  CTS0_N),
-       PINMUX_IPSR_GPSR(IP1SR1_23_20,  PWM8_A),
+       PINMUX_IPSR_GPSR(IP1SR1_23_20,  PWM8),
 
        PINMUX_IPSR_GPSR(IP1SR1_27_24,  HRTS0_N),
        PINMUX_IPSR_GPSR(IP1SR1_27_24,  RTS0_N),
-       PINMUX_IPSR_GPSR(IP1SR1_27_24,  PWM9_A),
+       PINMUX_IPSR_GPSR(IP1SR1_27_24,  PWM9),
 
        PINMUX_IPSR_GPSR(IP1SR1_31_28,  HSCK0),
        PINMUX_IPSR_GPSR(IP1SR1_31_28,  SCK0),
-       PINMUX_IPSR_GPSR(IP1SR1_31_28,  PWM0_A),
+       PINMUX_IPSR_GPSR(IP1SR1_31_28,  PWM0),
 
        /* IP2SR1 */
        PINMUX_IPSR_GPSR(IP2SR1_3_0,    HRX0),
@@ -937,7 +937,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP1SR2_23_20,  TCLK4_A),
 
        PINMUX_IPSR_GPSR(IP1SR2_27_24,  CANFD3_TX),
-       PINMUX_IPSR_GPSR(IP1SR2_27_24,  PWM2_B),
+       PINMUX_IPSR_GPSR(IP1SR2_27_24,  PWM2),
 
        PINMUX_IPSR_GPSR(IP1SR2_31_28,  CANFD3_RX),
        PINMUX_IPSR_GPSR(IP1SR2_31_28,  PWM3_B),
@@ -2090,13 +2090,13 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
        PCIE1_CLKREQ_N_MARK,
 };
 
-/* - PWM0_A ------------------------------------------------------------------- */
-static const unsigned int pwm0_a_pins[] = {
-       /* PWM0_A */
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+       /* PWM0 */
        RCAR_GP_PIN(1, 15),
 };
-static const unsigned int pwm0_a_mux[] = {
-       PWM0_A_MARK,
+static const unsigned int pwm0_mux[] = {
+       PWM0_MARK,
 };
 
 /* - PWM1_A ------------------------------------------------------------------- */
@@ -2117,13 +2117,13 @@ static const unsigned int pwm1_b_mux[] = {
        PWM1_B_MARK,
 };
 
-/* - PWM2_B ------------------------------------------------------------------- */
-static const unsigned int pwm2_b_pins[] = {
-       /* PWM2_B */
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_pins[] = {
+       /* PWM2 */
        RCAR_GP_PIN(2, 14),
 };
-static const unsigned int pwm2_b_mux[] = {
-       PWM2_B_MARK,
+static const unsigned int pwm2_mux[] = {
+       PWM2_MARK,
 };
 
 /* - PWM3_A ------------------------------------------------------------------- */
@@ -2180,22 +2180,22 @@ static const unsigned int pwm7_mux[] = {
        PWM7_MARK,
 };
 
-/* - PWM8_A ------------------------------------------------------------------- */
-static const unsigned int pwm8_a_pins[] = {
-       /* PWM8_A */
+/* - PWM8 ------------------------------------------------------------------- */
+static const unsigned int pwm8_pins[] = {
+       /* PWM8 */
        RCAR_GP_PIN(1, 13),
 };
-static const unsigned int pwm8_a_mux[] = {
-       PWM8_A_MARK,
+static const unsigned int pwm8_mux[] = {
+       PWM8_MARK,
 };
 
-/* - PWM9_A ------------------------------------------------------------------- */
-static const unsigned int pwm9_a_pins[] = {
-       /* PWM9_A */
+/* - PWM9 ------------------------------------------------------------------- */
+static const unsigned int pwm9_pins[] = {
+       /* PWM9 */
        RCAR_GP_PIN(1, 14),
 };
-static const unsigned int pwm9_a_mux[] = {
-       PWM9_A_MARK,
+static const unsigned int pwm9_mux[] = {
+       PWM9_MARK,
 };
 
 /* - QSPI0 ------------------------------------------------------------------ */
@@ -2658,18 +2658,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(pcie0_clkreq_n),
        SH_PFC_PIN_GROUP(pcie1_clkreq_n),
 
-       SH_PFC_PIN_GROUP(pwm0_a),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm0),
        SH_PFC_PIN_GROUP(pwm1_a),
        SH_PFC_PIN_GROUP(pwm1_b),
-       SH_PFC_PIN_GROUP(pwm2_b),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm2),
        SH_PFC_PIN_GROUP(pwm3_a),
        SH_PFC_PIN_GROUP(pwm3_b),
        SH_PFC_PIN_GROUP(pwm4),
        SH_PFC_PIN_GROUP(pwm5),
        SH_PFC_PIN_GROUP(pwm6),
        SH_PFC_PIN_GROUP(pwm7),
-       SH_PFC_PIN_GROUP(pwm8_a),               /* suffix might be updated */
-       SH_PFC_PIN_GROUP(pwm9_a),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm8),
+       SH_PFC_PIN_GROUP(pwm9),
 
        SH_PFC_PIN_GROUP(qspi0_ctrl),
        BUS_DATA_PIN_GROUP(qspi0_data, 2),
@@ -2923,8 +2923,7 @@ static const char * const pcie_groups[] = {
 };
 
 static const char * const pwm0_groups[] = {
-       /* suffix might be updated */
-       "pwm0_a",
+       "pwm0",
 };
 
 static const char * const pwm1_groups[] = {
@@ -2933,8 +2932,7 @@ static const char * const pwm1_groups[] = {
 };
 
 static const char * const pwm2_groups[] = {
-       /* suffix might be updated */
-       "pwm2_b",
+       "pwm2",
 };
 
 static const char * const pwm3_groups[] = {
@@ -2959,13 +2957,11 @@ static const char * const pwm7_groups[] = {
 };
 
 static const char * const pwm8_groups[] = {
-       /* suffix might be updated */
-       "pwm8_a",
+       "pwm8",
 };
 
 static const char * const pwm9_groups[] = {
-       /* suffix might be updated */
-       "pwm9_a",
+       "pwm9",
 };
 
 static const char * const qspi0_groups[] = {