]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
RISC-V: Add augmented hypervisor extension 'sha' support.
authorJiawei <jiawei@iscas.ac.cn>
Fri, 9 May 2025 02:55:25 +0000 (10:55 +0800)
committerNelson Chu <nelson@rivosinc.com>
Fri, 9 May 2025 04:30:52 +0000 (12:30 +0800)
The augmented hypervisor extension 'sha'[1] is a new profile-defined extension
that captures the full set of features that are mandated to be supported along
with the H extension.

https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile

bfd/ChangeLog:

* elfxx-riscv.c: New extension and implies.

gas/ChangeLog:

* NEWS: New extension.
* testsuite/gas/riscv/imply.d: New test for sha.
* testsuite/gas/riscv/imply.s: Ditto.
* testsuite/gas/riscv/march-help.l: New extension.

bfd/elfxx-riscv.c
gas/NEWS
gas/testsuite/gas/riscv/imply.d
gas/testsuite/gas/riscv/imply.s
gas/testsuite/gas/riscv/march-help.l

index 5cb2500a35a6066bf896b1f9fb85e019b386e0c4..83e237c2a03627a47bafabbad13a34240f03abef 100644 (file)
@@ -1223,6 +1223,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zicfilp", "+zicsr", check_implicit_always},
   {"zicfiss", "+zimop,+zicsr", check_implicit_always},
 
+  {"sha", "+h,+ssstateen,+shcounterenw,+shvstvala,+shtvala,+shvstvecd,+shvsatpa,+shgatpa", check_implicit_always},
+
   {"shcounterenw", "+h", check_implicit_always},
   {"shgatpa", "+h", check_implicit_always},
   {"shtvala", "+h", check_implicit_always},
@@ -1447,6 +1449,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
+  {"sha",              ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"shcounterenw",     ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"shgatpa",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"shtvala",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
index af0c37c480a053f6c6828418bf51c715451d1fd7..9d845a8bdca415609ee0b0085d09670804b566c2 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -11,7 +11,8 @@
 * Add support for RISC-V privileged version 1.13.
 
 * Add support for RISC-V standard extensions:
-  ssqosid v1.0, ssnpm v1.0, smnpm v1.0, smmpm v1.0, sspm v1.0, supm v1.0.
+  ssqosid v1.0, ssnpm v1.0, smnpm v1.0, smmpm v1.0, sspm v1.0, supm v1.0,
+  sha v1.0.
 
 * Add support for RISC-V vendor extensions:
   T-Head: xtheadvdot v1.0.
index 78ff200e810fa514f8e932bdc807780a2ee97cb9..bce97ddf471a1bbc72e48a71a01593ec0269c407 100644 (file)
@@ -51,6 +51,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zca1p0_zcmt1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicfilp1p0_zicsr2p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0
index d696b52655ab4e9f9df23b8755007e20ea51051e..c047ed6b758ea183557e0669f9aa93aa90b9f06e 100644 (file)
@@ -57,6 +57,8 @@ imply zcmt
 imply zicfilp
 imply zicfiss
 
+imply sha
+
 imply shcounterenw
 imply shgatpa
 imply shtvala
index e71795663f5d464081dc6ea28d4005c8e18e157f..bcc3a8f1fbd09eb010ea4b749c47cdcb1be138a3 100644 (file)
@@ -107,6 +107,7 @@ All available -march extensions for RISC-V:
        zcmop                                   1.0
        zcmp                                    1.0
        zcmt                                    1.0
+       sha                                     1.0
        shcounterenw                            1.0
        shgatpa                                 1.0
        shtvala                                 1.0