perf/amd/ibs: Update DTLB/PageSize decode logic

IBS Op PMU on Zen5 reports DTLB and page size information differently
compared to prior generation. The change is enumerated by
CPUID_Fn8000001B_EAX[19].

  IBS_OP_DATA3     Zen3/4                 Zen5
  ----------------------------------------------------------------
  19               IbsDcL2TlbHit1G        Reserved
  ----------------------------------------------------------------
   6               IbsDcL2tlbHit2M        Reserved
  ----------------------------------------------------------------
   5               IbsDcL1TlbHit1G        PageSize:
   4               IbsDcL1TlbHit2M          0 - 4K
                                            1 - 2M
                                            2 - 1G
                                            3 - Reserved
                                          Valid only if
                                            IbsDcPhyAddrValid = 1
  ----------------------------------------------------------------
   3               IbsDcL2TlbMiss         IbsDcL2TlbMiss
                                          Valid only if
                                            IbsDcPhyAddrValid = 1
  ----------------------------------------------------------------
   2               IbsDcL1tlbMiss         IbsDcL1tlbMiss
                                          Valid only if
                                            IbsDcPhyAddrValid = 1
  ----------------------------------------------------------------

o Currently, only bit 2 and 3 are interpreted by IBS NMI handler for
  PERF_SAMPLE_DATA_SRC. Add dependency on IbsDcPhyAddrValid for those
  bits.

o Introduce new IBS Op PMU capability and expose it to userspace via
  PMU's sysfs directory.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250205060547.1337-3-ravi.bangoria@amd.com

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 85b29b3f305b2b97f99d38d2eb1aecbfe9e3e9d1..7b52b8e3a185157fc74812cdcc4f75fd9b932853 100644 (file)
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -629,6 +629,7 @@ PMU_EVENT_ATTR_STRING(l3missonly, op_l3missonly, "config:16");
 PMU_EVENT_ATTR_STRING(ldlat, ibs_op_ldlat_format, "config1:0-11");
 PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1");
 PMU_EVENT_ATTR_STRING(ldlat, ibs_op_ldlat_cap, "1");
+PMU_EVENT_ATTR_STRING(dtlb_pgsize, ibs_op_dtlb_pgsize_cap, "1");
 
 static umode_t
 zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *attr, int i)
@@ -642,6 +643,12 @@ ibs_op_ldlat_is_visible(struct kobject *kobj, struct attribute *attr, int i)
        return ibs_caps & IBS_CAPS_OPLDLAT ? attr->mode : 0;
 }
 
+static umode_t
+ibs_op_dtlb_pgsize_is_visible(struct kobject *kobj, struct attribute *attr, int i)
+{
+       return ibs_caps & IBS_CAPS_OPDTLBPGSIZE ? attr->mode : 0;
+}
+
 static struct attribute *fetch_attrs[] = {
        &format_attr_rand_en.attr,
        &format_attr_swfilt.attr,
@@ -663,6 +670,11 @@ static struct attribute *ibs_op_ldlat_cap_attrs[] = {
        NULL,
 };
 
+static struct attribute *ibs_op_dtlb_pgsize_cap_attrs[] = {
+       &ibs_op_dtlb_pgsize_cap.attr.attr,
+       NULL,
+};
+
 static struct attribute_group group_fetch_formats = {
        .name = "format",
        .attrs = fetch_attrs,
@@ -686,6 +698,12 @@ static struct attribute_group group_ibs_op_ldlat_cap = {
        .is_visible = ibs_op_ldlat_is_visible,
 };
 
+static struct attribute_group group_ibs_op_dtlb_pgsize_cap = {
+       .name = "caps",
+       .attrs = ibs_op_dtlb_pgsize_cap_attrs,
+       .is_visible = ibs_op_dtlb_pgsize_is_visible,
+};
+
 static const struct attribute_group *fetch_attr_groups[] = {
        &group_fetch_formats,
        &empty_caps_group,
@@ -759,6 +777,7 @@ static const struct attribute_group *op_attr_update[] = {
        &group_zen4_ibs_extensions,
        &group_ibs_op_ldlat_cap,
        &group_ibs_op_ldlat_format,
+       &group_ibs_op_dtlb_pgsize_cap,
        NULL,
 };
 
@@ -1007,6 +1026,10 @@ static void perf_ibs_get_tlb_lvl(union ibs_op_data3 *op_data3,
        if (!op_data3->dc_lin_addr_valid)
                return;
 
+       if ((ibs_caps & IBS_CAPS_OPDTLBPGSIZE) &&
+           !op_data3->dc_phy_addr_valid)
+               return;
+
        if (!op_data3->dc_l1tlb_miss) {
                data_src->mem_dtlb = PERF_MEM_TLB_L1 | PERF_MEM_TLB_HIT;
                return;

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index a60efe47498dec4033215a2f560a5a2b09fe58af..43b17b7b6ac078a810449c9a66550f16e9f91666 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -503,6 +503,7 @@ struct pebs_cntr_header {
 #define IBS_CAPS_OPDATA4               (1U<<10)
 #define IBS_CAPS_ZEN4                  (1U<<11)
 #define IBS_CAPS_OPLDLAT               (1U<<12)
+#define IBS_CAPS_OPDTLBPGSIZE          (1U<<19)
 
 #define IBS_CAPS_DEFAULT               (IBS_CAPS_AVAIL         \
                                         | IBS_CAPS_FETCHSAM    \