/* Check that we have an UNDI entry point */
cmpw $0, undinet_entry_point
je chain
-
+
+ /* Mask interrupt and set rearm flag */
+ movw undiisr_imr, %dx
+ inb %dx, %al
+ orb undiisr_bit, %al
+ outb %al, %dx
+ movb %al, undiisr_rearm
+
/* Issue UNDI API call */
+ movw %ds, %ax
movw %ax, %es
movw $undinet_params, %di
movw $PXENV_UNDI_ISR, %bx
uint8_t __data16 ( undiisr_irq );
#define undiisr_irq __use_data16 ( undiisr_irq )
+/** IRQ mask register */
+uint16_t __data16 ( undiisr_imr );
+#define undiisr_imr __use_data16 ( undiisr_imr )
+
+/** IRQ mask bit */
+uint8_t __data16 ( undiisr_bit );
+#define undiisr_bit __use_data16 ( undiisr_bit )
+
+/** IRQ rearm flag */
+uint8_t __data16 ( undiisr_rearm );
+#define undiisr_rearm __use_data16 ( undiisr_rearm )
+
/** IRQ chain vector */
struct segoff __data16 ( undiisr_next_handler );
#define undiisr_next_handler __use_data16 ( undiisr_next_handler )
assert ( undiisr_irq == 0 );
undiisr_irq = irq;
+ undiisr_imr = IMR_REG ( irq );
+ undiisr_bit = IMR_BIT ( irq );
+ undiisr_rearm = 0;
hook_bios_interrupt ( IRQ_INT ( irq ), ( ( intptr_t ) undiisr ),
&undiisr_next_handler );
}
* support interrupts.
*/
if ( ! undinet_isr_triggered() ) {
+
+ /* Rearm interrupt if needed */
+ if ( undiisr_rearm ) {
+ undiisr_rearm = 0;
+ assert ( undinic->irq != 0 );
+ enable_irq ( undinic->irq );
+ }
+
/* Allow interrupt to occur */
profile_start ( &undinet_irq_profiler );
__asm__ __volatile__ ( "sti\n\t"