Merge tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu...

target-arm queue:
 * hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
 * tests/functional: Add a test for the realview-eb-mpcore machine
 * qemu-options.hx: Fix reversed description of icount sleep behavior
 * target/arm: Define raw write for PMU CLR registers
 * docs/interop: convert qed_spec.txt to reStructuredText format
 * hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
 * hw/intc/arm_gic: introduce a first-cpu-index property
 * hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
 * linux-user/arm: Fix return value of SYS_cacheflush

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# gpg: Signature made Mon 16 Jun 2025 10:05:44 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm:
  linux-user/arm: Fix return value of SYS_cacheflush
  hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
  hw/intc/arm_gic: introduce a first-cpu-index property
  hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
  docs/interop: convert qed_spec.txt to reStructuredText format
  target/arm: Define raw write for PMU CLR registers
  qemu-options.hx: Fix reversed description of icount sleep behavior
  tests/functional: Add a test for the realview-eb-mpcore machine
  hw/arm/virt: Check bypass iommu is not set for iommu-map DT property

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>