RISC-V: Add load/store instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	load/store instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLBV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index e509ed0971be8bbf0bfb4f25b3c2c74d5fe4cee9..d7cb1e1a4571bbe86dbe8bb77a1b211af81728a5 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -10,3 +10,135 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+80c5f557[     ]+th.vsetvl[    ]+a0,a1,a2
 [      ]+[0-9a-f]+:[   ]+0005f557[     ]+th.vsetvli[   ]+a0,a1,e8,m1,tu,mu
 [      ]+[0-9a-f]+:[   ]+7ff5f557[     ]+th.vsetvli[   ]+a0,a1,2047
+[      ]+[0-9a-f]+:[   ]+12050207[     ]+th.vlb.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+12050207[     ]+th.vlb.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+10050207[     ]+th.vlb.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+12055207[     ]+th.vlh.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+12055207[     ]+th.vlh.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+10055207[     ]+th.vlh.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+12056207[     ]+th.vlw.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+12056207[     ]+th.vlw.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+10056207[     ]+th.vlw.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02050207[     ]+th.vlbu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02050207[     ]+th.vlbu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00050207[     ]+th.vlbu.v[    ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02055207[     ]+th.vlhu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02055207[     ]+th.vlhu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00055207[     ]+th.vlhu.v[    ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02056207[     ]+th.vlwu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02056207[     ]+th.vlwu.v[    ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00056207[     ]+th.vlwu.v[    ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02057207[     ]+th.vle.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02057207[     ]+th.vle.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00057207[     ]+th.vle.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02050227[     ]+th.vsb.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02050227[     ]+th.vsb.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00050227[     ]+th.vsb.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02055227[     ]+th.vsh.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02055227[     ]+th.vsh.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00055227[     ]+th.vsh.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02056227[     ]+th.vsw.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02056227[     ]+th.vsw.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00056227[     ]+th.vsw.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+02057227[     ]+th.vse.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+02057227[     ]+th.vse.v[     ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+00057227[     ]+th.vse.v[     ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+1ab50207[     ]+th.vlsb.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+1ab50207[     ]+th.vlsb.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+18b50207[     ]+th.vlsb.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+1ab55207[     ]+th.vlsh.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+1ab55207[     ]+th.vlsh.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+18b55207[     ]+th.vlsh.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+1ab56207[     ]+th.vlsw.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+1ab56207[     ]+th.vlsw.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+18b56207[     ]+th.vlsw.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab50207[     ]+th.vlsbu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab50207[     ]+th.vlsbu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b50207[     ]+th.vlsbu.v[   ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab55207[     ]+th.vlshu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab55207[     ]+th.vlshu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b55207[     ]+th.vlshu.v[   ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab56207[     ]+th.vlswu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab56207[     ]+th.vlswu.v[   ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b56207[     ]+th.vlswu.v[   ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab57207[     ]+th.vlse.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab57207[     ]+th.vlse.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b57207[     ]+th.vlse.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab50227[     ]+th.vssb.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab50227[     ]+th.vssb.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b50227[     ]+th.vssb.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab55227[     ]+th.vssh.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab55227[     ]+th.vssh.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b55227[     ]+th.vssh.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab56227[     ]+th.vssw.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab56227[     ]+th.vssw.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b56227[     ]+th.vssw.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+0ab57227[     ]+th.vsse.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+0ab57227[     ]+th.vsse.v[    ]+v4,\(a0\),a1
+[      ]+[0-9a-f]+:[   ]+08b57227[     ]+th.vsse.v[    ]+v4,\(a0\),a1,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec50207[     ]+th.vlxb.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec50207[     ]+th.vlxb.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc50207[     ]+th.vlxb.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec55207[     ]+th.vlxh.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec55207[     ]+th.vlxh.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc55207[     ]+th.vlxh.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec56207[     ]+th.vlxw.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec56207[     ]+th.vlxw.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc56207[     ]+th.vlxw.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec50207[     ]+th.vlxbu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec50207[     ]+th.vlxbu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc50207[     ]+th.vlxbu.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec55207[     ]+th.vlxhu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec55207[     ]+th.vlxhu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc55207[     ]+th.vlxhu.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec56207[     ]+th.vlxwu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec56207[     ]+th.vlxwu.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc56207[     ]+th.vlxwu.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec57207[     ]+th.vlxe.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec57207[     ]+th.vlxe.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc57207[     ]+th.vlxe.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec50227[     ]+th.vsxb.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec50227[     ]+th.vsxb.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc50227[     ]+th.vsxb.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec55227[     ]+th.vsxh.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec55227[     ]+th.vsxh.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc55227[     ]+th.vsxh.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec56227[     ]+th.vsxw.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec56227[     ]+th.vsxw.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc56227[     ]+th.vsxw.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+0ec57227[     ]+th.vsxe.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0ec57227[     ]+th.vsxe.v[    ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+0cc57227[     ]+th.vsxe.v[    ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec50227[     ]+th.vsuxb.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec50227[     ]+th.vsuxb.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc50227[     ]+th.vsuxb.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec55227[     ]+th.vsuxh.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec55227[     ]+th.vsuxh.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc55227[     ]+th.vsuxh.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec56227[     ]+th.vsuxw.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec56227[     ]+th.vsuxw.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc56227[     ]+th.vsuxw.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1ec57227[     ]+th.vsuxe.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1ec57227[     ]+th.vsuxe.v[   ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+1cc57227[     ]+th.vsuxe.v[   ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+13050207[     ]+th.vlbff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+13050207[     ]+th.vlbff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+11050207[     ]+th.vlbff.v[   ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+13055207[     ]+th.vlhff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+13055207[     ]+th.vlhff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+11055207[     ]+th.vlhff.v[   ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+13056207[     ]+th.vlwff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+13056207[     ]+th.vlwff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+11056207[     ]+th.vlwff.v[   ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+03050207[     ]+th.vlbuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+03050207[     ]+th.vlbuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+01050207[     ]+th.vlbuff.v[  ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+03055207[     ]+th.vlhuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+03055207[     ]+th.vlhuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+01055207[     ]+th.vlhuff.v[  ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+03056207[     ]+th.vlwuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+03056207[     ]+th.vlwuff.v[  ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+01056207[     ]+th.vlwuff.v[  ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+03057207[     ]+th.vleff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+03057207[     ]+th.vleff.v[   ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+01057207[     ]+th.vleff.v[   ]+v4,\(a0\),v0.t

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index ffea0a6f9f99c52243fa6f6a41683ac3bda7f107..c65e9e8790cf2cf80da7815c87551c28dc6951cc 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1,3 +1,139 @@
        th.vsetvl a0, a1, a2
        th.vsetvli a0, a1, 0
        th.vsetvli a0, a1, 0x7ff
+
+       th.vlb.v v4, (a0)
+       th.vlb.v v4, 0(a0)
+       th.vlb.v v4, (a0), v0.t
+       th.vlh.v v4, (a0)
+       th.vlh.v v4, 0(a0)
+       th.vlh.v v4, (a0), v0.t
+       th.vlw.v v4, (a0)
+       th.vlw.v v4, 0(a0)
+       th.vlw.v v4, (a0), v0.t
+       th.vlbu.v v4, (a0)
+       th.vlbu.v v4, 0(a0)
+       th.vlbu.v v4, (a0), v0.t
+       th.vlhu.v v4, (a0)
+       th.vlhu.v v4, 0(a0)
+       th.vlhu.v v4, (a0), v0.t
+       th.vlwu.v v4, (a0)
+       th.vlwu.v v4, 0(a0)
+       th.vlwu.v v4, (a0), v0.t
+       th.vle.v v4, (a0)
+       th.vle.v v4, 0(a0)
+       th.vle.v v4, (a0), v0.t
+       th.vsb.v v4, (a0)
+       th.vsb.v v4, 0(a0)
+       th.vsb.v v4, (a0), v0.t
+       th.vsh.v v4, (a0)
+       th.vsh.v v4, 0(a0)
+       th.vsh.v v4, (a0), v0.t
+       th.vsw.v v4, (a0)
+       th.vsw.v v4, 0(a0)
+       th.vsw.v v4, (a0), v0.t
+       th.vse.v v4, (a0)
+       th.vse.v v4, 0(a0)
+       th.vse.v v4, (a0), v0.t
+
+       th.vlsb.v v4, (a0), a1
+       th.vlsb.v v4, 0(a0), a1
+       th.vlsb.v v4, (a0), a1, v0.t
+       th.vlsh.v v4, (a0), a1
+       th.vlsh.v v4, 0(a0), a1
+       th.vlsh.v v4, (a0), a1, v0.t
+       th.vlsw.v v4, (a0), a1
+       th.vlsw.v v4, 0(a0), a1
+       th.vlsw.v v4, (a0), a1, v0.t
+       th.vlsbu.v v4, (a0), a1
+       th.vlsbu.v v4, 0(a0), a1
+       th.vlsbu.v v4, (a0), a1, v0.t
+       th.vlshu.v v4, (a0), a1
+       th.vlshu.v v4, 0(a0), a1
+       th.vlshu.v v4, (a0), a1, v0.t
+       th.vlswu.v v4, (a0), a1
+       th.vlswu.v v4, 0(a0), a1
+       th.vlswu.v v4, (a0), a1, v0.t
+       th.vlse.v v4, (a0), a1
+       th.vlse.v v4, 0(a0), a1
+       th.vlse.v v4, (a0), a1, v0.t
+       th.vssb.v v4, (a0), a1
+       th.vssb.v v4, 0(a0), a1
+       th.vssb.v v4, (a0), a1, v0.t
+       th.vssh.v v4, (a0), a1
+       th.vssh.v v4, 0(a0), a1
+       th.vssh.v v4, (a0), a1, v0.t
+       th.vssw.v v4, (a0), a1
+       th.vssw.v v4, 0(a0), a1
+       th.vssw.v v4, (a0), a1, v0.t
+       th.vsse.v v4, (a0), a1
+       th.vsse.v v4, 0(a0), a1
+       th.vsse.v v4, (a0), a1, v0.t
+
+       th.vlxb.v v4, (a0), v12
+       th.vlxb.v v4, 0(a0), v12
+       th.vlxb.v v4, (a0), v12, v0.t
+       th.vlxh.v v4, (a0), v12
+       th.vlxh.v v4, 0(a0), v12
+       th.vlxh.v v4, (a0), v12, v0.t
+       th.vlxw.v v4, (a0), v12
+       th.vlxw.v v4, 0(a0), v12
+       th.vlxw.v v4, (a0), v12, v0.t
+       th.vlxbu.v v4, (a0), v12
+       th.vlxbu.v v4, 0(a0), v12
+       th.vlxbu.v v4, (a0), v12, v0.t
+       th.vlxhu.v v4, (a0), v12
+       th.vlxhu.v v4, 0(a0), v12
+       th.vlxhu.v v4, (a0), v12, v0.t
+       th.vlxwu.v v4, (a0), v12
+       th.vlxwu.v v4, 0(a0), v12
+       th.vlxwu.v v4, (a0), v12, v0.t
+       th.vlxe.v v4, (a0), v12
+       th.vlxe.v v4, 0(a0), v12
+       th.vlxe.v v4, (a0), v12, v0.t
+       th.vsxb.v v4, (a0), v12
+       th.vsxb.v v4, 0(a0), v12
+       th.vsxb.v v4, (a0), v12, v0.t
+       th.vsxh.v v4, (a0), v12
+       th.vsxh.v v4, 0(a0), v12
+       th.vsxh.v v4, (a0), v12, v0.t
+       th.vsxw.v v4, (a0), v12
+       th.vsxw.v v4, 0(a0), v12
+       th.vsxw.v v4, (a0), v12, v0.t
+       th.vsxe.v v4, (a0), v12
+       th.vsxe.v v4, 0(a0), v12
+       th.vsxe.v v4, (a0), v12, v0.t
+       th.vsuxb.v v4, (a0), v12
+       th.vsuxb.v v4, 0(a0), v12
+       th.vsuxb.v v4, (a0), v12, v0.t
+       th.vsuxh.v v4, (a0), v12
+       th.vsuxh.v v4, 0(a0), v12
+       th.vsuxh.v v4, (a0), v12, v0.t
+       th.vsuxw.v v4, (a0), v12
+       th.vsuxw.v v4, 0(a0), v12
+       th.vsuxw.v v4, (a0), v12, v0.t
+       th.vsuxe.v v4, (a0), v12
+       th.vsuxe.v v4, 0(a0), v12
+       th.vsuxe.v v4, (a0), v12, v0.t
+
+       th.vlbff.v v4, (a0)
+       th.vlbff.v v4, 0(a0)
+       th.vlbff.v v4, (a0), v0.t
+       th.vlhff.v v4, (a0)
+       th.vlhff.v v4, 0(a0)
+       th.vlhff.v v4, (a0), v0.t
+       th.vlwff.v v4, (a0)
+       th.vlwff.v v4, 0(a0)
+       th.vlwff.v v4, (a0), v0.t
+       th.vlbuff.v v4, (a0)
+       th.vlbuff.v v4, 0(a0)
+       th.vlbuff.v v4, (a0), v0.t
+       th.vlhuff.v v4, (a0)
+       th.vlhuff.v v4, 0(a0)
+       th.vlhuff.v v4, (a0), v0.t
+       th.vlwuff.v v4, (a0)
+       th.vlwuff.v v4, 0(a0)
+       th.vlwuff.v v4, (a0), v0.t
+       th.vleff.v v4, (a0)
+       th.vleff.v v4, 0(a0)
+       th.vleff.v v4, (a0), v0.t

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ed29384e825b2f90400ee846e662cd47acd505a3..792958b892515d181b78631994b45017080fd28c 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2648,6 +2648,39 @@
 #define MASK_TH_SYNC_IS 0xffffffff
 #define MATCH_TH_SYNC_S 0x0190000b
 #define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific (T-Head) XTheadVector instructions.  */
+#define MATCH_TH_VLBV  0x10000007
+#define MASK_TH_VLBV   0xfdf0707f
+#define MATCH_TH_VLHV  0x10005007
+#define MASK_TH_VLHV   0xfdf0707f
+#define MATCH_TH_VLWV  0x10006007
+#define MASK_TH_VLWV   0xfdf0707f
+#define MATCH_TH_VLSBV    0x18000007
+#define MASK_TH_VLSBV     0xfc00707f
+#define MATCH_TH_VLSHV    0x18005007
+#define MASK_TH_VLSHV     0xfc00707f
+#define MATCH_TH_VLSWV    0x18006007
+#define MASK_TH_VLSWV     0xfc00707f
+#define MATCH_TH_VLXBV    0x1c000007
+#define MASK_TH_VLXBV     0xfc00707f
+#define MATCH_TH_VLXHV    0x1c005007
+#define MASK_TH_VLXHV     0xfc00707f
+#define MATCH_TH_VLXWV    0x1c006007
+#define MASK_TH_VLXWV     0xfc00707f
+#define MATCH_TH_VSUXBV   0x1c000027
+#define MASK_TH_VSUXBV    0xfc00707f
+#define MATCH_TH_VSUXHV   0x1c005027
+#define MASK_TH_VSUXHV    0xfc00707f
+#define MATCH_TH_VSUXWV   0x1c006027
+#define MASK_TH_VSUXWV    0xfc00707f
+#define MATCH_TH_VSUXEV   0x1c007027
+#define MASK_TH_VSUXEV    0xfc00707f
+#define MATCH_TH_VLBFFV  0x11000007
+#define MASK_TH_VLBFFV   0xfdf0707f
+#define MATCH_TH_VLHFFV  0x11005007
+#define MASK_TH_VLHFFV   0xfdf0707f
+#define MATCH_TH_VLWFFV  0x11006007
+#define MASK_TH_VLWFFV   0xfdf0707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4c2a9b5abefa5de1a53c9ffbeacb6e0df344d968..54c1e8a62d96dcdc986c3a0bffd504b7c22d1dec 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2237,6 +2237,50 @@ const struct riscv_opcode riscv_opcodes[] =
 /* Vendor-specific (T-Head) XTheadVector instructions.  */
 {"th.vsetvl",     0, INSN_CLASS_XTHEADVECTOR,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
 {"th.vsetvli",    0, INSN_CLASS_XTHEADVECTOR,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+{"th.vlb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBV, MASK_TH_VLBV, match_opcode, INSN_DREF },
+{"th.vlh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHV, MASK_TH_VLHV, match_opcode, INSN_DREF },
+{"th.vlw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWV, MASK_TH_VLWV, match_opcode, INSN_DREF },
+{"th.vlbu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
+{"th.vlhu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
+{"th.vlwu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
+{"th.vle.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
+{"th.vsb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
+{"th.vsh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
+{"th.vsw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
+{"th.vse.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
+{"th.vlsb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSBV, MASK_TH_VLSBV, match_opcode, INSN_DREF },
+{"th.vlsh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSHV, MASK_TH_VLSHV, match_opcode, INSN_DREF },
+{"th.vlsw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSWV, MASK_TH_VLSWV, match_opcode, INSN_DREF },
+{"th.vlsbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
+{"th.vlshu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
+{"th.vlswu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
+{"th.vlse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
+{"th.vssb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
+{"th.vssh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
+{"th.vssw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
+{"th.vsse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
+{"th.vlxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXBV, MASK_TH_VLXBV, match_opcode, INSN_DREF },
+{"th.vlxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXHV, MASK_TH_VLXHV, match_opcode, INSN_DREF },
+{"th.vlxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXWV, MASK_TH_VLXWV, match_opcode, INSN_DREF },
+{"th.vlxbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF },
+{"th.vlxhu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"th.vlxwu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF },
+{"th.vlxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF },
+{"th.vsxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF },
+{"th.vsxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF },
+{"th.vsxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF },
+{"th.vsxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF },
+{"th.vsuxb.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXBV, MASK_TH_VSUXBV, match_opcode, INSN_DREF },
+{"th.vsuxh.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXHV, MASK_TH_VSUXHV, match_opcode, INSN_DREF },
+{"th.vsuxw.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXWV, MASK_TH_VSUXWV, match_opcode, INSN_DREF },
+{"th.vsuxe.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXEV, MASK_TH_VSUXEV, match_opcode, INSN_DREF },
+{"th.vlbff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBFFV, MASK_TH_VLBFFV, match_opcode, INSN_DREF },
+{"th.vlhff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHFFV, MASK_TH_VLHFFV, match_opcode, INSN_DREF },
+{"th.vlwff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWFFV, MASK_TH_VLWFFV, match_opcode, INSN_DREF },
+{"th.vlbuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+{"th.vlhuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+{"th.vlwuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
+{"th.vleff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },