clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers

Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets
on MT6735.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/20241106111402.200940-3-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/MAINTAINERS b/MAINTAINERS
index c6d4f0c48cda5e8c951fb65a50a65188b6782981..262b23805ab37cd292acca2c1905635b2943b421 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14534,9 +14534,13 @@ L:     linux-clk@vger.kernel.org
 L:     linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
 F:     drivers/clk/mediatek/clk-mt6735-apmixedsys.c
+F:     drivers/clk/mediatek/clk-mt6735-imgsys.c
 F:     drivers/clk/mediatek/clk-mt6735-infracfg.c
+F:     drivers/clk/mediatek/clk-mt6735-mfgcfg.c
 F:     drivers/clk/mediatek/clk-mt6735-pericfg.c
 F:     drivers/clk/mediatek/clk-mt6735-topckgen.c
+F:     drivers/clk/mediatek/clk-mt6735-vdecsys.c
+F:     drivers/clk/mediatek/clk-mt6735-vencsys.c
 F:     include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 F:     include/dt-bindings/clock/mediatek,mt6735-imgsys.h
 F:     include/dt-bindings/clock/mediatek,mt6735-infracfg.h

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 7a33f9e92d96311967b761406563deabe2ac2f7c..5f8e6d68fa148d01504a214c6c1f3157e81e70d0 100644 (file)
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -133,6 +133,34 @@ config COMMON_CLK_MT6735
          by apmixedsys, topckgen, infracfg and pericfg on the
          MediaTek MT6735 SoC.
 
+config COMMON_CLK_MT6735_IMGSYS
+       tristate "Clock driver for MediaTek MT6735 imgsys"
+       depends on COMMON_CLK_MT6735
+       help
+         This enables a driver for clocks provided by imgsys
+         on the MediaTek MT6735 SoC.
+
+config COMMON_CLK_MT6735_MFGCFG
+       tristate "Clock driver for MediaTek MT6735 mfgcfg"
+       depends on COMMON_CLK_MT6735
+       help
+         This enables a driver for clocks and resets provided
+         by mfgcfg on the MediaTek MT6735 SoC.
+
+config COMMON_CLK_MT6735_VDECSYS
+       tristate "Clock driver for MediaTek MT6735 vdecsys"
+       depends on COMMON_CLK_MT6735
+       help
+         This enables a driver for clocks and resets provided
+         by vdecsys on the MediaTek MT6735 SoC.
+
+config COMMON_CLK_MT6735_VENCSYS
+       tristate "Clock driver for MediaTek MT6735 vencsys"
+       depends on COMMON_CLK_MT6735
+       help
+         This enables a driver for clocks provided by vencsys
+         on the MediaTek MT6735 SoC.
+
 config COMMON_CLK_MT6765
        bool "Clock driver for MediaTek MT6765"
        depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 70456ffc6c492e3f66fc79adb2fa59e576326b5f..6efec95406bd5c3770b3865c5c1c96f46807ef35 100644 (file)
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.
 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
 
 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
+obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
+obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o

diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediatek/clk-mt6735-imgsys.c
new file mode 100644 (file)
index 0000000..c564f8f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-imgsys.h>
+
+#define IMG_CG_CON                     0x00
+#define IMG_CG_SET                     0x04
+#define IMG_CG_CLR                     0x08
+
+static struct mtk_gate_regs imgsys_cg_regs = {
+       .set_ofs = IMG_CG_SET,
+       .clr_ofs = IMG_CG_CLR,
+       .sta_ofs = IMG_CG_CON,
+};
+
+static const struct mtk_gate imgsys_gates[] = {
+       GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr),
+       GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr),
+};
+
+static const struct mtk_clk_desc imgsys_clks = {
+       .clks = imgsys_gates,
+       .num_clks = ARRAY_SIZE(imgsys_gates),
+};
+
+static const struct of_device_id of_match_mt6735_imgsys[] = {
+       { .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks },
+       { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_imgsys = {
+       .probe = mtk_clk_simple_probe,
+       .remove = mtk_clk_simple_remove,
+       .driver = {
+               .name = "clk-mt6735-imgsys",
+               .of_match_table = of_match_mt6735_imgsys,
+       },
+};
+module_platform_driver(clk_mt6735_imgsys);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver");
+MODULE_LICENSE("GPL");

diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c
new file mode 100644 (file)
index 0000000..1f5aedd
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-mfgcfg.h>
+
+#define MFG_CG_CON                     0x00
+#define MFG_CG_SET                     0x04
+#define MFG_CG_CLR                     0x08
+#define MFG_RESET                      0x0c
+
+static struct mtk_gate_regs mfgcfg_cg_regs = {
+       .set_ofs = MFG_CG_SET,
+       .clr_ofs = MFG_CG_CLR,
+       .sta_ofs = MFG_CG_CON,
+};
+
+static const struct mtk_gate mfgcfg_gates[] = {
+       GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_gate_ops_setclr),
+};
+
+static u16 mfgcfg_rst_ofs[] = { MFG_RESET };
+
+static const struct mtk_clk_rst_desc mfgcfg_resets = {
+       .version = MTK_RST_SIMPLE,
+       .rst_bank_ofs = mfgcfg_rst_ofs,
+       .rst_bank_nr = ARRAY_SIZE(mfgcfg_rst_ofs)
+};
+
+static const struct mtk_clk_desc mfgcfg_clks = {
+       .clks = mfgcfg_gates,
+       .num_clks = ARRAY_SIZE(mfgcfg_gates),
+
+       .rst_desc = &mfgcfg_resets
+};
+
+static const struct of_device_id of_match_mt6735_mfgcfg[] = {
+       { .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks },
+       { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_mfgcfg = {
+       .probe = mtk_clk_simple_probe,
+       .remove = mtk_clk_simple_remove,
+       .driver = {
+               .name = "clk-mt6735-mfgcfg",
+               .of_match_table = of_match_mt6735_mfgcfg,
+       },
+};
+module_platform_driver(clk_mt6735_mfgcfg);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver");
+MODULE_LICENSE("GPL");

diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediatek/clk-mt6735-vdecsys.c
new file mode 100644 (file)
index 0000000..8817085
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-vdecsys.h>
+#include <dt-bindings/reset/mediatek,mt6735-vdecsys.h>
+
+#define VDEC_CKEN_SET                  0x00
+#define VDEC_CKEN_CLR                  0x04
+#define SMI_LARB1_CKEN_SET             0x08
+#define SMI_LARB1_CKEN_CLR             0x0c
+#define VDEC_RESETB_CON                        0x10
+#define SMI_LARB1_RESETB_CON           0x14
+
+#define RST_NR_PER_BANK                        32
+
+static struct mtk_gate_regs vdec_cg_regs = {
+       .set_ofs = VDEC_CKEN_SET,
+       .clr_ofs = VDEC_CKEN_CLR,
+       .sta_ofs = VDEC_CKEN_SET,
+};
+
+static struct mtk_gate_regs smi_larb1_cg_regs = {
+       .set_ofs = SMI_LARB1_CKEN_SET,
+       .clr_ofs = SMI_LARB1_CKEN_CLR,
+       .sta_ofs = SMI_LARB1_CKEN_SET,
+};
+
+static const struct mtk_gate vdecsys_gates[] = {
+       GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
+       GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
+};
+
+static u16 vdecsys_rst_bank_ofs[] = { VDEC_RESETB_CON, SMI_LARB1_RESETB_CON };
+
+static u16 vdecsys_rst_idx_map[] = {
+       [MT6735_VDEC_RST0_VDEC]         = 0 * RST_NR_PER_BANK + 0,
+       [MT6735_VDEC_RST1_SMI_LARB1]    = 1 * RST_NR_PER_BANK + 0,
+};
+
+static const struct mtk_clk_rst_desc vdecsys_resets = {
+       .version = MTK_RST_SIMPLE,
+       .rst_bank_ofs = vdecsys_rst_bank_ofs,
+       .rst_bank_nr = ARRAY_SIZE(vdecsys_rst_bank_ofs),
+       .rst_idx_map = vdecsys_rst_idx_map,
+       .rst_idx_map_nr = ARRAY_SIZE(vdecsys_rst_idx_map)
+};
+
+static const struct mtk_clk_desc vdecsys_clks = {
+       .clks = vdecsys_gates,
+       .num_clks = ARRAY_SIZE(vdecsys_gates),
+       .rst_desc = &vdecsys_resets
+};
+
+static const struct of_device_id of_match_mt6735_vdecsys[] = {
+       { .compatible = "mediatek,mt6735-vdecsys", .data = &vdecsys_clks },
+       { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_vdecsys = {
+       .probe = mtk_clk_simple_probe,
+       .remove = mtk_clk_simple_remove,
+       .driver = {
+               .name = "clk-mt6735-vdecsys",
+               .of_match_table = of_match_mt6735_vdecsys,
+       },
+};
+module_platform_driver(clk_mt6735_vdecsys);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver");
+MODULE_LICENSE("GPL");

diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediatek/clk-mt6735-vencsys.c
new file mode 100644 (file)
index 0000000..8dec7f9
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-vencsys.h>
+
+#define VENC_CG_CON                    0x00
+#define VENC_CG_SET                    0x04
+#define VENC_CG_CLR                    0x08
+
+static struct mtk_gate_regs venc_cg_regs = {
+       .set_ofs = VENC_CG_SET,
+       .clr_ofs = VENC_CG_CLR,
+       .sta_ofs = VENC_CG_CON,
+};
+
+static const struct mtk_gate vencsys_gates[] = {
+       GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
+       GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv),
+       GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv),
+       GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv),
+};
+
+static const struct mtk_clk_desc vencsys_clks = {
+       .clks = vencsys_gates,
+       .num_clks = ARRAY_SIZE(vencsys_gates),
+};
+
+static const struct of_device_id of_match_mt6735_vencsys[] = {
+       { .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks },
+       { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_vencsys = {
+       .probe = mtk_clk_simple_probe,
+       .remove = mtk_clk_simple_remove,
+       .driver = {
+               .name = "clk-mt6735-vencsys",
+               .of_match_table = of_match_mt6735_vencsys,
+       },
+};
+module_platform_driver(clk_mt6735_vencsys);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver");
+MODULE_LICENSE("GPL");