net: dsa: b53: ensure BCM5325 PHYs are enabled

[ Upstream commit 966a83df36c6f27476ac3501771422e7852098bc ]

According to the datasheet, BCM5325 uses B53_PD_MODE_CTRL_25 register to
disable clocking to individual PHYs.
Only ports 1-4 can be enabled or disabled and the datasheet is explicit
about not toggling BIT(0) since it disables the PLL power and the switch.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20250614080000.1884236-15-noltari@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index dc2f4adac9bc968db8d85ab4c487bb76641d8c96..184946e8cee9dfe02c31e5e3b6bcec3f7f142f5c 100644 (file)
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -615,6 +615,19 @@ int b53_setup_port(struct dsa_switch *ds, int port)
        if (dsa_is_user_port(ds, port))
                b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
 
+       if (is5325(dev) &&
+           in_range(port, 1, 4)) {
+               u8 reg;
+
+               b53_read8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, &reg);
+               reg &= ~PD_MODE_POWER_DOWN_PORT(0);
+               if (dsa_is_unused_port(ds, port))
+                       reg |= PD_MODE_POWER_DOWN_PORT(port);
+               else
+                       reg &= ~PD_MODE_POWER_DOWN_PORT(port);
+               b53_write8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, reg);
+       }
+
        return 0;
 }
 EXPORT_SYMBOL(b53_setup_port);

diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h
index 1fbc5a204bc7212c9165da63853cd033721aa215..d31c8ad9a9b6e9a10a916b47a9575a2f8628f4cb 100644 (file)
--- a/drivers/net/dsa/b53/b53_regs.h
+++ b/drivers/net/dsa/b53/b53_regs.h
@@ -101,8 +101,11 @@
 #define   PORT_OVERRIDE_SPEED_2000M    BIT(6) /* BCM5301X only, requires setting 1000M */
 #define   PORT_OVERRIDE_EN             BIT(7) /* Use the register contents */
 
-/* Power-down mode control */
+/* Power-down mode control (8 bit) */
 #define B53_PD_MODE_CTRL_25            0x0f
+#define  PD_MODE_PORT_MASK             0x1f
+/* Bit 0 also powers down the switch. */
+#define  PD_MODE_POWER_DOWN_PORT(i)    BIT(i)
 
 /* IP Multicast control (8 bit) */
 #define B53_IP_MULTICAST_CTRL          0x21