arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk

The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 98934e4a81b2ebca546f0d907581a5bacaed4e20..31f52df6b67ede412684872034652548c9e0b45c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -978,10 +978,6 @@
        status = "okay";
 };
 
-&pcie_1_phy_aux_clk {
-       clock-frequency = <1000>;
-};
-
 &pm8550_gpios {
        sdc2_card_det_n: sdc2-card-det-state {
                pins = "gpio12";

diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index d3fd001762337f84250157069022cad00b98ee5f..42d4d558b7aac4a934b7ae4b273085329d806b65 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -738,10 +738,6 @@
        data-lanes = <0 1>;
 };
 
-&pcie_1_phy_aux_clk {
-       clock-frequency = <1000>;
-};
-
 &pcie0 {
        wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
        perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 1d487c42a39b5efcb3eb1634cbf798368d875241..2ed1715000c93c92b7035dc74dbaed901f7a7760 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -720,17 +720,6 @@
        status = "okay";
 };
 
-&gcc {
-       clocks = <&bi_tcxo_div2>, <&sleep_clk>,
-                <&pcie0_phy>,
-                <&pcie1_phy>,
-                <0>,
-                <&ufs_mem_phy 0>,
-                <&ufs_mem_phy 1>,
-                <&ufs_mem_phy 2>,
-                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-};
-
 &gpi_dma1 {
        status = "okay";
 };
@@ -809,10 +798,6 @@
        data-lanes = <0 1>;
 };
 
-&pcie_1_phy_aux_clk {
-       status = "disabled";
-};
-
 &pcie0 {
        wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
        perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -906,10 +891,6 @@
        status = "okay";
 };
 
-&pcie_1_phy_aux_clk {
-       clock-frequency = <1000>;
-};
-
 &qupv3_id_0 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 9980504f66dbaf2988310c13825edfddfa62fadf..79311a6bd1ad6e691bcaa0757b4993f1b8952991 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@
                        clock-mult = <1>;
                        clock-div = <2>;
                };
-
-               pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-               };
        };
 
        cpus {
@@ -776,8 +771,8 @@
                        #power-domain-cells = <1>;
                        clocks = <&bi_tcxo_div2>, <&sleep_clk>,
                                 <&pcie0_phy>,
-                                <&pcie1_phy>,
-                                <&pcie_1_phy_aux_clk>,
+                                <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+                                <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
                                 <&ufs_mem_phy 0>,
                                 <&ufs_mem_phy 1>,
                                 <&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@
 
                        power-domains = <&gcc PCIE_1_PHY_GDSC>;
 
-                       #clock-cells = <0>;
-                       clock-output-names = "pcie1_pipe_clk";
+                       #clock-cells = <1>;
+                       clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
 
                        #phy-cells = <0>;