+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
- */
-
-#include <dt-bindings/clock/thead,th1520-clk-ap.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "thead,th1520";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- bootph-pre-ram;
- timebase-frequency = <3000000>;
-
- c910_0: cpu@0 {
- compatible = "thead,c910", "riscv";
- device_type = "cpu";
- riscv,isa = "rv64imafdc";
- reg = <0>;
- bootph-pre-ram;
- i-cache-block-size = <64>;
- i-cache-size = <65536>;
- i-cache-sets = <512>;
- d-cache-block-size = <64>;
- d-cache-size = <65536>;
- d-cache-sets = <512>;
- next-level-cache = <&l2_cache>;
- mmu-type = "riscv,sv39";
-
- cpu0_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- c910_1: cpu@1 {
- compatible = "thead,c910", "riscv";
- device_type = "cpu";
- riscv,isa = "rv64imafdc";
- reg = <1>;
- bootph-pre-ram;
- i-cache-block-size = <64>;
- i-cache-size = <65536>;
- i-cache-sets = <512>;
- d-cache-block-size = <64>;
- d-cache-size = <65536>;
- d-cache-sets = <512>;
- next-level-cache = <&l2_cache>;
- mmu-type = "riscv,sv39";
-
- cpu1_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- c910_2: cpu@2 {
- compatible = "thead,c910", "riscv";
- device_type = "cpu";
- riscv,isa = "rv64imafdc";
- reg = <2>;
- bootph-pre-ram;
- i-cache-block-size = <64>;
- i-cache-size = <65536>;
- i-cache-sets = <512>;
- d-cache-block-size = <64>;
- d-cache-size = <65536>;
- d-cache-sets = <512>;
- next-level-cache = <&l2_cache>;
- mmu-type = "riscv,sv39";
-
- cpu2_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- c910_3: cpu@3 {
- compatible = "thead,c910", "riscv";
- device_type = "cpu";
- riscv,isa = "rv64imafdc";
- reg = <3>;
- bootph-pre-ram;
- i-cache-block-size = <64>;
- i-cache-size = <65536>;
- i-cache-sets = <512>;
- d-cache-block-size = <64>;
- d-cache-size = <65536>;
- d-cache-sets = <512>;
- next-level-cache = <&l2_cache>;
- mmu-type = "riscv,sv39";
-
- cpu3_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- l2_cache: l2-cache {
- compatible = "cache";
- cache-block-size = <64>;
- cache-level = <2>;
- cache-size = <1048576>;
- cache-sets = <1024>;
- cache-unified;
- };
- };
-
- osc: oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_24m";
- #clock-cells = <0>;
- };
-
- osc_32k: 32k-oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_32k";
- #clock-cells = <0>;
- };
-
- aonsys_clk: clock-73728000 {
- compatible = "fixed-clock";
- clock-frequency = <73728000>;
- clock-output-names = "aonsys_clk";
- #clock-cells = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&plic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- plic: interrupt-controller@ffd8000000 {
- compatible = "thead,th1520-plic", "thead,c900-plic";
- reg = <0xff 0xd8000000 0x0 0x01000000>;
- interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- riscv,ndev = <240>;
- };
-
- clint: timer@ffdc000000 {
- compatible = "thead,th1520-clint", "thead,c900-clint";
- reg = <0xff 0xdc000000 0x0 0x00010000>;
- bootph-pre-ram;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>;
- };
-
- uart0: serial@ffe7014000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xe7014000 0x0 0x100>;
- bootph-pre-ram;
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- gmac1: ethernet@ffe7060000 {
- compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
- reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
- reg-names = "dwmac", "apb";
- interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
- clock-names = "stmmaceth", "pclk";
- snps,pbl = <32>;
- snps,fixed-burst;
- snps,multicast-filter-bins = <64>;
- snps,perfect-filter-entries = <32>;
- status = "disabled";
-
- mdio1: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- gmac0: ethernet@ffe7070000 {
- compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
- reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
- reg-names = "dwmac", "apb";
- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
- clock-names = "stmmaceth", "pclk";
- snps,pbl = <32>;
- snps,fixed-burst;
- snps,multicast-filter-bins = <64>;
- snps,perfect-filter-entries = <32>;
- status = "disabled";
-
- mdio0: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- emmc: mmc@ffe7080000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe7080000 0x0 0x10000>;
- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_EMMC_SDIO>;
- clock-names = "core";
- status = "disabled";
- };
-
- sdio0: mmc@ffe7090000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe7090000 0x0 0x10000>;
- interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_EMMC_SDIO>;
- clock-names = "core";
- status = "disabled";
- };
-
- sdio1: mmc@ffe70a0000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe70a0000 0x0 0x10000>;
- interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_EMMC_SDIO>;
- clock-names = "core";
- status = "disabled";
- };
-
- uart1: serial@ffe7f00000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xe7f00000 0x0 0x100>;
- interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@ffe7f04000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xe7f04000 0x0 0x100>;
- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- gpio2: gpio@ffe7f34000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xe7f34000 0x0 0x1000>;
- clocks = <&clk CLK_GPIO2>;
- clock-names = "bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- portc: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio3: gpio@ffe7f38000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xe7f38000 0x0 0x1000>;
- clocks = <&clk CLK_GPIO3>;
- clock-names = "bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- portd: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- padctrl1_apsys: pinctrl@ffe7f3c000 {
- compatible = "thead,th1520-pinctrl";
- reg = <0xff 0xe7f3c000 0x0 0x1000>;
- clocks = <&clk CLK_PADCTRL1>;
- thead,pad-group = <2>;
- };
-
- gpio0: gpio@ffec005000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xec005000 0x0 0x1000>;
- clocks = <&clk CLK_GPIO0>;
- clock-names = "bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio1: gpio@ffec006000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xec006000 0x0 0x1000>;
- clocks = <&clk CLK_GPIO1>;
- clock-names = "bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- portb: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- padctrl0_apsys: pinctrl@ffec007000 {
- compatible = "thead,th1520-pinctrl";
- reg = <0xff 0xec007000 0x0 0x1000>;
- clocks = <&clk CLK_PADCTRL0>;
- thead,pad-group = <3>;
- };
-
- uart2: serial@ffec010000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xec010000 0x0 0x4000>;
- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- clk: clock-controller@ffef010000 {
- compatible = "thead,th1520-clk-ap";
- reg = <0xff 0xef010000 0x0 0x1000>;
- clocks = <&osc>;
- #clock-cells = <1>;
- };
-
- timer0: timer@ffefc32000 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xefc32000 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer1: timer@ffefc32014 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xefc32014 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer2: timer@ffefc32028 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xefc32028 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer3: timer@ffefc3203c {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xefc3203c 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart4: serial@fff7f08000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xf7f08000 0x0 0x4000>;
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart5: serial@fff7f0c000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xf7f0c000 0x0 0x4000>;
- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
- clock-names = "buadclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- ddrc: ddrc@fffd000000 {
- compatible = "thead,th1520-ddrc";
- reg = <0xff 0xfd000000 0x0 0x1000000>,
- <0xff 0xfe000000 0x0 0x1000000>,
- <0xff 0xff000000 0x0 0x4000>,
- <0xff 0xff005000 0x0 0x1000>;
- reg-names = "phy-0", "phy-1", "ctrl", "sys";
- bootph-pre-ram;
- };
-
- timer4: timer@ffffc33000 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xffc33000 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer5: timer@ffffc33014 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xffc33014 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer6: timer@ffffc33028 {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xffc33028 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer7: timer@ffffc3303c {
- compatible = "snps,dw-apb-timer";
- reg = <0xff 0xffc3303c 0x0 0x14>;
- clocks = <&clk CLK_PERI_APB_PCLK>;
- clock-names = "timer";
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- ao_gpio0: gpio@fffff41000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xfff41000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- porte: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- padctrl_aosys: pinctrl@fffff4a000 {
- compatible = "thead,th1520-pinctrl";
- reg = <0xff 0xfff4a000 0x0 0x2000>;
- clocks = <&aonsys_clk>;
- thead,pad-group = <1>;
- };
-
- ao_gpio1: gpio@fffff52000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xfff52000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portf: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-};
projects / thirdparty / u-boot.git / commitdiff
