+2001-10-08 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * cgen-asm.in: Fix compile time warning messages in generated
+ C files.
+ * cgen-dis.in: The same.
+ * cgen-ibld.in: The same.
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * fr30-dis.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * fr30-opc.c: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opinst.c Regenerate.
+ * openrisc-asm.c: Regenerate.
+ * openrisc-desc.c: Regenerate.
+ * openrisc-dis.c: Regenerate.
+ * openrisc-ibld.c: Regenerate.
+ * openrisc-opc.c: Regenerate.
+ * openrisc-opc.h: Regenerate.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
2001-10-08 Aldy Hernandez <aldyh@redhat.com>
* arm-opc.h (arm_opcodes): Add cirrus insns.
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
-TAR = tar
+TAR = gtar
GZIP_ENV = --best
SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
#include "@prefix@-opc.h"
#include "opintl.h"
#include "xregex.h"
+#include "libiberty.h"
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
It then compiles the regex and stores it in the opcode, for
later use by @arch@_cgen_assemble_insn
- returns NULL for success, an error message for failure
-*/
+ Returns NULL for success, an error message for failure. */
char *
@arch@_cgen_build_insn_regex (insn)
CGEN_INSN *insn;
{
- CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn);
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
int mnem_len;
char rxbuf[CGEN_MAX_RX_ELEMENTS];
static void print_insn_normal
PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
-static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
- disassemble_info *, char *, int));
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
\f
/* -- disassembler routines inserted here */
\f
static void
print_normal (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
long value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
static void
print_address (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
bfd_vma value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
the extract info.
Returns 0 if all is well, non-zero otherwise. */
+
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
bfd_vma pc;
disassemble_info *info;
char *buf;
- int buflen;
+ unsigned int buflen;
{
CGEN_INSN_INT insn_value;
const CGEN_INSN_LIST *insn_list;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! @arch@_cgen_insn_supported (cd, insn))
{
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
- if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
static const char * insert_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-
static int extract_normal
PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
unsigned int, unsigned int, unsigned int, unsigned int,
static int extract_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
-
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
\f
/* Operand insertion. */
{
unsigned long x,mask;
int shift;
- int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
x = cgen_get_insn_value (cd, bufp, word_length);
#else
- cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields)),
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
#endif /* ! CGEN_INT_INSN_P */
return NULL;
}
+#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
+#endif
\f
/* Operand extraction. */
static CGEN_INLINE int
fill_cache (cd, ex_info, offset, bytes, pc)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
CGEN_EXTRACT_INFO *ex_info;
int offset, bytes;
bfd_vma pc;
{
/* It's doubtful that the middle part has already been fetched so
we don't optimize that case. kiss. */
- int mask;
+ unsigned int mask;
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
/* First do a quick check. */
static CGEN_INLINE long
extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
CGEN_CPU_DESC cd;
- CGEN_EXTRACT_INFO *ex_info;
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
int start,length,word_length;
unsigned char *bufp;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
unsigned long x;
int shift;
+#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
x = cgen_get_insn_value (cd, bufp, word_length);
-
+#endif
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
-#include "safe-ctype.h"
#include "bfd.h"
#include "symcat.h"
#include "fr30-desc.h"
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
-static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
-static int parse_register_number PARAMS ((const char **));
-static const char * parse_register_list PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int));
-static const char * parse_low_register_list_ld PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi_register_list_ld PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_low_register_list_st PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi_register_list_st PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
- const char * fr30_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+static const char * parse_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
\f
/* -- assembler routines inserted here */
/* -- asm.c */
-/* Handle register lists for LDMx and STMx */
+/* Handle register lists for LDMx and STMx. */
+
+static int parse_register_number
+ PARAMS ((const char **));
+static const char * parse_register_list
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int));
+static const char * parse_low_register_list_ld
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_hi_register_list_ld
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_low_register_list_st
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_hi_register_list_st
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static int
parse_register_number (strp)
{
int regno;
if (**strp < '0' || **strp > '9')
- return -1; /* error */
+ return -1; /* error. */
regno = **strp - '0';
++*strp;
int load_store; /* 0 == load, 1 == store */
{
int regno;
+
*valuep = 0;
while (**strp && **strp != ')')
{
if (high_low)
regno -= 8;
- if (load_store) /* mask is reversed for store */
+ if (load_store) /* Mask is reversed for store. */
*valuep |= 0x80 >> regno;
else
*valuep |= 1 << regno;
/* -- */
+const char * fr30_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
/* Main entry point for operand parsing.
This function is basically just a big switch statement. Earlier versions
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. */
+ the handlers.
+*/
const char *
fr30_cgen_parse_operand (cd, opindex, strp, fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
- long junk;
+ long junk ATTRIBUTE_UNUSED;
switch (opindex)
{
It then compiles the regex and stores it in the opcode, for
later use by fr30_cgen_assemble_insn
- returns NULL for success, an error message for failure
-*/
+ Returns NULL for success, an error message for failure. */
char *
fr30_cgen_build_insn_regex (insn)
GAS's input scrubber will ensure mnemonics are lowercase, but we may
not be called from GAS. */
p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
+ while (*p && tolower (*p) == tolower (*str))
++p, ++str;
if (* p)
return _("unrecognized instruction");
#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && !ISSPACE (* str))
+ if (* str && !isspace (* str))
return _("unrecognized instruction");
#endif
first char after the mnemonic part is a space. */
/* FIXME: We also take inappropriate advantage of the fact that
GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
{
#ifdef CGEN_MNEMONIC_OPERANDS
if (CGEN_SYNTAX_CHAR(* syn) == ' ')
blanks now. IE: We needn't try again with a longer version of
the insn and it is assumed that longer versions of insns appear
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
if (* str != '\0')
int recognized_mnemonic = 0;
/* Skip leading white space. */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
/* The instructions are stored in hashed lists.
*/
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "opintl.h"
#include "libiberty.h"
-static void init_tables PARAMS ((void));
-static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
-static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
-
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
static void
init_tables ()
{
}
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
/* Default text to print if an instruction isn't recognized. */
#define UNKNOWN_INSN_MSG _("*unknown*")
-static void print_normal PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_address PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned, bfd_vma, int));
-static void print_keyword PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
-static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int));
-static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int));
-static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
-static void print_register_list PARAMS ((PTR, long, long, int));
-static void print_hi_register_list_ld PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_low_register_list_ld PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_hi_register_list_st PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_low_register_list_st PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_m4 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
- void fr30_cgen_print_operand PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
-static int read_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *));
+static void print_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+ PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+ PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static void print_insn_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+ bfd_vma, int));
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
+static int default_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
\f
/* -- disassembler routines inserted here */
/* -- dis.c */
+static void print_register_list
+ PARAMS ((PTR, long, long, int));
+static void print_hi_register_list_ld
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static void print_low_register_list_ld
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static void print_hi_register_list_st
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static void print_low_register_list_st
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static void print_m4
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void
print_register_list (dis_info, value, offset, load_store)
static void
print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
long value;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
print_register_list (dis_info, value, 8, 0/*load*/);
}
static void
print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
long value;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
print_register_list (dis_info, value, 0, 0/*load*/);
}
static void
print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
long value;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
print_register_list (dis_info, value, 8, 1/*store*/);
}
static void
print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
long value;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
print_register_list (dis_info, value, 0, 1/*store*/);
}
static void
print_m4 (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
long value;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "%ld", value);
}
/* -- */
+void fr30_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+ void const *, bfd_vma, int));
+
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
of dis-asm.h on cgen.h.
static void
print_normal (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
long value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
static void
print_address (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
bfd_vma value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
the extract info.
Returns 0 if all is well, non-zero otherwise. */
+
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
- int buflen;
+ unsigned int buflen;
{
CGEN_INSN_INT insn_value;
const CGEN_INSN_LIST *insn_list;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! fr30_cgen_insn_supported (cd, insn))
{
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
- if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
#endif
-static CGEN_INLINE int fill_cache
- PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
-static CGEN_INLINE long extract_1
- PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *,
- bfd_vma));
+#if ! CGEN_INT_INSN_P
static CGEN_INLINE void insert_1
PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
-const char * fr30_cgen_insert_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-int fr30_cgen_extract_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *,
- bfd_vma));
-int fr30_cgen_get_int_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma fr30_cgen_get_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-void fr30_cgen_set_int_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void fr30_cgen_set_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
-
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
\f
/* Operand insertion. */
{
unsigned long x,mask;
int shift;
- int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
+ x = cgen_get_insn_value (cd, bufp, word_length);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
- bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
}
#endif /* ! CGEN_INT_INSN_P */
#else
- cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
{
unsigned long x;
int shift;
+#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
-
+ x = cgen_get_insn_value (cd, bufp, word_length);
+#endif
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
\f
/* machine generated code added here */
+const char * fr30_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
/* Main entry point for operand insertion.
This function is basically just a big switch statement. Earlier versions
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
return errmsg;
}
+int fr30_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ CGEN_FIELDS *, bfd_vma));
+
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
??? Actual values aren't well defined right now.
extract_insn_normal,
};
+int fr30_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma fr30_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
TODO: floating point, inlining support, remove cases where result type
return value;
}
+void fr30_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void fr30_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
TODO: floating point, inlining support, remove cases where argument type
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Instruction formats. */
static unsigned int
dis_hash_insn (buf, value)
- const char * buf;
+ const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
-#include "safe-ctype.h"
#include "bfd.h"
#include "symcat.h"
#include "m32r-desc.h"
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
-static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
-static const char * parse_hash PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_slo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_ulo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
- const char * m32r_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+static const char * parse_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
\f
/* -- assembler routines inserted here */
/* -- asm.c */
+static const char * parse_hash
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_hi16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_slo16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_ulo16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
/* Handle '#' prefixes (i.e. skip over them). */
/* -- */
+const char * m32r_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
/* Main entry point for operand parsing.
This function is basically just a big switch statement. Earlier versions
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
- long junk;
+ long junk ATTRIBUTE_UNUSED;
switch (opindex)
{
It then compiles the regex and stores it in the opcode, for
later use by m32r_cgen_assemble_insn
- returns NULL for success, an error message for failure
-*/
+ Returns NULL for success, an error message for failure. */
char *
m32r_cgen_build_insn_regex (insn)
GAS's input scrubber will ensure mnemonics are lowercase, but we may
not be called from GAS. */
p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
+ while (*p && tolower (*p) == tolower (*str))
++p, ++str;
if (* p)
return _("unrecognized instruction");
#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && !ISSPACE (* str))
+ if (* str && !isspace (* str))
return _("unrecognized instruction");
#endif
first char after the mnemonic part is a space. */
/* FIXME: We also take inappropriate advantage of the fact that
GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
{
#ifdef CGEN_MNEMONIC_OPERANDS
if (CGEN_SYNTAX_CHAR(* syn) == ' ')
blanks now. IE: We needn't try again with a longer version of
the insn and it is assumed that longer versions of insns appear
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
if (* str != '\0')
int recognized_mnemonic = 0;
/* Skip leading white space. */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
/* The instructions are stored in hashed lists.
*/
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "opintl.h"
#include "libiberty.h"
-static void init_tables PARAMS ((void));
-static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
-static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
static void
init_tables ()
{
}
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
static int print_insn
- PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int));
-static void print_hash
- PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static int my_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
+static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
-void m32r_cgen_print_operand
- PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
static int read_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
CGEN_EXTRACT_INFO *, unsigned long *));
/* -- disassembler routines inserted here */
/* -- dis.c */
+static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Immediate values are prefixed with '#'. */
-#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
-do { \
- if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
- (*info->fprintf_func) (info->stream, "#"); \
-} while (0)
+#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
+ do \
+ { \
+ if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
+ (*info->fprintf_func) (info->stream, "#"); \
+ } \
+ while (0)
/* Handle '#' prefixes as operands. */
static void
print_hash (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_CPU_DESC cd;
PTR dis_info;
- long value ATTRIBUTE_UNUSED;
- unsigned int attrs ATTRIBUTE_UNUSED;
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
}
-#undef CGEN_PRINT_INSN
+#undef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN my_print_insn
static int
/* -- */
+void m32r_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+ void const *, bfd_vma, int));
+
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
of dis-asm.h on cgen.h.
static void
print_normal (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#else
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
long value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
static void
print_address (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
bfd_vma value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#else
- bfd_vma pc ATTRIBUTE_UNUSED;
- int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
the extract info.
Returns 0 if all is well, non-zero otherwise. */
+
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
- int buflen;
+ unsigned int buflen;
{
CGEN_INSN_INT insn_value;
const CGEN_INSN_LIST *insn_list;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! m32r_cgen_insn_supported (cd, insn))
{
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
- if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen
- && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize
- && ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
-
-static int default_print_insn
- PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+#endif
static int
default_print_insn (cd, pc, info)
return print_insn (cd, pc, info, buf, buflen);
}
-#endif
/* Main entry point.
Print one instruction from PC on INFO->STREAM.
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
static const char * insert_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-
static int extract_normal
PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
unsigned int, unsigned int, unsigned int, unsigned int,
static int extract_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
-const char * m32r_cgen_insert_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-int m32r_cgen_extract_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
-int m32r_cgen_get_int_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma m32r_cgen_get_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-void m32r_cgen_set_int_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void m32r_cgen_set_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
\f
/* Operand insertion. */
{
unsigned long x,mask;
int shift;
- int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
+ x = cgen_get_insn_value (cd, bufp, word_length);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
- bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
}
#endif /* ! CGEN_INT_INSN_P */
#else
- cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields)),
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
#endif /* ! CGEN_INT_INSN_P */
return NULL;
}
+#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
+#endif
\f
/* Operand extraction. */
static CGEN_INLINE int
fill_cache (cd, ex_info, offset, bytes, pc)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
CGEN_EXTRACT_INFO *ex_info;
int offset, bytes;
bfd_vma pc;
{
/* It's doubtful that the middle part has already been fetched so
we don't optimize that case. kiss. */
- int mask;
+ unsigned int mask;
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
/* First do a quick check. */
static CGEN_INLINE long
extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
CGEN_CPU_DESC cd;
- CGEN_EXTRACT_INFO *ex_info;
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
int start,length,word_length;
unsigned char *bufp;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
unsigned long x;
int shift;
+#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
-
+ x = cgen_get_insn_value (cd, bufp, word_length);
+#endif
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
\f
/* machine generated code added here */
+const char * m32r_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
/* Main entry point for operand insertion.
This function is basically just a big switch statement. Earlier versions
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
return errmsg;
}
+int m32r_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ CGEN_FIELDS *, bfd_vma));
+
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
??? Actual values aren't well defined right now.
extract_insn_normal,
};
+int m32r_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma m32r_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
TODO: floating point, inlining support, remove cases where result type
return value;
}
+void m32r_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void m32r_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
TODO: floating point, inlining support, remove cases where argument type
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Instruction formats. */
static unsigned int
dis_hash_insn (buf, value)
- const char * buf;
+ const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
#else
#define OP_ENT(op) M32R_OPERAND_/**/op
#endif
-#define INPUT CGEN_OPINST_INPUT
-#define OUTPUT CGEN_OPINST_OUTPUT
-#define END CGEN_OPINST_END, "", 0, 0, 0, 0, 0
+#define INPUT CGEN_OPINST_INPUT
+#define OUTPUT CGEN_OPINST_OUTPUT
+#define END CGEN_OPINST_END
#define COND_REF CGEN_OPINST_COND_REF
static const CGEN_OPINST sfmt_empty_ops[] = {
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
-#include "safe-ctype.h"
#include "bfd.h"
#include "symcat.h"
#include "openrisc-desc.h"
static const char * parse_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
-long openrisc_sign_extend_16bit
- PARAMS ((long));
-static const char * parse_hi16
- PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_lo16
- PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-const char * openrisc_cgen_parse_operand
- PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
\f
/* -- assembler routines inserted here */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+static const char * parse_hi16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_lo16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+
long
openrisc_sign_extend_16bit (value)
long value;
return (long) (short) value;
}
-
/* Handle hi(). */
static const char *
return errmsg;
}
-
-/* Handle lo() */
+/* Handle lo(). */
static const char *
parse_lo16 (cd, strp, opindex, valuep)
/* -- */
+const char * openrisc_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
/* Main entry point for operand parsing.
This function is basically just a big switch statement. Earlier versions
It then compiles the regex and stores it in the opcode, for
later use by openrisc_cgen_assemble_insn
- returns NULL for success, an error message for failure
-*/
+ Returns NULL for success, an error message for failure. */
char *
openrisc_cgen_build_insn_regex (insn)
GAS's input scrubber will ensure mnemonics are lowercase, but we may
not be called from GAS. */
p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
+ while (*p && tolower (*p) == tolower (*str))
++p, ++str;
if (* p)
return _("unrecognized instruction");
#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && !ISSPACE (* str))
+ if (* str && !isspace (* str))
return _("unrecognized instruction");
#endif
first char after the mnemonic part is a space. */
/* FIXME: We also take inappropriate advantage of the fact that
GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
{
#ifdef CGEN_MNEMONIC_OPERANDS
if (CGEN_SYNTAX_CHAR(* syn) == ' ')
blanks now. IE: We needn't try again with a longer version of
the insn and it is assumed that longer versions of insns appear
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
if (* str != '\0')
int recognized_mnemonic = 0;
/* Skip leading white space. */
- while (ISSPACE (* str))
+ while (isspace (* str))
++ str;
/* The instructions are stored in hashed lists.
*/
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "opintl.h"
#include "libiberty.h"
-static void init_tables PARAMS ((void));
-static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
-static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
static void
init_tables ()
{
}
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
/* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
static void print_insn_normal
PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
-static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
- disassemble_info *, char *, int));
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
-void openrisc_cgen_print_operand
- PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
static int read_insn
- PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *));
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
\f
/* -- disassembler routines inserted here */
+void openrisc_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+ void const *, bfd_vma, int));
+
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
of dis-asm.h on cgen.h.
static void
print_normal (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
long value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
static void
print_address (cd, dis_info, value, attrs, pc, length)
-#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
-#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-#endif
PTR dis_info;
bfd_vma value;
unsigned int attrs;
-#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
-#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
-#endif
{
disassemble_info *info = (disassemble_info *) dis_info;
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
the extract info.
Returns 0 if all is well, non-zero otherwise. */
+
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
- int buflen;
+ unsigned int buflen;
{
CGEN_INSN_INT insn_value;
const CGEN_INSN_LIST *insn_list;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! openrisc_cgen_insn_supported (cd, insn))
{
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
- if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if ( (unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
- ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
Keep that in mind. */
#include "sysdep.h"
+#include <ctype.h>
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
static const char * insert_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-
static int extract_normal
PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
unsigned int, unsigned int, unsigned int, unsigned int,
static int extract_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
-const char * openrisc_cgen_insert_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
-int openrisc_cgen_extract_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
-int openrisc_cgen_get_int_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma openrisc_cgen_get_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-void openrisc_cgen_set_int_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void openrisc_cgen_set_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
\f
/* Operand insertion. */
{
unsigned long x,mask;
int shift;
- int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
+ x = cgen_get_insn_value (cd, bufp, word_length);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
- bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
}
#endif /* ! CGEN_INT_INSN_P */
#else
- cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields)),
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
#endif /* ! CGEN_INT_INSN_P */
return NULL;
}
+#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
+#endif
\f
/* Operand extraction. */
static CGEN_INLINE int
fill_cache (cd, ex_info, offset, bytes, pc)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
CGEN_EXTRACT_INFO *ex_info;
int offset, bytes;
bfd_vma pc;
{
/* It's doubtful that the middle part has already been fetched so
we don't optimize that case. kiss. */
- int mask;
+ unsigned int mask;
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
/* First do a quick check. */
static CGEN_INLINE long
extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
CGEN_CPU_DESC cd;
- CGEN_EXTRACT_INFO *ex_info;
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
int start,length,word_length;
unsigned char *bufp;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
unsigned long x;
int shift;
+#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
- x = bfd_get_bits (bufp, word_length, big_p);
-
+ x = cgen_get_insn_value (cd, bufp, word_length);
+#endif
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
\f
/* machine generated code added here */
+const char * openrisc_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
/* Main entry point for operand insertion.
This function is basically just a big switch statement. Earlier versions
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
- bfd_vma pc;
+ bfd_vma pc ATTRIBUTE_UNUSED;
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
return errmsg;
}
+int openrisc_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ CGEN_FIELDS *, bfd_vma));
+
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
??? Actual values aren't well defined right now.
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2);
if (length <= 0) break;
{
- extern long openrisc_sign_extend_16bit PARAMS ((long));
-
FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1))));
}
}
extract_insn_normal,
};
+int openrisc_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma openrisc_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
TODO: floating point, inlining support, remove cases where result type
return value;
}
+void openrisc_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void openrisc_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
TODO: floating point, inlining support, remove cases where argument type
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Instruction formats. */
static unsigned int
dis_hash_insn (buf, value)
- const char * buf;
+ const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
#define OPENRISC_OPC_H
/* -- opc.h */
-#undef CGEN_DIS_HASH_SIZE
+#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 64
-#undef CGEN_DIS_HASH
+#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
+extern long openrisc_sign_extend_16bit PARAMS ((long));
/* -- */
/* Enum declaration for openrisc instruction types. */
typedef enum cgen_insn_type {
d10v-opc.c
d30v-dis.c
d30v-opc.c
-dis-buf.c
disassemble.c
+dis-buf.c
fr30-asm.c
fr30-desc.c
fr30-desc.h
ia64-gen.c
ia64-opc-a.c
ia64-opc-b.c
+ia64-opc.c
ia64-opc-d.c
ia64-opc-f.c
+ia64-opc.h
ia64-opc-i.c
ia64-opc-m.c
-ia64-opc.c
-ia64-opc.h
m10200-dis.c
m10200-opc.c
m10300-dis.c
m88k-dis.c
mcore-dis.c
mcore-opc.h
+mips16-opc.c
mips-dis.c
mips-opc.c
-mips16-opc.c
ns32k-dis.c
openrisc-asm.c
openrisc-desc.c
w65-dis.c
w65-opc.h
z8k-dis.c
-z8k-opc.h
z8kgen.c
+z8k-opc.h
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-04-27 15:23+0100\n"
+"POT-Creation-Date: 2001-10-09 09:40+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgid "jump hint unaligned"
msgstr ""
-#: arm-dis.c:490
+#: arm-dis.c:509
msgid "<illegal precision>"
msgstr ""
-#: arm-dis.c:922
+#: arm-dis.c:941
#, c-format
msgid "Unrecognised register name set: %s\n"
msgstr ""
-#: arm-dis.c:929
+#: arm-dis.c:948
#, c-format
msgid "Unrecognised disassembler option: %s\n"
msgstr ""
-#: arm-dis.c:1101
+#: arm-dis.c:1120
msgid ""
"\n"
"The following ARM specific disassembler options are supported for use with\n"
msgid "unknown constraint `%c'"
msgstr ""
-#: cgen-asm.c:224
+#: cgen-asm.c:232
msgid "unrecognized keyword/register name"
msgstr ""
-#: cgen-asm.c:332 fr30-ibld.c:172 m32r-ibld.c:172 openrisc-ibld.c:172
+#: cgen-asm.c:340 fr30-ibld.c:207 m32r-ibld.c:197 openrisc-ibld.c:197
#, c-format
msgid "operand out of range (%ld not between %ld and %ld)"
msgstr ""
-#: cgen-asm.c:353
+#: cgen-asm.c:361
#, c-format
msgid "operand out of range (%lu not between %lu and %lu)"
msgstr ""
-#: d30v-dis.c:306
+#: d30v-dis.c:312
#, c-format
msgid "<unknown register %d>"
msgstr ""
msgid "Address 0x%x is out of bounds.\n"
msgstr ""
-#: fr30-asm.c:305 m32r-asm.c:313 openrisc-asm.c:237
+#: fr30-asm.c:312 m32r-asm.c:319 openrisc-asm.c:247
#, c-format
msgid "Unrecognized field %d while parsing.\n"
msgstr ""
#. We couldn't parse it.
-#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:458 fr30-asm.c:552 m32r-asm.c:377
-#: m32r-asm.c:381 m32r-asm.c:466 m32r-asm.c:560 openrisc-asm.c:301
-#: openrisc-asm.c:305 openrisc-asm.c:390 openrisc-asm.c:484
+#: fr30-asm.c:474 fr30-asm.c:478 fr30-asm.c:563 fr30-asm.c:665 m32r-asm.c:481
+#: m32r-asm.c:485 m32r-asm.c:570 m32r-asm.c:672 openrisc-asm.c:409
+#: openrisc-asm.c:413 openrisc-asm.c:498 openrisc-asm.c:600
msgid "unrecognized instruction"
msgstr ""
-#: fr30-asm.c:415 m32r-asm.c:423 openrisc-asm.c:347
+#: fr30-asm.c:520 m32r-asm.c:527 openrisc-asm.c:455
#, c-format
msgid "syntax error (expected char `%c', found `%c')"
msgstr ""
-#: fr30-asm.c:424 m32r-asm.c:432 openrisc-asm.c:356
+#: fr30-asm.c:529 m32r-asm.c:536 openrisc-asm.c:464
#, c-format
msgid "syntax error (expected char `%c', found end of instruction)"
msgstr ""
-#: fr30-asm.c:452 m32r-asm.c:460 openrisc-asm.c:384
+#: fr30-asm.c:557 m32r-asm.c:564 openrisc-asm.c:492
msgid "junk at end of line"
msgstr ""
-#: fr30-asm.c:563 m32r-asm.c:571 openrisc-asm.c:495
+#: fr30-asm.c:664 m32r-asm.c:671 openrisc-asm.c:599
+msgid "unrecognized form of instruction"
+msgstr ""
+
+#: fr30-asm.c:676 m32r-asm.c:683 openrisc-asm.c:611
#, c-format
msgid "bad instruction `%.50s...'"
msgstr ""
-#: fr30-asm.c:566 m32r-asm.c:574 openrisc-asm.c:498
+#: fr30-asm.c:679 m32r-asm.c:686 openrisc-asm.c:614
#, c-format
msgid "bad instruction `%.50s'"
msgstr ""
-#: fr30-dis.c:300 m32r-dis.c:239 openrisc-dis.c:130
+#: fr30-dis.c:301 m32r-dis.c:246 openrisc-dis.c:134
#, c-format
msgid "Unrecognized field %d while printing insn.\n"
msgstr ""
-#: fr30-ibld.c:156 m32r-ibld.c:156 openrisc-ibld.c:156
+#: fr30-ibld.c:178 m32r-ibld.c:168 openrisc-ibld.c:168
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr ""
+
+#: fr30-ibld.c:191 m32r-ibld.c:181 openrisc-ibld.c:181
#, c-format
msgid "operand out of range (%lu not between 0 and %lu)"
msgstr ""
-#: fr30-ibld.c:702 m32r-ibld.c:631 openrisc-ibld.c:605
+#: fr30-ibld.c:739 m32r-ibld.c:656 openrisc-ibld.c:630
#, c-format
msgid "Unrecognized field %d while building insn.\n"
msgstr ""
-#: fr30-ibld.c:906 m32r-ibld.c:761 openrisc-ibld.c:704
+#: fr30-ibld.c:943 m32r-ibld.c:786 openrisc-ibld.c:731
#, c-format
msgid "Unrecognized field %d while decoding insn.\n"
msgstr ""
-#: fr30-ibld.c:1050 m32r-ibld.c:866 openrisc-ibld.c:779
+#: fr30-ibld.c:1087 m32r-ibld.c:891 openrisc-ibld.c:806
#, c-format
msgid "Unrecognized field %d while getting int operand.\n"
msgstr ""
-#: fr30-ibld.c:1179 m32r-ibld.c:956 openrisc-ibld.c:839
+#: fr30-ibld.c:1216 m32r-ibld.c:981 openrisc-ibld.c:866
#, c-format
msgid "Unrecognized field %d while getting vma operand.\n"
msgstr ""
-#: fr30-ibld.c:1308 m32r-ibld.c:1049 openrisc-ibld.c:903
+#: fr30-ibld.c:1345 m32r-ibld.c:1074 openrisc-ibld.c:930
#, c-format
msgid "Unrecognized field %d while setting int operand.\n"
msgstr ""
-#: fr30-ibld.c:1430 m32r-ibld.c:1135 openrisc-ibld.c:960
+#: fr30-ibld.c:1467 m32r-ibld.c:1160 openrisc-ibld.c:987
#, c-format
msgid "Unrecognized field %d while setting vma operand.\n"
msgstr ""
-#: h8300-dis.c:380
+#: h8300-dis.c:384
#, c-format
msgid "Hmmmm %x"
msgstr ""
-#: h8300-dis.c:391
+#: h8300-dis.c:395
#, c-format
msgid "Don't understand %x \n"
msgstr ""
-#: h8500-dis.c:141
+#: h8500-dis.c:143
#, c-format
msgid "can't cope with insert %d\n"
msgstr ""
#. Couldn't understand anything.
-#: h8500-dis.c:348
+#: h8500-dis.c:350
#, c-format
msgid "%02x\t\t*unknown*"
msgstr ""
msgid "unknown\t0x%04x"
msgstr ""
-#: m68k-dis.c:430
+#: m68k-dis.c:429
#, c-format
msgid "<internal error in opcode table: %s %s>\n"
msgstr ""
-#: m68k-dis.c:1008
+#: m68k-dis.c:1007
#, c-format
msgid "<function code %d>"
msgstr ""
-#: m88k-dis.c:274
+#: m88k-dis.c:255
#, c-format
msgid "# <dis error: %08x>"
msgstr ""
-#: mips-dis.c:274
+#: mips-dis.c:292
#, c-format
msgid "# internal error, undefined modifier(%c)"
msgstr ""
+#: mips-dis.c:1129
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr ""
+
#. I and Z are output operands and can`t be immediate
#. * A is an address and we can`t have the address of
#. * an immediate either. We don't know how much to increase
#. * aoffsetp by since whatever generated this is broken
#. * anyway!
#.
-#: ns32k-dis.c:619
+#: ns32k-dis.c:628
msgid "$<undefined>"
msgstr ""
-#: ppc-opc.c:620 ppc-opc.c:651
+#: ppc-opc.c:625 ppc-opc.c:656
msgid "invalid conditional option"
msgstr ""
-#: ppc-opc.c:653
+#: ppc-opc.c:658
msgid "attempt to set y bit when using + or - modifier"
msgstr ""
-#: ppc-opc.c:708
+#: ppc-opc.c:688
+msgid "offset not a multiple of 4"
+msgstr ""
+
+#: ppc-opc.c:715
msgid "ignoring least significant bits in branch offset"
msgstr ""
-#: ppc-opc.c:743 ppc-opc.c:780
+#: ppc-opc.c:750 ppc-opc.c:787
msgid "illegal bitmask"
msgstr ""
-#: ppc-opc.c:849
+#: ppc-opc.c:856
msgid "value out of range"
msgstr ""
-#: ppc-opc.c:923
+#: ppc-opc.c:930
msgid "index register in load range"
msgstr ""
-#: ppc-opc.c:938
+#: ppc-opc.c:945
msgid "invalid register operand when updating"
msgstr ""
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
msgstr ""
-#: v850-dis.c:221
+#: v850-dis.c:224
#, c-format
msgid "unknown operand shift: %x\n"
msgstr ""
-#: v850-dis.c:233
+#: v850-dis.c:236
#, c-format
msgid "unknown pop reg: %d\n"
msgstr ""
#. v850_insert_operand() in gas/config/tc-v850.c. Error messages
#. containing the string 'out of range' will be ignored unless a
#. specific command line option is given to GAS.
-#: v850-opc.c:46
+#: v850-opc.c:68
msgid "displacement value is not in range and is not aligned"
msgstr ""
-#: v850-opc.c:47
+#: v850-opc.c:69
msgid "displacement value is out of range"
msgstr ""
-#: v850-opc.c:48
+#: v850-opc.c:70
msgid "displacement value is not aligned"
msgstr ""
-#: v850-opc.c:50
+#: v850-opc.c:72
msgid "immediate value is out of range"
msgstr ""
-#: v850-opc.c:61
+#: v850-opc.c:83
msgid "branch value not in range and to odd offset"
msgstr ""
-#: v850-opc.c:63 v850-opc.c:95
+#: v850-opc.c:85 v850-opc.c:117
msgid "branch value out of range"
msgstr ""
-#: v850-opc.c:66 v850-opc.c:98
+#: v850-opc.c:88 v850-opc.c:120
msgid "branch to odd offset"
msgstr ""
-#: v850-opc.c:93
+#: v850-opc.c:115
msgid "branch value not in range and to an odd offset"
msgstr ""
-#: v850-opc.c:321
+#: v850-opc.c:346
msgid "invalid register for stack adjustment"
msgstr ""
-#: v850-opc.c:343
+#: v850-opc.c:370
msgid "immediate value not in range and not even"
msgstr ""
-#: v850-opc.c:348
+#: v850-opc.c:375
msgid "immediate value must be even"
msgstr ""
projects / thirdparty / binutils-gdb.git / commitdiff
