RISC-V: Add vmin.vx C++ API tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_rv64-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.C: New test.
	* g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.C: New test.

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C
new file mode 100644 (file)
index 0000000..2be444b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C
new file mode 100644 (file)
index 0000000..12cb402
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C
new file mode 100644 (file)
index 0000000..f7b3cdd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C
new file mode 100644 (file)
index 0000000..d337e56
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C
new file mode 100644 (file)
index 0000000..994aa32
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C
new file mode 100644 (file)
index 0000000..ab23110
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C
new file mode 100644 (file)
index 0000000..a33bca8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C
new file mode 100644 (file)
index 0000000..cc8dcfc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C
new file mode 100644 (file)
index 0000000..aefd8b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C
new file mode 100644 (file)
index 0000000..5b91e39
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C
new file mode 100644 (file)
index 0000000..dcab363
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C
new file mode 100644 (file)
index 0000000..a89291e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmin(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C
new file mode 100644 (file)
index 0000000..1c92c95
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C
new file mode 100644 (file)
index 0000000..c8b7593
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C
new file mode 100644 (file)
index 0000000..ada791c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C
new file mode 100644 (file)
index 0000000..bf9e5a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C
new file mode 100644 (file)
index 0000000..8336c0b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C
new file mode 100644 (file)
index 0000000..1add111
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C
new file mode 100644 (file)
index 0000000..20f5873
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C
new file mode 100644 (file)
index 0000000..f871e6b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C
new file mode 100644 (file)
index 0000000..93feb03
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C
new file mode 100644 (file)
index 0000000..fe90b35
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C
new file mode 100644 (file)
index 0000000..bcf2c27
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C
new file mode 100644 (file)
index 0000000..434b2bc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.C
new file mode 100644 (file)
index 0000000..f424a42
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.C
new file mode 100644 (file)
index 0000000..92d4864
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.C
new file mode 100644 (file)
index 0000000..1137f62
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.C
new file mode 100644 (file)
index 0000000..045adf0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.C
new file mode 100644 (file)
index 0000000..54bbca4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.C
new file mode 100644 (file)
index 0000000..2a92ebf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmin_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmin_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmin_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmin_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmin_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmin_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmin_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmin_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmin_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmin_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmin_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmin_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmin_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmin_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmin_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmin_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmin_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmin_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmin_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmin_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmin_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmin_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmin_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */