dt-bindings: clock: add Amlogic C3 PLL clock controller

Add the PLL clock controller dt-bindings for Amlogic C3 SoC family.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-2-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
new file mode 100644 (file)
index 0000000..43de3c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic C3 series PLL Clock Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+  - Jerome Brunet <jbrunet@baylibre.com>
+  - Chuan Liu <chuan.liu@amlogic.com>
+  - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+  compatible:
+    const: amlogic,c3-pll-clkc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: input top pll
+      - description: input mclk pll
+
+  clock-names:
+    items:
+      - const: top
+      - const: mclk
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    apb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clock-controller@8000 {
+            compatible = "amlogic,c3-pll-clkc";
+            reg = <0x0 0x8000 0x0 0x1a4>;
+            clocks = <&scmi_clk 2>,
+                     <&scmi_clk 5>;
+            clock-names = "top", "mclk";
+            #clock-cells = <1>;
+        };
+    };

diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
new file mode 100644 (file)
index 0000000..fcdc558
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+
+#define CLKID_FCLK_50M_EN                      0
+#define CLKID_FCLK_50M                         1
+#define CLKID_FCLK_DIV2_DIV                    2
+#define CLKID_FCLK_DIV2                                3
+#define CLKID_FCLK_DIV2P5_DIV                  4
+#define CLKID_FCLK_DIV2P5                      5
+#define CLKID_FCLK_DIV3_DIV                    6
+#define CLKID_FCLK_DIV3                                7
+#define CLKID_FCLK_DIV4_DIV                    8
+#define CLKID_FCLK_DIV4                                9
+#define CLKID_FCLK_DIV5_DIV                    10
+#define CLKID_FCLK_DIV5                                11
+#define CLKID_FCLK_DIV7_DIV                    12
+#define CLKID_FCLK_DIV7                                13
+#define CLKID_GP0_PLL_DCO                      14
+#define CLKID_GP0_PLL                          15
+#define CLKID_HIFI_PLL_DCO                     16
+#define CLKID_HIFI_PLL                         17
+#define CLKID_MCLK_PLL_DCO                     18
+#define CLKID_MCLK_PLL_OD                      19
+#define CLKID_MCLK_PLL                         20
+#define CLKID_MCLK0_SEL                                21
+#define CLKID_MCLK0_SEL_EN                     22
+#define CLKID_MCLK0_DIV                                23
+#define CLKID_MCLK0                            24
+#define CLKID_MCLK1_SEL                                25
+#define CLKID_MCLK1_SEL_EN                     26
+#define CLKID_MCLK1_DIV                                27
+#define CLKID_MCLK1                            28
+
+#endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */