inst.instruction |= 0x00000100;
}
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+ inst.reloc.pc_rel = is_pc;
}
else if (inst.operands[i].postind)
{
X(asrs, 1000, fa50f000), \
X(bic, 4380, ea200000), \
X(bics, 4380, ea300000), \
- X(blx, 4780, f000c000), \
X(cmn, 42c0, eb100f00), \
X(cmp, 2800, ebb00f00), \
X(cpsie, b660, f3af8400), \
inst.instruction |= inst.operands[0].reg << 8;
inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- if (inst.reloc.pc_rel)
- inst.reloc.exp.X_add_number -= 4; /* pipeline offset */
return;
}
&& fixP->fx_subsy == NULL)
return 0;
- if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
+ /* PC relative addressing on the Thumb is slightly odd as the bottom
+ two bits of the PC are forced to zero for the calculation. This
+ happens *after* application of the pipeline offset. However,
+ Thumb adrl already adjusts for this, so we need not do it again. */
+ switch (fixP->fx_r_type)
{
- /* PC relative addressing on the Thumb is slightly odd
- as the bottom two bits of the PC are forced to zero
- for the calculation. */
+ case BFD_RELOC_ARM_THUMB_ADD:
return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
+
+ case BFD_RELOC_ARM_THUMB_OFFSET:
+ case BFD_RELOC_ARM_T32_OFFSET_IMM:
+ return (fixP->fx_where + fixP->fx_frag->fr_address + 4) & ~3;
+
+ default:
+ break;
}
#ifdef TE_WINCE
/* If this symbol is in a different section then we need to leave it for
the linker to deal with. Unfortunately, md_pcrel_from can't tell,
- so we have to undo it's effects here. */
+ so we have to undo its effects here. */
if (fixP->fx_pcrel)
{
if (fixP->fx_addsy != NULL
}
newval &= ~0xff;
}
- else if ((newval & 0x0000f000) == 0x0000f0000)
+ else if ((newval & 0x000f0000) == 0x000f0000)
{
/* PC-relative, 12-bit offset. */
if (value >= 0)
{
case 4: /* PC load. */
/* Thumb PC loads are somewhat odd, bit 1 of the PC is
- forced to zero for these loads, so we will need to round
- up the offset if the instruction address is not word
- aligned (since the final address produced must be, and
- we can only describe word-aligned immediate offsets). */
-
+ forced to zero for these loads; md_pcrel_from has already
+ compensated for this. */
if (value & 3)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid offset, target not word aligned (0x%08lX)"),
(((unsigned int) fixP->fx_frag->fr_address
+ (unsigned int) fixP->fx_where) & ~3) + value);
- if ((value + 2) & ~0x3fe)
+ if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid offset, value too big (0x%08lX)"),
(long) value);
- /* Round up, since pc will be rounded down. */
- newval |= (value + 2) >> 2;
+ newval |= value >> 2;
break;
case 9: /* SP load/store. */
0+2ce <[^>]+> f3c0 5040 ubfx r0, r0, #21, #1
0+2d2 <[^>]+> f340 0011 sbfx r0, r0, #0, #18
0+2d6 <[^>]+> d0fe beq\.n 0+2d6 <[^>]+>
-0+2d8 <[^>]+> d029 beq\.n 0+32e <[^>]+>
+0+2d8 <[^>]+> d02a beq\.n 0+330 <[^>]+>
0+2da <[^>]+> d1fc bne\.n 0+2d6 <[^>]+>
-0+2dc <[^>]+> d127 bne\.n 0+32e <[^>]+>
+0+2dc <[^>]+> d128 bne\.n 0+330 <[^>]+>
0+2de <[^>]+> d2fa bcs\.n 0+2d6 <[^>]+>
-0+2e0 <[^>]+> d225 bcs\.n 0+32e <[^>]+>
+0+2e0 <[^>]+> d226 bcs\.n 0+330 <[^>]+>
0+2e2 <[^>]+> d2f8 bcs\.n 0+2d6 <[^>]+>
-0+2e4 <[^>]+> d223 bcs\.n 0+32e <[^>]+>
+0+2e4 <[^>]+> d224 bcs\.n 0+330 <[^>]+>
0+2e6 <[^>]+> d3f6 bcc\.n 0+2d6 <[^>]+>
-0+2e8 <[^>]+> d321 bcc\.n 0+32e <[^>]+>
+0+2e8 <[^>]+> d322 bcc\.n 0+330 <[^>]+>
0+2ea <[^>]+> d3f4 bcc\.n 0+2d6 <[^>]+>
-0+2ec <[^>]+> d31f bcc\.n 0+32e <[^>]+>
+0+2ec <[^>]+> d320 bcc\.n 0+330 <[^>]+>
0+2ee <[^>]+> d3f2 bcc\.n 0+2d6 <[^>]+>
-0+2f0 <[^>]+> d31d bcc\.n 0+32e <[^>]+>
+0+2f0 <[^>]+> d31e bcc\.n 0+330 <[^>]+>
0+2f2 <[^>]+> d4f0 bmi\.n 0+2d6 <[^>]+>
-0+2f4 <[^>]+> d41b bmi\.n 0+32e <[^>]+>
+0+2f4 <[^>]+> d41c bmi\.n 0+330 <[^>]+>
0+2f6 <[^>]+> d5ee bpl\.n 0+2d6 <[^>]+>
-0+2f8 <[^>]+> d519 bpl\.n 0+32e <[^>]+>
+0+2f8 <[^>]+> d51a bpl\.n 0+330 <[^>]+>
0+2fa <[^>]+> d6ec bvs\.n 0+2d6 <[^>]+>
-0+2fc <[^>]+> d617 bvs\.n 0+32e <[^>]+>
+0+2fc <[^>]+> d618 bvs\.n 0+330 <[^>]+>
0+2fe <[^>]+> d7ea bvc\.n 0+2d6 <[^>]+>
-0+300 <[^>]+> d715 bvc\.n 0+32e <[^>]+>
+0+300 <[^>]+> d716 bvc\.n 0+330 <[^>]+>
0+302 <[^>]+> d8e8 bhi\.n 0+2d6 <[^>]+>
-0+304 <[^>]+> d813 bhi\.n 0+32e <[^>]+>
+0+304 <[^>]+> d814 bhi\.n 0+330 <[^>]+>
0+306 <[^>]+> d9e6 bls\.n 0+2d6 <[^>]+>
-0+308 <[^>]+> d911 bls\.n 0+32e <[^>]+>
+0+308 <[^>]+> d912 bls\.n 0+330 <[^>]+>
0+30a <[^>]+> d7e4 bvc\.n 0+2d6 <[^>]+>
-0+30c <[^>]+> d70f bvc\.n 0+32e <[^>]+>
+0+30c <[^>]+> d710 bvc\.n 0+330 <[^>]+>
0+30e <[^>]+> d8e2 bhi\.n 0+2d6 <[^>]+>
-0+310 <[^>]+> d80d bhi\.n 0+32e <[^>]+>
+0+310 <[^>]+> d80e bhi\.n 0+330 <[^>]+>
0+312 <[^>]+> d9e0 bls\.n 0+2d6 <[^>]+>
-0+314 <[^>]+> d90b bls\.n 0+32e <[^>]+>
+0+314 <[^>]+> d90c bls\.n 0+330 <[^>]+>
0+316 <[^>]+> dade bge\.n 0+2d6 <[^>]+>
-0+318 <[^>]+> da09 bge\.n 0+32e <[^>]+>
+0+318 <[^>]+> da0a bge\.n 0+330 <[^>]+>
0+31a <[^>]+> dbdc blt\.n 0+2d6 <[^>]+>
-0+31c <[^>]+> db07 blt\.n 0+32e <[^>]+>
+0+31c <[^>]+> db08 blt\.n 0+330 <[^>]+>
0+31e <[^>]+> dcda bgt\.n 0+2d6 <[^>]+>
-0+320 <[^>]+> dc05 bgt\.n 0+32e <[^>]+>
+0+320 <[^>]+> dc06 bgt\.n 0+330 <[^>]+>
0+322 <[^>]+> ddd8 ble\.n 0+2d6 <[^>]+>
-0+324 <[^>]+> dd03 ble\.n 0+32e <[^>]+>
+0+324 <[^>]+> dd04 ble\.n 0+330 <[^>]+>
0+326 <[^>]+> ded6 bal\.n 0+2d6 <[^>]+>
-0+328 <[^>]+> de01 bal\.n 0+32e <[^>]+>
+0+328 <[^>]+> de02 bal\.n 0+330 <[^>]+>
0+32a <[^>]+> e7d4 b\.n 0+2d6 <[^>]+>
-0+32c <[^>]+> e7ff b\.n 0+32e <[^>]+>
-0+32e <[^>]+> f43f affe beq\.w 0+32e <[^>]+>
-0+332 <[^>]+> f000 8058 beq\.w 0+3e6 <[^>]+>
-0+336 <[^>]+> f47f affa bne\.w 0+32e <[^>]+>
-0+33a <[^>]+> f040 8054 bne\.w 0+3e6 <[^>]+>
-0+33e <[^>]+> f4bf aff6 bcs\.w 0+32e <[^>]+>
-0+342 <[^>]+> f080 8050 bcs\.w 0+3e6 <[^>]+>
-0+346 <[^>]+> f4bf aff2 bcs\.w 0+32e <[^>]+>
-0+34a <[^>]+> f080 804c bcs\.w 0+3e6 <[^>]+>
-0+34e <[^>]+> f4ff afee bcc\.w 0+32e <[^>]+>
-0+352 <[^>]+> f0c0 8048 bcc\.w 0+3e6 <[^>]+>
-0+356 <[^>]+> f4ff afea bcc\.w 0+32e <[^>]+>
-0+35a <[^>]+> f0c0 8044 bcc\.w 0+3e6 <[^>]+>
-0+35e <[^>]+> f4ff afe6 bcc\.w 0+32e <[^>]+>
-0+362 <[^>]+> f0c0 8040 bcc\.w 0+3e6 <[^>]+>
-0+366 <[^>]+> f53f afe2 bmi\.w 0+32e <[^>]+>
-0+36a <[^>]+> f100 803c bmi\.w 0+3e6 <[^>]+>
-0+36e <[^>]+> f57f afde bpl\.w 0+32e <[^>]+>
-0+372 <[^>]+> f140 8038 bpl\.w 0+3e6 <[^>]+>
-0+376 <[^>]+> f5bf afda bvs\.w 0+32e <[^>]+>
-0+37a <[^>]+> f180 8034 bvs\.w 0+3e6 <[^>]+>
-0+37e <[^>]+> f5ff afd6 bvc\.w 0+32e <[^>]+>
-0+382 <[^>]+> f1c0 8030 bvc\.w 0+3e6 <[^>]+>
-0+386 <[^>]+> f63f afd2 bhi\.w 0+32e <[^>]+>
-0+38a <[^>]+> f200 802c bhi\.w 0+3e6 <[^>]+>
-0+38e <[^>]+> f67f afce bls\.w 0+32e <[^>]+>
-0+392 <[^>]+> f240 8028 bls\.w 0+3e6 <[^>]+>
-0+396 <[^>]+> f5ff afca bvc\.w 0+32e <[^>]+>
-0+39a <[^>]+> f1c0 8024 bvc\.w 0+3e6 <[^>]+>
-0+39e <[^>]+> f63f afc6 bhi\.w 0+32e <[^>]+>
-0+3a2 <[^>]+> f200 8020 bhi\.w 0+3e6 <[^>]+>
-0+3a6 <[^>]+> f67f afc2 bls\.w 0+32e <[^>]+>
-0+3aa <[^>]+> f240 801c bls\.w 0+3e6 <[^>]+>
-0+3ae <[^>]+> f6bf afbe bge\.w 0+32e <[^>]+>
-0+3b2 <[^>]+> f280 8018 bge\.w 0+3e6 <[^>]+>
-0+3b6 <[^>]+> f6ff afba blt\.w 0+32e <[^>]+>
-0+3ba <[^>]+> f2c0 8014 blt\.w 0+3e6 <[^>]+>
-0+3be <[^>]+> f73f afb6 bgt\.w 0+32e <[^>]+>
-0+3c2 <[^>]+> f300 8010 bgt\.w 0+3e6 <[^>]+>
-0+3c6 <[^>]+> f77f afb2 ble\.w 0+32e <[^>]+>
-0+3ca <[^>]+> f340 800c ble\.w 0+3e6 <[^>]+>
-0+3ce <[^>]+> f7ff bfae b\.w 0+32e <[^>]+>
-0+3d2 <[^>]+> f000 b808 b\.w 0+3e6 <[^>]+>
-0+3d6 <[^>]+> f000 f995 bl 0+32e <[^>]+>
- 3d6: R_ARM_THM_CALL \.text
-0+3da <[^>]+> f000 f9f1 bl 0+3e6 <[^>]+>
- 3da: R_ARM_THM_CALL \.text
-0+3de <[^>]+> f000 e995 blx 0+32e <[^>]+>
- 3de: R_ARM_THM_XPC22 \.text
-0+3e2 <[^>]+> f000 e9f1 blx 0+3e6 <[^>]+>
- 3e2: R_ARM_THM_XPC22 \.text
-0+3e6 <[^>]+> 4700 bx r0
+0+32c <[^>]+> e000 b\.n 0+330 <[^>]+>
+0+32e <[^>]+> 46c0 nop \(mov r8, r8\)
+0+330 <[^>]+> f43f affe beq\.w 0+330 <[^>]+>
+0+334 <[^>]+> f000 8058 beq\.w 0+3e8 <[^>]+>
+0+338 <[^>]+> f47f affa bne\.w 0+330 <[^>]+>
+0+33c <[^>]+> f040 8054 bne\.w 0+3e8 <[^>]+>
+0+340 <[^>]+> f4bf aff6 bcs\.w 0+330 <[^>]+>
+0+344 <[^>]+> f080 8050 bcs\.w 0+3e8 <[^>]+>
+0+348 <[^>]+> f4bf aff2 bcs\.w 0+330 <[^>]+>
+0+34c <[^>]+> f080 804c bcs\.w 0+3e8 <[^>]+>
+0+350 <[^>]+> f4ff afee bcc\.w 0+330 <[^>]+>
+0+354 <[^>]+> f0c0 8048 bcc\.w 0+3e8 <[^>]+>
+0+358 <[^>]+> f4ff afea bcc\.w 0+330 <[^>]+>
+0+35c <[^>]+> f0c0 8044 bcc\.w 0+3e8 <[^>]+>
+0+360 <[^>]+> f4ff afe6 bcc\.w 0+330 <[^>]+>
+0+364 <[^>]+> f0c0 8040 bcc\.w 0+3e8 <[^>]+>
+0+368 <[^>]+> f53f afe2 bmi\.w 0+330 <[^>]+>
+0+36c <[^>]+> f100 803c bmi\.w 0+3e8 <[^>]+>
+0+370 <[^>]+> f57f afde bpl\.w 0+330 <[^>]+>
+0+374 <[^>]+> f140 8038 bpl\.w 0+3e8 <[^>]+>
+0+378 <[^>]+> f5bf afda bvs\.w 0+330 <[^>]+>
+0+37c <[^>]+> f180 8034 bvs\.w 0+3e8 <[^>]+>
+0+380 <[^>]+> f5ff afd6 bvc\.w 0+330 <[^>]+>
+0+384 <[^>]+> f1c0 8030 bvc\.w 0+3e8 <[^>]+>
+0+388 <[^>]+> f63f afd2 bhi\.w 0+330 <[^>]+>
+0+38c <[^>]+> f200 802c bhi\.w 0+3e8 <[^>]+>
+0+390 <[^>]+> f67f afce bls\.w 0+330 <[^>]+>
+0+394 <[^>]+> f240 8028 bls\.w 0+3e8 <[^>]+>
+0+398 <[^>]+> f5ff afca bvc\.w 0+330 <[^>]+>
+0+39c <[^>]+> f1c0 8024 bvc\.w 0+3e8 <[^>]+>
+0+3a0 <[^>]+> f63f afc6 bhi\.w 0+330 <[^>]+>
+0+3a4 <[^>]+> f200 8020 bhi\.w 0+3e8 <[^>]+>
+0+3a8 <[^>]+> f67f afc2 bls\.w 0+330 <[^>]+>
+0+3ac <[^>]+> f240 801c bls\.w 0+3e8 <[^>]+>
+0+3b0 <[^>]+> f6bf afbe bge\.w 0+330 <[^>]+>
+0+3b4 <[^>]+> f280 8018 bge\.w 0+3e8 <[^>]+>
+0+3b8 <[^>]+> f6ff afba blt\.w 0+330 <[^>]+>
+0+3bc <[^>]+> f2c0 8014 blt\.w 0+3e8 <[^>]+>
+0+3c0 <[^>]+> f73f afb6 bgt\.w 0+330 <[^>]+>
+0+3c4 <[^>]+> f300 8010 bgt\.w 0+3e8 <[^>]+>
+0+3c8 <[^>]+> f77f afb2 ble\.w 0+330 <[^>]+>
+0+3cc <[^>]+> f340 800c ble\.w 0+3e8 <[^>]+>
+0+3d0 <[^>]+> f7ff bfae b\.w 0+330 <[^>]+>
+0+3d4 <[^>]+> f000 b808 b\.w 0+3e8 <[^>]+>
+0+3d8 <[^>]+> f000 f996 bl 0+330 <[^>]+>
+ 3d8: R_ARM_THM_CALL \.text
+0+3dc <[^>]+> f000 f9f2 bl 0+3e8 <[^>]+>
+ 3dc: R_ARM_THM_CALL \.text
+0+3e0 <[^>]+> f000 e996 blx 0+330 <[^>]+>
+ 3e0: R_ARM_THM_XPC22 \.text
+0+3e4 <[^>]+> f000 e9f2 blx 0+3e8 <[^>]+>
+ 3e4: R_ARM_THM_XPC22 \.text
0+3e8 <[^>]+> 4748 bx r9
0+3ea <[^>]+> 4780 blx r0
0+3ec <[^>]+> 47c8 blx r9
0+5b2 <[^>]+> f815 1d30 ldrb\.w r1, \[r5\], #-48
0+5b6 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
0+5b8 <[^>]+> f819 100c ldrb\.w r1, \[r9, ip\]
-0+5bc <[^>]+> f89f 10b0 ldrb\.w r1, \[pc, #176\]
-0+5c0 <[^>]+> f81f 1c26 ldrb\.w r1, \[pc, #-3110\]
+0+5bc <[^>]+> f89f 10ac ldrb\.w r1, \[pc, #172\] ; 0+66c <[^>]+>
+0+5c0 <[^>]+> f81f 102a ldrb\.w r1, \[pc, #-42\] ; 0+59a <[^>]+>
0+5c4 <[^>]+> f995 1000 ldrsb\.w r1, \[r5\]
0+5c8 <[^>]+> f995 1330 ldrsb\.w r1, \[r5, #816\]
0+5cc <[^>]+> f915 1c30 ldrsb\.w r1, \[r5, #-48\]
0+5dc <[^>]+> f915 1d30 ldrsb\.w r1, \[r5\], #-48
0+5e0 <[^>]+> 5729 ldrsb r1, \[r5, r4\]
0+5e2 <[^>]+> f919 100c ldrsb\.w r1, \[r9, ip\]
-0+5e6 <[^>]+> f99f 1086 ldrsb\.w r1, \[pc, #134\]
-0+5ea <[^>]+> f91f 1c50 ldrsb\.w r1, \[pc, #-3152\]
+0+5e6 <[^>]+> f99f 1084 ldrsb\.w r1, \[pc, #132\] ; 0+66c <[^>]+>
+0+5ea <[^>]+> f91f 1052 ldrsb\.w r1, \[pc, #-82\] ; 0+59a <[^>]+>
0+5ee <[^>]+> f8b5 1000 ldrh\.w r1, \[r5\]
0+5f2 <[^>]+> f8b5 1330 ldrh\.w r1, \[r5, #816\]
0+5f6 <[^>]+> f835 1c30 ldrh\.w r1, \[r5, #-48\]
0+606 <[^>]+> f835 1d30 ldrh\.w r1, \[r5\], #-48
0+60a <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+60c <[^>]+> f839 100c ldrh\.w r1, \[r9, ip\]
-0+610 <[^>]+> f8bf 105c ldrh\.w r1, \[pc, #92\]
-0+614 <[^>]+> f83f 1c7a ldrh\.w r1, \[pc, #-3194\]
+0+610 <[^>]+> f8bf 1058 ldrh\.w r1, \[pc, #88\] ; 0+66c <[^>]+>
+0+614 <[^>]+> f83f 107e ldrh\.w r1, \[pc, #-126\] ; 0+59a <[^>]+>
0+618 <[^>]+> f9b5 1000 ldrsh\.w r1, \[r5\]
0+61c <[^>]+> f9b5 1330 ldrsh\.w r1, \[r5, #816\]
0+620 <[^>]+> f935 1c30 ldrsh\.w r1, \[r5, #-48\]
0+630 <[^>]+> f935 1d30 ldrsh\.w r1, \[r5\], #-48
0+634 <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+636 <[^>]+> f939 100c ldrsh\.w r1, \[r9, ip\]
-0+63a <[^>]+> f9bf 1032 ldrsh\.w r1, \[pc, #50\]
-0+63e <[^>]+> f93f 1ca4 ldrsh\.w r1, \[pc, #-3236\]
+0+63a <[^>]+> f9bf 1030 ldrsh\.w r1, \[pc, #48\] ; 0+66c <[^>]+>
+0+63e <[^>]+> f93f 10a6 ldrsh\.w r1, \[pc, #-166\] ; 0+59a <[^>]+>
0+642 <[^>]+> f8d5 1000 ldr\.w r1, \[r5\]
0+646 <[^>]+> f8d5 1330 ldr\.w r1, \[r5, #816\]
0+64a <[^>]+> f855 1c30 ldr\.w r1, \[r5, #-48\]
0+65a <[^>]+> f855 1d30 ldr\.w r1, \[r5\], #-48
0+65e <[^>]+> 5929 ldr r1, \[r5, r4\]
0+660 <[^>]+> f859 100c ldr\.w r1, \[r9, ip\]
-0+664 <[^>]+> f8df 1008 ldr\.w r1, \[pc, #8\]
-0+668 <[^>]+> f85f 1cce ldr\.w r1, \[pc, #-3278\]
+0+664 <[^>]+> f8df 1004 ldr\.w r1, \[pc, #4\] ; 0+66c <[^>]+>
+0+668 <[^>]+> f85f 10d2 ldr\.w r1, \[pc, #-210\] ; 0+59a <[^>]+>
0+66c <[^>]+> f885 1000 strb\.w r1, \[r5\]
0+670 <[^>]+> f885 1330 strb\.w r1, \[r5, #816\]
0+674 <[^>]+> f805 1c30 strb\.w r1, \[r5, #-48\]
0+684 <[^>]+> f805 1d30 strb\.w r1, \[r5\], #-48
0+688 <[^>]+> 5529 strb r1, \[r5, r4\]
0+68a <[^>]+> f809 100c strb\.w r1, \[r9, ip\]
-0+68e <[^>]+> f88f 1088 strb\.w r1, \[pc, #136\]
-0+692 <[^>]+> f80f 1c26 strb\.w r1, \[pc, #-3110\]
+0+68e <[^>]+> f88f 1086 strb\.w r1, \[pc, #134\] ; 0+716 <[^>]+>
+0+692 <[^>]+> f80f 1028 strb\.w r1, \[pc, #-40\] ; 0+66c <[^>]+>
0+696 <[^>]+> f8a5 1000 strh\.w r1, \[r5\]
0+69a <[^>]+> f8a5 1330 strh\.w r1, \[r5, #816\]
0+69e <[^>]+> f825 1c30 strh\.w r1, \[r5, #-48\]
0+6ae <[^>]+> f825 1d30 strh\.w r1, \[r5\], #-48
0+6b2 <[^>]+> 5329 strh r1, \[r5, r4\]
0+6b4 <[^>]+> f829 100c strh\.w r1, \[r9, ip\]
-0+6b8 <[^>]+> f8af 105e strh\.w r1, \[pc, #94\]
-0+6bc <[^>]+> f82f 1c50 strh\.w r1, \[pc, #-3152\]
+0+6b8 <[^>]+> f8af 105a strh\.w r1, \[pc, #90\] ; 0+716 <[^>]+>
+0+6bc <[^>]+> f82f 1054 strh\.w r1, \[pc, #-84\] ; 0+66c <[^>]+>
0+6c0 <[^>]+> f8c5 1000 str\.w r1, \[r5\]
0+6c4 <[^>]+> f8c5 1330 str\.w r1, \[r5, #816\]
0+6c8 <[^>]+> f845 1c30 str\.w r1, \[r5, #-48\]
0+6d8 <[^>]+> f845 1d30 str\.w r1, \[r5\], #-48
0+6dc <[^>]+> 5129 str r1, \[r5, r4\]
0+6de <[^>]+> f849 100c str\.w r1, \[r9, ip\]
-0+6e2 <[^>]+> f8cf 1034 str\.w r1, \[pc, #52\]
-0+6e6 <[^>]+> f84f 1c7a str\.w r1, \[pc, #-3194\]
+0+6e2 <[^>]+> f8cf 1032 str\.w r1, \[pc, #50\] ; 0+716 <[^>]+>
+0+6e6 <[^>]+> f84f 107c str\.w r1, \[pc, #-124\] ; 0+66c <[^>]+>
0+6ea <[^>]+> f895 f000 pld \[r5\]
0+6ee <[^>]+> f895 f330 pld \[r5, #816\]
0+6f2 <[^>]+> f815 fc30 pld \[r5, #-48\]
0+702 <[^>]+> f815 fd30 pld \[r5\], #-48
0+706 <[^>]+> f815 f000 pld \[r5, r0\]
0+70a <[^>]+> f819 f000 pld \[r9, r0\]
-0+70e <[^>]+> f89f f008 pld \[pc, #8\]
-0+712 <[^>]+> f81f fca6 pld \[pc, #-3238\]
+0+70e <[^>]+> f89f f006 pld \[pc, #6\] ; 0+716 <[^>]+>
+0+712 <[^>]+> f81f f0a8 pld \[pc, #-168\] ; 0+66c <[^>]+>
0+716 <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0+71a <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\]
0+71e <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\]
unsigned int op = (given & 0x00000f00) >> 8;
unsigned int i12 = (given & 0x00000fff);
unsigned int i8 = (given & 0x000000ff);
+ bfd_boolean writeback = FALSE, postind = FALSE;
+ int offset = 0;
func (stream, "[%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset */
+ offset = i12;
+ else if (Rn == 15) /* 12-bit negative immediate offset */
+ offset = -(int)i12;
+ else if (op == 0x0) /* shifted register offset */
{
- if (i12)
- func (stream, ", #%u", i12);
+ unsigned int Rm = (i8 & 0x0f);
+ unsigned int sh = (i8 & 0x30) >> 4;
+ func (stream, ", %s", arm_regnames[Rm]);
+ if (sh)
+ func (stream, ", lsl #%u", sh);
func (stream, "]");
+ break;
}
- else if (Rn == 15) /* 12-bit negative immediate offset */
- func (stream, ", #-%u]", i12);
else switch (op)
{
- case 0x0: /* shifted register offset */
- {
- unsigned int Rm = (i8 & 0x0f);
- unsigned int sh = (i8 & 0x30) >> 4;
- func (stream, ", %s", arm_regnames[Rm]);
- if (sh)
- func (stream, ", lsl #%u", sh);
- func (stream, "]");
- }
- break;
-
case 0xE: /* 8-bit positive immediate offset */
- if (i8)
- func (stream, ", #%u", i8);
- func (stream, "]");
+ offset = i8;
break;
case 0xC: /* 8-bit negative immediate offset */
- func (stream, ", #-%u]", i8);
+ offset = -i8;
break;
case 0xB: /* 8-bit + preindex with wb */
- if (i8)
- func (stream, ", #%u", i8);
- func (stream, "]!");
+ offset = i8;
+ writeback = TRUE;
break;
case 0x9: /* 8-bit - preindex with wb */
- func (stream, ", #-%u]!", i8);
+ offset = -i8;
+ writeback = TRUE;
break;
case 0xF: /* 8-bit + postindex */
- func (stream, "], #%u", i8);
+ offset = i8;
+ postind = TRUE;
break;
case 0xD: /* 8-bit - postindex */
- func (stream, "], #-%u", i8);
+ offset = -i8;
+ postind = TRUE;
break;
default:
func (stream, ", <undefined>]");
+ goto skip;
+ }
+
+ if (postind)
+ func (stream, "], #%d", offset);
+ else
+ {
+ if (offset)
+ func (stream, ", #%d", offset);
+ func (stream, writeback ? "]!" : "]");
+ }
+
+ if (Rn == 15)
+ {
+ func (stream, "\t; ");
+ info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
+ skip:
break;
case 'A':
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int J1 = (given & 0x00002000u) >> 13;
unsigned int J2 = (given & 0x00000800u) >> 11;
- unsigned int offset = 0;
+ int offset = 0;
offset |= !S << 20;
offset |= J2 << 19;
offset |= (given & 0x000007ff) << 1;
offset -= (1 << 20);
- info->print_address_func ((bfd_vma)offset + pc + 4, info);
+ info->print_address_func (pc + 4 + offset, info);
}
break;
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int I1 = (given & 0x00002000u) >> 13;
unsigned int I2 = (given & 0x00000800u) >> 11;
- unsigned int offset = 0;
+ int offset = 0;
offset |= !S << 24;
offset |= !(I1 ^ S) << 23;
offset |= (given & 0x000007ffu) << 1;
offset -= (1 << 24);
- info->print_address_func ((bfd_vma)offset + pc + 4, info);
+ info->print_address_func (pc + 4 + offset, info);
}
break;
projects / thirdparty / binutils-gdb.git / commitdiff
