--- /dev/null
+From 238962ac71910d6c20162ea5230685fead1836a4 Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Tue, 4 Nov 2014 11:40:46 +0100
+Subject: ARM: 8191/1: decompressor: ensure I-side picks up relocated code
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 238962ac71910d6c20162ea5230685fead1836a4 upstream.
+
+To speed up decompression, the decompressor sets up a flat, cacheable
+mapping of memory. However, when there is insufficient space to hold
+the page tables for this mapping, we don't bother to enable the caches
+and subsequently skip all the cache maintenance hooks.
+
+Skipping the cache maintenance before jumping to the relocated code
+allows the processor to predict the branch and populate the I-cache
+with stale data before the relocation loop has completed (since a
+bootloader may have SCTLR.I set, which permits normal, cacheable
+instruction fetches regardless of SCTLR.M).
+
+This patch moves the cache maintenance check into the maintenance
+routines themselves, allowing the v6/v7 versions to invalidate the
+I-cache regardless of the MMU state.
+
+Reported-by: Marc Carino <marc.ceeeee@gmail.com>
+Tested-by: Julien Grall <julien.grall@linaro.org>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/compressed/head.S | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -397,8 +397,7 @@ dtb_check_done:
+ add sp, sp, r6
+ #endif
+
+- tst r4, #1
+- bleq cache_clean_flush
++ bl cache_clean_flush
+
+ adr r0, BSYM(restart)
+ add r0, r0, r6
+@@ -1047,6 +1046,8 @@ cache_clean_flush:
+ b call_cache_fn
+
+ __armv4_mpu_cache_flush:
++ tst r4, #1
++ movne pc, lr
+ mov r2, #1
+ mov r3, #0
+ mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
+@@ -1064,6 +1065,8 @@ __armv4_mpu_cache_flush:
+ mov pc, lr
+
+ __fa526_cache_flush:
++ tst r4, #1
++ movne pc, lr
+ mov r1, #0
+ mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
+ mcr p15, 0, r1, c7, c5, 0 @ flush I cache
+@@ -1072,13 +1075,16 @@ __fa526_cache_flush:
+
+ __armv6_mmu_cache_flush:
+ mov r1, #0
+- mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
++ tst r4, #1
++ mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
+ mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
+- mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
++ mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
+ mcr p15, 0, r1, c7, c10, 4 @ drain WB
+ mov pc, lr
+
+ __armv7_mmu_cache_flush:
++ tst r4, #1
++ bne iflush
+ mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
+ tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
+ mov r10, #0
+@@ -1139,6 +1145,8 @@ iflush:
+ mov pc, lr
+
+ __armv5tej_mmu_cache_flush:
++ tst r4, #1
++ movne pc, lr
+ 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+ bne 1b
+ mcr p15, 0, r0, c7, c5, 0 @ flush I cache
+@@ -1146,6 +1154,8 @@ __armv5tej_mmu_cache_flush:
+ mov pc, lr
+
+ __armv4_mmu_cache_flush:
++ tst r4, #1
++ movne pc, lr
+ mov r2, #64*1024 @ default: 32K dcache size (*2)
+ mov r11, #32 @ default: 32 byte line size
+ mrc p15, 0, r3, c0, c0, 1 @ read cache type
+@@ -1179,6 +1189,8 @@ no_cache_id:
+
+ __armv3_mmu_cache_flush:
+ __armv3_mpu_cache_flush:
++ tst r4, #1
++ movne pc, lr
+ mov r1, #0
+ mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
+ mov pc, lr
--- /dev/null
+From 08b964ff3c51b10aaf2e6ba639f40054c09f0f7a Mon Sep 17 00:00:00 2001
+From: Nathan Lynch <nathan_lynch@mentor.com>
+Date: Mon, 10 Nov 2014 23:46:27 +0100
+Subject: ARM: 8198/1: make kuser helpers depend on MMU
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Nathan Lynch <nathan_lynch@mentor.com>
+
+commit 08b964ff3c51b10aaf2e6ba639f40054c09f0f7a upstream.
+
+The kuser helpers page is not set up on non-MMU systems, so it does
+not make sense to allow CONFIG_KUSER_HELPERS to be enabled when
+CONFIG_MMU=n. Allowing it to be set on !MMU results in an oops in
+set_tls (used in execve and the arm_syscall trap handler):
+
+Unhandled exception: IPSR = 00000005 LR = fffffff1
+CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216
+task: 8b838000 ti: 8b82a000 task.ti: 8b82a000
+PC is at flush_thread+0x32/0x40
+LR is at flush_thread+0x21/0x40
+pc : [<8f00157a>] lr : [<8f001569>] psr: 4100000b
+sp : 8b82be20 ip : 00000000 fp : 8b83c000
+r10: 00000001 r9 : 88018c84 r8 : 8bb85000
+r7 : 8b838000 r6 : 00000000 r5 : 8bb77400 r4 : 8b82a000
+r3 : ffff0ff0 r2 : 8b82a000 r1 : 00000000 r0 : 88020354
+xPSR: 4100000b
+CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216
+[<8f002bc1>] (unwind_backtrace) from [<8f002033>] (show_stack+0xb/0xc)
+[<8f002033>] (show_stack) from [<8f00265b>] (__invalid_entry+0x4b/0x4c)
+
+As best I can tell this issue existed for the set_tls ARM syscall
+before commit fbfb872f5f41 "ARM: 8148/1: flush TLS and thumbee
+register state during exec" consolidated the TLS manipulation code
+into the set_tls helper function, but now that we're using it to flush
+register state during execve, !MMU users encounter the oops at the
+first exec.
+
+Prevent CONFIG_MMU=n configurations from enabling
+CONFIG_KUSER_HELPERS.
+
+Fixes: fbfb872f5f41 (ARM: 8148/1: flush TLS and thumbee register state during exec)
+
+Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
+Reported-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -798,6 +798,7 @@ config NEED_KUSER_HELPERS
+
+ config KUSER_HELPERS
+ bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
++ depends on MMU
+ default y
+ help
+ Warning: disabling this option may break user programs.
--- /dev/null
+From a8ead0ecb9d4ce472f4cdab936d6f18e41e3a9ee Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Tue, 21 Oct 2014 14:25:45 +0300
+Subject: ARM: dts: am335x-evm: Fix 5th NAND partition's name
+
+From: Roger Quadros <rogerq@ti.com>
+
+commit a8ead0ecb9d4ce472f4cdab936d6f18e41e3a9ee upstream.
+
+The 5th NAND partition should be named "NAND.u-boot-spl-os"
+instead of "NAND.u-boot-spl". This is to be consistent with other
+TI boards as well as u-boot.
+
+Fixes: 91994facdd2d ("ARM: dts: am335x-evm: NAND: update MTD partition table")
+
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Signed-off-by: Sekhar Nori <nsekhar@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/am335x-evm.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/am335x-evm.dts
++++ b/arch/arm/boot/dts/am335x-evm.dts
+@@ -489,7 +489,7 @@
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+- label = "NAND.u-boot-spl";
++ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
--- /dev/null
+From 5129ee22ce4aff7c5907d4c3d67d23f86cd6db9b Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Sat, 26 Jul 2014 19:20:37 +0200
+Subject: ARM: mvebu: armada xp: Generalize use of i2c quirk
+
+From: Andrew Lunn <andrew@lunn.ch>
+
+commit 5129ee22ce4aff7c5907d4c3d67d23f86cd6db9b upstream.
+
+A second product has come to light which makes use of the A0 stepping
+of the Armada XP SoC. A0 stepping has a hardware bug in the i2c core
+meaning that hardware offload does not work, resulting in the kernel
+failing to boot. The quirk detects that the kernel is running on an A0
+stepping SoC and disables the use of hardware offload.
+
+Currently the quirk is only enabled for PlatHome Openblocks AX3. The
+AX3 has been produced with both A0 and B0 stepping SoCs. The second
+product is the Lenovo Iomega IX4-300d. It seems likely that this
+device will also swap from A0 to B0 SoC sometime during its life.
+
+If there are two products using A0, it seems likely there are more
+products with A0. Also, since the number of A0 SoCs is limited, these
+products are also likely to transition to B0. Hence detecting at run
+time is the safest option. So enable the quirk for all Armada XP
+boards.
+
+Tested on an AX3 with A0 stepping.
+
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Fixes: 930ab3d403ae: ("i2c: mv64xxx: Add I2C Transaction Generator support")
+Link: https://lkml.kernel.org/r/1406395238-29758-2-git-send-email-andrew@lunn.ch
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-mvebu/board-v7.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-mvebu/board-v7.c
++++ b/arch/arm/mach-mvebu/board-v7.c
+@@ -188,7 +188,7 @@ static void __init thermal_quirk(void)
+
+ static void __init mvebu_dt_init(void)
+ {
+- if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
++ if (of_machine_is_compatible("marvell,armadaxp"))
+ i2c_quirk();
+ if (of_machine_is_compatible("marvell,a375-db")) {
+ external_abort_quirk();
--- /dev/null
+From 73b3a6657a88ef5348a0d69c9a8107d6f01ae862 Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Mon, 3 Nov 2014 12:09:52 +0200
+Subject: pinctrl: dra: dt-bindings: Fix output pull up/down
+
+From: Roger Quadros <rogerq@ti.com>
+
+commit 73b3a6657a88ef5348a0d69c9a8107d6f01ae862 upstream.
+
+For PIN_OUTPUT_PULLUP and PIN_OUTPUT_PULLDOWN we must not set the
+PULL_DIS bit which disables the PULLs.
+
+PULL_ENA is a 0 and using it in an OR operation is a NOP, so don't
+use it in the PIN_OUTPUT_PULLUP/DOWN macros.
+
+Fixes: 23d9cec07c58 ("pinctrl: dra: dt-bindings: Fix pull enable/disable")
+
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Acked-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/dt-bindings/pinctrl/dra.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/include/dt-bindings/pinctrl/dra.h
++++ b/include/dt-bindings/pinctrl/dra.h
+@@ -40,8 +40,8 @@
+
+ /* Active pin states */
+ #define PIN_OUTPUT (0 | PULL_DIS)
+-#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
+-#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
++#define PIN_OUTPUT_PULLUP (PULL_UP)
++#define PIN_OUTPUT_PULLDOWN (0)
+ #define PIN_INPUT (INPUT_EN | PULL_DIS)
+ #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
+ #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
drm-radeon-use-gart-for-dma-ib-tests.patch
drm-radeon-add-missing-crtc-unlock-when-setting-up-the-mc.patch
drm-radeon-add-locking-around-atombios-scratch-space-usage.patch
+arm-8198-1-make-kuser-helpers-depend-on-mmu.patch
+arm-8191-1-decompressor-ensure-i-side-picks-up-relocated-code.patch
+arm-dts-am335x-evm-fix-5th-nand-partition-s-name.patch
+arm-mvebu-armada-xp-generalize-use-of-i2c-quirk.patch
+pinctrl-dra-dt-bindings-fix-output-pull-up-down.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
