Fixes for 4.4

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-4.4/perf-amd-uncore-replace-manual-sampling-check-with-c.patch b/queue-4.4/perf-amd-uncore-replace-manual-sampling-check-with-c.patch
new file mode 100644 (file)
index 0000000..8e35bb3
--- /dev/null
+++ b/queue-4.4/perf-amd-uncore-replace-manual-sampling-check-with-c.patch
@@ -0,0 +1,90 @@
+From 2c769ccb879f2de786c3c2b95f56281f9d145abb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 11 Mar 2020 14:13:21 -0500
+Subject: perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT
+ flag
+
+From: Kim Phillips <kim.phillips@amd.com>
+
+[ Upstream commit f967140dfb7442e2db0868b03b961f9c59418a1b ]
+
+Enable the sampling check in kernel/events/core.c::perf_event_open(),
+which returns the more appropriate -EOPNOTSUPP.
+
+BEFORE:
+
+  $ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
+  Error:
+  The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (l3_request_g1.caching_l3_cache_accesses).
+  /bin/dmesg | grep -i perf may provide additional information.
+
+With nothing relevant in dmesg.
+
+AFTER:
+
+  $ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
+  Error:
+  l3_request_g1.caching_l3_cache_accesses: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'
+
+Fixes: c43ca5091a37 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters")
+Signed-off-by: Kim Phillips <kim.phillips@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Peter Zijlstra <peterz@infradead.org>
+Cc: stable@vger.kernel.org
+Link: https://lkml.kernel.org/r/20200311191323.13124-1-kim.phillips@amd.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/cpu/perf_event_amd_uncore.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/perf_event_amd_uncore.c b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
+index 49742746a6c96..98e786a779fd0 100644
+--- a/arch/x86/kernel/cpu/perf_event_amd_uncore.c
++++ b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
+@@ -181,21 +181,19 @@ static int amd_uncore_event_init(struct perf_event *event)
+               return -ENOENT;
+ 
+       /*
+-       * NB and L2 counters (MSRs) are shared across all cores that share the
+-       * same NB / L2 cache. Interrupts can be directed to a single target
+-       * core, however, event counts generated by processes running on other
+-       * cores cannot be masked out. So we do not support sampling and
+-       * per-thread events.
++       * NB and Last level cache counters (MSRs) are shared across all cores
++       * that share the same NB / Last level cache.  On family 16h and below,
++       * Interrupts can be directed to a single target core, however, event
++       * counts generated by processes running on other cores cannot be masked
++       * out. So we do not support sampling and per-thread events via
++       * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
+        */
+-      if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+-              return -EINVAL;
+ 
+       /* NB and L2 counters do not have usr/os/guest/host bits */
+       if (event->attr.exclude_user || event->attr.exclude_kernel ||
+           event->attr.exclude_host || event->attr.exclude_guest)
+               return -EINVAL;
+ 
+-      /* and we do not enable counter overflow interrupts */
+       hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
+       hwc->idx = -1;
+ 
+@@ -271,6 +269,7 @@ static struct pmu amd_nb_pmu = {
+       .start          = amd_uncore_start,
+       .stop           = amd_uncore_stop,
+       .read           = amd_uncore_read,
++      .capabilities   = PERF_PMU_CAP_NO_INTERRUPT,
+ };
+ 
+ static struct pmu amd_l2_pmu = {
+@@ -282,6 +281,7 @@ static struct pmu amd_l2_pmu = {
+       .start          = amd_uncore_start,
+       .stop           = amd_uncore_stop,
+       .read           = amd_uncore_read,
++      .capabilities   = PERF_PMU_CAP_NO_INTERRUPT,
+ };
+ 
+ static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
+-- 
+2.20.1
+

diff --git a/queue-4.4/series b/queue-4.4/series
index 99ba57bfc210ba8e1296fec4c4ea6b32303ae89c..9cd455c5bdb244660000537bfbbd61847c024ec1 100644 (file)
--- a/queue-4.4/series
+++ b/queue-4.4/series
@@ -83,3 +83,4 @@ batman-adv-reduce-tt_global-hash-refcnt-only-for-removed-entry.patch
 batman-adv-only-read-ogm-tvlv_len-after-buffer-len-check.patch
 batman-adv-avoid-free-alloc-race-when-handling-ogm-buffer.patch
 batman-adv-don-t-schedule-ogm-for-disabled-interface.patch
+perf-amd-uncore-replace-manual-sampling-check-with-c.patch