RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN...

riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct minimal
VLEN info, the size difference between different RVV modes can be up to 64
times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
versus [64, 64] respectively.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
	max_power to 64.
	* config/riscv/riscv.h (MAX_POLY_VARIANT): New.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/autovec/bug-01.C: New.
	* g++.target/riscv/rvv/rvv.exp: Add autovec folder.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 66a55a73cb508b36dd0a4eb7fd26152b23ca4850..44746256f6113789f8e378e53234b14fced3f013 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2404,9 +2404,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
     }
   else
     {
-      /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096.  */
-      int max_power = exact_log2 (4096 / 128);
-      for (int i = 0; i < max_power; i++)
+      int max_power = exact_log2 (MAX_POLY_VARIANT);
+      for (int i = 0; i <= max_power; i++)
        {
          int possible_div_factor = 1 << i;
          if (factor % (vlenb / possible_div_factor) == 0)

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index f43ff10bc8339534de28892a8bc263b93a395830..01645141935fd3bc49190e9eb9d69cf26975482e 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1191,4 +1191,9 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
 
+
+/* The size difference between different RVV modes can be up to 64 times.
+   e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
+#define MAX_POLY_VARIANT 64
+
 #endif /* ! GCC_RISCV_H */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
new file mode 100644 (file)
index 0000000..fd10009
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
@@ -0,0 +1,33 @@
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
+
+class c {
+public:
+  int e();
+  void j();
+};
+float *d;
+class k {
+  int f;
+
+public:
+  k(int m) : f(m) {}
+  float g;
+  float h;
+  void n(int m) {
+    for (int i; i < m; i++) {
+      d[0] = d[1] = d[2] = g;
+      d[3] = h;
+      d += f;
+    }
+  }
+};
+c l;
+void o() {
+  int b = l.e();
+  k a(b);
+  for (;;)
+    if (b == 4) {
+      l.j();
+      a.n(2);
+    }
+}

diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index 249530580d701625dec1f40b6a314eab2a4df18c..c30d6e93144c519f70e61e387001cedd43fe5e91 100644 (file)
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
        "" $CFLAGS
 
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
+        "" $CFLAGS
+
 # All done.
 dg-finish