clk: renesas: r9a09g057: Add clock and reset entries for ISP

Add entries detailing the clocks and resets for the ISP in the
RZ/V2H(P) SoC.

Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251010-rzv2h_isp_clk-v2-1-2c8853a9af7c@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 6389c4b6a5231e444d5d54eba963eec7bbfd47e3..c9c117c6782cb281b987ecfcece572961138ee7c 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -55,6 +55,7 @@ enum clk_ids {
        CLK_PLLVDO_CRU1,
        CLK_PLLVDO_CRU2,
        CLK_PLLVDO_CRU3,
+       CLK_PLLVDO_ISP,
        CLK_PLLETH_DIV_250_FIX,
        CLK_PLLETH_DIV_125_FIX,
        CLK_CSDIV_PLLETH_GBE0,
@@ -157,6 +158,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
        DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
        DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
+       DEF_DDIV(".pllvdo_isp",  CLK_PLLVDO_ISP,  CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
 
        DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
        DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -371,6 +373,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(7))),
        DEF_MOD("cru_3_pclk",                   CLK_PLLDTY_DIV16, 13, 13, 6, 29,
                                                BUS_MSTOP(9, BIT(7))),
+       DEF_MOD("isp_0_reg_aclk",               CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
+                                               BUS_MSTOP(9, BIT(8))),
+       DEF_MOD("isp_0_pclk",                   CLK_PLLDTY_DIV16, 14, 3, 7, 3,
+                                               BUS_MSTOP(9, BIT(8))),
+       DEF_MOD("isp_0_vin_aclk",               CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
+                                               BUS_MSTOP(9, BIT(9))),
+       DEF_MOD("isp_0_isp_sclk",               CLK_PLLVDO_ISP, 14, 5, 7, 5,
+                                               BUS_MSTOP(9, BIT(9))),
        DEF_MOD("gpu_0_clk",                    CLK_PLLGPU_GEAR, 15, 0, 7, 16,
                                                BUS_MSTOP(3, BIT(4))),
        DEF_MOD("gpu_0_axi_clk",                CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -442,6 +452,10 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(12, 14, 5, 31),         /* CRU_3_PRESETN */
        DEF_RST(12, 15, 6, 0),          /* CRU_3_ARESETN */
        DEF_RST(13, 0, 6, 1),           /* CRU_3_S_RESETN */
+       DEF_RST(13, 1, 6, 2),           /* ISP_0_VIN_ARESETN */
+       DEF_RST(13, 2, 6, 3),           /* ISP_0_REG_ARESETN */
+       DEF_RST(13, 3, 6, 4),           /* ISP_0_ISP_SRESETN */
+       DEF_RST(13, 4, 6, 5),           /* ISP_0_PRESETN */
        DEF_RST(13, 13, 6, 14),         /* GPU_0_RESETN */
        DEF_RST(13, 14, 6, 15),         /* GPU_0_AXI_RESETN */
        DEF_RST(13, 15, 6, 16),         /* GPU_0_ACE_RESETN */

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 840eed25aeda72f83644c6ba60d3f4368979b60e..e020d9624dfd75fbbf3dccf5ea045f81d26e0ae3 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -115,6 +115,7 @@ struct fixed_mod_conf {
 #define CPG_SSEL1              (0x304)
 #define CPG_CDDIV0             (0x400)
 #define CPG_CDDIV1             (0x404)
+#define CPG_CDDIV2             (0x408)
 #define CPG_CDDIV3             (0x40C)
 #define CPG_CDDIV4             (0x410)
 #define CPG_CSDIV0             (0x500)
@@ -125,6 +126,7 @@ struct fixed_mod_conf {
 #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
 #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
 #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
+#define CDDIV2_DIVCTL3 DDIV_PACK(CPG_CDDIV2, 12, 3, 11)
 #define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
 #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
 #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)