]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
authorChen-Yu Tsai <wens@csie.org>
Thu, 11 Sep 2025 17:47:05 +0000 (01:47 +0800)
committerChen-Yu Tsai <wens@csie.org>
Sat, 13 Sep 2025 05:49:09 +0000 (13:49 +0800)
There are four clock controllers in the A523 SoC. The existing binding
already covers two of them that are critical for basic operation. The
remaining ones are the MCU clock controller and CPU PLL clock
controller.

Add a description for the MCU CCU. This unit controls and provides
clocks to the MCU (RISC-V) subsystem and peripherals meant to operate
under low power conditions.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml
include/dt-bindings/clock/sun55i-a523-mcu-ccu.h [new file with mode: 0644]
include/dt-bindings/reset/sun55i-a523-mcu-ccu.h [new file with mode: 0644]

index f5f62e9a10a1f6baeb819b022c842ab06eee38be..58be701a720ea34c2aefc9e1b79b8436182fe29c 100644 (file)
@@ -19,6 +19,7 @@ properties:
   compatible:
     enum:
       - allwinner,sun55i-a523-ccu
+      - allwinner,sun55i-a523-mcu-ccu
       - allwinner,sun55i-a523-r-ccu
 
   reg:
@@ -26,11 +27,11 @@ properties:
 
   clocks:
     minItems: 4
-    maxItems: 5
+    maxItems: 9
 
   clock-names:
     minItems: 4
-    maxItems: 5
+    maxItems: 9
 
 required:
   - "#clock-cells"
@@ -63,6 +64,38 @@ allOf:
             - const: iosc
             - const: losc-fanout
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - allwinner,sun55i-a523-mcu-ccu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: High Frequency Oscillator (usually at 24MHz)
+            - description: Low Frequency Oscillator (usually at 32kHz)
+            - description: Internal Oscillator
+            - description: Audio PLL (4x)
+            - description: Peripherals PLL 0 (300 MHz output)
+            - description: DSP module clock
+            - description: MBUS clock
+            - description: PRCM AHB clock
+            - description: PRCM APB0 clock
+
+        clock-names:
+          items:
+            - const: hosc
+            - const: losc
+            - const: iosc
+            - const: pll-audio0-4x
+            - const: pll-periph0-300m
+            - const: dsp
+            - const: mbus
+            - const: r-ahb
+            - const: r-apb0
+
   - if:
       properties:
         compatible:
diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h
new file mode 100644 (file)
index 0000000..6efc6bc
--- /dev/null
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
+#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
+
+#define CLK_MCU_PLL_AUDIO1     0
+#define CLK_MCU_PLL_AUDIO1_DIV2        1
+#define CLK_MCU_PLL_AUDIO1_DIV5        2
+#define CLK_MCU_AUDIO_OUT      3
+#define CLK_MCU_DSP            4
+#define CLK_MCU_I2S0           5
+#define CLK_MCU_I2S1           6
+#define CLK_MCU_I2S2           7
+#define CLK_MCU_I2S3           8
+#define CLK_MCU_I2S3_ASRC      9
+#define CLK_BUS_MCU_I2S0       10
+#define CLK_BUS_MCU_I2S1       11
+#define CLK_BUS_MCU_I2S2       12
+#define CLK_BUS_MCU_I2S3       13
+#define CLK_MCU_SPDIF_TX       14
+#define CLK_MCU_SPDIF_RX       15
+#define CLK_BUS_MCU_SPDIF      16
+#define CLK_MCU_DMIC           17
+#define CLK_BUS_MCU_DMIC       18
+#define CLK_MCU_AUDIO_CODEC_DAC        19
+#define CLK_MCU_AUDIO_CODEC_ADC        20
+#define CLK_BUS_MCU_AUDIO_CODEC        21
+#define CLK_BUS_MCU_DSP_MSGBOX 22
+#define CLK_BUS_MCU_DSP_CFG    23
+#define CLK_BUS_MCU_NPU_HCLK   24
+#define CLK_BUS_MCU_NPU_ACLK   25
+#define CLK_MCU_TIMER0         26
+#define CLK_MCU_TIMER1         27
+#define CLK_MCU_TIMER2         28
+#define CLK_MCU_TIMER3         29
+#define CLK_MCU_TIMER4         30
+#define CLK_MCU_TIMER5         31
+#define CLK_BUS_MCU_TIMER      32
+#define CLK_BUS_MCU_DMA                33
+#define CLK_MCU_TZMA0          34
+#define CLK_MCU_TZMA1          35
+#define CLK_BUS_MCU_PUBSRAM    36
+#define CLK_MCU_MBUS_DMA       37
+#define CLK_MCU_MBUS           38
+#define CLK_MCU_RISCV          39
+#define CLK_BUS_MCU_RISCV_CFG  40
+#define CLK_BUS_MCU_RISCV_MSGBOX       41
+#define CLK_MCU_PWM0           42
+#define CLK_BUS_MCU_PWM0       43
+
+#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h
new file mode 100644 (file)
index 0000000..a89a0b4
--- /dev/null
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
+#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
+
+#define RST_BUS_MCU_I2S0               0
+#define RST_BUS_MCU_I2S1               1
+#define RST_BUS_MCU_I2S2               2
+#define RST_BUS_MCU_I2S3               3
+#define RST_BUS_MCU_SPDIF              4
+#define RST_BUS_MCU_DMIC               5
+#define RST_BUS_MCU_AUDIO_CODEC                6
+#define RST_BUS_MCU_DSP_MSGBOX         7
+#define RST_BUS_MCU_DSP_CFG            8
+#define RST_BUS_MCU_NPU                        9
+#define RST_BUS_MCU_TIMER              10
+#define RST_BUS_MCU_DSP_DEBUG          11
+#define RST_BUS_MCU_DSP                        12
+#define RST_BUS_MCU_DMA                        13
+#define RST_BUS_MCU_PUBSRAM            14
+#define RST_BUS_MCU_RISCV_CFG          15
+#define RST_BUS_MCU_RISCV_DEBUG                16
+#define RST_BUS_MCU_RISCV_CORE         17
+#define RST_BUS_MCU_RISCV_MSGBOX       18
+#define RST_BUS_MCU_PWM0               19
+
+#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */