RISC-V: Add test for vec_duplicate + vmslt.vv combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vmslt.vv
combine to vmslt.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vmslt.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 14a961de054c94aa843df028ddcc35598bdc0542..1b7a0d8061b7b8cc4172eb467eae7ad7bcbfe38b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 738caa81a71b9ed900f0d8438c50f7d11a15a3de..8e2c6315b08b76aff6a8cca083a1107ff0ff2d9c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 1e7a977cd85cf27852312af3cae6331bbf814913..a16623ee2941e160dbe72d430469b83a5c192c8d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -32,3 +32,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 70257d3b54733501196e9a78a975f6a85410a1ea..be50b83c7260f1f1c66fb30eb5db7442bddddcd2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index bced1568c3e9ac8e6c20eae218dd53a5311142e5..fb50baecf596cda07f7ccf5ff4feb3a34d22ed04 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index cfb52fbadcfc6ca0928841a10ef5deec3da8f5d8..d79e0e04c85a73e088df7eeea10227831ff3d0f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 31846eff9b44d6ffbf8c188428f2155622df3fb7..6cdaf5d65387da535bdc80cfc8bae8c96d0d78ed 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index ea28e2b3dd65e04c7270a31b84a181fd37c804ed..9e3879aadb75e4b827ec39d9d162bf4101602188 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index e3cddc4fb21caa9ea046299a36c46682015d15eb..e3ef3e35deb05e48ed1a512077e77c4824b72cf1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index c5cce621f92a5ed79ebde95551b76540f1720ffb..20039c7e3b370127ec23edff400eae72ac9cdad0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -28,4 +28,5 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 6ef8681011eee19deaf6f091656e7d7fce986aed..c973ea7c430d807dfa756be1ca126b7f9a07c010 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index cc789591dc91d9be3a3e4d67679121eedfe1ff29..e781c627b8dca7569476f5b3dd98babd42ecbc77 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmslt.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 764f301d0820a1ccf3df1f539a7b5c6e2ecb656a..a9bba40a55d4715c466556d943ef365cf241cfc4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -404,6 +404,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
   DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne)                            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, <, lt)                             \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)           \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index d4834c794148b9d65571018afdfe4fc4f4480dba..fad479a260f6a41c88e29f08fe4e70def665cb4d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6566,4 +6566,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, ltu)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, lt)[][3][N] =
+{
+  {
+    { 127 },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+       127,  127,  127,  127,
+      -128, -128, -128, -128,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { -1 },
+    {
+         0,    0,    0,    0,
+         1,    1,    1,    1,
+        -2,   -2,   -2,   -2,
+      -128, -128, -128, -128,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, lt)[][3][N] =
+{
+  {
+    { 32767 },
+    {
+           0,      0,      0,      0,
+          -1,     -1,     -1,     -1,
+       32767,  32767,  32767,  32767,
+      -32768, -32768, -32768, -32768,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { -1 },
+    {
+           0,      0,      0,      0,
+           1,      1,      1,      1,
+          -2,     -2,     -2,     -2,
+      -32768, -32768, -32768, -32768,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, lt)[][3][N] =
+{
+  {
+    { 2147483647 },
+    {
+                0,           0,           0,           0,
+               -1,          -1,          -1,          -1,
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { -1 },
+    {
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+               -2,          -2,          -2,          -2,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, lt)[][3][N] =
+{
+  {
+    { 9223372036854775807ll },
+    {
+                            0,                       0,                       0,                       0,
+                           -1,                      -1,                      -1,                      -1,
+        9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,   9223372036854775807ll,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { -1 },
+    {
+                            0,                       0,                       0,                       0,
+                            1,                       1,                       1,                       1,
+                           -2,                      -2,                      -2,                      -2,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c
new file mode 100644 (file)
index 0000000..865a2f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME lt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c
new file mode 100644 (file)
index 0000000..eeb2a66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c
@@ -0,0 +1,16 @@
+
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME lt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c
new file mode 100644 (file)
index 0000000..c3a2052
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME lt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c
new file mode 100644 (file)
index 0000000..92a84f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME lt
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"