ARM: dts: socfpga: fix register entry for timer3 on Arria10

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index fc4abef143a066eb86d0d704600c30170faca7c8..0013ec3463c46569750d52d8f0ce6867285d664a 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -821,7 +821,7 @@
                timer3: timer3@ffd00100 {
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
-                       reg = <0xffd01000 0x100>;
+                       reg = <0xffd00100 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
                        resets = <&rst L4SYSTIMER1_RESET>;