drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engine

[Why & How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.

Reviewed-by: HaoPing Liu <haoping.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 6fdc306a4a86bbbfcca21cb090311539791f6c6b..5cc84dce001d71598e48f09fd76a8ebb39d7ff0e 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -709,7 +709,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
        }
 
        if (dm_is_crc_source_crtc(cur_crc_src)) {
-               if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
+               if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 0,
                                       &crcs[0], &crcs[1], &crcs[2]))
                        return;
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 97b3237772f90882a0dfe9f943f93d8396954819..2c0ca47336112641d584e48a026d9b24a5777da6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -753,6 +753,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
  *
  * @dc: DC object.
  * @stream: The DC stream state of the stream to get CRCs from.
+ * @idx: index of crc engine to get CRC from
  * @r_cr: CRC value for the red component.
  * @g_y:  CRC value for the green component.
  * @b_cb: CRC value for the blue component.
@@ -762,7 +763,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
  * Return:
  * %false if stream is not found, or if CRCs are not enabled.
  */
-bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
+bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,
                       uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 {
        int i;
@@ -783,7 +784,7 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
        tg = pipe->stream_res.tg;
 
        if (tg->funcs->get_crc)
-               return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
+               return tg->funcs->get_crc(tg, idx, r_cr, g_y, b_cb);
        DC_LOG_WARNING("CRC capture not supported.");
        return false;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 50cbf0661f2ec23725fc1b0e347e468eb923a0ce..dbf0832eb706bc31f46ca2b6efac50c8ba986c27 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -554,6 +554,7 @@ bool dc_stream_configure_crc(struct dc *dc,
 
 bool dc_stream_get_crc(struct dc *dc,
                       struct dc_stream_state *stream,
+                      uint8_t idx,
                       uint32_t *r_cr,
                       uint32_t *g_y,
                       uint32_t *b_cb);

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index fa422a8cbced5a26997dda2cd4a66c78dc4865cb..e32dd96a99cb8f42347f09b040659c0ffe805859 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -2190,7 +2190,7 @@ bool dce110_configure_crc(struct timing_generator *tg,
        return true;
 }
 
-bool dce110_get_crc(struct timing_generator *tg,
+bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,
                    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 {
        uint32_t addr = 0;
@@ -2206,14 +2206,30 @@ bool dce110_get_crc(struct timing_generator *tg,
        if (!field)
                return false;
 
-       addr = CRTC_REG(mmCRTC_CRC0_DATA_RG);
-       value = dm_read_reg(tg->ctx, addr);
-       *r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR);
-       *g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y);
+       switch (idx) {
+       case 0:
+               addr = CRTC_REG(mmCRTC_CRC0_DATA_RG);
+               value = dm_read_reg(tg->ctx, addr);
+               *r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR);
+               *g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y);
 
-       addr = CRTC_REG(mmCRTC_CRC0_DATA_B);
-       value = dm_read_reg(tg->ctx, addr);
-       *b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB);
+               addr = CRTC_REG(mmCRTC_CRC0_DATA_B);
+               value = dm_read_reg(tg->ctx, addr);
+               *b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB);
+               break;
+       case 1:
+               addr = CRTC_REG(mmCRTC_CRC1_DATA_RG);
+               value = dm_read_reg(tg->ctx, addr);
+               *r_cr = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_R_CR);
+               *g_y = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_G_Y);
+
+               addr = CRTC_REG(mmCRTC_CRC1_DATA_B);
+               value = dm_read_reg(tg->ctx, addr);
+               *b_cb = get_reg_field_value(value, CRTC_CRC1_DATA_B, CRC1_B_CB);
+               break;
+       default:
+               return false;
+       }
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index ee4de740aceb3c97dc398800caccfb408824b743..e4f5cad64f3285543a5629eae5ff3e2fd6716c85 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -286,7 +286,7 @@ bool dce110_arm_vert_intr(
 bool dce110_configure_crc(struct timing_generator *tg,
                          const struct crc_params *params);
 
-bool dce110_get_crc(struct timing_generator *tg,
+bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,
                    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 
 bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index fcf59348eb6249fc8abb488bdd57701c5dd5885d..4984adce077ebcdd400ce133aa8e0862dea6c626 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1137,8 +1137,8 @@ static bool dce120_configure_crc(struct timing_generator *tg,
        return true;
 }
 
-static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr,
-                          uint32_t *g_y, uint32_t *b_cb)
+static bool dce120_get_crc(struct timing_generator *tg, uint8_t idx,
+                       uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 {
        struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
        uint32_t value, field;
@@ -1151,14 +1151,30 @@ static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr,
        if (!field)
                return false;
 
-       value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_RG,
-                                 tg110->offsets.crtc);
-       *r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR);
-       *g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y);
+       switch (idx) {
+       case 0:
+               value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_RG,
+                                         tg110->offsets.crtc);
+               *r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR);
+               *g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y);
 
-       value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_B,
-                                 tg110->offsets.crtc);
-       *b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB);
+               value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_B,
+                                         tg110->offsets.crtc);
+               *b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB);
+               break;
+       case 1:
+               value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC1_DATA_RG,
+                                         tg110->offsets.crtc);
+               *r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_R_CR);
+               *g_y = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_G_Y);
+
+               value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC1_DATA_B,
+                                         tg110->offsets.crtc);
+               *b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_B, CRC1_B_CB);
+               break;
+       default:
+               return false;
+       }
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
index 03cbcbb36f1c1638d3976275421365ee07f9262b..6fdc9809280ca2db60fec4f16c8b67149711a2ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
@@ -210,7 +210,7 @@ void optc1_enable_crtc_reset(struct timing_generator *optc,
 
 bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);
 
-bool optc1_get_crc(struct timing_generator *optc,
+bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,
                   uint32_t *r_cr,
                   uint32_t *g_y,
                   uint32_t *b_cb);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index b74e18cc1e667e42fad369ba2a5eaba8222bcaa0..4807b9f9f5a52095b1ad64ffe173b83ffbdaa982 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -291,7 +291,7 @@ struct timing_generator_funcs {
         * @get_crc: Get CRCs for the given timing generator. Return false if
         * CRCs are not enabled (via configure_crc).
         */
-       bool (*get_crc)(struct timing_generator *tg,
+       bool (*get_crc)(struct timing_generator *tg, uint8_t idx,
                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 
        void (*program_manual_trigger)(struct timing_generator *optc);

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
index 097d06023e64447e822471b05dea8b2c79ce1f72..d4ef874327ba7146339d2fd91c3cfb1a1ac6d5ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
@@ -1510,6 +1510,7 @@ bool optc1_configure_crc(struct timing_generator *optc,
  * optc1_get_crc - Capture CRC result per component
  *
  * @optc: timing_generator instance.
+ * @idx: index of crc engine to get CRC from
  * @r_cr: 16-bit primary CRC signature for red data.
  * @g_y: 16-bit primary CRC signature for green data.
  * @b_cb: 16-bit primary CRC signature for blue data.
@@ -1521,7 +1522,7 @@ bool optc1_configure_crc(struct timing_generator *optc,
  * If CRC is disabled, return false; otherwise, return true, and the CRC
  * results in the parameters.
  */
-bool optc1_get_crc(struct timing_generator *optc,
+bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,
                   uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 {
        uint32_t field = 0;
@@ -1533,14 +1534,30 @@ bool optc1_get_crc(struct timing_generator *optc,
        if (!field)
                return false;
 
-       /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
-       REG_GET_2(OTG_CRC0_DATA_RG,
-                 CRC0_R_CR, r_cr,
-                 CRC0_G_Y, g_y);
+       switch (idx) {
+       case 0:
+               /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
+               REG_GET_2(OTG_CRC0_DATA_RG,
+                         CRC0_R_CR, r_cr,
+                         CRC0_G_Y, g_y);
 
-       /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
-       REG_GET(OTG_CRC0_DATA_B,
-               CRC0_B_CB, b_cb);
+               /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
+               REG_GET(OTG_CRC0_DATA_B,
+                       CRC0_B_CB, b_cb);
+               break;
+       case 1:
+               /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */
+               REG_GET_2(OTG_CRC1_DATA_RG,
+                         CRC1_R_CR, r_cr,
+                         CRC1_G_Y, g_y);
+
+               /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */
+               REG_GET(OTG_CRC1_DATA_B,
+                       CRC1_B_CB, b_cb);
+               break;
+       default:
+               return false;
+       }
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
index 40757f20d73f41f3aea9e0864a588465516b694d..159172178d51c1e32a8c403b92c0871b008def15 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
@@ -86,6 +86,12 @@
        SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
        SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
        SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC1_DATA_RG, OTG, inst),\
+       SRI(OTG_CRC1_DATA_B, OTG, inst),\
+       SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
        SR(GSL_SOURCE_SELECT),\
        SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
        SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
@@ -315,6 +321,7 @@ struct dcn_optc_registers {
        SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
        SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
        SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
        SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
        SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
        SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
@@ -327,6 +334,17 @@ struct dcn_optc_registers {
        SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
        SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
        SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
        SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
        SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
        SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
@@ -482,6 +500,7 @@ struct dcn_optc_registers {
        type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\
        type OTG_CRC_CONT_EN;\
        type OTG_CRC0_SELECT;\
+       type OTG_CRC1_SELECT;\
        type OTG_CRC_EN;\
        type CRC0_R_CR;\
        type CRC0_G_Y;\