riscv: dts: renesas: Add specific RZ/Five cache compatible

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20250512-sphere-plenty-8ce4cd772745@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index e0ddf8f602c79bc87253aff10925ad7edd08bf9c..a8bcb26f42700644a431958b5bff985bef3bd4c5 100644 (file)
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -143,7 +143,8 @@
        };
 
        l2cache: cache-controller@13400000 {
-               compatible = "andestech,ax45mp-cache", "cache";
+               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+                            "cache";
                reg = <0x0 0x13400000 0x0 0x100000>;
                interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
                cache-size = <0x40000>;